3
4063
Description
Th
e MC
34063
A
Se
r
ies is
a
monolithic con
t
r
ol
ci
r
c
ui
t
con
t
ainin
g th
e
pr
im
ary
func
ti
o
ns
re
q
ui
r
e
d fo
r
DC
-t
o
-
DC
con
v
er
t
e
r
s
.
Th
ese devi
ces con
sis
t
of
an in
te
rna
l
t
e
mperatur
e
co
mp
ensa
t
e
d
referenc
e
,
comparat
or
,
cont
r
olled du
t
y
cy
cl
e
osc
i
llato
r
w
i
t
h an
ac
ti
ve
c
u
rrent
li
m
i
t
ci
r
c
ui
t
,
dr
i
v
er
and
hig
h
c
u
rrent
out
put
sw
itc
h
.
Th
is se
ri
es
wa
s s
p
ec
ific
a
lly desi
gned
to
be
inco
rpo
r
a
t
e
d
in Ste
p
-
D
own and Ste
p
-
U
p
and
Vo
lta
g
e
-
In
ve
rt
in
g
ap
pl
i
c
at
i
o
ns wi
t
h
a
mi
ni
m
u
m
num
b
e
r
of
ex
t
e
r
nal
compo
n
e
n
s
.
Features
•
Operation from 3.0 V to 40 V Input
•
Low Standby Current
•
Current Limiting
•
Output Switch Current to 1.5 A
•
Output Voltage Adjustable
•
Frequency Operation to 100 kHz
•
Precision 2% Reference
Plastic
Package
Pin Connections
Int
e
rn
a
l
Blo
c
k Di
g
r
a
m
D
r
i
v
er
C
o
llec
t
o
r
8
1
S
w
i
t
c
h
C
o
llec
t
o
r
S
Q
Q2
I
pk
Se
n
s
e
V
CC
Com
p
ar
a
t
o
r
In
v
e
rt
i
n
g
In
p
u
t
7
6
5
I
pk
Os
cilla
t
o
r
C
o
m
p
ara
t
or
C
T
R
1
0
0
1.25
V
Ref
e
r
ence
Q1
2
3
4
Sw
it
c
h
Em
i
tt
e
r
Tim
i
n
g
Ca
pa
c
i
t
o
r
Gn
d
1
BEIJING ESTEK ELECTRONICS CO.,LTD
34063
Absolute Maximum Ratings
Symbol Parameter Maximum Units
V
CC
Power Supply Voltage 40 Vdc
V
IR
Comparator Input Voltage Range -0.3 to +40 Vdc
V
C(switch)
Switch Collector Voltage 40 Vdc
V
E(switch)
Switch Emitter Voltage (V
PIN1
= 40 V) 40 Vdc
V
CE(switch)
Switch Collector to Emitter Voltage 40 Vdc
V
C(driver)
Driver Collector Voltage 40 Vdc
I
C(driver)
Driver Collector Current (Note 1) 100 mA
I
SW
Switch Current 1.5 A
T
J
Operating Junction Temperature +150 °C
T
A
Operating Ambient Temperature Range 0 to +70 °C
Tstg
Storage Temperature Range
-
65 to +150
°C
Ele
ctr
ic
a
l
C
h
ara
ct
e
r
i
st
ic
s
(Vcc=5.0V, Ta=T
low
to T
high
unless otherwise
specified)
OSCILL
A
TOR
Characteristic
s
S
y
mbo
l
Mi
n
T
y
p
Ma
x
Units
Frequency (V
pin5
= 0V, C
T
= 1.0 nF, T
A
= 25°C) f
OSC
24 33 42 kHz
Charge Current(V
CC
= 5.0V to 40V, T
A
= 25°C) I
chg
24 35 42 µA
Discharge Current (V
CC
= 5.0V to 40V, T
A
= 25°C) I
dischg
140 220 260 µA
Discharge to Charge Current Ratio (Pin 7 to V
CC
, T
A
= 25°C) I
dischg
/
I
c
h
5.2
6.5
7.5
–
Current Limit Sense Voltage (I
chg
= I
dischg
, T
A
= 25°C) V
ipk(sence)
250 300 350 mV
OUTPUT SWITCH (NOTE 2)
Saturation Voltage, Darlington Connection (I
SW
= 1.0 A, Pins 1, 8 connected) V
CE(sat)
– 1.0 1.3 V
Saturation Voltage, Darlington Connection (I
SW
= 1.0 A, R
pin 8
= 82Ωto V
CC
, Forced
β
≅
20) V
CE(sat)
– 0.45 0.7 V
DC Current Gain (I
SW
= 1.0 A, V
CE
= 5.0 V, T
A
= 25°C) h
FE
50 75 – –
Collector Off-State Current (V
CE
= 40 V) I
C(off)
– 40 100 µA
CO
MP
A
R
A
TO
R
Threshold Voltage
(T
A
=25°C)
(T
A
=
T
lo
w
to
T
high
)
Vth
1.225
1.21
1.25
–
1.275
1.29
V
Threshold Voltage Line Regulation
(Vcc=3.0 V to 40 V)
Input Bias Current
(Vin=0 V)
TOTAL DEVICE
Supply Current (Vcc = 5.0 V to 40 V, C
T
= 1.0 nF, Pin 7 = V
CC
, Vpin 5 > Vth, Pin 2 =
Gnd, remaining pins open)
Re
g
line
–
1.4
5.0
mV
I
IB
– -20 -400 nA
I
CC
–
–
4.0
mA
NOTES :
1.Maximum package power dissipation limits must be observed.
2.Low duty cycle pulse techniques are used during test to maintain junction temperature
as close to ambient temperature as possible
BEIJING ESTEK ELECTRONICS CO.,LTD
2
34063
T
y
pi
c
a
l P
e
rf
or
m
an
c
e
C
h
a
r
a
c
te
ri
s
t
i
c
s
F
i
g
u
r
e
1
.
O
u
tp
u
S
w
i
c
h
O
n
-
O
ff
T
i
m
e
v
e
r
s
us
O
s
c
i
ll
a
t
o
r
T
i
m
i
n
g
C
a
pa
c
i
t
o
r
F
i
g
u
r
e
2.
T
i
m
i
n
g
Capa
c
i
t
o
r
Wav
e
f
o
rm
A
F
i
g
u
r
e
3
.
E
m
i
tt
e
r
F
o
ll
o
w
e
r
C
o
n
f
i
g
u
r
a
t
i
o
n
Out
p
u
t
F
i
g
u
r
e
4
.
C
o
m
m
o
n
E
m
i
tt
e
r
C
o
n
f
i
g
u
r
a
t
i
o
n
Sa
tura
ti
on
Vo
lta
g
e
ve
rs
us
Em
it
te
r
Cu
rr
en
t
Outp
ut
Sw
i
t
c
h
Sa
tu
ra
ti
o
n
Vo
lta
g
e
ve
rs
us
C
o
l
l
e
c
t
o
r
C
u
rr
e
nt
Fi
g
u
r
e
5.
Cu
rrent
Limi
t
Sense
Vo
lta
g
e
Fi
g
u
r
e
6.
Stand
b
y
Su
pp
ly Curren
t
ve
rs
us
v
e
r
s
u
s
T
e
m
p
e
r
a
ure
Su
p
p
l
y
V
o
lta
g
e
3
BEIJING ESTEK ELECTRONICS CO.,LTD
34063
T
y
pi
c
a
l A
p
pli
c
ati
o
ns
C
ircui
t
F
i
g
u
e
1
.
S
t
e
p
-
U
p
C
o
n
v
e
te
.
N
o
t
e
:
R
t
o
0
f
o
r
c
o
n
s
t
a
n
t
V
in
F
i
g
u
e
2
a.
E
x
t
e
n
a
l
NP
N
S
wit
ch
.
F
i
g
u
e
2
b.
E
x
t
e
n
al
N
P
N
S
a
t
u
a
t
e
d
S
w
it
c
h
.
F
i
g
u
e
2
.
E
x
t
e
n
al
C
u
rr
en
t
B
o
o
st
C
o
n
n
ec
t
i
o
n
s
f
o
I
P
e
a
k
Gr
ea
t
e
t
h
a
n
1
.5
.
A
4
BEIJING ESTEK ELECTRONICS CO.,LTD
34063
F
i
g
u
e
3
.
S
t
e
p
-
D
o
w
n
C
o
n
v
e
t
e
.
F
i
g
u
e
4
a.
E
x
t
e
n
a
l
NP
N
S
wit
ch
.
F
i
g
u
e
4
b.
E
x
t
e
n
a
l
PN
P
S
u
t
u
a
t
e
d
Swi
t
c
h
.
F
i
g
u
e
4
.
E
x
t
e
n
al
C
u
rr
en
t
B
o
o
st
C
o
n
n
ec
t
i
o
n
s
f
o
I
P
e
a
k
G
e
a
t
e
t
h
an
1
.5
.
A
5
BEIJING ESTEK ELECTRONICS CO.,LTD
34063
F
i
g
u
e
5
.
V
o
lt
a
g
e
I
nv
e
rt
i
n
g
C
o
n
ve
t
e
.
F
i
g
u
e
6
a.
E
x
t
e
n
a
l
NP
N
S
wit
ch
.
F
i
g
u
e
6
b.
E
x
t
e
n
a
l
PN
P
S
a
t
u
a
t
e
d
Swi
t
c
h
.
F
i
g
u
e
6
.
E
x
t
e
n
al
C
u
rr
e
n
t
B
o
o
st
C
o
n
n
ec
ti
o
n
s
f
o
I
P
e
a
k
G
e
a
t
e
t
h
an
1
.5
.
A
BEIJING ESTEK ELECTRONICS CO.,LTD
6
34063
Design Formula Table
C
a
lc
ulatio
n
S
t
ep
-
Up
S
t
ep
-
D
own
V
o
ltage
-
I
n
v
e
rti
n
g
t
on
/
t
of
f
ou
t
V
+
−
in
V
+
V
F
ou
t
V
+
V
F
in
V
(min)
−
sat
V
(t
on
+t
of
f
)m
a
x
1
f
in
V
(min)
−
V
sat
−
out
V
1
f
in
V
+
V
sat
1
min
f
C
T
4.
0
x
10
-5
t
on
4.
0
x
10
-5
t
on
4.
0
x
10
-5
l
pk(
s
w
i
t
ch)
2
+
1
2
t
I
on
+
1
2
I
out(max)
I
o
n
t
(max)
R
SC
0.3/l
pk(
s
w
i
t
ch)
0.3/l
pk(
s
w
i
t
ch)
0.3/l
pk(
s
w
i
t
ch)
L
(m
in
)
−
V
in
(min)
V
sat
−
in
V
sa
t
V
×
t
on(max)
V
in(min)
V
sat
V
out
×
on
(max)
I
t
on
(max)
I
pk (switch)
I
pk(switch )
pk
(
switch
)
C
O
9
I
out
on
I
pk (switch )
(
+
)
9
I
V
ripple(pp)
8
V
ripple(pp)
V
ripple(pp)
TERMS
A
ND DEFINITIONS
V
sat
- Saturation voltage of the output switch.
V
F
- Forward voltage drop of the output rectifier.
T
he
follo
wi
ng
po
w
er
suppl
y
characteristics
must
be
chosen:
R
=
.1
25 1
+
V
out
1
R
V
in
- Nominal input voltage.
V
out
- Desired output voltage,
I
out
- Desired output current.
f
min
- Minimum desired output switching frequency at the selected values of V
in
and I
O
.
V
ripple(p-p)
–Desired peack-to-peack output ripple voltage. In practice, the calculated capacitor value w
ill need to be increased due to its
equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly
affect the
line and load regulation.
Or
d
e
ri
n
g
I
n
for
m
a
t
io
n
O
R
DER
NG
NU
M
B
E
R
P
A
C
K
AGE
M
A
R
K
NG
34063A
SOP
-
8
/DIP
-
8
MC34063A
Address :
6A06--6A07
Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
Postalcode:100039
Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Fax : 010-58895793
Http://www.estek.com.cn
Email:sales@estek.com.cn
REV No:01
-
060810
7
BEIJING ESTEK ELECTRONICS CO.,LTD