To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
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Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
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contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
1
Outline: 52PTG-A
N C : No Connection
A0 ~ A18
DQ1 ~ DQ16
W#
OE#
BC1#
Address input
Data input / output
Chip select input 1
Write control input
Output enable input
Lower Byte (DQ1 ~ 8)
Pin Function
Vcc
GND Power supply
Ground supply
BC2# Upper Byte (DQ9 ~ 16)
S2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
52
51
50
49
A16
DQ1
A0
GND
OE#
BYTE#
DQ9
DQ2
DQ3
NC
GND
DQ4
DQ5
DQ6
DQ7
DQ8
DQ16/A-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A17
A11
A10
A15
17
18
19
20
21
22
23
24
A13
A12
A14
A9
A8
A7
A6
A5
A4
A1
A2
A3
W#
NC
VCC
S1#
28
27
25
26
BC1#
S2
NC
NC
NC
NC
BC2#
10.49mm
30mA
(10MHz)
5mA
(1MHz)
Operating
temperature Part name Power
Supply Access time
max.
Stand-by current
Ratings (max.) Active
(3.3V, Typ.)
Icc1
70ºC25ºC
-40 ~ +85°C 2.7 ~ 3.6V
* Typical 40ºC25ºC 40ºC
20851.21.0
NC
S1# Chip select input 2
1
M5M5W817KT -70HI 70ns
The M5M5W817KT is a family of low voltage 8Mbit static RAMs
organized as 524288-words by 16-bit / 1048576-words by 8-bit,
fabricated by Mitsubishi's high-performance 0.18µm CMOS
technology.
The M5M5W817KT is suitable for memory applications where a
simple interfacing , battery operating and battery backup are
the important design objectives.
The M5M5W817KT is packaged in a 52pin-µTSOP with the outline
of 10.79mm x 10.49mm, and pin pitch of 0.40mm. It gives the
best solution for a compaction of mounting area as well as
flexibility of wiring pattern of printed circuit boards.
The operating temperature range is -40 ~ +85°C
DESCRIPTION
- Single 2.7~3.6V power supply
- Small stand-by current: 0.1µA (2.0V, typ.)
- No clocks, No refresh
- Data retention supply voltage =2.0~3.6V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1# and BC2#
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prevents data contention in the I/O bus
- Byte function (x8 mode) available by Byte# & A-1.
- Process technology: 0.18µm CMOS
- Package: 52pin 10.79mm x 10.49mm µTSOP
[0.4mm pin pitch]
FEATURES
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
current
PIN CONFIGURATION
85ºC
40
BYTE# Byte (x8 mode) enable input
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
22
FUNCTION
The M5M5W817KT is organized as 524288-words by 16-
bit / 1048576-words by 8-bit. These devices operate on a
single +2.7~3.6V power supply, and are directly TTL
compatible to both input and output. Its fully static circuit
needs no clocks and no refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1# , BC2# , S1#, S2 , W#,
OE# and BYTE#. Each mode is summarized in the function
table.
A write operation is executed whenever the low level W#
overlaps with the low level BC1# and/or BC2# and the low
level S1# and the high level S2. The address (A-1~A18 :
Byte mode, A0~A18 : Word mode) must be set up before
the write cycle and must be stable during the entire cycle.
A read operation is executed by setting W# at a high
level and OE# at a low level while BC1# and/or BC2# and
S1#and S2 are in an active state (S1#=L, S2=H).
When setting BYTE# at a low level, the function will be
in the x8 mede, which is, DQ1-8 are available and DQ9-16
are not available. In the x8 mode, A-1 is used as the
additional address. During the active function for x8 mode,
BC1# BC2# must be low level.
When setting BC1# and BC2# at a high level or S1# at
a high level or S2 at a low level, the chips are in a non-
selectable mode in which both reading and writing are
disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by
BC1#, BC2# and S1#, S2.
The power supply current is reduced as low as 0.1µA
(25°C, typical), and the memory data can be held at +2.0V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
Note1 : "H" and "L" in this table mean VIH and VIL, respectively.
Note2 : "X" in this table should be "H" or "L".
S1# S2 BYTE# BC1# BC2# W# OE# Mode DQ1~8 DQ9~15 DQ16 Icc
H H H or L XXXXNon selection High-Z High-Z High-Z Standby
XLH or L XXXXNon selection High-Z High-Z High-Z Standby
X X HHHX X Non selection High-Z High-Z High-Z Standby
LH H LHLXWrite Din High-Z High-Z Active
LH H LH H LRead Dout High-Z High-Z Active
LH H LHHH ------- High-Z High-Z High-Z Active
LHHHL L XWrite High-Z Din Din Active
LHHHLHLRead High-Z Dout Dout Active
LHHHLHX------- High-Z High-Z High-Z Active
LH H LLLXWrite Din Din Din Active
LH H L L HLRead Dout Dout Dout Active
LH H L L HX------- High-Z High-Z High-Z Active
LHLLLLXWrite Din High-Z A-1 Active
LHLLLHLRead Dout High-Z A-1 Active
LHLLLH H ------- High-Z High-Z A-1 Active
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
3
S2
W#
OE#
A0
A18
524288WORDS X
16 BITS
or
1048576WORDS X
8 BITS
CLOCK
GENERATOR
8
DQ
DQ1
16 /
DQ
A-1
DQ9
VCC
GND
S1#
BC2#
BC1#
8MS
BLOCK DIAGRAM
x8/x16
Switching
circuit
BYTE#
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
4
pF
10
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
CO
DC ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC Vcc=2.7V~3.6V,unless otherwise noted)
Note 4: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
CAPACITANCE (Ta=-40~+85ºC Vcc=2.7V~3.6V,unless otherwise noted)
Symbol Parameter Conditions Limits Max
Typ
Min Units
Input capacitance
Output capacitance
10
Symbol Parameter Limits
Conditions Units
µA
mA
mA
V
Icc1
Icc2
Icc4
VIH
VIL
IO
Icc3
VOH IOH= - 0.5mA
VOL IOL= 2.0mA
IIVI =0 ~ Vcc
BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc
Vcc+0.2V
0.6
2.2
- 0.2 *
2.4
2.0
0.4
±1
5030 ±1
15
MaxTypMin
f= 10MHz
f= 1MHz
-
-
-
-
-
f= 10MHz
f= 1MHz
55030 155
-
High-level input voltage
Input leakage current
Active supply current
( AC,MOS level )
( AC,TTL level )
Active supply current
Stand by supply current
( AC,MOS level )
( AC,TTL level )
Other inputs= 0 ~ Vcc
Note 3: Direction for current flowing into IC is indicated as positive (no mark)
BC1# and BC2# < 0.2V, S1# < 0.2V, S2 >Vcc-0.2V
other inputs < 0.2V or > Vcc-0.2V
Output - open (duty 100%)
BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =VIH or VIL
BC1# and BC2# =VIH or S1# =VIH or S2=VIL
µA
20
~ +70°C
~ +40°C
1.0
-
-
~ +25°C -
1.2
5
8
-
(1)
S1# > Vcc - 0.2V and S2 > Vcc - 0.2V,
other inputs = 0 ~ Vcc
S2 < 0.2V,
(2)
other inputs = 0 ~ Vcc
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
(3)
other inputs = 0 ~ Vcc
Low-level input voltage
High-level output voltage
Low-level output voltage
Output leakage current
Stand by supply current
Output - open (duty 100%)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
V
mW
Conditions
Ta = 25°C 700
- 65 ~ +150
Ratings
Vcc
VI
VO
Pd
Ta
Tstg
- 0.3* ~ +4.6
- 0.3* ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
Symbol Parameter Units
-40 ~ +85
With respect to GND
With respect to GND
With respect to GND
* -3.0V in case of AC (Pulse width 30ns)
ºC
ºC
* -1.0V in case of AC (Pulse width 30ns)
<
=
<
=
40
~ +85°C
- -
BYTE# > Vcc - 0.2V or < 0.2V,
BYTE# > Vcc - 0.2V or < 0.2V,
BYTE# > Vcc - 0.2V or < 0.2V,
BYTE# > Vcc - 0.2V or < 0.2V,
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
AC ELECTRICAL CHARACTERISTICS (Ta=-40~+85ºC, Vcc=2.7V ~3.6V,unless otherwise noted)
Input rise time and fall time
Reference level
Output loads
2.7~3.6V
VIH=2.7V, VIL=0.2V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
5ns
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
(1) TEST CONDITIONS
Supply voltage
Input pulse
1TTL
CL
DQ
tCR ns
ta(S1)
ta(OE)
tdis(S1)
tdis(OE)
ten(S1)
ten(OE)
tV(A)
ta(A)
10
35
ns
ns
ns
ns
ns
ns
ns
ns
ta(BC1)
ta(BC2)
tdis(BC1)
tdis(BC2)
ten(BC1)
ten(BC2)
ns
ns
ns
ns
ns
ns
70
70
70
70
25
25
25
25
5
5
5
10
ta(S2) ns
70
ten(S2) 10 ns
tdis(S2) ns
25
70
70HI
5
tsu(A-WH)
tCW
tw(W)
tsu(A)
tsu(S1)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(BC1)
tsu(BC2)
tsu(S2) ns
Symbol Parameter MaxMin Units
(2) READ CYCLE
(3) WRITE CYCLE
MaxMin
Limits Units
Symbol Parameter
VOH=VOL=1.5V
70HI
25
25
70
55
0
65
5
5
65
65
65
35
0
0
65
Limits
Fig.1 Output load
Including scope and
jig capacitance
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S2 low
Output disable time after S1# high
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
Output enable time after S1# low
Output enable time after S2 high
Output enable time after BC1# low
Output enable time after BC2# low
Output enable time after OE# low
Data valid time after address
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W#
Byte control 1 setup time
Byte control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W# low
Output disable time from OE# high
Output enable time from W# high
Output enable time from OE# low
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
BC1#,
BC2#
Read cycle
ta(A)
t
a(BC1)
tv (A)
tdis (BC1) or tdis (BC2)
ta (OE)
t
en (OE) tdis (OE)
tCR
t
en
(S1)
W# = "H" level
OE#
(Note5)
(Note5)
(Note5)
(Note5)
VALID DATA
ta(S1)
tdis (S1)
S1#
(Note5) (Note5)
t
a(BC2)
or
ten (BC2)
ten (BC1)
ta(S2)
tdis (S2)
S2
(Note5) (Note5)
t
en
(S2)
A0~18
(Word Mode)
A-1~18
(Byte Mode)
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
6
(5) TIMING DIAGRAMS
(4) Byte# function
t
su (BYTE)
t
rec (BYTE)
ms
Symbol Parameter Test conditions Limits
Min
Typ
Max Units
BYTE# set up time
BYTE# recovery time 5ms
5
tsu (BYTE) trec (BYTE)
S2
BYTE#
S1#
BYTE#
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
7
Note 5: Hatching indicates the state is "don't care".
Note 6: A Write occurs during S1# low, S2 high overlaps BC1# and/or BC2# low and W# low.
Note 8: Don't apply inverted phase signal externally when DQ pin is in output mode.
Note 7: When the falling edge of W# is simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of
S1# or rising edge of S2, the outputs are maintained in the high impedance state.
th (D)tsu (D)
tsu (BC1) or
tsu (BC2) trec (W)
tsu
(A)
tCW
W#
Write cycle (BC# control mode)
(Note5)(Note5)
(Note6)
(Note7)
(Note5)(Note5)
S1#
BC1#,
BC2#
(Note5)(Note5)
S2
S2
(Note5) (Note5)
tsu (S2)
ten (W)
th (D)tsu (D)
tsu (BC1) or tsu(BC2)
ten
(OE)
tdis(OE)
tw
(W)
trec (W)
tsu
(A)
tdis (W)
tCW
OE#
W#
Write cycle( W# control mode )
(Note5) (Note5)
t
su (A-WH)
S1#
(Note5) (Note5)
tsu (S1)
BC1#,
BC2#
DATA IN
STABLE
DATA IN
STABLE
A0~18
(Word Mode)
A-1~18
(Byte Mode)
A0~18
(Word Mode)
A-1~18
(Byte Mode)
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
th (D)tsu (D)
tsu (S1) trec (W)
tsu
(A)
tCW
W#
S1#
Write cycle (S1# control mode)
(Note5)
(Note5)
(Note6)
(Note7)
(Note5)
(Note5)
BC1#,
BC2#
(Note5)
(Note5)
S2
th (D)tsu (D)
tsu (S2) trec (W)
tsu
(A)
tCW
W#
S1#
Write cycle (S2 control mode)
(Note5)
(Note5)
(Note6)
(Note7)
(Note5)
(Note5)
BC1#,
BC2#
S2
8
DATA IN
STABLE
DATA IN
STABLE
A0~18
(Word Mode)
A-1~18
(Byte Mode)
A0~18
(Word Mode)
A-1~18
(Byte Mode)
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
(Note5)
(Note5)
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
9
tsu (PD)
trec (PD) ns
ms
2.2V
tsu (PD) 2.7V2.7V trec (PD)
Vcc
V
2.0
Vcc (PD)
V
I (S1#)
Icc (PD)
2.0
BC1#
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC, Vcc=2.7V~3.6V,unless otherwise noted)
Symbol Parameter Test conditions Limits
Min
Typ
Max Units
Power down supply voltage
Chip select input S1#
Power down
supply current
(2) TIMING REQUIREMENTS
Symbol Parameter Test conditions Limits Units
Power down set up time
Power down recovery time
(3) TIMING DIAGRAM note10:On the BC# control mode, the level of S1# and S2 must be fixed
at S1#, S2 > Vcc-0.2V or S2 <0.2V
VI (BC)
Byte control input
BC1# & BC2# V
BC1# , BC2# > Vcc - 0.2V
BC2#
tsu (PD) 2.7V2.7V trec (PD)
Vcc
S1#
note11:On the S1# control mode, the level of S2 must be fixed
at S2 > Vcc-0.2V or S2 <0.2V
S1# >
Vcc - 0.2V
0
5
VI (S2) 0.2
0.2V
tsu (PD) 2.7V2.7V trec (PD)
Vcc
S2
S2 control mode
µA
(1)
S1# > Vcc - 0.2V, BYTE# > Vcc - 0.2V or < 0.2V
other inputs = 0 ~ Vcc
S2 < 0.2V , BYTE# > Vcc - 0.2V or < 0.2V
(2)
other inputs = 0 ~ Vcc
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
(3)
other inputs = 0 ~ Vcc
Vcc=2.0V
2.2V
2.2V 2.2V
2.0 V
S2 < 0.2V
0.2V
Note 9: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 2.0V, and not 100% tested.
30
~ +70°C
~ +40°C
0.2
-
-
~ +25°C -0.4 3.0
6.0
-
Chip select input S2
Min
Typ
Max
BC# control mode
S1# control mode
60
~ +85°C
- -
BYTE#
>
Vcc - 0.2V or
<
0.2V
M5M5W817KT - 70HI
2002.9.3 Ver. 0.0
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
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