LT3094
1
Rev. B
For more information www.analog.com
Document Feedback
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
L
= –500mA
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0
15
30
45
60
75
90
105
120
PSRR (dB)
3094 TA01b
TYPICAL APPLICATION
FEATURES DESCRIPTION
–20V, 500mA, Ultralow
Noise, Ultrahigh PSRR
Negative Linear Regulator
The LT
®
3094 is a high performance low dropout negative
linear regulator featuring ADI’s ultralow noise and ultrahigh
PSRR architecture for powering noise sensitive applica-
tions. The device can be easily paralleled to further reduce
noise, increase output current and spread heat on a PCB.
The LT3094 supplies 500mA at a typical 235mV dropout
voltage. Operating quiescent current is nominally 2.35mA
and drops to 3µA in shutdown. The device’s wide output
voltage range (0V to –19.5V) error amplifier operates in
unity-gain and provides virtually constant output noise,
PSRR, bandwidth, and load regulation independent of
the programmed output voltage. Additional features are a
bipolar enable pin, programmable current limit, fast start-
up capability and programmable power good to indicate
output voltage regulation. The regulator incorporates a
tracking function to control an upstream supply to maintain
a constant voltage across the LT3094 to minimize power
dissipation and optimize PSRR.
The LT3094 is stable with a minimum 10µF ceramic out-
put capacitor. Built-in protection includes internal current
limit with foldback and thermal limit with hysteresis. The
LT3094 is available in thermally enhanced 12-Lead MSOP
and 3mm × 3mm DFN Packages.
APPLICATIONS
n Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)
n Ultralow Spot Noise: 2.2nV/√Hz at 10kHz
n Ultrahigh PSRR: 74dB at 1MHz
n Output Current: 500mA
n Wide Input Voltage Range: –1.8V to –20V
n Single Capacitor Improves Noise and PSRR
n 100µA SET Pin Current: ±1% Initial Accuracy
n Single Resistor Programs Output Voltage
n Programmable Current Limit
n Low Dropout Voltage: 235mV
n Output Voltage Range: 0V to –19.5V
n Programmable Power Good and Fast Start-Up
n Bipolar Precision Enable/UVLO Pin
n VIOC Pin Controls Upstream Regulator to Minimize
Power Dissipation and Optimize PSRR
n Minimum Output Capacitor: 10µF Ceramic
n 12-Lead MSOP and 3mm × 3mm DFN Packages
n RF and Precision Power Supplies
n Very Low Noise Instrumentation
n High Speed/High Precision Data Converters
n Medical Applications: Diagnostics and Imaging
n Post-Regulator for Switching Supplies All registered trademarks and trademarks are the property of their respective owners.
Power Supply Ripple Rejection
LT3094
SET GND
3094 TA01a
–
+
100µA
ILIM PGFB OUTS
OUT
4.7µF
3.3V
10µF
33.2k
200k
PIN NOT USED IN THIS CIRCUIT: VIOC
7.5k
VOUT
–3.3V
IOUT(MAX)
500mA
IN
PG
VIN
–5V
EN/UV
10µF
50k
450k
LT3094
2
Rev. B
For more information www.analog.com
TABLE OF CONTENTS
Features ............................................................................................................................ 1
Applications ....................................................................................................................... 1
Typical Application ............................................................................................................... 1
Description......................................................................................................................... 1
Absolute Maximum Ratings ..................................................................................................... 3
Pin Configuration ................................................................................................................. 3
Order Information ................................................................................................................. 4
Electrical Characteristics ........................................................................................................ 4
Typical Performance Characteristics .......................................................................................... 7
Pin Functions .....................................................................................................................15
Block Diagram ....................................................................................................................16
Applications Information .......................................................................................................17
Typical Applications .............................................................................................................29
Package Description ............................................................................................................31
Revision History .................................................................................................................33
Typical Application ..............................................................................................................34
Related Parts .....................................................................................................................34
LT3094
3
Rev. B
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
IN Pin Voltage
with Respect to GND Pin ...........................–22V, 0.3V
EN/UV Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 30V
with Respect to GND Pin ....................................±22V
PG Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 30V
with Respect to GND Pin ...........................–0.3V, 22V
PGFB Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 30V
with Respect to GND Pin ....................................±22V
ILIM Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 22V
VIOC Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 22V
with Respect to GND Pin .............................–2V, 0.3V
SET Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 22V
with Respect to GND Pin ....................................±22V
(Note 1)
TOP VIEW
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 34°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 13) IS IN, MUST BE SOLDERED TO PCB
12
11
8
9
10
4
5
3
2
1OUT
OUT
OUTS
GND
SET
VIOC
IN
IN
EN/UV
PG
PGFB
ILIM 67
13
IN
1
2
3
4
5
6
IN
IN
EN/UV
PG
PGFB
ILIM
12
11
10
9
8
7
OUT
OUT
OUTS
GND
SET
VIOC
TOP VIEW
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 33°C/W, θJC = 8°C/W
EXPOSED PAD (PIN 13) IS IN, MUST BE SOLDERED TO PCB
13
IN
SET Pin Current (Note 4) .....................................±10mA
OUTS Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 22V
with Respect to GND Pin ....................................±22V
OUTS Pin Current (Note 4) ................................... ±10mA
SET-to-OUTS Differential (Note 5) ..........................±22V
OUT Pin Voltage
with Respect to IN Pin (Note 2) .................–0.3V, 22V
with Respect to GND Pin ....................................±22V
OUT-to-OUTS Differential (Note 6) ..........................±22V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Note 3)
E-, I-Grades ....................................... –40°C to 125°C
H-Grade ............................................. –40°C to 150°C
MP-Grade (Note 17)........................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSE Package Only ............................................300°C
LT3094
4
Rev. B
For more information www.analog.com
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Range ILOAD = 500mA l–20 –2.3 V
Minimum IN Pin Voltage
(Note 8) ILOAD = 500mA, VIN UVLO Rising
VIN UVLO Hysteresis
l–2.3 –1.8
130 V
mV
SET Pin Current (ISET) VIN = –2.3V, ILOAD = 1mA, VOUT = –1.5V
–20V < VIN < –2.3V, –19.5V < VOUT <0V, 1mA < ILOAD <500mA (Note 7)
l
99
98 100
100 101
102 µA
µA
Fast Start-Up SET Pin
Current VPGFB = –286mV, VIN = –2.3V, VSET = –1.5V 1.8 mA
Output Offset Voltage
VOS (VOUT – VSET)
(Note 9)
VIN = –2.3V, ILOAD = 1mA, VOUT = –1.5V
–20V < VIN < –2.3V, –19.5V < VOUT <0V, 1mA < ILOAD <500mA (Note 7)
l
–1
–2 1
2mV
mV
Line Regulation: ∆ISET
Line Regulation: ∆ISET
Line Regulation: ∆VOS
VIN = –2.3V to –20V, ILOAD = 1mA, VOUT = –1.5V
VIN = –2.3V to –20V, ILOAD = 1mA, VOUT = –1.5V (MP-Grade)
VIN = –2.3V to –20V, ILOAD = 1mA, VOUT = –1.5V (Note 9)
l
l
l
–5
–10
–6
0.5
0.5
0.1
5
10
6
nA/V
nA/V
µV/V
Load Regulation: ∆ISET
Load Regulation: ∆VOS
ILOAD = 1mA to 500mA, VIN = –2.3V, VOUT = –1.5V
ILOAD = 1mA to 500mA, VIN = –2.3V, VOUT = –1.5V (Note 9)
l
0.1
0.03
0.5 nA
mV
Change in ISET with VSET
Change in VOS with VSET
Change in ISET with VSET
Change in VOS with VSET
VSET = –1.5V to –19.5V, VIN = –20V, ILOAD = 1mA
VSET = –1.5V to –19.5V, VIN = –20V, ILOAD = 1mA (Note 9)
VSET = 0V to –1.5V, VIN = –20V, ILOAD = 1mA
VSET = 0V to –1.5V, VIN = –20V, ILOAD = 1mA (Note 9)
l
l
l
l
100
0.02
150
0.15
850
0.5
500
2
nA
mV
nA
mV
Dropout Voltage
(Note 10) ILOAD = 1mA, 50mA
l
185 225
275 mV
mV
ILOAD = 100mA
l
185 230
280 mV
mV
ILOAD = 500mA
l
235 310
410 mV
mV
GND Pin Current
VIN = VOUT(NOMINAL)
(Note 11)
ILOAD = 10µA
ILOAD = 1mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 500mA
l
l
l
l
2.35
2.4
3.1
3.8
12
4
5.5
6.5
23
mA
mA
mA
mA
mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3094EDD#PBF LT3094EDD#TRPBF LHCC 12-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3094IDD#PBF LT3094IDD#TRPBF LHCC 12-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3094HDD#PBF LT3094HDD#TRPBF LHCC 12-Lead (3mm × 3mm) Plastic DFN –40°C to 150°C
LT3094MPDD#PBF LT3094MPDD#TRPBF LHCC 12-Lead (3mm × 3mm) Plastic DFN –55°C to 150°C
LT3094EMSE#PBF LT3094EMSE#TRPBF 3094 12-Lead Plastic MSOP –40°C to 125°C
LT3094IMSE#PBF LT3094IMSE#TRPBF 3094 12-Lead Plastic MSOP –40°C to 125°C
LT3094HMSE#PBF LT3094HMSE#TRPBF 3094 12-Lead Plastic MSOP –40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LT3094
5
Rev. B
For more information www.analog.com
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Noise Spectral
Density (Notes 9, 12) ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 0.47µF, VOUT = –3.3V
ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 4.7µF, –19.5V ≤ VOUT ≤ –1.5V
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, –19.5V ≤ VOUT ≤ –1.5V
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, –1.5V ≤ VOUT ≤ 0V
700
70
2.2
6
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Output RMS Noise
(Notes 9, 12) ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 0.47µF, VOUT = –3.3V
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, –19.5V ≤ VOUT ≤ –1.5V
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, –1.5V ≤ VOUT ≤ 0V
3
0.8
1.8
µVRMS
µVRMS
µVRMS
Reference Current RMS
Output Noise (Notes 9,
12)
BW = 10Hz to 100kHz 8 nARMS
Ripple Rejection
–18V ≤ VOUT ≤ –1.5V
VIN – VOUT = 2V (Avg)
(Notes 9, 12)
VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 4.7µF
VRIPPLE = 500mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 500mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 500mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 500mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
108
94
75
74
28
dB
dB
dB
dB
dB
Ripple Rejection
–1.5V ≤ VOUT ≤ 0V
VIN – VOUT = 2V (Avg)
(Notes 9, 12)
VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 4.7µF
VRIPPLE = 500mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 500mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 500mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 500mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
108
90
72
78
30
dB
dB
dB
dB
dB
EN/UV Pin Threshold Positive EN/UV Trip Point Rising (Turn-On), VIN = –2.3V
Negative EN/UV Trip Point Rising (Turn-On), VIN = –2.3V
l
l
1.20
–1.33
1.26
–1.26
1.35
–1.20
V
V
EN/UV Pin Hysteresis Positive EN/UV Trip Point Hysteresis, VIN = –2.3V
Negative EN/UV Trip Point Hysteresis, VIN = –2.3V
200
215
mV
mV
EN/UV Pin Current VEN/UV = 0V, VIN = –20V
VEN/UV = –1.5V, VIN = –20V
VEN/UV = –20V, VIN = –20V
VEN/UV = 1.5V, VIN = –20V
VEN/UV = 20V, VIN = 0V
l
l
l
–1
–35
–0.5
–18.5
8
25
1
45
µA
µA
µA
µA
µA
Quiescent Current in
Shutdown (VEN/UV = 0V)
VIN = –6V, VPG = Open
l
3 8
10
µA
µA
Internal Current Limit
(Note 14)
VIN = –2.3V, VOUT = 0V
VIN = –12V, VOUT = 0V
VIN = –20V, VOUT = 0V
l
l
550
40
750
425
85
160
mA
mA
mA
Programmable Current
Limit
Programming Scale Factor: –20V < VIN < –2.3V (Note 13)
VIN = –2.3V, VOUT = 0V, RILIM = 7.5kΩ
VIN = –2.3V, VOUT = 0V, RILIM = 37.5kΩ
l
l
450
90
3.75
500
105
560
120
A • kΩ
mA
mA
PGFB Trip Point PGFB Trip Point Rising l288 300 312 mV
PGFB Hysteresis PGFB Trip Point Hysteresis 7 mV
PGFB Pin Current VIN = –2.3V, VPGFB = –300mV 30 100 nA
PG Output Low Voltage IPG = 100µA l17 50 mV
PG Leakage Current VPG = 20V l1 µA
VIOC Amplifier Gain –20V ≤ VIN ≤ –2.3V, VOUT ≤ –1.5V 1 V/V
VIOC Maximum Output
Voltage Swing
VIN – VOUT = –2V, VOUT ≤ –1.5V l–1.35 –1.2 V
VIOC Sink Current VIN – VOUT = –2V, VVIOC = –1V l100 µA
VIOC Voltage for Low
Output Voltages (Note 15)
VIN = –2.3V, VOUT > –1.5V –0.8 V
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LT3094
6
Rev. B
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Parasitic diodes exist internally between the EN/UV, ILIM, PG,
PGFB, SET, GND, VIOC, OUTS and OUT pins and the IN pin. Do not drive
these pins more than 0.3V below the IN pin during a fault condition.
These pins must remain at a voltage more positive than IN during normal
operation.
Note 3: The LT3094 is tested and specified under pulse load conditions
such that TJ TA. The LT3094E is tested at TA = 25°C and performance
is guaranteed from 0°C to 125°C. Performance of the LT3094E over the
full –40°C and 125°C operating temperature range is assured by design,
characterization, and correlation with statistical process controls. The
LT3094I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3094H is 100% tested at the 150°C operating
temperature. The LT3094MP is 100% tested and guaranteed over the full
–55°C to 150°C operating temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 4: SET and OUTS pins are clamped using diodes and two 400Ω
series resistors. For less than 5ms transients, this clamp circuitry can
carry more than the rated current.
Note 5: Maximum SET and OUTS pin current requirement must be
satisfied.
Note 6: Maximum OUT-to-OUTS differential is guaranteed by design.
Note 7: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current, especially due to the
internal current limit foldback which starts to decrease current limit at
VOUT – VIN > 7V. If operating at maximum output current, limit the input
voltage range. If operating at maximum input voltage, limit the output
current range.
Note 8: The EN/UV pin threshold must be met to ensure device operation.
Note 9: OUTS ties directly to OUT.
Note 10: Dropout voltage is the minimum input-to-output differential
voltage needed to maintain regulation at a specified output current. The
dropout voltage is measured when output is 1% out of regulation. This
definition results in a higher dropout voltage compared to hard dropout—
which is measured when VIN = VOUT(NOMINAL). For output voltages
between 0V and –1.8V, dropout voltage is limited by the minimum input
voltage specification.
Note 11: GND pin current is tested with VIN = VOUT(NOMINAL) and a current
source load. Therefore, the device is tested while operating in dropout.
This is the worst-case GND pin current. GND pin current decreases at
higher input voltages. Note that GND pin current does not include SET pin
or ILIM pin current, but they are included in quiescent current.
Note 12: Adding a capacitor across the SET pin resistor decreases output
voltage noise. Adding this capacitor bypasses the SET pin resistor’s
thermal noise as well as the reference current’s noise. The output noise
then equals the error amplifier noise. Use of a SET pin bypass capacitor
also increases start-up time.
Note 13: The current limit programming scale factor is specified while the
internal backup current limit is not active. Note that the internal current
limit has foldback protection for VOUT – VIN differentials greater than 7V.
Note 14: The internal backup current limit circuitry incorporates foldback
protection that decreases current limit for VOUT – VIN > 7V. Some level of
output current is provided at all VOUT – VIN differential voltages. Consult
the Typical Performance Characteristics graph for current limit vs VIN –
VOUT.
Note 15: The VIOC amplifier outputs a voltage equal to VIN – VOUT or VIN
+ 1.5V (when VOUT is between 0V and –1.5V). See Block Diagram and
Applications Information for further information.
Note 16: For output voltages between 0V and –1.5V, the LT3094 requires
a 10µA minimum load current for stability.
Note 17: MP-Grade is only offered in the DFN package.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Load Current
(Note 16)
VOUT > –1.5V l10 µA
Thermal Shutdown TJ Rising
Hysteresis
167
8
°C
°C
Start-Up Time RSET = 49.9k, VOUT(NOM) = –5V, ILOAD = 500mA, CSET = 0.47µF, VIN = –6V, VPGFB = –6V
RSET = 49.9k, VOUT(NOM) = –5V, ILOAD = 500mA, CSET = 4.7µF, VIN = –6V, VPGFB = –6V
RSET = 49.9k, VOUT(NOM) = –5V, ILOAD = 500mA, CSET = 4.7µF, VIN = –6V, RPG1 = 50kΩ,
RPG2 = 700kΩ (with Fast Start-Up to 90% of VOUT)
55
550
10
ms
ms
ms
Thermal Regulation 10ms Pulse –0.01 %/W
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LT3094
7
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Voltage SET Pin Current Offset Voltage (VOUT – VSET)
SET Pin Current Offset Voltage (VOUT – VSET)Load Regulation
TA = 25°C, unless otherwise noted.
I
L
= –1mA
V
OUT
= –1.5V
–55°C
25°C
125°C
150°C
INPUT VOLTAGE (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
SET PIN CURRENT (µA)
3094 G05
N = 5732
V
OS
DISTRIBUTION (mV)
–2
–1
0
1
2
3094 G04
I
L
= –1mA
V
OUT
= –1.5V
–55°C
25°C
125°C
150°C
INPUT VOLTAGE (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
OFFSET VOLTAGE (mV)
3094 G06
V
IN
= –20V
I
L
= –1mA
–55°C
25°C
125°C
150°C
OUTPUT VOLTAGE (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
SET PIN CURRENT (µA)
3094 G07
V
IN
= –20V
I
L
= –1mA
–55°C
25°C
125°C
150°C
OUTPUT VOLTAGE (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OFFSET VOLTAGE (mV)
3094 G08
V
IN
= –2.3V
V
OUT
= –1.5V
∆I
L
= –1mA to –500mA
I
SET
V
OS
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–2
0
2
4
6
8
10
12
14
16
18
0
0.025
0.050
0.075
0.100
0.125
0.150
0.175
0.200
0.225
0.250
∆I
SET
(nA)
∆V
OS
(mV)
3094 G09
SET Pin Current SET Pin Current Offset Voltage (VOUT – VSET)
V
IN
= –2.3V
I
L
= –1mA
V
OUT
= –1.5V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
SET PIN CURRENT (µA)
3094 G01
N = 5732
I
SET
DISTRIBUTION (µA)
98
99
100
101
102
3094 G02
V
IN
= –2.3V
I
L
= –1mA
V
OUT
= –1.5V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OFFSET VOLTAGE (mV)
3094 G03
LT3094
8
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current Quiescent Current Quiescent Current
TA = 25°C, unless otherwise noted.
V
IN
= –2.3V
V
EN/UV
= V
IN
I
L
= –10µA
R
SET
= 15k
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
QUIESCENT CURRENT (mA)
3094 G10
V
EN/UV
= 0V
V
IN
= –2.3V
V
IN
= –20V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
50
QUIESCENT CURRENT (µA)
3094 G11
V
EN/UV
= V
IN
I
L
= –10µA
R
SET
= 15k
INPUT VOLTAGE (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
QUIESCENT CURRENT (mA)
3094 G12
Quiescent Current Typical Dropout Voltage Dropout Voltage
GND Pin Current GND Pin Current GND Pin Current
V
IN
= –5V
R
SET
= 33.2k
I
L
= –1mA
I
L
= –100mA
I
L
= –300mA
I
L
= –500mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
GND PIN CURRENT (mA)
3094 G16
V
IN
= –4.3V
R
SET
= 33.2k
–55°C
25°C
125°C
150°C
OUTPUT CURRENT (mA)
0
–100
–200
–300
–400
–500
0
2
4
6
8
10
12
14
16
GND PIN CURRENT (mA)
3094 G17
R
SET
= 33.2k
R
L
= 6.6Ω
R
L
= 11Ω
R
L
= 33Ω
R
L
= 3.3k
R
L
= 330Ω
INPUT VOLTAGE (V)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0
2
4
6
8
10
12
GND PIN CURRENT (mA)
3094 G18
V
IN
= –6V
V
EN/UV
= V
IN
I
L
= –10µA
–55°C
25°C
125°C
150°C
OUTPUT VOLTAGE (V)
0
–1
–2
–3
–4
–5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
QUIESCENT CURRENT (mA)
3094 G13
R
SET
= 33.2k
–55°C
25°C
125°C
150°C
OUTPUT CURRENT (mA)
0
–100
–200
–300
–400
–500
0
50
100
150
200
250
300
350
400
450
500
DROPOUT VOLTAGE (mV)
3094 G14
R
SET
= 33.2k
I
L
= –1mA
I
L
= –400mA
I
L
= –500mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
350
400
450
500
DROPOUT VOLTAGE (mV)
3094 G15
LT3094
9
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input Voltage
Negative EN/UV Turn-On
Threshold Positive EN/UV Turn-On Threshold
TA = 25°C, unless otherwise noted.
RISING UVLO
FALLING UVLO
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
–2.25
–2.50
INPUT UVLO THRESHOLD (V)
3094 G19
V
IN
= –2.3V
V
IN
= –20V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–1.16
–1.18
–1.20
–1.22
–1.24
–1.26
–1.28
–1.30
–1.32
–1.34
–1.36
NEGATIVE EN/UV TURN-ON THRESHOLD (V)
3094 G20
V
IN
= –2.3V
V
IN
= –20V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
POSITIVE EN/UV TURN-ON THRESHOLD (V)
3094 G21
EN/UV Pin Hysteresis EN/UV Pin Current Internal Current Limit
Internal Current Limit Internal Current Limit Programmable Current Limit
V
IN
= –2.3V
POSITIVE HYSTERESIS
NEGATIVE HYSTERESIS
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
EN/UV PIN HYSTERESIS (mV)
3094 G22
V
IN
= –5V (V
EN/UV
≥ 0V)
V
IN
= –20V (V
EN/UV
< 0V)
–55°C
25°C
125°C
150°C
EN/UV PIN VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
–20
–16
–12
–8
–4
0
4
8
12
16
20
EN/UV PIN CURRENT (µA)
3094 G23
R
ILIM
= 0Ω
V
OUT
= 0V
V
IN
= –2.3V
V
IN
= –8V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
800
900
1000
CURRENT LIMIT (mA)
3094 G24
V
IN
= –20V
R
ILIM
= 0Ω
V
OUT
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
20
40
60
80
100
120
140
160
180
200
CURRENT LIMIT (mA)
3094 G25
R
ILIM
= 0Ω
–55°C
25°C
125°C
150°C
INPUT-TO-OUTPUT DIFFERENTIAL (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0
100
200
300
400
500
600
700
800
900
1000
CURRENT LIMIT (mA)
3094 G26
R
ILIM
= 7.5k
V
OUT
= 0V
V
IN
= –2.3V
V
IN
= –8V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
800
900
1000
CURRENT LIMIT (mA)
3094 G27
LT3094
10
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Programmable Current Limit ILIM Pin Voltage ILIM Pin Current
TA = 25°C, unless otherwise noted.
R
ILIM
= 37.5k
V
OUT
= 0V
V
IN
= –2.3V
V
IN
= –8V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
20
40
60
80
100
120
140
160
180
200
CURRENT LIMIT (mA)
3094 G28
V
IN
= –2.3V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–302
–304
–306
–308
–310
–300
–290
–292
–294
–296
–298
ILIM PIN VOLTAGE (mV)
3094 G29
V
IN
= –2.3V
V
ILIM
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
30
60
90
120
150
180
210
240
270
300
ILIM PIN CURRENT (µA)
3094 G30
PGFB Rising Threshold PGFB Hysteresis PG Output Low Voltage
PG Pin Leakage Current
ISET During Start-Up with Fast
Start-Up Enabled
ISET During Start-Up with Fast
Start-Up Enabled
V
IN
= –2.3V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–290
–292
–294
–296
–298
–300
–302
–304
–306
–308
–310
PGFB RISING THRESHOLD (mV)
3094 G31
V
IN
= –2.3V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
PGFB HYSTERESIS (mV)
3094 G32
V
IN
= –2.3V
V
PGFB
= –286mV
V
SET
= –1.5V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
0.5
1.0
1.5
2.0
2.5
3.0
I
SET
(mA)
3094 G35
V
PGFB
= –286mV
V
OUT
= –1.3V
V
IN
–TO–V
SET
DIFFERENTIAL (V)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
I
SET
(mA)
3094 G36
V
IN
= –2.3V
V
PGFB
= –314mV
V
PG
= 5V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
20
40
60
80
100
120
140
160
180
200
I
PG
(nA)
3094 G34
V
IN
= –2.3V
V
PGFB
= –286mV
I
PG
= 100µA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
50
V
PG
(mV)
3094 G33
LT3094
11
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Output Overshoot Recovery
Source Current
Output Overshoot Recovery
Source Current VIOC Voltage
TA = 25°C, unless otherwise noted.
V
IN
= –5V
R
SET
= 33.2k
–55°C
25°C
125°C
150°C
V
OUT
– V
SET
(mV)
0
–5
–10
–15
–20
0
1
2
3
4
5
6
OUTPUT SOURCE CURRENT (mA)
3094 G37
V
IN
= –5V
R
SET
= 33.2k
V
OUT
– V
SET
= –20mV
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
6
OUTPUT SOURCE CURRENT (mA)
3094 G38
V
IN
= –4.3V
V
OUT
= –3.3V
I
VIOC
= –100µA
I
L
= –1mA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–0.90
–0.92
–0.94
–0.96
–0.98
–1.00
–1.02
–1.04
–1.06
–1.08
–1.10
VIOC VOLTAGE (V)
3094 G39
VIOC Voltage Maximum VIOC Voltage VIOC Source Current
Power Supply Ripple Rejection Power Supply Ripple Rejection Power Supply Ripple Rejection
V
IN
= –5V
V
OUT
= –3.3V
I
L
= –1mA
I
VIOC
= 0
I
VIOC
= –100µA
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–1.10
–1.15
–1.20
–1.25
–1.30
–1.35
–1.40
–1.45
–1.50
–1.55
–1.60
VIOC VOLTAGE (V)
3094 G41
V
IN
= –3.6V
V
OUT
= –3.3V
I
L
= –1mA
VIOC VOLTAGE (V)
0
–0.3
–0.6
–0.9
–1.2
–1.5
0
5
10
15
20
25
30
35
40
VIOC SOURCE CURRENT (µA)
3094 G42
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
I
L
= –500mA
C
SET
= 4.7µF
C
SET
= 0.47µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
3094 G43
V
IN
= –5V
R
SET
= 33.2k
C
SET
= 4.7µF
I
L
= –500mA
C
OUT
= 10µF
C
OUT
= 22µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
3094 G44
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
I
L
= –500mA
I
L
= –300mA
I
L
= –100mA
I
L
= –50mA
I
L
= –1mA
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
3094 G45
V
IN
= –4.3V
V
OUT
= –3.3V
I
L
= –1mA
–55°C
25°C
125°C
150°C
VIOC CURRENT (µA)
0
–25
–50
–75
–100
–125
–150
–175
–200
–0.90
–0.92
–0.94
–0.96
–0.98
–1.00
–1.02
–1.04
–1.06
–1.08
–1.10
VIOC VOLTAGE (V)
3094 G40
LT3094
12
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Ripple Rejection
as a Function of Error Amplifier
Input Pair Power Supply Ripple Rejection
Integrated RMS Output Noise
(10Hz to 100kHz)
TA = 25°C, unless otherwise noted.
V
IN
= V
OUT
– 2.3V
I
L
= –500mA
C
OUT
= 10µF
C
SET
= 4.7µF
V
OUT
≤ –1.5V
–0.8V > V
OUT
> –1.5V
V
OUT
≥ –0.8V
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
100
110
120
PSRR (dB)
3094 G46
I
L
= –500mA
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 0.47µF
100kHz
500kHz
1MHz
2MHz
INPUT–TO–OUTPUT DIFFERENTIAL (V)
0
–1
–2
–3
–4
–5
0
10
20
30
40
50
60
70
80
PSRR (dB)
3094 G47
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
LOAD CURRENT (mA)
0
–100
–200
–300
–400
–500
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
RMS OUTPUT NOISE (µV
RMS
)
3094 G48
Integrated RMS Output Noise
(10Hz to 100kHz)
Integrated RMS Output Noise
(10Hz to 100kHz)
Noise Spectral Density
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
I
LOAD
= –500mA
SET PIN CAPACITANCE (µF)
0.01
0.1
1
10
100
0
2
4
6
8
10
12
RMS OUTPUT NOISE (µV
RMS
)
3094 G49
V
IN
= V
OUT
– 2.3V
C
OUT
= 10µF
C
SET
= 4.7µF
I
LOAD
= –500mA
OUTPUT VOLTAGE (V)
0
–2.5
–5
–7.5
–10
–12.5
–15
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
RMS OUTPUT NOISE (µV
RMS
)
3094 G50
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
I
LOAD
= –500mA
C
SET
= 0.047µF
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
OUTPUT NOISE (nV/√
Hz
)
3094 G51
C
SET
= 0.47µF
C
SET
= 1µF
C
SET
= 4.7µF
NOISE FLOOR
C
SET
= 22µF
Noise Spectral Density
V
IN
= –5V
R
SET
= 33.2k
C
SET
= 4.7µF
I
LOAD
= –500mA
C
OUT
= 10µF
C
OUT
= 22µF
NOISE FLOOR
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
OUTPUT NOISE (nV/√
Hz
)
3094 G52
LT3094
13
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Noise Spectral Density
Noise Spectral Density as a
Function of Error Amplifier Input
Pair
Noise Spectral Density (0.1Hz to
10Hz)
TA = 25°C, unless otherwise noted.
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
I
LOAD
= –500mA
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
OUTPUT NOISE (nV/√
Hz
)
3094 G53
NOISE FLOOR
I
LOAD
= –10mA
I
LOAD
= –1mA
I
LOAD
= –100mA
I
LOAD
= –300mA
V
IN
= V
OUT
– 2.3V
C
OUT
= 10µF
C
SET
= 4.7µF
I
LOAD
= –500mA
V
OUT
≤ –1.5V
NOISE FLOOR
V
OUT
≥ –0.5V
–0.5V > V
OUT
> –1.5V
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
OUTPUT NOISE (nV/√
Hz
)
3094 G54
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
I
L
= –500mA
C
SET
= 4.7µF
C
SET
= 22µF
FREQUENCY (Hz)
0.1
1
10
10
100
1k
10k
NOISE SPECTRAL DENSITY (nV/√
Hz
)
3094 G55
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
I
LOAD
= –500mA
1ms/DIV
5µV/DIV
3094 G56
V
IN
= – 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
I
LOAD
= –500mA
1s/DIV
2µV/DIV
3094 G57
Output Noise (10Hz to 100kHz) Output Voltage Noise (0.1Hz to
10Hz)
Output Voltage Noise (0.1Hz to
10Hz) Load Transient Response
V
IN
= – 5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 22µF
I
LOAD
= –500mA
1s/DIV
2µV/DIV
3094 G58
t
r
= t
f
= 50ns
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
∆I
L
= –10mA to –500mA
5µs/DIV
OUTPUT
VOLTAGE
10mV/DIV
OUTPUT
CURRENT
500mA/DIV
3094 G59
LT3094
14
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Line Transient Response
Start-Up Time with and without
Fast Start-Up Circuitry for Large
CSET
Input Supply Ramp-Up and
Ramp-Down
TA = 25°C, unless otherwise noted.
t
r
= t
f
= 1µs
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
∆V
IN
= –4.5V to –5.5V
I
L
= –500mA
5µs/DIV
INPUT
VOLTAGE
1V/DIV
OUTPUT
VOLTAGE
1mV/DIV
3094 G60
INPUT VOLTAGE
V
IN
= 0 TO –5V
V
EN/UV
= V
IN
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
R
L
= 6.6Ω
OUTPUT VOLTAGE
50ms/DIV
1V/DIV
3094 G62
PULSE EN/UV
2V/DIV
OUTPUT WITH
FAST START–UP
(SET TO 90%)
500mV/DIV
OUTPUT WITHOUT
FAST START–UP
V
IN
= –5V
R
SET
= 33.2k
C
OUT
= 10µF
C
SET
= 4.7µF
R
L
= 6.6Ω
100ms/DIV
3094 G61
LT3094
15
Rev. B
For more information www.analog.com
PIN FUNCTIONS
IN (Pins 1, 2, Exposed Pad Pin 13): Input. These pins
supply power to the regulator. The LT3094 requires a
bypass capacitor at the IN pin. In general, a battery’s out-
put impedance rises with frequency, so include a bypass
capacitor in battery-powered applications. While a 10µF
input bypass capacitor generally suffices, applications with
large load transients may require higher input capacitance
to prevent input supply droop. Consult the Applications
Information section on the proper use of an input capacitor
and its effect on circuit performance.
EN/UV (Pin 3): Enable/UVLO. Pulling the LT3094’s EN/UV
pin low places the part in shutdown. Quiescent current
in shutdown drops to 3µA and the output voltage turns
off. Alternatively, the EN/UV pin can set an input supply
undervoltage lockout (UVLO) threshold using a resistor
divider between IN, EN/UV and GND. The EN/UV pin is
bidirectional and can be switched with either a positive
or negative voltage. The LT3094 typically turns on when
the EN/UV voltage exceeds 1.26V above ground (with
a 200mV hysteresis on its falling edge) or 1.26V below
ground (with a 215mV hysteresis). If unused, tie EN/UV
to IN. Do not float the EN/UV pin.
PG (Pin 4): Power Good. PG is an open-collector flag that
indicates output voltage regulation. PG pulls low if PGFB
is between OV and –300mV. If the power good functional-
ity is not needed, float the PG pin. The PG flag status is
valid even if the LT3094 is in shutdown, with the PG pin
being pulled low.
PGFB (Pin 5): Power Good Feedback. The PG pin pulls
high if PGFB is below –300mV on its rising edge, with
7mV hysteresis on its falling edge. Connecting an external
resistor divider between OUT, PGFB, and GND sets the
programmable power good threshold with the following
transfer function: –0.3V • (1 + RPG1/RPG2) – IPGFB • RPG1.
As discussed in the Applications Information section, PGFB
also activates the fast start-up circuitry. If power good and
fast start-up functionality are not needed, tie PGFB to IN.
ILIM (Pin 6): Current Limit Programming Pin. Connecting a
resistor between ILIM and GND programs the current limit.
For best accuracy, Kelvin connect this resistor directly to
the LT3094’s GND pin. The programming scale factor is
nominally 3.75A • kΩ. If the programmable current limit
functionality is not needed, tie ILIM to GND. Do not float
the ILIM pin.
VIOC (Pin 7): Voltage for Input-to-Output Control. The
LT3094 incorporates a tracking feature to control a circuit
supplying power to the LT3094 to maintain the differential
voltage across the LT3094. This function maximizes ef-
ficiency and PSRR performance while minimizing power
dissipation. See the Applications Information section for
further information. If unused, float the VIOC pin.
SET (Pin 8): Set. This pin is the inverting input of the error
amplifier and the regulation setpoint for the LT3094. The
SET pin sinks a precision 100µA current that flows through
an external resistor connected between SET and GND. The
LT3094’s output voltage is determined by VSET = ISET •
RSET. Output voltage range is from zero to –19.5V. Adding
a capacitor from SET to GND improves noise, PSRR, and
transient response at the expense of increased start-up
time unless the fast start-up capability is used via the
PGFB pin. For optimum load regulation, Kelvin connect
the ground side of the SET pin directly to the load.
GND (Pin 9): Ground.
OUTS (Pin 10): Output Sense. This pin is the noninvert-
ing input to the error amplifier. For optimal transient
performance and load regulation, Kelvin connect OUTS
directly to the output capacitor and the load. Also, tie the
GND connections of the output capacitor and the SET pin
capacitor directly together. Exercise care with regards to
placement of input capacitors relative to output capaci-
tors due to potential PSRR degradation from magnetic
coupling effects; see the Applications Information section
for further information on capacitor placement and board
layout. A parasitic substrate diode exists between OUTS
and IN pins of the LT3094; do not drive OUTS more than
0.3V below IN during normal operation or a fault condition.
OUT (Pins 11, 12): Output. This pin supplies power to the
load. For stability, use a minimum 10µF output capacitor
with an ESR below 30mΩ and an ESL below 1.5nH. Large
load transients require larger output capacitance to limit
peak voltage transients. Refer to the Applications Informa-
tion section for more information on output capacitance. A
parasitic substrate diode exists between OUT and IN pins
of the LT3094; do not drive OUT more than 0.3V below
IN during normal operation or during a fault condition.
LT3094
16
Rev. B
For more information www.analog.com
BLOCK DIAGRAM
GND
EN/UV
BIDIRECTIONAL
ENABLE
COMPARATOR
INPUT-TO-OUTPUT
CONTROL
FAST
START-UP
IDEAL
DIODE
PROGRAMMABLE
POWER GOOD
ERROR
AMPLIFIER
–300mV
3090 BD
–1.26V
1.26V
–
+
–
+
BIAS
PGFB
PG
–300mV
–
+
FAST START-UP
DISABLE LOGIC
INPUT UVLO
CURRENT LIMIT
THERMAL SHUTDOWN
DROPOUT
CURRENT
REFERENCE
1.8mA 100µA
VIOC SET OUTS ILIM
–1.5V
IN
+
–
–
–
+
SET-TO-OUTS
PROTECTION
CLAMP
THERMAL
SHUTDOWN
INPUT
UVLO
INTERNAL
CURRENT LIMIT
PROGRAMMABLE
CURRENT LIMIT
90mV
–
+
–
+
–
+
DRIVER
1.5K
0.12Ω
OUT 11, 12
IN 1, 2, 13
VIN
CIN
RPG
V+
RPG2
RPG1
RILIM
VOUT
RSET
CSET
RL
COUT
5
4
3
9 7 8 610
AV = 1
LT3094
17
Rev. B
For more information www.analog.com
The LT3094 is a high performance low dropout negative
linear regulator featuring ADI’s ultralow noise (2.2nV/√Hz
at 10kHz) and ultrahigh PSRR (74dB at 1MHz) architecture
for powering noise sensitive applications. Designed as a
precision current reference followed by a high performance
rail-to-rail voltage buffer, the LT3094 can be easily paral-
leled to further reduce noise, increase output current and
spread heat on the PCB. The device additionally features
programmable current limit, fast start-up capability and
programmable power good.
The LT3094 is easy to use and incorporates all of the
protection features expected in high performance regula-
tors. Included are short-circuit protection, safe operating
area protection, and thermal shutdown with hysteresis.
Output Voltage
The LT3094 incorporates a precision 100µA current
reference flowing into the SET pin, which also ties to the
error amplifier’s inverting input. Figure1 illustrates that
connecting a resistor from SET to ground generates a
reference voltage for the error amplifier. This reference
voltage is simply the product of the SET pin current
and the SET pin resistor. The error amplifier’s unity-gain
configuration produces a low impedance version of this
voltage on its noninverting input, i.e. the OUTS pin, which
is externally tied to the OUT pin. The LT3094's output
voltage is determined by VSET = ISET • RSET.
APPLICATIONS INFORMATION
The LT3094’s rail-to-rail error amplifier and current refer-
ence architecture allows for a wide output voltage range
from 0V (using a 0Ω resistor) to VIN minus dropout. An
NPN-based input pair is active for a 0V to –0.8V output
and a PNP-based input pair is active for output voltages
beyond –1.5V, with a smooth transition between the two
input pairs from –0.8V to –1.5V output. The PNP-based
input pair offers the best overall performance; refer to the
Electrical Characteristics table for details on offset voltage,
SET pin current, output noise and PSRR variation depend-
ing on the output voltage and corresponding active input
pair(s). Table1 lists common output voltages and their
corresponding 1% RSET resistors.
Table1. 1% Resistor for Common Output Voltages
VOUT (V) RSET (kΩ)
–2.5 24.9
–3.3 33.2
–5 49.9
–12 121
–15 150
The benefit of using a current reference compared with a
voltage reference as used in conventional regulators is that
the regulator always operates in a unity-gain configura-
tion, independent of the programmed output voltage. This
allows the LT3094 to have loop gain, frequency response
and bandwidth independent of the output voltage. As a
result, noise, PSRR and transient performance do not
change with output voltage. Moreover, since error ampli-
fier gain is not needed to amplify the SET pin voltage to
a higher output voltage, output load regulation is more
tightly specified in the hundreds of microvolts range and
not as a fixed percentage of the output voltage.
Since the zero TC current reference is highly accurate,
the SET pin resistor can become the limiting factor in
achieving high accuracy. Hence, it should be a precision
resistor. Additionally, any leakage paths to or from the
SET pin create errors in the output voltage. If necessary,
use high quality insulation (e.g. Teflon, Kel-F); moreover,
cleaning of all insulating surfaces to remove fluxes and
other residues may be required. High humidity environ-
ments may require a surface coating at the SET pin to
provide a moisture barrier.
LT3094
SET GND
3094 F01
–
+
100µA
ILIM OUTS
OUT
4.7µF RSET
33.2k
PINS NOT USED IN THIS CIRCUIT: PG, VIOC
VOUT
–3.3V
IOUT(MAX)
500mA
IN
PGFB
VIN
–5V
EN/UV
10µF
Figure1. Basic Adjustable Regulator
LT3094
18
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Minimize board leakage by encircling the SET pin with a
guard ring operated at a similar potential—ideally tied to
the OUT pin. Guarding both sides of the circuit board is
recommended. Bulk leakage reduction depends on the
guard ring width. Leakage of 100nA into or out of the SET
pin creates a 0.1% error in the reference voltage. Leakages
of this magnitude, coupled with other sources of leakage,
can cause significant errors in the output voltage, especially
over wide operating temperature range. Figure2 illustrates
a typical guard ring layout technique.
to avoid adding extra impedance (ESR and ESL) outside
the feedback loop. To that end, minimize the effects of
PCB trace and solder inductance by tying the OUTS pin
directly to COUT and the GND side of CSET directly to the
GND side of COUT, as well as keep the GND sides of CIN
and COUT reasonably close, as shown in Figure3. Refer
to the LT3094 demo board manual for more information
on the recommended layout that meets these require-
ments. While the LT3094 is robust and will not oscillate
if the recommended layout is not followed, depending
on the actual layout, phase/gain margin, noise and PSRR
performance may degrade.
Figure2. DFN Guard Ring Layout
Figure3. COUT and CSET Connections for Best Performance
3094 F02
13
OUT
SET
12
11
8
9
10
4
5
3
2
1
7
6
Since the SET pin is a high impedance node, unwanted
signals may couple into the SET pin and cause erratic
behavior. This is most noticeable when operating with a
minimum output capacitor at heavy load currents. By-
passing the SET pin with a small capacitance to ground
resolves this issue—10nF is sufficient.
For applications requiring higher accuracy or an adjust-
able output voltage, the SET pin may be actively driven
by an external voltage source capable of sourcing 100µA.
Connecting a precision voltage reference to the SET pin
eliminates any errors present in the output voltage due
to the reference current and SET pin resistor tolerances.
Output Sensing and Stability
The LT3094’s OUTS pin provides a Kelvin sense connection
to the output. The SET pin resistor’s GND side provides a
Kelvin sense connection to the load’s GND side.
Additionally, for ultrahigh PSRR, the LT3094 bandwidth
is made quite high (~1MHz), making it very close to a
typical 10µF (1206 case size) ceramic output capacitor’s
self-resonance frequency (~1.6MHz). It is very important
Stability and Output Capacitance
The LT3094 requires an output capacitor for stability. Given
its high bandwidth, ADI recommends low ESR and ESL
ceramic capacitors. A minimum 10µF output capacitance
with an ESR below 30mΩ and an ESL below 1.5nH is
required for stability.
Given the high PSRR and low noise performance attained
with using a single 10µF ceramic output capacitor, larger
values of output capacitor only marginally improve the
performance because the regulator bandwidth decreases
with increasing output capacitance—hence, there is little to
be gained by using larger than the minimum 10µF output
capacitor. Nonetheless, larger values of output capacitance
do decrease peak output deviations during a load transient.
LT3094
SET GND
3094 F03
–
+
100µA
ILIM OUTS
OUT
CSET RSET
PINS NOT USED IN THIS CIRCUIT: PG, VIOC
VOUT
IOUT(MAX)
500mA
DEMO BOARD
PCB LAYOUT
ILLUSTRATES
4-TERMINAL
CONNECTION
TO COUT
COUT
IN
PGFB
VIN
CIN
EN/UV
LT3094
19
Rev. B
For more information www.analog.com
Note that bypass capacitors used to decouple individual
components powered by the LT3094 increase the effective
output capacitance.
Give extra consideration to the type of ceramic capacitors
used. They are manufactured with a variety of dielectrics,
each with different behavior across temperature and applied
voltage. The most common dielectrics used are specified
with EIA temperature characteristic codes of Z5U, Y5V,
X5R and X7R. The Z5U and Y5V dielectrics are good for
providing high capacitance in small packages, but they
tend to have stronger voltage and temperature coefficients
as shown in Figure4 and Figure5. When used with a 5V
regulator, a 16V 10µF Y5V capacitor can exhibit an effective
value as low as 1µF to 2µF for the DC bias voltage applied
over the operating temperature range.
The X5R and X7R dielectrics result in more stable char-
acteristics and are thus more suitable for use with the
LT3094. The X7R dielectric has better stability across
temperature, while the X5R is less expensive and is available
in higher values. Nonetheless, care must still be exercised
when using X5R and X7R capacitors. The X5R and X7R
codes only specify operating temperature range and the
maximum capacitance change over temperature. While
capacitance change due to DC bias for X5R and X7R is
better than Y5V and Z5U dielectrics, it can still be signifi-
cant enough to drop capacitance below sufficient levels.
As shown in Figure6, capacitor DC bias characteristics
tend to improve as component case size increases, but
verification of expected capacitance at the operating
voltage is highly recommended. Due to its good voltage
coefficient in small case sizes, ADI recommends using
Murata’s GJ8 series ceramic capacitor.
High Vibration Environments
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress upon
it, similar to how a piezoelectric microphone works. For a
ceramic capacitor, this stress can be induced by mechanical
vibrations within the system or due to thermal transients.
LT3094 applications in high vibration environments have
three distinct piezoelectric noise generators: ceramic
APPLICATIONS INFORMATION
Figure4. Ceramic Capacitor DC Bias Characteristics
Figure5. Ceramic Capacitor Temperature Characteristics
Figure6. Capacitor Voltage Coefficient for Different
Case Sizes
DC BIAS VOLTAGE (V)
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
–100
CHANGE IN VALUE (%)
–80
642 810 12
3094 F04
14
0
20
–60
–40
X5R
Y5V
–20
16
TEMPERATURE (°C)
–50
–100
CHANGE IN VALUE (%)
–80
250–25 50 75 100
3094 F05
0
20
40
–60
–40 Y5V
–20
125
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
X5R
DC BIAS (V)
0
–100
CHANGE IN VALUE (%)
–80
–60
–40
–20
0
20
5 10 15 20
3094 F06
25
GRM SERIES, 0805, 1.45mm THICK
GRM SERIES, 1206, 1.8mm THICK
GRM SERIES, 1210, 2.2mm THICK
GJ8 SERIES, 1206, 1.9mm THICK
MURATA: 25V,10%,
X7R/X5R, 10µF CERAMIC
LT3094
20
Rev. B
For more information www.analog.com
output, input, and SET pin capacitors. However, due to the
LT3094’s very low output impedance over a wide frequency
range, negligible output noise is generated using a ceramic
output capacitor. Similarly, due to the LT3094’s ultrahigh
PSRR, negligible output noise is generated using a ceramic
input capacitor. Given the high SET pin impedance, any
piezoelectric response from a ceramic SET pin capacitor
generates significant output noise; peak-to-peak excur-
sions of hundreds of µVs are possible. However, due to
the SET pin capacitor’s high ESR and ESL tolerance, any
non-piezoelectrically responsive (tantalum, electrolytic,
or film) capacitor can be used at the SET pin; do note
that electrolytic capacitors tend to have high 1/f noise.
In any case, use of surface mount capacitors is highly
recommended.
Stability and Input Capacitance
The LT3094 is stable with a minimum 10µF IN pin capacitor.
ADI recommends using low ESR ceramic capacitors. Ap-
plications using long wires to connect the power supply to
the LT3094’s input and ground terminals together with low
ESR ceramic input capacitors are prone to voltage spikes,
reliability concerns and application-specific board oscil-
lations. The wire inductance combined with the low ESR
ceramic input capacitor forms a high Q resonant LC tank
circuit. In some instances, this resonant frequency beats
against the output current LDO bandwidth and interferes
with stable operation. The resonant LC tank circuit formed
by the wire inductance and input capacitor is the cause
and not because of LT3094’s instability.
The self inductance, or isolated inductance, of a wire is di-
rectly proportional to its length. The wire diameter, however,
has less influence on its self inductance. For example, the
self inductance of a 2-AWG isolated wire with a diameter
of 0.26” is about half the inductance of a 30-AWG wire
with a diameter of 0.01”. One foot of 30-AWG wire has
465nH of self inductance.
Several methods exist to reduce a wire’s self inductance.
One method divides the current flowing towards the LT3094
between two parallel conductors. In this case, placing wire
further apart reduces the inductance; up to a 50% reduc-
tion when placed only a few inches apart. Splitting the
wires connects two equal inductors in parallel. However,
when placed in close proximity to each other, their mu-
tual inductance adds to the overall self inductance of the
wires—therefore a 50% reduction is not possible in such
cases. The second and more effective technique to reduce
the overall inductance is to place the forward and return
current conductors (the input and ground wires) in close
proximity. Two 30-AWG wires separated by 0.02” reduce
the overall inductance to about one-fifth of a single wire.
If a battery mounted in close proximity powers the LT3094,
a 10µF input capacitor suffices for stability. If a distantly
located supply powers the LT3094, use a larger value
input capacitor. Use a rough guideline of 1µF (in addition
to the 10µF minimum) per 6” of wire length. The minimum
input capacitance needed to stabilize the application also
varies with the output capacitance as well as the load
current. Placing additional capacitance on the LT3094’s
output helps. However, this requires significantly more
capacitance compared to additional input bypassing. Series
resistance between the supply and the LT3094 input also
helps stabilize the application; as little as 0.1Ω to 0.5Ω
suffices. This impedance dampens the LC tank circuit at
the expense of dropout voltage. A better alternative is to
use a higher ESR tantalum or electrolytic capacitor at the
LT3094 input in parallel with a 10µF ceramic capacitor.
PSRR and Input Capacitance
For applications utilizing the LT3094 for post-regulating
switching converters, placing a capacitor directly at the
LT3094 input results in AC current (at the switching
frequency) to flow near the LT3094. This relatively high
frequency switching current generates magnetic fields
that couple to the LT3094 output, degrading the effective
PSRR. While highly dependent on the PCB layout, the
switching preregulator, the size of the input capacitor and
other factors, the PSRR degradation can easily be over
30dB at 1MHz. This degradation is present even with the
LT3094 desoldered from the board, it is a degradation in
the PSRR of the PCB itself. While negligible for conventional
low PSRR LDOs, the LT3094’s ultrahigh PSRR requires
careful attention to higher order parasitics in order to realize
the full performance offered by the regulator.
To mitigate the flow of high frequency switching cur-
rent near the LT3094, the input capacitor can be entirely
removed as long as the switching converter’s output
capacitor is located more than an inch away from the
APPLICATIONS INFORMATION
LT3094
21
Rev. B
For more information www.analog.com
LT3094. Magnetic coupling decreases rapidly with increas-
ing distance. If the switching regulator is placed too far
away (conservatively more than a couple inches) from
the LT3094, the lack of an input capacitor presents a high
impedance at the input of the LT3094 and oscillation may
occur. It is generally a common (and preferred) practice
to bypass regulator inputs with some capacitance, so
this option is fairly limited in its scope and not the most
palatable solution.
To that end, ADI recommends referencing the LT3094
demo board layout for achieving the best possible PSRR
performance. Two main factors contribute to higher PSRR
with a poor layout. Parasitic trace inductance coupled
with the low ESR ceramic input capacitor can lead to
higher ripple at the input of the LDO than at the output of
the driving supply. Also, physical loops create magnetic
fields that couple from the input to the output. The LT3094
demo board utilizes layout techniques to minimize both
parasitic inductance in traces and coupling of magnetic
loops, preventing PSRR degradation while keeping the
input capacitor.
Filtering High Frequency Spikes
For applications where the LT3094 is used to post-regulate
a switching converter, its high PSRR effectively sup-
presses any harmonic content present at the switching
frequency (typically 100kHz to 4MHz). However, there are
very high frequency (hundreds of MHz) spikes associated
with the switcher’s power switch transition times that are
beyond the LT3094’s bandwidth and will almost directly
pass through to the output. While the output capacitor is
partly intended to absorb these spikes, its ESL will limit
its ability at these frequencies. A ferrite bead or even the
inductance associated with a short (e.g. 0.5”) PCB trace
coupled with a capacitor with a low impedance at the
transition frequency can serve as an LC-filter to suppress
these very high frequency spikes.
Output Noise
The LT3094 offers many advantages with respect to noise
performance. Traditional linear regulators have several
sources of noise. The most critical noise sources for a
traditional regulator are its voltage reference, error amplifier,
noise from the resistor divider network used for setting
output voltage and the noise gain created by this resistor
divider. Many low noise regulators pin out their voltage
reference to allow for noise reduction by bypassing the
reference voltage.
Unlike most linear regulators, the LT3094 does not use a
voltage reference; instead it uses a 100µA current refer-
ence. The current reference operates with typical noise
current level of 27pA/√Hz (8nARMS over the 10Hz to
100kHz bandwidth). The resultant voltage noise equals
the current noise multiplied by the resistor values, which
is then RMS summed with the error amplifier’s noise and
the resistor’s Johnson noise of √4kTR (k = Boltzmann’s
constant, 1.38 • 10–23 J/K, and T is absolute temperature)
to give the net output noise.
One problem faced by conventional linear regulators is
that the resistor divider setting the output voltage gains up
the reference noise. In contrast, the LT3094’s unity-gain
follower architecture presents no gain from the SET pin to
the output. Therefore, using a capacitor to bypass the SET
pin resistor allows output voltage noise to be independent
of the programmed output voltage. The resultant output
noise is then determined only by the error amplifier’s noise,
typically 2nV/√Hz from 1kHz to 1MHz and 0.8µVRMS in
the 10Hz to 100kHz bandwidth when using a 4.7µF SET
pin capacitor. Paralleling multiple LT3094s further reduces
noise by √N for N parallel regulators.
Refer to the Typical Performance Characteristics sec-
tion for noise spectral density and RMS integrated noise
performance over various load currents and SET pin
capacitances.
SET Pin (Bypass) Capacitance: Noise, PSRR,
Transient Response and Soft-Start
In addition to reducing output noise, using a SET pin bypass
capacitor also improves PSRR and transient performance.
Note that any bypass capacitor leakage deteriorates the
LT3094’s DC regulation. Capacitor leakage of as little as
100nA causes a 0.1% DC error. ADI recommends the use
of a good quality low leakage ceramic capacitor.
Using a SET pin bypass capacitor also soft starts the output
and limits inrush current. The RC time constant formed by
the SET pin resistor and capacitor determines soft-start
APPLICATIONS INFORMATION
LT3094
22
Rev. B
For more information www.analog.com
time. Without the use of fast start-up, the ramp-up rate
from 0 to 90% of nominal VOUT is:
tSS ≈ 2.3 • RSET • CSET (Fast Start-Up Disabled)
Fast Start-Up
For ultralow noise applications that require low 1/f noise
(i.e. at frequencies below 100Hz) a larger value SET pin
capacitor is required; up to 22µF may be used. While
normally this would significantly increase the regulator’s
start-up time, the LT3094 incorporates fast start-up cir-
cuitry that increases the SET pin current to about 1.8mA
during start-up.
As shown in the Block Diagram, the 1.8mA current source
remains engaged while PGFB is less than –300mV unless
the regulator is in current limit, dropout, thermal shutdown,
or input voltage is below the minimum VIN.
If fast start-up capability is not used, tie PGFB to IN or to
OUT (for output voltages more than –300mV). Note that
doing so also disables power good functionality.
ENABLE/UVLO
The EN/UV pin is used to put the regulator into a mi-
cropower shutdown state. The LT3094 has an accurate
–1.26V turn-on threshold on the EN/UV pin with 215mV
of hysteresis. This threshold can be used in conjunction
with a resistor divider from the input supply to define an
accurate undervoltage lockout (UVLO) threshold for the
regulator. The EN/UV pin current (IEN) at the threshold
needs to be considered when calculating the resistor di-
vider network. See the Electrical Characteristics table and
Typical Performance curves for EN/UV pin characteristics.
The EN/UV pin current can be ignored if REN1 is less than
100k. Use the following formula to determine resistor
divider values (See Programming Undervoltage Lockout
in the Typical Applications section):
VIN(UVLO) = –1.26V • (1 + REN2 / REN1) – IEN • REN2
Since the EN/UV pin is bidirectional, it can also be pulled
above 1.26V to turn on the LT3094. In bipolar supply
applications, the positive EN/UV threshold can be used
to sequence the turn-on of the LT3094 after the positive
regulator has turned on. If unused, tie the EN/UV pin to IN.
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
The VIOC pin is used to control an upstream switching
converter and facilitate a design solution that maximizes
system efficiency while providing good transient response,
low noise, and high power supply ripple rejection (PSRR)
by maintaining a constant voltage across the LT3094
regardless of the device’s output voltage. This works
well in applications where the output voltage is varied for
the application requirements. This regulation loop also
minimizes total power dissipation in fault conditions; if the
output is short-circuited and the LT3094 current limits,
the VIOC amplifier lowers the switching regulator output
voltage and limits the power dissipation in the LT3094.
The VIOC pin is the output of a fast unity-gain amplifier that
measures the voltage differential between IN and OUTS
or –1.5V, whichever is lower. It typically connects to the
feedback node or into the resistor divider of most LTC
®
switching regulators or LTM
®
power modules and sinks
at least 100µA of current. Targeting –1V differential from
input-to-output provides an optimum tradeoff in terms
of power dissipation and PSRR. If paralleling multiple
LT3094’s, tie the VIOC pin of one of the devices to the
upstream switching converter’s feedback pin and float the
remaining VIOC pins.
The VIOC amplifier is designed to sink current, and only
sources current through its internal impedance to ground.
The VIOC pin has a typical impedance to ground of 40k
±15%, this is important to consider if using a maximum
input voltage configuration or if the LT3094 is disabled.
As the VIOC buffer operates with high bandwidth, the
switching converter’s frequency compensation doesn’t
need to be adjusted while the VIOC buffer is inside the
switching converter’s feedback loop. Phase delay through
the VIOC buffer is typically less than 4° for frequencies
as high as 100kHz; within the switching converter’s
bandwidth (usually well below 100kHz) the VIOC buffer is
transparent and acts like an ideal wire. For example, with
a switching converter with less than 100kHz bandwidth
and a phase margin of 50°, using the VIOC buffer will
degrade the phase margin by at most 4°. The net phase
margin for the switching converter (using the VIOC pin)
APPLICATIONS INFORMATION
LT3094
23
Rev. B
For more information www.analog.com
Figure8. VIOC Connection Using LT8330 Delivers –4.3V
When Operating, –5V When LT3094 is Disabled
3094 F08
38.3k
9.53k
VIN
SW
FBX
LT8330
IN
VIOC
LT3094
•
•
86.6k
on the VIOC pin) when the LT3094 is operating at –3.3V
output and is –5V when the LT3094 is disabled.
is at least 46°. With the VIOC buffer inside the switching
converter’s feedback loop, keep the total capacitance on
the VIOC pin to below 20pF.
For 0 ≥ VOUT ≥ –1.5V, VIN = VVIOC(NOM) – 1.5V. For VOUT
≤ –1.5V, VIN = VOUT + VVIOC(NOM). The VIOC pin voltage
(and the input-to-output differential) is programmable
to anywhere between –0.41V (the dropout voltage of the
regulator) and –1.3V. As shown in Figure7, the input-
to-output differential is easily programmed using the
following equation:
V
LDOIN – VLDOOUT =VVIOC(NOM) =VFBSWITCHER •R1+R2
R1
In the event that the SET pin has an open-circuit fault
condition, the LT3094’s input voltage will increase to the
switching converter’s maximum output voltage and may
violate the LT3094’s absolute maximum rating for VIN.
To prevent this, adding an optional resistor (R3) between
the VIOC and IN pins of the regulator gives a maximum
voltage configuration based on the following equation:
VLDOIN(MAX) =VFBSWITCHER
R1+R2 +R3
R1
+VVIOC(NOM)
R3
40k
Typical VIOC Applications
Figure8 shows an application using the LT8330 configured
as an inverting regulator powering the LT3094 to deliver
a –3.3V output. The resistors shown drive the FBX pin of
the LT8330 to –0.8V so that its output is –4.3V (with –1V
Figure9. VIOC Connection Using LT8580
APPLICATIONS INFORMATION
3094 F09
36.5k
12.1k
VIN
SW
FBX
LT8580
IN
VIOC
LT3094
•
•
Figure7. Typical VIOC Application
Another inverting regulator configuration is shown in
Figure9, this time using the LT8580. The LT8580 FBX pin
regulates at 3mV (typical) with 83.3µA flowing out of the
pin (IFBX). Because of this, only a single resistor is needed
between the FBX pin and VIOC (from Figure 7, only R2 is
OUT
LT3094
–1.5V
3094 F07
– – +
OUTS
IN
PGFB
VIOC
EN/UV
GND
40k
SET
VLDOOUT: VARIABLE
IOUT(MAX): 500mA
VLDOIN
VFBSWITCHER
VIN
FB
UPSTREAM
SWITCHING
CONVERTER
SWIN
10µF
AV = 1
R3
(OPTIONAL)
4.7µF
R2
R1
LT3094
24
Rev. B
For more information www.analog.com
necessary, R1 is not needed). In this case, the resistor is
calculated as follows:
VLDOIN – VLDOOUT = VVIOC(NOM) = VFBX – R2 • IFBX
For the optional maximum voltage configuration, R3 is
added and the maximum input voltage to the LT3094 is
calculated as follows:
VLDOIN(MAX) =VVIOC(NOM) +VVIOC(NOM)
R3
40k
– R3 • IFBX
Again, the resistors shown are configured to drive the out-
put of the switcher to –4.3V when the LT3094 is operating
at –3.3V output and –5V when disabled. Using the circuit
from Figure9, the LDO’s input and output is shown in
Figure10 when pulsing the LT3094’s EN/UV pin. As can
be seen, when the LDO is disabled, the LDO input voltage
goes to the maximum voltage set by the resistor divider
on the VIOC pin. Figure10 shows the load step response
of the LT8580 using the VIOC buffer. Figure12 shows the
LDO’s input and output voltage response to stepping the
SET pin voltage from –3V to –4V. Figure13 shows the
LDO’s input and output voltage while ramping the SET
pin from 0V to –4.5V, and as can be seen, the LT8580’s
output voltage tracks the LT3094’s output voltage when
below –1.5V and limits at the maximum voltage set by the
resistor divider set on the VIOC pin. Last, Figure14 shows
the noise spectral density at the LT3094’s input and output.
APPLICATIONS INFORMATION
I
L
= –500mA
V
LDOIN
V
SET
AND V
LDOOUT
ARE OVERLAID
5ms/DIV
1V/DIV
0V
3094 F13
V
LDOIN
= –4.3V
V
LDOOUT
= –3.3V
I
L
= –500mA
LDOOUT
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.001
0.01
0.1
1
10
100
NOISE (µV/√
Hz
)
3094 F14
LDOIN
NOISE FLOOR
Figure10. LT3094 EN/UV Pulse
Figure11. Load Step Response Using the VIOC Buffer
Figure12. Stepping VSET from –3V to –4V (and Back to –3V)
Figure13. Ramping VSET from 0V to –4.5V (and Back to 0V)
Figure14. LT3094’s Input and Output Noise Spectral Density
V
SET
= –3V TO –4V
I
L
= –500mA
V
LDOIN
V
SET
AND V
LDOOUT
ARE OVERLAID
500µs/DIV
0V
1V/DIV
3094 F12
R
SET
= 33.2k
R
L
= 6.6Ω
V
EN/UV
V
LDOIN
V
LDOOUT
500ms/DIV
0V
2V/DIV
0V
2V/DIV
3094 F10
R
SET
= 33.2k
I
L
= –10mA TO –500mA
I
LOAD
V
LDOIN
V
LDOOUT
200µs/DIV
0mA
500mA/DIV
200mV/DIV
50mV/DIV
3094 F11
LT3094
25
Rev. B
For more information www.analog.com
Programmable Power Good
As illustrated in the Block Diagram, power good thresh-
old is user programmable using the ratio of two external
resistors, RPG1 and RPG2:
VOUT(PG_THRESH) = –0.3V(1 + RPG1/RPG2) – IPGFB • RPG1
If the PGFB pin becomes less than –300mV, the open-
collector PG pin deasserts and becomes high impedance.
The power good comparator has 7mV hysteresis and 5µs
of deglitching. The PGFB pin current (IPGFB) can be ignored
if RPG2 is less than 30k, otherwise it must be considered
when determining the resistor divider network. If power
good functionality is not used, float the PG pin. Please
note that programmable power good and fast start-up
capabilities are disabled for output voltages between OV
and –300mV.
Take care when laying out traces for PG and PGFB on a
PCB. If the PG and PGFB pins are run close to each other
for a distance (typically greater than two inches), stray
capacitance from trace-to-trace couples the PG signal into
the high impedance PGFB signal. Since PG is out of phase
relative to PGFB, this results in oscillation. To avoid this,
minimize the distance the two traces run close to each
other; lowering the impedance seen at the PGFB pin by
using lower value resistors for the PGFB divider also helps.
Externally Programmable Current Limit
The ILIM pin internally regulates to –300mV. Connecting a
resistor from ground to ILIM sets the current flowing into
the ILIM pin, which in turn programs the LT3094’s current
limit. With the 3.75kΩ • A programming scale factor, the
current limit can be calculated as follows:
Current Limit = 3.75kΩ • A / RILIM
For example, a 7.5k resistor programs the current limit to
500mA and a 15k resistor programs the current limit to
250mA. For good accuracy, Kelvin connect this resistor
to the LT3094’s GND pin.
In cases where IN-to-OUT differential is greater than 7V,
the LT3094’s foldback circuitry decreases the internal
current limit. As a result, the internal current limit may
override the externally programmed current limit to keep
the LT3094 within its safe-operating-area (SOA). See the
graph of Internal Current Limit vs Input-to-Output Differ-
ential in the Typical Performance Characteristics section.
If not used, tie ILIM to GND.
Output Overshoot Recovery
During a load step from heavy load to very light or no
load, the output voltage overshoots before the regulator
responds to turn the power transistor off. With very light
or no load, it takes a long time to discharge the output
capacitor.
The LT3094 incorporates an overshoot recovery circuit
that turns on a current source to discharge the capacitor
in the event that OUTS is higher than SET. This current is
typically 3.5mA.
If OUTS is externally held above SET, the current source
turns on in an attempt to restore OUTS to its programmed
voltage. The current source remains on until the external
circuitry releases OUTS.
Direct Paralleling for Higher Current
Higher output current is obtained by paralleling multiple
LT3094s. Tie all SET pins together and all IN pins together.
Connect the OUT pins together using small pieces of PCB
trace (used as a ballast resistor) to equalize currents in
the LT3094s. PCB trace resistance in mΩ/inch is shown
in Table2.
Table2. PC Board Trace Resistance
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
1 54.3 27.1
2 27.1 13.6
Trace resistance is measured in mΩ/in.
The small worst-case offset of 2mV for each paralleled
LT3094 minimizes the required ballast resistor value.
Figure15 illustrates that two LT3094s, each using a 20mΩ
PCB trace ballast resistor, provide better than 20% ac-
curate output current sharing at full load. The two 20mΩ
external resistors only add 10mV of output regulation
drop with a 1A maximum current. With a –3.3V output,
this only adds 0.3% to the regulation accuracy. As has
been discussed previously, tie the OUTS pins directly to
the output capacitors.
APPLICATIONS INFORMATION
LT3094
26
Rev. B
For more information www.analog.com
Figure15. Parallel Devices
LT3094
SET GND
–
+
100µA
ILIM OUTS
OUT
4.7µF 16.5k
10µF
IN
PGFB
VIN
–5V ±5%
22µF
EN/UV
LT3094
SET GND
3094 F15
–
+
100µA
ILIM OUTS
OUT
20mΩ
20mΩ
PINS NOT USED IN THESE CIRCUITS: PG, VIOC
VOUT
–3.3V
IOUT(MAX)
1A
IN
PGFB
EN/UV
10µF
More than two LT3094s can also be paralleled for even
higher output current and lower output noise. Paralleling
multiple LT3094s is also useful for distributing heat on the
PCB. For applications with high input-to-output voltage
differential, an input series resistor or a resistor in parallel
with the LT3094 can also be used to spread heat.
PCB Layout Considerations
Given the LT3094’s high bandwidth and ultrahigh PSRR,
careful PCB layout must be employed to achieve full device
performance. Figure 16 shows a recommended layout
that delivers full performance of the regulator. Refer to the
LT3094’s DC2624A demo board manual for further details.
Thermal Considerations
The LT3094 has internal power and thermal limiting circuits
that protect the device under overload conditions. The ther-
mal shutdown temperature is nominally 165°C with about
8°C of hysteresis. For continuous normal load conditions,
do not exceed the maximum junction temperature (125°C
for E- and I-grades, 150°C for H- and MP-grades). It is
important to consider all sources of thermal resistance
from junction to ambient. This includes junction-to-case,
case-to-heat sink interface, heat sink resistance or circuit
board-to-ambient as the application dictates. Additionally,
consider all heat sources in close proximity to the LT3094.
The undersides of the DFN and MSOP packages have
exposed metal from the lead frame to the die attachment.
Both packages allow heat to directly transfer from the die
junction to the PCB metal to limit maximum operating
junction temperature. The dual-in-line pin arrangement
allows metal to extend beyond the ends of the package
on the topside (component side) of the PCB.
APPLICATIONS INFORMATION
LT3094
27
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PCB and its
copper traces. Copper board stiffeners and plated through-
holes can also be used to spread the heat generated by
the regulator.
Table3 and Table4 list thermal resistance as a function
of copper area on a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes and 2oz top/bottom planes with a total
board thickness of 1.6mm. The four layers were electrically
isolated with no thermal vias present. PCB layers, copper
weight, board layout and thermal vias affect the resultant
thermal resistance. For more information on thermal
resistance and high thermal conductivity test boards,
refer to JEDEC standard JESD51, notably JESD51-7 and
JESD51-12. Achieving low thermal resistance necessitates
attention to detail and careful PCB layout.
Table3. Measured Thermal Resistance for DFN Package
COPPER AREA
BOARD AREA
THERMAL
RESISTANCETOP SIDE* BOTTOM SIDE
2500mm22500mm22500mm234°C/W
1000mm22500mm22500mm234°C/W
225mm22500mm22500mm235°C/W
100mm22500mm22500mm236°C/W
*Device is mounted on topside
Figure16. Recommended DFN Layout
3094 F16
LT3094
28
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Table4. Measured Thermal Resistance for MSOP Package
COPPER AREA
BOARD AREA
THERMAL
RESISTANCETOP SIDE* BOTTOM SIDE
2500mm22500mm22500mm233°C/W
1000mm22500mm22500mm233°C/W
225mm22500mm22500mm234°C/W
100mm22500mm22500mm235°C/W
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of –3.3V and input
voltage of –5V ±5%, output current range from 1mA to
500mA, and a maximum ambient temperature of 85°C,
what is the maximum junction temperature?
The LT3094’s power dissipation is:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
IOUT(MAX) = –500mA
VIN(MAX) = –5.25V
IGND (at IOUT = 500mA and VIN = –5.25V) = –9mA
thus:
PDISS = –0.5A • (–5.25V + 3.3V) + 9mA • 5.25V = 1.02W
Using a DFN package, the thermal resistance is in the
range of 34°C/W to 36°C/W depending on the copper area.
Therefore, the junction temperature rise above ambient
approximately equals:
1.02W • 35°C/W = 35.7°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient:
TJ(MAX) = 85°C + 35.8°C = 120.7°C
Overload Recovery
Like many IC power regulators, the LT3094 incorporates
safe-operating-area (SOA) protection. The SOA protection
activates at input-to-output differential voltages greater
than 7V. The SOA protection decreases the current limit
as the input-to-output differential increases and keeps
the power transistor inside a safe operating region for
all values of input-to-output voltages up to the LT3094’s
absolute maximum ratings. The LT3094 provides some
level of output current for all values of input-to-output
differential voltage. Refer to the Current Limit curves in
the Typical Performance Characteristics section. When
power is first applied and input voltage rises, the output
follows the input and keeps the input-to-output differential
low to allow the regulator to supply large output current
and start-up into high current loads.
Due to current limit foldback, however, at high input volt-
ages a problem can occur if the output voltage is low and
the load current is high. Such situations occur after the
removal of a short-circuit or if the EN/UV pin is pulled high
after the input voltage has already turned on. The load line
in such cases intersects the output current profile at two
points. The regulator now has two stable operating points.
With this double intersection, the input power supply may
need to be cycled down to zero and brought back up again
to make the output recover. Other linear regulators with
foldback current limit protection (such as the LT3090,
LT1964 and LT1175) also exhibit this phenomenon, so it
is not unique to the LT3094.
Protection Features
The LT3094 incorporates several protection features for
sensitive applications. Precision current limit and thermal
overload protection safeguard the LT3094 against overload
and fault conditions at the device’s output. For normal
operation, do not allow the junction temperature to exceed
125°C (E- and I-grades) or 150°C (H- and MP-grades).
Pulling the LT3094’s output above ground induces no
damage to the part. If IN is left open circuit or grounded,
OUT can be pulled 20V above GND. In this condition, a
maximum current of 25mA flows into the OUT pin and out
of the GND pin. If IN is powered by a voltage source, OUT
sinks the LT3094’s (foldback) short circuit current and
protects itself by thermal limiting. In this case, however,
grounding the EN/UV pin turns off the device and stops
OUT from sinking the short-circuit current.
LT3094
29
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
Programming Undervoltage Lookout
LT3094
SET GND
3094 TA02
–
+
100µA
ILIM OUTS
OUT
4.7µF
10µF
33.2k
PINS NOT USED IN THIS CIRCUIT: PG, VIOC
VOUT
–3.3V
IOUT(MAX)
500mA
IN
PGFB
VIN
–4V TURN-ON
–3.35V TURN-OFF
EN/UV
10µF
7.5k
REN1
49.9k
REN2
110k
VIN(UVLO)RISING = –1.26 • 1110k
49.9k
£
¤
²¥
¦
´
LT3094
30
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
Positive and Negative Variable Supply
4.7µF
OUTS
OUT
OUT
OUTS
10µF
10µF
267k
249k
IN
EN/UV
PGFB
VIOC
IN
EN/UV
PGFB
VIOC
+
–
100µA
+
–
100µA
SET GND ILIM
150k
4.7µF
47µF
47µF
187k
187k
L1B
L2BL2A
L1A
4.7µF
10µF
150k
4.7µF
100pF
100pF
47nF
47nF
0.1µF
0.1µF
80.6k
80.6k
2k
2k
LT3094
SET GND ILIM
LT3045-1
FBX1
GATE1
VC1
SS1
RT1
SWA1
SWA2
SWB1
SWB2
VIN1
SHDN1
RT2
SS2
VC2
GATE2
FBX2
VPOS: VARIABLE
IPOS(MAX): 500mA
VNEG: VARIABLE
INEG(MAX): –500mA
PG1
SYNC1
CLKOUT1
CLKOUT2
SYNC2
PG2
SHDN2
VIN2
100k
100k
LT8582
VIN
12V
14.7k
D2
2.2µF D1
2.2µF
3094 TA04
L1: DRQ125-8R2
L2: DRQ125-4R7
D1, D2: DFLS230L
LT3094
31
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
0.75 ±0.05
R = 0.115
TYP
16
127
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD12) DFN 0106 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.23 ±0.05
0.25 ±0.05
2.25 REF
2.38 ±0.05
1.65 ±0.05
2.10 ±0.05
0.70 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
2.38 ±0.10
2.25 REF
0.45 BSC
0.45 BSC
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
LT3094
32
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
MSOP (MSE12) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 –0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12
12 11 10 9 8 7
7
DETAIL “B”
16
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
0.1016 ±0.0508
(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.406 ±0.076
(.016 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
0.42 ±0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
LT3094
33
Rev. B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 01/19 Added H temperature range, TJMAX increased to 150°C.
Modified Note 3 for H temperature range.
Added Positive and Negative Supply application circuit.
3, 4, 26, 28
6
30
B 01/20 Added MP temperature range.
Updated Noise Spectral Density (0.1Hz to 10Hz) curve.
3, 4, 6, 26, 28
13
LT3094
34
Rev. B
For more information www.analog.com
01/20
www.analog.com
ANALOG DEVICES, INC. 2018-2020
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1185 3A, Negative Linear Regulator 750mV Dropout Voltage, VIN = –4.3V to –35V, DD-PAK and TO-220 Packages
LT1175 500mA, Negative Low Dropout
Micropower Regulator
500mV Dropout Voltage, VIN = –4.5V to –20V, N8, S8, DD-PAK, TO-220 and SOT-223
Packages
LT1964 200mA, Negative Low Noise Low Dropout
Regulator
340mV Dropout Voltage, Low Noise: 30µVRMS, VIN = –1.9V to –20V, DFN and SOT-23
Packages
LT3015 1.5A, Fast Transient Response, Negative
LDO Regulator
310mV Dropout Voltage, Low Noise: 60µVRMS, VIN = –2.3V to –30V, DFN, MSOP,
TO-220 and DD-PAK Packages
LT3080 1.1A, Parallelable, Low Noise, Low
Dropout Linear Regulator
350mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V,
Single Resistor Output, DFN, MSOP, TO-220, DD and SOT-223 Packages
LT3085 500mA, Parallelable, Low Noise, Low
Dropout Linear Regulator
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V,
Single Resistor Output, DFN and MSOP Packages
LT3090 –36V, 600mA Negative Linear Regulator
with Programmable Current Limit
300mV Dropout Voltage, Low Noise: 18µVRMS, VIN: –1.5V to –36V,
Single Resistor Output, DFN and MSOP Packages
LT3091 –36V, 1.5A Negative Linear Regulator 300mV Dropout Voltage, Low Noise: 18µVRMS, VIN: –1.5V to –36V, Single Resistor Output,
DFN, TSSOP, TO-220 and DD-Pak Packages
LT3045 20V, 500mA, Ultralow Noise Ultrahigh
PSRR Linear Regulator
0.8µVRMS Noise and 75dB PSRR at 1MHz, VIN = 1.8V to 20V, 260mV Dropout Voltage,
3mm × 3mm DFN and MSOP Packages
LT3042 20V, 200mA, Ultralow Noise Ultrahigh
PSRR Linear Regulator
0.8µVRMS Noise and 79dB PSRR at 1MHz, VIN = 1.8V to 20V, 350mV Dropout Voltage,
Programmable Current Limit and Power Good, 3mm × 3mm DFN and MSOP Packages
Parallel Devices
VIN
–5V ±5%
GND
–
+
100µA
LT3094
SET OUTS
OUT
ILIM
VOUT
–3.3V
IOUT(MAX)
1A
IN
PGFB
EN/UV
10µF
16.5k
4.7µF
3094 TA03
10µF
20mΩ
GND
–
+
100µA
LT3094
SET OUTS
OUT
ILIM
IN
PGFB
EN/UV
PINS NOT USED IN THIS CIRCUIT: PG, VIOC
10µF
20mΩ