FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
ICS840021
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 1
ICS840021AG REV. B APRIL 28, 2009
General Description
The ICS840021 is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocksTM
family of high performance devices from IDT. The
ICS840021 uses a 25MHz crystal to synthesize
125MHz. The ICS840021 has excellent phase jitter
performance, over the 1.875MHz – 20MHz integration range. The
ICS840021 is packaged in a small 8-pin TSSOP, making it ideal for
use in systems with limited board space.
Features
•One LVCMOS/LVTTL output, 7Ω output impedance
•Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
•Output frequency: 125MHz
•VCO range: 560MHz to 680MHz
•RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.34ps (typical) 3.3V
•RMS phase noise at 125MHz (typical)
•Phase noise:
Offset Noise Power
100Hz ................-96.9 dBc/Hz
1kHz ..............-122.2 dBc/Hz
10kHz ..............-131.1 dBc/Hz
100Hz ..............-129.5 dBc/Hz
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
1
2
3
4
8
7
6
5
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
RESERVED
Pin Assignment
ICS840021
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
Block Diagram
OSC Phase
Detector VCO ÷5
÷25
(fixed)
Q0
Pullup
OE
XTAL_IN
XTAL_OUT
25MHz
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 2
ICS840021AG REV. B APRIL 28, 2009
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 1, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Control Function Table
Number Name Type Description
1V
DDA Power Analog supply pin.
2 OE Input Pullup Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to
high-impedance state. LVCMOS/LVTTL interface levels.
3,
4
XTAL_OUT,
XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5 Reserved Reserved Reserve pin.
6 GND Power Power supply ground.
7 Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω output impedance.
8V
DD Power Core supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
CPD Power Dissipation Capacitance VDD = 3.465V 24 pF
RPULLUP Input Pullup Resistor 51 kΩ
ROUT Output Impedance 5 7 12 Ω
Control Input Output
OE Q0
0 High-Impedance
1Active
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 3
ICS840021AG REV. B APRIL 28, 2009
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit"
diagram.
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 75 mA
IDDA Analog Supply Current 15 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD+0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current VDD = VIN = 3.465V 5µA
IIL Input Low Current VDD =3.465V, VIN = 0V -150 µA
VOH Output High Voltage; NOTE 1 2.6 V
VOL Output High Voltage; NOTE 1 0.5 V
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 4
ICS840021AG REV. B APRIL 28, 2009
Table 5. Crystal Characteristics
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
Drive Level 1mW
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 125 MHz
tjit(Ø) RMS Phase Jitter, Random;
NOTE 1 Integration Range: 1.875MHz – 20MHz 0.34 ps
tR / tFOutput Rise/Fall Time 20% to 80% 250 550 ps
odc Output Duty Cycle 48 52 %
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 5
ICS840021AG REV. B APRIL 28, 2009
Typical Phase Noise at 125MHz
10 Gb Ethernet Filter
Phase Noise Result by adding a
10 Gb Ethernet filter to raw data
Raw Phase Noise Data
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.34ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
←
←
←
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 6
ICS840021AG REV. B APRIL 28, 2009
Parameter Measurement Information
3.3V Output Load AC Test Circuit
Output Duty Cycle/Pulse Width/Period
RMS Phase Jitter
Output Rise/Fall Time
SCOPE
Qx
LVCMOS
GND
VDD,
1.65V ± 5
-1.65V ± 5
VDDA
tPERIOD
tPW
tPERIOD
odc =
V
DD
2
x 100%
tPW
Q0
Phase Noise Mas
k
Offset Frequency
f1f2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
Q0 20%
80% 80%
20%
tRtF
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 7
ICS840021AG REV. B APRIL 28, 2009
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS840021provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD and VDDA should be individ-
ually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS840021 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
Figure 2. Crystal Input Interface
VDD
VDDA
3.3V
10Ω
10µF.01µF
.01µF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
33p
C2
22p
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 8
ICS840021AG REV. B APRIL 28, 2009
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50Ω0.1µf
R1
R2
V
DD
V
DD
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 9
ICS840021AG REV. B APRIL 28, 2009
Application Schematic
Figure 4A shows a schematic example of the ICS840021. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 27pF and C2 = 33pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 values may be slightly adjusted for optimizing
frequency accuracy.
Figure 4A. ICS840021 Schematic Example
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of ICS840021 P.C. board layout. The
crystal X1 footprint shown in this example allows installation of
either surface mount HC49S or through-hole HC49 package. The
footprints of other components in this example are listed in the
Table 7. There should be at least one decoupling capacitor per
power pin. The decoupling capacitors should be located as close
as possible to the power pins. The layout assumes that the board
has clean analog power ground plane.
Figure 4B. ICS840021 PC Board Layout Example
Table 7. Footprint Table
NOTE: Table 7, lists component sizes shown
in this layout example.
VDD
OE
VDDAVDD
C1
22pF
R2
10
R3
43
C5
0.1u
C4
0.1u
C2
33pF
X1
Zo = 50 Ohm
C3
10uF
Q
LVCMOS
U1
ICS840021i
VDDA
1
OE
2
XTAL_OUT
3
XTAL_IN
4
VDD 8
Q0 7
GND 6
Reserved 5
VDD=3.3V
Reference Size
C1, C2 0402
C3 0805
C4, C5 0603
R2, R3 0603
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 10
ICS840021AG REV. B APRIL 28, 2009
Reliability Information
Table 8. θJA vs. Air Flow Table for a 8 Lead TSSOP
Transistor Count
The transistor count for ICS840021 is: 1961
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 11
ICS840021AG REV. B APRIL 28, 2009
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
Table 9. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
All Dimensions in Millimeters
Symbol Minimum Maximum
N8
A1.20
A1 0.5 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D2.90 3.10
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 12
ICS840021AG REV. B APRIL 28, 2009
Ordering Information
Table 10. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
840021AG 021AG 8 Lead TSSOP Tube 0°C to 70°C
840021AGT 021AG 8 Lead TSSOP 2500 Tape & Reel 0°C to 70°C
840021AGLF 021AL “Lead-Free” 8 Lead TSSOP Tube 0°C to 70°C
840021AGLFT 021AL “Lead-Free” 8 Lead TSSOP 2500 Tape & Reel 0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
IDT™ / ICS™
LVCMOS CLOCK GENERATOR 13
ICS840021AG REV. B APRIL 28, 2009
Revision History Sheet
Rev Table Page Description of Change Date
A T10 10 Ordering Information Table - correct count from 154 to 100. 10/14/04
AT8 3
8
Absolute Maximum Ratings - corrected Package Thermal Impedance air flow.
Corrected air flow in table. 11/30/04
AT10 1
10
Features section - added Lead-free bullet.
Ordering Information Table - added lead-free part number and marking. 10/7/05
A8 Added LVCMOS to XTAL Interface section.
Changed formatting throughout data sheet. 1/10/09
BT1
1
2
Pin Assignment - changed pin 5 from nc to Reserved.
Pin Description Table - changed pin 5 from nc to Reserved. 4/15/09
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
www.IDT.com
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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+480-763-2056
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