ANALOG Microprocessor-Compatible DEVICES 12-Bit D/A Converter AD567 REV. C 1.1 Scope. This specification covers the requirements for a high speed 12-bit resolution bipolar current output D/A converter with double buffered latch and high stability buried Zener reference. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number -1 AD567SD/883B 1.2.3 Case Outline. See Appendix ] of General Specification ADI-M-1000: package outline: D-28. 1.3 Absolute Maximum Ratings. (T,= + 25C unless otherwise noted) Veco to Power Ground .. 2. 2. ee 0 to +18V Ver to Power Ground... 2... ee Oto 18V Voltage on DAC Output (Pin 2) 2.2... ee -3V to +12V Digital Inputs (Pins 10-15, 17-28) to Power Ground ............-2.04-% -1.0V to +7.0V Ref In to Reference Ground... 2.2... ee ee ee +12V Bipolar Offset to Reference Ground .. 0... 0. et es +12V 10V Span R to Reference Ground... 2... ee es +12V 20V Span R to Reference Ground .. 1... 0. ee es +24V Ref Out 2. 0. ee ee Indefinite Short to Power Ground Momentary Short to Vcc Power Dissipation... 6. 0. ee 1000mW Storage Temperature Range... 1... 1. ee 65C to + 150C Lead Temperature (Soldering 10sec) . 2... 2 ee + 300C 1.5 Thermal Characteristics. 25C/W 60C/W Thermal Resistance 8jc 8 JA nod DIGITAL-TO-ANALOG CONVERTERS 8-31 DIGITAL-TO-ANALOG CONVERTERS aAD567SPECIFICATIONS Table 1. Design Sub Sub Limit Group | Group Test Symbol | Device | @+25C | 1 2,3 Test Condition! Units Relative Accuracy RA -1 V2 1/2 3/4 All Bits with Positive ErrorsOn. | + LSB max All Bits with Negative Errors On. Differential Nonlinearity DNL |-1 3/4 3/4 1 Major Carry Errors + LSB max Gain Error? Ag ~1 0.25 0.25 All Bits On +% FSR max Gain Temperature TCAg | -} 30 30 All Bits On + ppm/C max Coefficient Unipolar Offset Error Vos -1 0.05 0.05 All Bits Off +% FSR max Temperature Coefficient TCVos | - 1 2 2 All Bits Off + ppm/C max Unipolar Offset Bipolar Zero Error? Beze -1 0.15 0.15 MSB On, All Other Bits Off +% FSR max Bipolar B/P Zero Temperature TCBszx} -1 10 10 MSB On, All Other Bits Off + ppm/C max Coefficient Bipolar Reference Input Resistance Rin ~1 1S kN min 25 kO max Output Resistance Rour | -1 6 Exclusive of Span Resistor kQ min 10 kQ min Reference Output Voltage Veer -1 9.9 9.9 9.9 Bipolar,0.1mA External Load Vmin 10.10 10.10 | 10.10 | Voc= +12V, Veg= 12V* Vmax Compliance Voltage Vor. -1 1.5 -Vmin 10.0 V max Output Current Settling Time (si. -1 500 See Figure | ; ns max Output Current lout -1 1.6 1.6 Unipolar All Bits On -mA min 2.4 2.4 Vin + 5.0V mA max 0.8 0.8 Bipolar All Bits On mAmin 1.2 1.2 Vin + 5.0V ~mA max Power Supply Rejection Ratio | PSRR | -1 10 10 +11.4V=Vocs + 16.5V ppm of FSR/ 25 25 - 16.5V<Vees - 11.4V max Power Supply Current Icc -1 5 5 Vec= +16.5V, Vez= 16.5V | mAmax ge -1 25 25 All Bits Low mA max Power Dissipation Pp -1 495 495 Vec= +16.5V, Veg= 16.5V | mW max All Bits Low Digital Input High Voltage Vin -1 2.0 2.0 Vmin 5.5 V max Digital Input Low Voltage Vit -1 0.8 0.8 V max Digital Input High Current Ton -1 300 300 Vin = 5.5V pA max Digital Input Low Current In -1 100 100 Vir = 0.0V pA max Write Pulse Width twr -1 100 See Note 5 ns min Data Setup Time low -1 50 See Note 5 ns min Data Hold Time tou -1 10 See Note 5 ns min CS Valid to End of WR tow -1 100 See Note 5 ns min Address Valid End of WR taw -1 100 See Note 5 ns min Latch Functionality Aga -1 1 i 1 See Notes 6 and 7 + LSB max Latch Functionality Vosa -1 1 1 1 See Note 6 + LSB max 8-32 DIGITAL-TO-ANALOG CONVERTERS REV. CAD567 NOTES "Voc = + 15V, Veg = 15V, 502 resistor pin 6 to pin 8, Ay A, A, A;CS, WR = Logic0, Vy, = 2.0V, Vz, = 0.8V, Unipolar configuration unless otherwise specified. Vj, = +2.0V, Vy, = + 0.7V guaranteed design limits at 55C and + 125C. Unipolar ~ pin 3 connected to amplifier output to utilize 10 volt span. Bipolar pin 4 connected to amplifier output to utilize 20 volt span, 502 resistor pin 1 to pin 6. Gain adjustment range + 0.25% min. 3Bipolar zero adjustment range + 0.15% min. In subgroup 1, the reference output is loaded with 0.5mA nominal reference current, 1.0mA bipolar offset current and 0.1mA additional current. In subgroups 2 and 3, only the 0.5mA reference input current is applied. The reference must be buffered to supply external loads at elevated temperatures. >See Figure | and Table 2. 5All bits low, Ap, Ay, Az, Az = Logic 0; Ap, Ai, Az, A; initialized to Logic 1, each 4-bit register set to Logic 1, and Ag, A,, Az set sequentially to Logic 0 and back to Logic 1 to latch data into first rank, 7A, set to Logic 0 and back to Logic 1 to latch full scale output into second rank. 3.2.1 Functional Block Diagram and Terminal Assignments. OB11 - DBE OB7 --~ DBS DB3 === 080 ABITS I 12-BIT PARALLEL LATCH [tj tt i ft 12.BIT HIGH SPEED DAC Low Tc REFERENCE BIPOFFSET| 1] 28 | 0B11(MSB) DAC OUT (-2mA FS.) [ 2 27| 0810 PINT 10V SPAN R [ 3 )DENTIFIER =| 26] DBO 20V SPAN R [ 4 25] oB8 REF eno [ 5 24| DB7 VREF OUT [| 23| DB6 Voc [7] _aD867 22| DBS TOP VIEW VREF IN [ 8 (Not to Scale) 21| OB4 -Vee [ 9 20| DBs es [10] 19 | DB2 WR fa] [1a] DB1 a3 [12 17 | DBO (LSB) a2 [13] 16 | POWER GROUND at [14] 15 | Ao 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (56). REV. C DIGITAL-TO-ANALOG CONVERTERS 8-33 DIGITAL-TO-ANALOG CONVERTERS aADS67 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). 0811-D80 WR OUTPUT *V/2L8B Figure 1. Table 2. Truth Table CS WR A3 A2 Al AO|Operation 1 X |X X X X |No Operation X 2 |X X X X |No Operation Oo O {1 #1 #1 = O |Enable 4 LSBs of First Rank 0 O |1 1 #O 1 |Enable 4 Middle Bits of First Rank o 60 1 O 1. 1 |Enable 4 MSBs of First Rank 0 O {0 1 1 1 |Loads Second Rank from First Rank 0 0 {0 0 O O |AII Latches Transparent X = Dont Care 8-34 DIGITAL-TO-ANALOG CONVERTERS REV. C