© 1999 Fairchild Semiconductor Corporation DS009936 www.fairchildsemi.com
November 1988
Revised November 1999
74AC175 • 74ACT175 Quad D-Type Flip-Flop
74AC175 • 74ACT175
Quad D-Type Flip-Flop
General Description
The AC/A CT 17 5 i s a hi g h-s pee d q uad D-type fl ip- fl op . T he
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D-type inputs is stored during the LOW-to-HIGH clock tran-
sition. Both true and complemented outputs of each flip-
flop are provided. A Master Rese t input r esets all flip -flops,
independent of the Clock or D-type inputs, when LOW.
Features
■ICC reduced by 50%
■Edge-triggered D-type inputs
■Buffered positive edg e- trigg er ed cl ock
■Asynchronous common reset
■True and complement output
■Outputs source/sink 24 mA
■ACT175 has TTL-compatible inputs
Ordering Code:
Device a ls o av ailable in Tape and Reel. Specify by a ppending s uffix let te r “X” to the or dering co de.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D0–D3Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q0–Q3True Outputs
Q0–Q3Complement Outputs
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74AC175 • 74ACT175
Functional Description
The AC/ACT175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops
will store the st ate of their individu al D inputs on th e LOW-
to-HIGH clock (CP) transition, causing individua l Q and Q
outputs to follow. A LOW input on the Master R eset (MR)
will force all Q output s LOW an d Q outp uts HIGH inde pen-
dent of Clock or Data inputs. The AC/ACT175 is useful for
general logic applications where a common Master Reset
and Clock are acceptable.
Truth Table
H = HIGH Voltage Lev el
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
@ tn, MR = H@ t
n+1
DnQnQn
LLH
HHL
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74AC175 • 74ACT175
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absol ut e ma x i mu m rat ings are thos e v alue s beyond wh ich damage
to the dev ice may occ ur. The databoo k specific ations sh ould be m et, with-
out exc eption, to e nsure that the system des ign is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside da t abook spe c if ic at ions
DC Electrical Characteristics for AC
Note 2: All outputs lo aded; thre sholds on input as s oc iated with outpu t un der test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are gu aranteed to be less t han or equa l t o th e respectiv e limit @ 5.5V VCC.
Supply Voltage (VCC)−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V −20 mA
V
I = VCC + 0.5V +20 mA
DC Input Voltage (VI)−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V −20 mA
VO = VCC + 0.5V +20 mA
DC Output Voltage (VO)−0.5V to VCC + 0.5V
DC Output So urce
or Sink Current (IO)± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)± 50 mA
Storage Temperature (TSTG)−65°C to +150°C
Junction Temperature (T J)
PDIP 140°C
Supply Voltage (VCC)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (VI)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA)−40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5 V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V 125 mV/ns
Symbol Parameter VCC TA = +25°CT
A = −40°C to +85°CUnits Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
VOH Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 µA
5.5 5.49 5.4 5.4 VIN = VIL or VIH
3.0 2 .56 2.46 IOH = −12 mA
4.5 3 .86 3.76 V IOH = −24 mA
5.5 4 .86 4.76 IOH = −24 mA (Note 2)
VOL Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA
5.5 0.001 0.1 0.1 VIN = VIL or VIH
3.0 0 .36 0.44 IOL = 12 mA
4.5 0 .36 0.44 V IOL = 24 mA
5.5 0 .36 0.44 IOL = 24 mA (Note 2)
IIN
(Note 4) Maximum Input
Leakage Current 5.5 ±0.1 ± 1.0 µAV
I = VCC, GND
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min
ICC
(Note 4) Maximum Quiescent
Supply Curre nt 5.5 4.0 40.0 µAV
IN = VCC or GND
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74AC175 • 74ACT175
DC Electrical Characteristics for ACT
Note 5: All outputs loaded; th resholds on input associate d w it h output under tes t.
Note 6: Maximum test du ration 2.0 m s, one out put loaded a t a tim e.
AC Electrical Characteristics for AC
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5. 0 is 5. 0V ± 0.5V
Symbol Parameter VCC TA = +25°CT
A = −40°C to +85°CUnits Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT = 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VVOUT = 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI
OUT = −50 µA
Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 5)
VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI
OUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 5)
IIN Maximum Input Leakage Current 5.5 ±0.1 ± 1.0 µAV
I = VCC, GND
ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current(Note 6) 5.5 −75 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC
Supply Current or GND
VCC TA = +25°CT
A = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 7) Min Typ Max Min Max
fMAX Maximum Clock 3.3 149 214 139 MHz
Frequency 5.0 187 244 187
tPLH Propagation Delay 3.3 2.0 9.5 12.0 2.0 13.5 ns
CP to Qn or Qn 5.0 1.5 7.0 9.0 1.0 9.5
tPHL Propagation Delay 3.3 2.5 8.5 13.0 2.0 14.5 ns
CP to Qn or Qn 5.0 1.5 6.0 9.5 1.5 10.5
tPLH Propagation Delay 3.3 3.0 7.5 12.5 2.5 13.5 ns
MR to Qn 5.0 2.0 5.5 9.0 1.5 10.0
tPHL Propagation Delay 3.3 3.0 8.5 11.0 2.5 12.5 ns
MR to Qn 5.0 2.0 6.0 8.5 1.5 9.0
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74AC175 • 74ACT175
AC Operating Requirements for AC
Note 8: Vo lt age Range 3.3 is 3.3V ± 0.3V
Voltage Range 5. 0 is 5. 0V ± 0.5V
AC Electrical Characteristics for ACT
Note 9: Vo lt age Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
Note 10: Voltage Range 5. 0 is 5.0V ± 0.5V
Capacitance
VCC TA = +25°CT
A = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 8) Typ Guaranteed Minimum
tSSetup Time, HIGH or LOW 3.3 2.0 4.5 4.5 ns
Dn to CP 5.0 1.0 3.0 3.0
tHHold Time, HIGH or LOW 3.3 1.0 1.0 1.0 ns
Dn to CP 5.0 1.0 1.0 1.0
tWCP Pulse Width 3.3 2.5 4.5 4.5 ns
HIGH or LOW 5.0 2.0 3.5 3.5
tWMR Pulse Width, LOW 3.3 2.5 4.5 5.0 ns
5.0 2.0 3.5 3.5
tREC Recovery Time 3.3 −2.0 0 0 ns
MR to CP 5.0 −1.0 0 0
VCC TA = +25°CT
A = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 9) Min Typ Max Min Max
fMAX Max imum Clock 5.0 175 236 145 MHz
Frequency
tPLH Propagation Delay 5.0 2.0 6.0 10.0 1.5 11.0 ns
CP to Qn or Qn
tPHL Propagation Delay 5.0 2.0 7.0 11.0 1.5 12.0 ns
CP to Qn or Qn
tPLH Propagation Delay 5.0 2.0 6.0 9.5 1.5 10.5 ns
MR to Qn
tPHL Propagation Delay 5.0 2.0 5.5 9.5 1.5 10.5 ns
MR to Qn
VCC TA = +25°CT
A = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 10) Typ Guaranteed Minimum
tS (H) Setup Time 5.0 3.0 2.0 2.0 ns
tS (L) Dn to CP 3.0 2.5 2.5
tHHold Time, HIGH or LOW 5.001.0 1.0 ns
Dn to CP
tWCP Pulse Width 5.0 4.0 3.0 3.5 ns
HIGH or LOW
tWMR Pulse Width, LOW 5.0 4.0 3.0 4.0 ns
trec Recovery Time, MR to CP 5.0 0 0 0 ns
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC = OPEN
CPD Power Dissipation Capacitance 45.0 pF VCC = 5.0V
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74AC175 • 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Out line Integrated Circuit (SOIC), JEDEC MS-120, 0. 150” Narrow Body
Package Number M16A
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74AC175 • 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74AC175 • 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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74AC175 • 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-L ead P lastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit pat ent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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