18-Bit, 250 kSPS, Differential
Programmable Input PulSAR® ADC
Data Sheet AD7631
Rev. B Document Feedbac
k
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Technical Suppor t www.analog.com
FEATURES
Multiple pins/software-programmable input ranges
+5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p),
±10 V (40 V p-p)
Pins or serial SPI-compatible input ranges/mode selection
Throughput: 250 kSPS
INL: ±1.5 LSB typical, ±2.5 LSB maximum (±9.5 ppm of FSR)
18-bit resolution with no missing codes
Dynamic range: 102.5 dB
SNR: 101 dB @ 2 kHz
THD: −112 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (18-/16-/8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation
73 mW @ 250 kSPS
10 mW @ 1 kSPS
Pb-free, 48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm)
APPLICATIONS
Process controls
High speed data acquisition
Digital signal processing
Spectrum analysis
ATE
GENERAL DESCRIPTION
The AD7631 is an 18-bit, charge redistribution, successive
approximation register (SAR), architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware
or via a dedicated write-only serial configuration port for input
range and operating mode. The AD7631 contains a high speed
18-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. A falling edge on CNVST
samples the fully differential analog inputs on IN+ and IN−.
The AD7631 features four different analog input ranges. Power is
scaled linearly with throughput. Operation is specified from
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
18
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7631
DGNDDVDD
AVDD
AGND
REF REFGND
IN+
PD
RESET
CNVST
PDBUF
REFBUFIN
PDREF REF
TEMP
D[17:0]
BUSY
RD
CS
D0/OB/2C
OGND
OVDD
D2/A1
D1/A0
REF
AMP SERIAL DATA
PORT
PARALLEL
INTERFACE
SWITCHED
CAP DAC
V
C
C
V
EE
BIPOLAR TEN
SERIAL
CONFIGURATION
PORT
IN–
MODE0 MODE1
06588-001
Figure 1.
Table 1. 48-Lead PulSAR Selection
Input Type
Res
(Bits)
100 to
250
(kSPS)
500 to
570
(kSPS)
570 to
1000
(kSPS)
>1000
(kSPS)
Bipolar 14 AD7951
Differential
Bipolar
14 AD7952
Unipolar 16 AD7651 AD7650 AD7653
AD7660 AD7652 AD7667
AD7661 AD7664
AD7666
Bipolar 16 AD7610 AD7665 AD7612
AD7663 AD7671
Differential 16 AD7675 AD7676 AD7677 AD7621
Unipolar AD7622
AD7623
Simultaneous/ 16 AD7654
Multichannel
Unipolar
AD7655
Differential 18 AD7678 AD7679 AD7674 AD7641
Unipolar AD7643
Differential
Bipolar
18 AD7631 AD7634
AD7631 Data Sheet
Rev. B | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Overvie w ...................................................................................... 17
Converter Operation .................................................................. 17
Transfer Functions...................................................................... 18
Typical Connection Diagram ................................................... 18
Analog Inputs .............................................................................. 19
Driver Amplifier Choice ........................................................... 20
Voltage Reference Input/Output .............................................. 21
Power Supplies ............................................................................ 22
Conversion Control ................................................................... 23
Interfaces.......................................................................................... 24
Digital Interface .......................................................................... 24
Parallel Interface ......................................................................... 24
Serial Interface ............................................................................ 25
Master Serial Interface ............................................................... 25
Slave Serial Interface .................................................................. 26
Hardware Configuration ........................................................... 29
Software Configuration ............................................................. 29
Microprocessor Interfacing ....................................................... 30
Application Information ................................................................ 31
Layout Guidelines....................................................................... 31
Evaluating Performance ............................................................ 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
12/12—Rev. A to Rev. B
Changes to Power Sequencing Section ........................................ 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
3/11—Rev. 0 to Rev. A
Changes to Resolution Parameter, Table 2 .................................... 3
Changes to Figure 4 and Table 6 ..................................................... 8
Added Exposed Pad Notation to Outline Dimensions ............. 32
2/07—Revision 0: Initial Version
Data Sheet AD7631
Rev. B | Page 3 of 32
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Conditions/Comments Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUTS
Differential Voltage Range, VIN (VIN+) − (VIN−)
0 V to 5 V VIN = 10 V p-p −VREF +VREF V
0 V to 10 V VIN = 20 V p-p −2 VREF +2 VREF V
±5 V VIN = 20 V p-p −2 VREF +2 VREF V
±10 V VIN = 40 V p-p −4 VREF +4 VREF V
Operating Voltage Range VIN+, VIN− to AGND
0 V to 5 V −0.1 +5.1 V
0 V to 10 V −0.1 +10.1 V
±5 V −5.1 +5.1 V
±10 V −10.1 +10.1 V
Common-Mode Voltage Range VIN+, VIN−
5 V VREF/2 − 0.1 VREF/2 VREF/2 + 0.1 V
10 V VREF − 0.2 VREF V
REF + 0.2 V
Bipolar Ranges −0.1 0 +0.1 V
Analog Input CMRR fIN = 100 kHz 75 dB
Input Current 250 kSPS throughput 801 µA
Input Impedance See Analog Inputs section
THROUGHPUT SPEED
Complete Cycle 4.0 µs
Throughput Rate 250 kSPS
DC ACCURACY
Integral Linearity Error2 250 kSPS throughput −2.5 ±1.5 +2.5 LSB3
No Missing Codes 18 Bits
Differential Linearity Error2 −1 +2.5 LSB
Transition Noise 0.75 LSB
Unipolar Zero Error −0.06 +0.06 %FS
Bipolar Zero Error −0.03 +0.03 %FS
Zero-Error Temperature Drift ±0.5 ppm/°C
Bipolar Full-Scale Error −0.09 +0.09 %FS
Unipolar Full-Scale Error −0.07 +0.07 %FS
Full-Scale Error Temperature Drift ±0.5 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB
AC ACCURACY
Dynamic Range VIN = 0 to 5 V, fIN = 2 kHz, −60 dB 100 101.8 dB4
V
IN = all other input ranges, fIN = 2 kHz, −60 dB 100 102.5 dB
Signal-to-Noise Ratio VIN = 0 to 5 V, fIN = 2 kHz 99.5 100.5 dB
V
IN = all other input ranges, fIN = 2 kHz 100 101 dB
Signal-to-(Noise + Distortion), SINAD fIN = 2 kHz 100 dB
Total Harmonic Distortion fIN = 2 kHz 112 dB
Spurious-Free Dynamic Range fIN = 2 kHz 113 dB
−3 dB Input Bandwidth VIN = 0 V to 5 V 45 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 500 ns
AD7631 Data Sheet
Rev. B | Page 4 of 32
Parameter Conditions/Comments Min Typ Max Unit
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 4.965 5.000 5.035 V
Temperature Drift –40°C to +85°C ±3 ppm/°C
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time CREF = 22 µF 10 ms
REFERENCE BUFFER PDREF = high
REFBUFIN Input Voltage Range 2.4 2.5 2.6 V
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 4.75 5 AVDD + 0.1 V
Current Drain 250 kSPS throughput 250 µA
TEMPERATURE PIN
Voltage Output @ 25°C 311 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.33 kΩ
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.6 V
VIH 2.1 OVDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Parallel or serial 18-bit
Pipeline Delay5
VOL I
SINK = 500 µA 0.4 V
VOH I
SOURCE = −500 µA OVDD − 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.756 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V
VCC 7 15 15.75 V
VEE −15.75 −15 0 V
Operating Current7 @ 250 kSPS throughput
AVDD
With Internal Reference8 8.5 mA
With Internal Reference Disabled8 6.1 mA
DVDD 4 mA
OVDD 0.1 mA
VCC VCC = 15 V, with internal reference buffer 1.4 mA
VCC = 15 V 0.8 mA
VEE VEE = −15 V 0.7 mA
Power Dissipation @ 250 kSPS throughput
With Internal Reference8 94 120 mW
With Internal Reference Disabled8 73 100 mW
In Power-Down Mode9 PD = high 10 µW
TEMPERATURE RANGE10
Specified Performance TMIN to TMAX −40 +85 °C
1 In all input ranges, the input current scales with throughput. See the Analog Inputs section.
2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4 All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5 Conversion results are available immediately after completed conversion.
6 4.75 V or VREF − 0.1 V, whichever is larger.
7 Tested in parallel reading mode.
8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9 With all digital inputs forced to OVDD.
10 Consult sales for extended temperature range.
Data Sheet AD7631
Rev. B | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 35 and Figure 36)
Convert Pulse Width t1 10 ns
Time Between Conversions t2 4.0 µs
CNVST Low to BUSY High Delay t3 35 ns
BUSY High All Modes (Except Master Serial Read After Convert) t4 1.68 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7 1.68 µs
Acquisition Time t8 2.32 ns
RESET Pulse Width t9 10 ns
PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)
CNVST Low to DATA Valid Delay t10 1.65 µs
DATA Valid to BUSY Low Delay t11 20 ns
Bus Access Request to DATA Valid t12 40 ns
Bus Relinquish Time t13 2 15 ns
MASTER SERIAL INTERFACE MODES1 (See Figure 41 and Figure 42)
CS Low to SYNC Valid Delay t14 10 ns
CS Low to Internal SDCLK Valid Delay1 t15 10 ns
CS Low to SDOUT Delay t16 10 ns
CNVST Low to SYNC Delay, Read During Convert t17 530 ns
SYNC Asserted to SDCLK First Edge Delay t18 3 ns
Internal SDCLK Period2 t
19 30 45 ns
Internal SDCLK High2 t
20 15 ns
Internal SDCLK Low2 t
21 10 ns
SDOUT Valid Setup Time2 t
22 4 ns
SDOUT Valid Hold Time2 t
23 5 ns
SDCLK Last Edge to SYNC Delay2 t
24 5 ns
CS High to SYNC HIGH-Z t25 10 ns
CS High to Internal SDCLK HIGH-Z t26 10 ns
CS High to SDOUT HIGH-Z t27 10 ns
BUSY High in Master Serial Read After Convert2 t
28 See Table 4
CNVST Low to SYNC Delay, Read After Convert t29 1.5 µs
SYNC Deasserted to BUSY Low Delay t30 25 ns
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1
(See Figure 44, Figure 45, and Figure 47)
External SDCLK, SCCLK Setup Time t31 5 ns
External SDCLK Active Edge to SDOUT Delay t32 2 18 ns
SDIN/SCIN Setup Time t33 5 ns
SDIN/SCIN Hold Time t34 5 ns
External SDCLK/SCCLK Period t35 25 ns
External SDCLK/SCCLK High t36 10 ns
External SDCLK/SCCLK Low t37 10 ns
1 In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
AD7631 Data Sheet
Rev. B | Page 6 of 32
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns
Internal SDCLK Period Minimum t19 30 60 120 240 ns
Internal SDCLK Period Maximum t19 45 90 180 360 ns
Internal SDCLK High Minimum t20 15 30 60 120 ns
Internal SDCLK Low Minimum t21 10 25 55 115 ns
SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns
SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns
BUSY High Width Maximum t28 2.55 3.40 5.00 8.20 µs
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK,
AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
1.6mA I
OL
500µA I
OH
1.4V
TO OUTPUT
PIN
C
L
60pF
0
6588-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF
0.8V
2V
2V
0.8V0.8V
2V
t
DELAY
t
DELAY
06588-003
Figure 3. Voltage Reference Levels for Timing
Data Sheet AD7631
Rev. B | Page 7 of 32
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V
REF, REFBUFIN, TEMP,
REFGND to AGND
AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD ±7 V
VCC to AGND, DGND –0.3 V to +16.5 V
VEE to GND +0.3 V to −16.5 V
Digital Inputs −0.3 V to OVDD + 0 .3 V
PDREF, PDBUF ±20 mA
Internal Power Dissipation2 700 mW
Internal Power Dissipation3 2.5 W
Junction Temperature 125°C
Storage Temperature Range −65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 See the Analog Inputs section.
2 Specification is for the device in free air: 48-lead LFQP; θJA = 91°C/W and θJC = 30°C/W.
3 Specification is for the device in free air: 48-lead LFCSP; θJA = 26°C/W.
AD7631 Data Sheet
Rev. B | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
VEE
VCC
IN–
REFGND
REF
D6/EXT/INT
D7/INVSYNC
D8/INVSCLK
D9/RDC/SDIN
OGND
OVDD
DVDD
DGND
D10/SDOUT
D11/SDCLK
D12/SYNC
D13/RDERROR
AGND
AVDD
MODE0
MODE1
D0/OB/2C
D1/A0
D3
D4/DIVSCLK[0]
D5/DIVSCLK[1]
OGND
OGND
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D17/SCCS
D16/SCCLK
D15/SCIN
D14/HW/SW
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
AD7631
TOP VIEW
(Not to Scale)
D2/A1
06588-004
NOTES
1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD
SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO
MEET THE ELECTRIC
A
L PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 µF and 100 nF capacitors.
3, 4 MODE[0:1] DI Data Input/Output Interface Mode Selection.
Interface Mode MODE1 MODE0 Description
0 Low Low 18-bit interface
1 Low High 16-bit interface
2 High Low 8-bit (byte) interface
3 High High Serial interface
5 D0/OB/2C DI/O2 In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus, and the data
coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos
complement.
When OB/2C = high, the digital output is straight binary.
When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal
shift register.
6, 7, 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should
be connected to the system digital ground ideally at the same potential as AGND and DGND.
8 D1/A0 DI/O
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Table 7.
9 D2/A1 DI/O
When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
10 D3 DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
Data Sheet AD7631
Rev. B | Page 9 of 32
Pin No. Mnemonic Type1 Description
11, 12 D[4:5] or DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
DIVSCLK[0:1]
When MODE[1:0] = 3, serial data clock division selection. When using serial master read after convert
mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated
serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13 D6 or DO/I When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.
EXT/INT When MODE[1:0] = 3, Serial Data Clock Source Select. In serial mode, this input is used to select the
internally generated (master) or the external (slave) serial data clock for the AD7631 output data.
When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output.
When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
14 D7 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
INVSYNC
When MODE[1:0] = 3, Serial Data Invert Sync Select. In serial master mode (MODE[1:0] = 3,
EXT/INT = low), this input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D8 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
INVSCLK
When MODE[1:0] = 3, Invert SDCLK/SCCLK Select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
16 D9 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 9 of the parallel port data output bus.
RDC or
When MODE[1:0] = 3, Serial Data Read During Convert. In serial master mode (MODE[1:0] = 3,
EXT/INT = low), RDC is used to select the read mode. See the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is
not attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
SDIN
When MODE[1:0] = 3, Serial Data In. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), SDIN can
be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single
SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after
the initiation of the read sequence.
18 OVDD P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface 2.5 V, 3 V, or 5 V and decoupled with 10 F and 100 nF capacitors.
19 DVDD P
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 F and 100 nF capacitors. Can
be supplied from AVDD.
20 DGND P
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.
21 D10 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
SDOUT
When MODE[1:0] = 3, Serial Data Output. In all serial modes, this pin is used as the serial data output
synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7631 provides
the conversion result, MSB first, from its internal shift register. The data format is determined by
the logic level of OB/2C.
When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode):
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
22 D11 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
SDCLK
When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock
input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data
SDOUT is updated depends on the logic state of the INVSCLK pin.
AD7631 Data Sheet
Rev. B | Page 10 of 32
Pin No. Mnemonic Type1 Description
23 D12 or DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
SYNC
When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3,
EXT/INT= low), this output is used as a digital output frame synchronization for use with the
internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while
the SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
the SDOUT output is valid.
24 D13 or DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
RDERROR
When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT = high),
this output is used as an incomplete data read error flag. If a data read is started and not completed when
the current conversion is completed, the current data is lost and RDERROR is pulsed high.
25 D14 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.
HW/SW When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is
used to configure the AD7631 by hardware or software. See the Hardware Configuration section and
Software Configuration section.
When HW/SW = low, the AD7631 is configured through software using the serial configuration register.
When HW/SW = high, the AD7631 is configured through dedicated hardware input pins.
26 D15 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
SCIN
When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW =
low), this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
27 D16 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
SCCLK
When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW = low)
this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated
depends on the logic state of the INVSCLK pin. See the Software Configuration section.
28 D17 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.
SCCS When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode
(HW/SW = low), this input enables the serial configuration port. See the Software Configuration section.
29 BUSY DO
Busy Output. Transitions high when a conversion is started and remains high until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3, EXT/INT = low,
RDC = low) the busy time changes according to Table 4.
30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following.
Input Range (V) BIPOLAR TEN
0 to 5 Low Low
0 to 10 Low High
±5 High Low
±10 High High
31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock in slave serial mode (not used for serial configurable port).
33 RESET DI
Reset Input. When high, reset the AD7631. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register.
See the Digital Interface section. If not used, this pin can be tied to OGND.
34 PD DI2 Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.
35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
36 BIPOLAR DI2 Input Range Select. See description for Pin 30.
Data Sheet AD7631
Rev. B | Page 11 of 32
Pin No. Mnemonic Type1 Description
37 REF AO/I
Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled
producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,
allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 F
capacitor is required with or without the internal reference and buffer. See the Voltage Reference
Input/Output section.
38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane.
39 IN− AI
Analog Input. Referenced to IN+.
In the 0 V to 5 V input range, IN− is between 0 V and VREF V centered about VREF/2. In the 0 V to 10 V
range, IN− is between 0 V and 2 VREF V centered about VREF.
In the ±5 V and ±10 V ranges, IN− is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range)
and centered about 0 V.
In all ranges, IN− must be driven 180° out of phase with IN+.
40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V.
41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
43 IN+ AI
Analog Input. Referenced to IN−.
In the 0 V to 5 V input range, IN+ is between 0 V and VREF V centered about VREF/2. In the 0 V to 10 V
range, IN+ is between 0 V and 2 VREF V centered about VREF.
In the ±5 V and ±10 V ranges, IN+ is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range)
and centered about 0 V.
In all ranges, IN+ must be driven 180° out of phase with IN−.
45 TEMP AO
Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low),
this pin outputs a voltage proportional to the temperature of the AD7631. See the Voltage Reference
Input/Output section.
46 REFBUFIN AI
Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,
PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference
Input/Output section.
47 PDREF DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
48 PDBUF DI
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered down.
49 EPAD3 NC
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered
to VEE.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power, NC = no internal
connection.
2 In serial configuration mode (MODE[1:0] = 3, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and the Software Configuration section.
3 LFCSP_VQ package only.
Table 7. Data Bus Interface Definition
MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-bit parallel
1 0 1 OB/2C A0 = 0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-bit high word
1 0 1 OB/2C A0 = 1 R[0] R[1] All zeros 16-bit low word
2 1 0 OB/2C A0 = 0 A1 = 0 All High-Z R[10:11] R[12:15] R[16:17] 8-bit high byte
2 1 0 OB/2C A0 = 0 A1 = 1 All High-Z R[2:3] R[4:7] R[8:9] 8-bit midbyte
2 1 0 OB/2C A0 = 1 A1 = 0 All High-Z R[0:1] All zeros 8-bit low byte
2 1 0 OB/2C A0 = 1 A1 = 1 All High-Z All zeros R[0:1] 8-bit low byte
3 1 1 OB/2C All High-Z Serial interface Serial interface
AD7631 Data Sheet
Rev. B | Page 12 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
06588-005
CODE
INL (LSB)
2.5
2.0
1.5
1.0
0.5
0
–2.5
–2.0
–1.5
–1.0
–0.5
655360 131072 196608 262144
POSITIVE INL = 1.15 LSB
NEGATIVE INL = –0.94 LSB
f
S
= 250kSPS
Figure 5. Integral Nonlinearity vs. Code, Bipolar 10 V Range
06588-006
INL DISTRIBUTION (LSB)
NUMBER OF UNITS
0
10
20
30
40
50
60
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
NEGATIVE INL
POSITIVE INL
Figure 6. Integral Nonlinearity Distribution, Unipolar 10 V Range
(86 Devices)
70000
0
1FFFE 20008
COUNTS
CODE IN HEX
20000 20002 20004 20006
60000
50000
40000
20000
30000
10000
06588-007
σ = 0.80
00
25
34164
2172 20 00
1997
32769
59925
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center, Bipolar 5 V Range
06588-008
CODE
DNL (LSB)
2.5
2.0
1.5
1.0
0.5
0
–2.5
–2.0
–1.5
–1.0
–0.5
655360 131072 196608 262144
POSITIVE DNL = 0.68 LSB
NEGATIVE DNL = –0.75 LSB
f
S
= 250kSPS
Figure 8. Differential Nonlinearity vs. Code, Bipolar 10 V Range
06588-009
DNL DISTRIBUTION (LSB)
NUMBER OF UNITS
0
10
20
30
40
50
60
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
NEGATIVE DNL
POSITIVE DNL
Figure 9. Differential Nonlinearity Distribution, Bipolar 5 V Range
(86 Devices)
COUNTS
CODE IN HEX
200061FFFC 1FFFE 20000 20002 20004
60000
0
50000
40000
30000
20000
10000
06588-010
00
σ = 0.75
56811
54874
005
6901
294349
11838
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition, Bipolar 5 V Range
Data Sheet AD7631
Rev. B | Page 13 of 32
0
–180
AMPLITUDE (dB OF FULL SCALE)
0
FREQUENCY (kHz)
200 250 30050 100 150
–20
–40
–60
–80
–100
–120
–140
–160
f
S
= 250kSPS
f
IN
= 20.1kHz
SNR = 98.3dB
THD = –116.8dB
SFDR = 121dB
SINAD = 97.8dB
06588-011
Figure 11. FFT 20 kHz, Bipolar 5 V Range, Internal Reference
ENOB (Bits)
80
82
84
86
88
90
92
94
96
98
100
1 10 100 1000
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
SNR
SINAD
ENOB
06588-012
FREQUENCY (kHz)
SNR, SINAD (dB)
Figure 12. SNR, SINAD, and ENOB vs. Frequency, Unipolar 5 V Range
0
6588-013
TEMPERATURE (°C)
SNR (dB)
97
98
99
100
101
102
103
–55 –35 –15 5 25 45 65 85 105 125
0V TO 10V
0V TO 5V
±5V ±10V
Figure 13. SNR vs. Temperature
06588-014
INPUT LEVEL (dB)
SNR, SINAD REFERRED TO FULL SCALE (dB)
100.0
100.5
101.0
101.5
102.0
102.5
103.0
–60 –50 –40 –30 –20 –10 0
±10V
±5V
0V TO 10V
0V TO 5V
SNR
SINAD
Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)
SFDR (dB)
1 10 100 1000
06588-015
FREQUENCY (kHz)
THD, HARMONICS (dB)
0
20
40
60
80
100
120
140
SFDR
THD SECOND
HARMONIC
THIRD
HARMONIC
–140
–130
–120
–110
–100
–90
–80
–
70
Figure 15. THD, Harmonics, and SFDR vs. Frequency, Unipolar 5 V Range
06588-016
TEMPERATURE (°C)
SINAD (dB)
–55 –35 –15 5 25 45 65 85 105 125
97
98
99
100
101
102
103
0V TO 10V
0V TO 5V
±5V ±10V
Figure 16. SINAD vs. Temperature
AD7631 Data Sheet
Rev. B | Page 14 of 32
06588-017
TEMPERATURE (°C)
THD (dB)
–55 –35 –15 5 25 45 65 85 105 125
–132
–128
–124
–120
–116
–112
–108
–
104
0V TO 10V ±5V
±10V 0V TO 5V
Figure 17. THD vs. Temperature
–20
–16
–12
–8
–4
0
4
8
12
16
20
–55 –35 –15 5 25 45 65 85 105 125
ZERO/OFFSET ERROR
POSITIVE
FULL-SCALE ERROR
NEGATIVE
FULL-SCALE ERROR
TEMPERATURE (°C)
ZERO/OFFSET ERROR, FULL-SCALE ERROR (LSB)
0
6588-018
Figure 18. Zero/Offset Error, Positive and Negative Full-Scale Error vs.
Temperature, All Normalized to 25°C
60
0
08
REFERENCE DRIFT (ppm/°C)
NUMBER OF UNITS
50
40
30
20
10
1234567
06588-019
Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)
06588-020
TEMPERATURE (°C)
SFDR (dB)
–55 –35 –15 5 25 45 65 85 105 125
104
108
112
116
120
124
128
132
0V TO 10V
0V TO 5V
±5V
±10V
Figure 20. SFDR vs. Temperature (Excludes Harmonics)
5.0080
4.9920
–55 125
TEMPERATURE (°C)
V
REF
(V)
–35 –15 5 25 45 65 85 105
06588-021
4.9940
4.9960
4.9980
5.0000
5.0020
5.0040
5.0060
Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)
0.001
0.01
0.1
1
10
100
1000
10000
100000
10 100 1000 10000 100000 1000000
OVDD
DVDD
AVDD
PDREF = PDBUF = HIGH
VCC +15V
VEE –15V
0
6588-022
SAMPLING RATE (SPS)
OPERATING CURRENTS (µA)
Figure 22. Operating Currents vs. Sample Rate
Data Sheet AD7631
Rev. B | Page 15 of 32
700
0
–55 105
TEMPERATURE (°C)
POWER-DOWN OPERATING CURRENTS (nA)
600
500
400
300
200
100
–35 –15 5 25 45 65 85
VEE, –15V
VCC, +15V
DVDD
OVDD
AVDD
PD = PDBUF = PDREF = HIGH
06588-023
Figure 23. Power-Down Operating Currents vs. Temperature
0
5
10
15
20
25
30
35
40
45
50
0 50 100 150 200
C
L
(pF)
t
12
DELAY (ns)
OVDD = 2.7V @ 25°C
OVDD = 2.7V @ 85°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
0
6588-024
Figure 24. Typical Delay vs. Load Capacitance CL
AD7631 Data Sheet
Rev. B | Page 16 of 32
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is
N
INp-p
V
VLSB 2
)(
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive full-
scale. The point used as negative full-scale occurs a ½ LSB
before the first code transition. Positive full-scale is defined as a
level 1½ LSBs beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
Unipolar Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Full-Scale Error
The last transition (from 111…10 to 111…11 in straight binary
format) should occur for an analog voltage 1½ LSB below the
nominal full scale. The full-scale error is the deviation in LSB
(or % of full-scale range) of the actual level of the last transition
from the ideal level and includes the effect of the offset error.
Closely related is the gain error (also in LSB or % of full-scale
range), which does not include the effects of the offset error.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured for an input typically at −60 dB. e
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7631 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
The reference voltage temperature coefficient is derived from
the typical shift of output voltage at 25°C on a sample of parts at
the maximum and minimum reference output voltage (VREF)
measured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as
6
10
C25
((
Cppm/
)T–T()(V
)MinV–)MaxV
)(TCV
MIN
MAX
REF
REFREF
REF
where:
VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX.
VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX.
VREF (25°C) = VREF at 25°C.
TMAX = +85°C.
TMIN = –40°C.
Data Sheet AD7631
Rev. B | Page 17 of 32
THEORY OF OPERATION
SW+
COMP
SW–
IN+
REF
REFGND
LSB
MSB
131,072C 65,536C 4C 2C C C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
IN–
4C 2C C C
LSB
MSB
AGND
AGND
131,072C 65,536C
06588-025
Figure 25. ADC Simplified Schematic
OVERVIEW
The AD7631 is a very fast, low power, precise, 18-bit ADC
using successive approximation, capacitive digital-to-analog
(CDAC) architecture.
The AD7631 can be configured at any time for one of four input
ranges with inputs in parallel and serial hardware modes or by a
dedicated write-only, SPI-compatible interface via a configuration
register in serial software mode. The AD7631 uses Analog
Devices’ patented iCMOS high voltage process to accommodate
0 V to +5 V (10 V p-p), 0 V to +10 V (20 V p-p), ±5 V (20 V p-p),
and ±10 V (40 V p-p) input ranges on the fully differential IN+
and IN− inputs without the use of conventional thin films. Only
one acquisition cycle, t8, is required for the inputs to latch to
the correct configuration. Resetting or power cycling is not
required for reconfiguring the ADC.
The AD7631 is capable of converting 250,000 samples per
second (250 kSPS) and power consumption scales linearly with
throughput, making it useful for battery-powered systems.
The AD7631 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple, multiplexed channel
applications.
For unipolar input ranges, the AD7631 typically requires three
supplies: VCC, AVDD (which can supply DVDD), and OVDD
(which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic).
For bipolar input ranges, the AD7631 requires the use of the
additional VEE supply.
The device is housed in a Pb-free, 48-lead LQFP or a tiny,
48-lead, 7 mm × 7 mm LFCSP that combines space savings with
flexibility. In addition, the AD7631 can be configured as either a
parallel or serial SPI-compatible interface.
CONVERTER OPERATION
The AD7631 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 18 binary weighted capacitors, which are connected
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on IN+ and IN− inputs. A
conversion phase is initiated once the acquisition phase is
complete and the CNVST input goes low. When the conversion
phase begins, SW+ and SW− are opened rst. e two capacitor
arrays are then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the comparator
to become unbalanced. By switching each element of the
capacitor array between REFGND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4
through VREF/262,144). The control logic toggles these switches,
starting with the MSB first, to bring the comparator back into a
balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
AD7631 Data Sheet
Rev. B | Page 18 of 32
TRANSFER FUNCTIONS
Using the D0/OB/2C digital input or via the configuration
register, except in 18-bit parallel interface mode, the AD7631
offers two output codings: straight binary and twos
complement. See Figure 26 and Table 8 for the ideal transfer
characteristic and digital output codes for the different analog
input ranges, VIN. Note that when using the configuration
register, the D0/OB/2C input is a don’t care and should be tied
to either high or low.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (Straight Binary)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR –1LSB–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
06588-026
Figure 26. ADC Ideal Transfer Function
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7631
using the internal reference, serial data interface, and serial
configuration port. Different circuitry from that shown in
Figure 27 is optional and is discussed in the following sections.
Table 8. Output Codes and Ideal Input Voltages
VREF = 5 V Digital Output Code
Description
VIN = 0 V to 5 V
(10 V p-p)
VIN = 0 V to 10 V
(20 V p-p)
VIN = ±5 V
(20 V p-p)
VIN = ±10 V
(40 V p-p) Straight Binary Twos Complement
FSR − 1 LSB +4.999962 V +9.999924 V +9.999924 V +19.999847 V 0x3FFFF1 0x1FFFF1
FSR − 2 LSB +4.999924 V +9.999847 V +9.999847 V +19.999695 V 0x3FFFE 0x1FFFE
Midscale + 1 LSB +38.15 µV −76.29 µV −76.29 µV +152.59 µV 0x20001 0x00001
Midscale 0 V 0 V 0 V 0 V 0x20000 0x00000
Midscale − 1 LSB −38.15 µV −76.29 µV −76.29 µV −152.59 µV 0x1FFFF 0x3FFFF
−FSR + 1 LSB −4.999962 V −9.999924 V −9.999924 V −19.999847 V 0x00001 0x20001
−FSR −5 V −10 V −10 V −20 V 0x000002 0x200002
1 This is also the code for overrange analog input.
2 This is also the code for underrange analog input.
Data Sheet AD7631
Rev. B | Page 19 of 32
RD CS
100nF 100nF
AVDD
10µF 100nF
10Ω
AGND DGND DVDD OVDD OGND
CNVST
BUSY
SDOUT
SDCLK
RESETPD
REFBUFIN
D
CLOCK
AD7631
DIGITAL
INTERFACE
SUPPLY
(2.5V, 3.3V, OR 5V)
ANALOG
SUPPLY (5V)
OVDD
DIGITAL
SUPPLY (5V)
IN+
IN–
NOTE 5
ANALOG
INPUT+
C
C
2.7nF
U1
NOTE 1
MODE[1:0]
D0/OB/2C
REFGND
REF
PDBUF
PDREF
100nF
NOTE 3
NOTE 4
NOTE 3
NOTE 7
10µF
10µF
C
REF
22µF
NOTES
1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION.
4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).
SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION.
5. OPTIONAL, SEE POWER SUPPLIES SECTION.
6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VIN(MIN) – 2V] FOR BIPOLAR INPUT RANGES.
FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOGETHER DIRECTLY UNDER THE ADC.
SEE LAYOUT GUIDELINES SECTION.
ANALOG
INPUT–
NOTE 2
VCC
VEE
10µF 100nF
+7V TO +15.75V
SUPPLY
10µF 100nF
–7V TO –15.75V
SUPPLY
NOTE 6
HW/SW
SCCS
SCCLK
SCIN
BIPOLAR
TEN
SERIAL
PORT 1
SERIAL
PORT 2
C
C
2.7nF
U1
NOTE 2
06588-027
15Ω
15Ω
33Ω
AGND DGND
NOTE 8
MicroConverter
®
/
MICROPROCESSOR/
DSP
Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port
ANALOG INPUTS
Input Range Selection
In parallel mode and serial hardware mode, the input range is
selected by using the BIPOLAR (bipolar) and TEN (10 V range)
inputs. See Table 6 for pin details and the Hardware
Configuration section and the Software Configuration section for
programming the mode selection with either pins or the
configuration register. Note that when using the configuration
register, the BIPOLAR and TEN inputs are don’t cares and
should be tied high or low.
Input Structure
Figure 28 shows an equivalent circuit for the input structure of
the AD7631.
D1 R
IN
C
IN
D2
IN+ OR IN–
VEE
VCC
C
PIN
AGND
D3
D4
AVDD
0
V
TO 5V
RANGE ONLY
0
6588-028
Figure 28. Simplified Analog Input
AD7631 Data Sheet
Rev. B | Page 20 of 32
The four diodes, D1 to D4, provide ESD protection for the analog
inputs, IN+ and IN−. Care must be taken to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V,
because this causes the diodes to become forward-biased and to
start conducting current. These diodes can handle a forward-
biased current of 120 mA maximum. For instance, these conditions
could eventually occur when the input buffer’s U1 supplies are
different from AVDD, VCC, and VEE. In such a case, an input
buffer with a short-circuit current limitation can be used to protect
the part although most op amps’ short-circuit current is <100 mA.
Note that D3 and D4 are only used in the 0 V to 5 V range to
allow for additional protection in applications that are switching
from the higher voltage ranges.
This analog input structure of the AD7631 is a true differential
structure allowing the sampling of the differential signal between
IN+ and IN−. By using this differential input, small signals
common to both inputs are rejected, as shown in Figure 29,
which represents the typical CMRR over frequency.
120
0
1 10000
FREQUENCY (kHz)
CMRR (dB)
100
80
60
40
20
10 100 1000
06588-029
0V TO 10V
±5V
0V TO 5V
±10V
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of Capacitor CPIN and the network formed by
the series connection of RIN and CIN. CPIN is primarily the pin
capacitance. RIN is typically 5 kΩ and is a lumped component
comprised of serial resistors and the on resistance of the switches.
CIN is primarily the ADC sampling capacitor and, depending on
the input range selected, is typically 48 pF in the 0 V to 5 V range,
typically 24 pF in the 0 V to 10 V and ±5 V ranges, and typically
12 pF in the ±10 V range. During the conversion phase, when the
switches are opened, the input impedance is limited to CPIN.
Because the input impedance of the AD7631 is very high, it can
be directly driven by a low impedance source without gain
error. To further improve the noise filtering achieved by the
AD7631 analog input circuit, an external, one-pole RC filter
between the amplifier’s outputs and the ADC analog inputs
can be used, as shown in Figure 27. However, large source
impedances significantly affect the ac performance, especially
the THD. The maximum source impedance depends on the
amount of THD that can be tolerated. The THD degrades as a
function of the source impedance and the maximum input
frequency, as shown in Figure 30.
–130
–110
–90
–
70
025 50 75 100
15Ω
33Ω
100Ω
200Ω
06588-030
FREQUENCY (kHz)
THD (dB)
Figure 30. THD vs. Analog Input Frequency and Source Resistance
DRIVER AMPLIFIER CHOICE
Although the AD7631 is easy to drive, the driver amplifier must
meet the following requirements:
For multichannel, multiplexed applications, the driver
amplifier and the AD7631 analog input circuit must be
able to settle for a full-scale step of the capacitor array
at a 18-bit level (0.0004%). For the amplifier, settling at
0.1% to 0.01% is more commonly specified. This differs
significantly from the settling time at a 18-bit level and
should be verified prior to driver selection. The AD8021 op
amp combines ultralow noise with high gain bandwidth and
meets this settling time requirement even when used with
gains of up to 13.
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7631. The noise coming from
the driver is filtered by the external, 1-pole, low-pass filter,
as shown in Figure 27. The SNR degradation due to the
amplifier is
2
3dB
2
3dB
2)(
2
)(
2
log20
NN
NADC
NADC
LOSS
NefNefV
V
SNR
where:
VNADC is the noise of the ADC, which is
20
10
22
2
SNR
INp-p
NADC
V
V
f–3dB is the cutoff frequency of the input filter (3.9 MHz).
Data Sheet AD7631
Rev. B | Page 21 of 32
N is the noise factor of the amplifier (1 in buffer
configuration).
eN+ and eN− are the equivalent input voltage noise densities
of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be utilized when the resistances
used around the amplifiers are small. If larger resistances are
used, their noise contributions should also be root-sum
squared.
The driver needs to have a THD performance suitable to
that of the AD7631. Figure 15 shows the THD vs. frequency
that the driver should exceed.
The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
The AD8022 can also be used when a dual version is needed
and a gain of 1 is present. The AD829 is an alternative in
applications where high frequency performance (above 100 kHz)
is not required. In applications with a gain of 1, an 82 pF
compensation capacitor is required. The AD8610 is an option
when low bias current is needed in low frequency applications.
Because the AD7631 uses a large geometry, high voltage input
switch, the best linearity performance is obtained when using
the amplifier at its maximum full power bandwidth. Gaining
the amplifier to make use of the more dynamic range of the
ADC results in increased linearity errors. For applications
requiring more resolution, the use of an additional amplifier
with gain should precede a unity follower driving the AD7631.
See Table 9 for a list of recommended op amps.
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
AD829 ±15 V supplies, very low noise, low frequency
AD8021 ±12 V supplies, very low noise, high frequency
AD8022 ±12 V supplies, very low noise, high frequency, dual
ADA4922-1 ±12 V supplies, low noise, high frequency,
single-ended-to-differential driver
AD8610/
AD8620
±13 V supplies, low bias current, low frequency,
single/dual
Single-to-Differential Driver
For single-ended sources, a single-to-differential driver, such
as the ADA4922-1, can be used because the AD7631 needs to
be driven differentially. The 1-pole filter using R = 15 Ω and
C = 2.7 nF provides a corner frequency of 3.9 MHz.
06588-031
ANALOG
INPUT
IN+
IN–
AD7631
REF
10µF
15Ω
15Ω
100nF
2.7nF
2.7nF
U2
R1
R2
ADA4922-1
OUT+ VCC
VEE
OUT–
IN
REF
R
F
R
G
Figure 31. Single-to-Differential Driver Using the ADA4922-1
For unipolar 5 V and 10 V input ranges, the internal (or
external) reference source can be used to level shift U2 for
the correct input span. If using an external reference, the values
for R1/R2 can be lowered to reduce resistive Johnson noise
(1.29E − 10 × √R). For the bipolar ±5 V and ±10 V input
ranges, the reference connection is not required because the
common-mode voltage is 0 V. See Table 10 for the different
input ranges for R1/R2.
Table 10.R1/R2 Configuration
Input Range (V) R1 (Ω) R2 (Ω)Common-Mode Voltage (V)
5 2.5 k 2.5 k 2.5
10 2.5 k Open 5
±5, ±10 100 0
This circuit can also be made discretely, and thus more flexible,
using any of the recommended low noise amplifiers in Table 9.
Again, to preserve the SNR of the converter, the resistors RF and
RG should be kept low.
VOLTAGE REFERENCE INPUT/OUTPUT
The AD7631 allows the choice of either a very low temperature
drift internal voltage reference, an external reference, or an
external buffered reference.
The internal reference of the AD7631 provides excellent
performance and can be used in almost all applications.
However, the linearity performance is guaranteed only with
an external reference.
Internal Reference (REF = 5 V)(PDREF = Low,
PDBUF = Low)
To use the internal reference, the PDREF and PDBUF inputs
must be low. This enables the on-chip band gap reference, buffer,
and TEMP sensor resulting in a 5.00 V reference on the REF pin.
The internal reference is temperature-compensated to 5.000 V
±35 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C. This typical drift characteristic is shown in Figure 19.
AD7631 Data Sheet
Rev. B | Page 22 of 32
External 2.5 V Reference and Internal Buffer (REF = 5 V)
(PDREF = High, PDBUF = Low)
To use an external reference with the internal buffer, PDREF
should be high and PDBUF should be low. This powers down
the internal reference and allows the 2.5 V reference to be applied
to REFBUFIN producing 5 V on the REF pin. The internal
reference buffer is useful in multiconverter applications because
a buffer is typically required in these applications to avoid
reference coupling amongst the different converters.
External 5 V Reference (PDREF = High, PDBUF = High)
To use an external reference directly on the REF pin, PDREF
and PDBUF should both be high. PDREF and PDBUF power
down the internal reference and the internal reference buffer,
respectively. For improved drift performance, an external
reference, such as the ADR445 or ADR435, is recommended.
Reference Decoupling
Whether using an internal or external reference, the AD7631
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs. This
decoupling depends on the choice of the voltage reference but
usually consists of a low ESR capacitor connected to REF and
REFGND with minimum parasitic inductance. A 22 µF (X5R,
1206 size) ceramic chip capacitor (or 47 µF low ESR tantalum
capacitor) is appropriate when using either the internal
reference or the ADR445/ADR435 external reference.
The placement of the reference decoupling is also important to
the performance of the AD7631. The decoupling capacitor should
be mounted on the same side as the ADC right at the REF pin
with a thick PCB trace. The REFGND should also connect to
the reference decoupling capacitor with the shortest distance
and to the analog ground plane with several vias.
For applications that use multiple AD7631s or other PulSAR
devices, it is more effective to use the internal reference buffer
to buffer the external 2.5 V reference voltage.
The voltage reference temperature coefficient (TC) directly
impacts full scale; therefore, in applications where full-scale
accuracy matters, care must be taken with the TC. For instance,
a ±4 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.
Temperature Sensor
The TEMP pin measures the temperature of the AD7631. To
improve the calibration accuracy over the temperature range, the
output of the TEMP pin is applied to one of the inputs of the
analog switch (such as ADG779), and the ADC itself is used to
measure its own temperature. This configuration is shown
in Figure 32.
ADG779
C
C
ANALOG INPUT
AD7631
IN+ TEMPERATURE
SENSOR
TEMP
06588-032
Figure 32. Use of the Temperature Sensor
POWER SUPPLIES
The AD7631 uses five sets of power supply pins:
AVDD: analog 5 V core supply
VCC: analog high voltage positive supply
VEE: high voltage negative supply
DVDD: digital 5 V core supply
OVDD: digital input/output interface supply
Core Supplies
The AVDD and DVDD supply the AD7631 analog and digital
cores, respectively. Sufficient decoupling of these supplies is
required consisting of at least a 10 F capacitor and a 100 nF
capacitor on each supply. The 100 nF capacitors should be
placed as close as possible to the AD7631. To reduce the number
of supplies needed, the DVDD can be supplied through a simple
RC filter from the analog supply, as shown in Figure 27.
High Voltage Supplies
The high voltage bipolar supplies, VCC and VEE, are required
and must be at least 2 V larger than the maximum input voltage.
For example, if using the ±10 V range, the supplies should be
±12 V minimum. This allows for 40 V p-p fully differential
input (±10 V on each input IN+ and IN−). Sufficient decoupling of
these supplies is also required consisting of at least a 10 F
capacitor and a 100 nF capacitor on each supply. For unipolar
operation, the VEE supply can be grounded with some slight
THD performance degradation.
Digital Output Supply
The OVDD supplies the digital outputs and allows direct interface
with any logic working between 2.3 V and 5.25 V. OVDD should
be set to the same level as the system interface. Sufficient
decoupling is required consisting of at least a 10 F capacitor and
a 100 nF capacitor with the 100 nF placed as close as possible
to the AD7631.
Data Sheet AD7631
Rev. B | Page 23 of 32
Power Sequencing
The AD7631 requires sequencing of the AVDD and DVDD
supplies. AVDD should come up prior to or simultaneously
with DVDD. This can be achieved using the configuration in
Figure 27 or sequencing the supplies in that manner. The
other supplies can be sequenced as desired as long as absolute
maximum ratings are observed. The AD7631 is very insensitive
to power supply variations on AVDD over a wide frequency
range, as shown in Figure 33.
30
35
40
45
50
55
60
65
70
75
1 10 100 1000 10000
0
6588-033
FREQUENCY (kHz)
PSRR (dB)
Figure 33. AVDD PSRR vs. Frequency
Power Dissipation vs. Throughput
In impulse mode, the AD7631 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 34). This feature makes the AD7631 ideal for very
low power, battery-operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails, that is, OVDD and OGND.
1
10
100
1000
1 10 100 1000 10000 100000 1000000
PDREF = PDBUF = HIGH
0
6588-034
SAMPLING RATE (kSPS)
POWER DISSIPATION (mW)
Figure 34. Power Dissipation vs. Sample Rate
Power Down
Setting PD = high powers down the AD7631, thus reducing
supply currents to their minimums, as shown in Figure 23.
When the ADC is in power-down, the current conversion
(if any) is completed and the digital bus remains active. To
further reduce the digital supply currents, drive the inputs to
OVDD or OGND.
Power-down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a don’t
care and should be tied to either high or low.
CONVERSION CONTROL
The AD7631 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion. A
detailed timing diagram of the conversion process is shown in
Figure 35. Once initiated, it cannot be restarted or aborted, even
by the power-down input, PD, until the conversion is complete.
The CNVST signal operates independently of CS and RD
signals.
BUSY
MODE CONVERT ACQUIREACQUIRE CONVERT
CNVST
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
0
6588-035
Figure 35. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot, undershoot, or ringing.
The CNVST trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 27.
AD7631 Data Sheet
Rev. B | Page 24 of 32
INTERFACES
DIGITAL INTERFACE
The AD7631 has a versatile digital interface that can be set up as
either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The
AD7631 digital interface also accommodates 2.5 V, 3.3 V, or 5 V
logic. In most applications, the OVDD supply pin is connected
to the host system interface 2.5 V to 5.25 V digital supply. Finally,
by using the D0/OB/2C input pin, both twos complement or
straight binary coding can be used, except for a 18-bit parallel
interface.
Two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7631 in
multicircuit applications and is held low in a single AD7631
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7631. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7631 and clears
the data bus and configuration register. See Figure 36 for the
RESET timing details.
t
9
t
8
RESET
DATA
BUS
BUSY
CNVST
0
6588-036
Figure 36. RESET Timing
PARALLEL INTERFACE
The AD7631 is configured to use the parallel interface when the
MODE[1:0] pins = 0, 1, or 2 for 18-/16-/8-bit interfaces,
respectively, as shown in Table 7.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 37 details the timing for this mode.
t
1
BUSY
DATA
BUS PREVIOUS CONVERSION DATA NEW DATA
CNVST
CS = RD = 0
t
10
t
4
t
11
t
3
06588-037
Figure 37. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 38 and
Figure 39, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
CURRENT
CONVERSION
t
13
t
12
BUSY
DATA
BUS
RD
CS
06588-038
Figure 38. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t
13
t
12
t
3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t
4
t
1
06588-039
Figure 39. Slave Parallel Data Timing for Reading (Read During Convert)
Data Sheet AD7631
Rev. B | Page 25 of 32
18-Bit Interface (Master or Slave)
The 18-bit interface is selected by setting MODE[1:0] = 0.
In this mode, the data output is straight binary.
16-Bit and 8-Bit Interface (Master or Slave)
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, Pin A0 and Pin A1 allow a glueless interface to a
16- or 8-bit bus, as shown in Figure 40 (refer to Table 7 for more
details). By connecting Pin A0 and Pin A1 to an address line(s),
the data can be read in two words for a 16-bit interface or three
bytes for an 8-bit interface. This interface can be used in both
master and slave parallel reading modes.
CS, RD
A1
D[17:2] HI-Z HIGH
WORD
LOW
WORD
HI-Z
t
12
t
13
HIGH
BYTE
A0
MID
BYTE
LOW
BYTE
D[17:10]
t
12
HI-Z HI-Z
t
12
0
6588-040
Figure 40. 8-Bit and16-Bit Parallel Interface
SERIAL INTERFACE
The AD7631 is configured to use the serial interface
when MODE[1:0]= 3. The AD7631 has a serial interface
(SPI-compatible) multiplexed on the data pins D[17:4].
Data Interface
The AD7631 outputs 18 bits of data, MSB first, on the SDOUT pin.
This data is synchronized with the 18 clock pulses provided on
the SDCLK pin. The output data is valid on both the rising and
falling edge of the data clock.
Serial Configuration Interface
The AD7631 can only be configured through the serial
configuration register in serial mode as the serial configuration
pins are also multiplexed on the data pins D[17:14]. See the
Hardware Configuration section and the Software Configuration
section for more information.
MASTER SERIAL INTERFACE
The pins multiplexed on D[12:4] and used for master serial
interface are: DIVSCLK[1:0], EXT/INT, INVSYNC, INVSCLK,
RDC, SDOUT, SDCLK, and SYNC.
Internal Clock (MODE[1:0] = 3, EXT/INT = Low)
The AD7631 is configured to generate and provide the serial
data clock, SDCLK, when the EXT/INT pin is held low. The
AD7631 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK and the SYNC signals
can be inverted, if desired, using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data
can be read during the following conversion or after each
conversion. Figure 41 and Figure 42 show detailed timing
diagrams of these two modes.
Read During Convert (RDC = High)
Setting RDC = high allows the master read (previous
conversion result) during conversion mode. Usually, because
the AD7631 is used with a fast throughput, this mode is the
most recommended serial mode. In this mode, the serial clock
and data switch on and off at appropriate instances, minimizing
potential feedthrough between digital activity and critical
conversion decisions. In this mode, the SDCLK period changes
because the LSBs require more time to settle, and the SDCLK is
derived from the SAR conversion cycle. In this mode, the
AD7631 generates a discontinuous SDCLK of two different
periods, and the host should use an SPI interface.
Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])
Setting RDC = low allows the read after conversion mode.
Unlike the other serial modes, the BUSY signal returns low after
the 18 data bits are pulsed out and not at the end of the conversion
phase, resulting in a longer BUSY width (see Table 4 for BUSY
timing specifications). The DIVSCLK[1:0] inputs control the
SDCLK period and SDOUT data rate. As a result, the maximum
throughput cannot be achieved in this mode. In this mode, the
AD7631 also generates a discontinuous SDCLK; however, a
fixed period and hosts supporting both SPI and serial ports can
also be used.
AD7631 Data Sheet
Rev. B | Page 26 of 32
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SDCLK
SDOUT
CNVST
CS, RD
t
23
t
18
t
15
t
14
t
17
t
3
t
22
t
16
t
1
t
25
t
26
t
24
t
27
t
19
t
20
t
21
MODE[1:0] = 3
06588-041
Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
BUSY
SYNC
SDCLK
SDOUT
123 161718
D17 D16 D2 D1 D0
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
CNVST
CS, RD
EXT/INT = 0
t
23
t
22
t
16
t
15
t
14
t
29
t
19
t
21
t
20
t
18
t
28
t
30
t
24
t
25
t
26
t
27
t
3
MODE[1:0] = 3
06588-042
Figure 42. Master Serial Data Timing for Reading (Read After Convert)
SLAVE SERIAL INTERFACE
The pins multiplexed on D[13:6] used for slave serial
interface are: EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK,
and RDERROR.
External Clock (MODE[1:0] = 3, EXT/INT = High)
Setting the EXT/INT = high allows the AD7631 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The external
serial clock is gated by CS. When CS and RD are both low, the
data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally
low when inactive. For detailed timing diagrams, see Figure 44
and Figure 45.
While the AD7631 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is
particularly important during the last 550 ns of the conversion
phase because the AD7631 provides error correction circuitry
that can correct for an improper bit decision made during
the first part of the conversion phase. For this reason, it is
recommended that any external clock provided is a
discontinuous clock that transitions only when BUSY is low,
or, more importantly, that it does not transition during the
last 450 ns of BUSY high.
Data Sheet AD7631
Rev. B | Page 27 of 32
External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 44 shows the detailed timing diagrams for this method.
After a conversion is completed, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 18 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
In addition, in the read after convert mode, the AD7631 provides a
daisy-chain feature for cascading multiple converters together
using the serial data input pin, SDIN. This feature is useful for
reducing component count and wiring connections when desired,
for instance, in isolated multiconverter applications. See Figure 44
for the timing details.
An example of the concatenation of two devices is shown
in Figure 43.
Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK
falling edge when INVSCLK = low). Therefore, the MSB of
the upstream converter follows the LSB of the downstream
converter on the next SDCLK cycle. In this mode, the 40 MHz
SDCLK rate cannot be used because the SDIN to SDCLK setup
time, t33, is less than the minimum time specified. (SDCLK
to SDOUT delay, t32, is the same for all converters when
simultaneously sampled). For proper operation, the SDCLK
edge for latching SDIN (or ½ period of SDCLK) needs to be
3332
SDCLK ttt
2/1
Or the maximum SDCLK frequency needs to be
)(2
1
3332
SDCLK tt
f
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
SDCLK
SDOUTRDC/SDIN
AD7631
#1
(DOWNSTREAM)
AD7631
#2
(UPSTREAM)
BUSY
OUT
BUSYBUSY
DATA
OUT
SDCLK
RDC/SDIN SDOUT
SDCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
0
6588-043
Figure 43. Two AD7631 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 45 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses and is valid on both the falling
and rising edges of the clock. The 18 bits have to be read before
the current conversion is completed; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR
conversion phase.
The daisy-chain feature should not be used in this mode because
digital activity occurs during the second half of the SAR
conversion phase likely resulting in performance degradation.
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
This method allows the full throughput and the use of a slower
SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize
potential incorrect bit decisions. The use of a slower SDCLK,
such as 13 MHz, can be used.
AD7631 Data Sheet
Rev. B | Page 28 of 32
SDIN
SDOUT D0
123 1718
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK 4
D2 D1
19 20
MODE[1:0] = 3 RD = 0
16
D17 D16 D15 X17 X16
21
X0
X2 X1
X17 X16 X15 Y17 Y16
t
31
t
31
X*
t
32
t
16
t
33
t
34
t
37
t
35
t
36
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
0
6588-044
Figure 44. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT D0
123
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK 17
D1
MODE[1:0] = 3 RD = 0
18
D17 D16
t
31
t
31
t
32
t
16
t
37
t
35
t
36
CNVST
X*
X* X* X* X* X*
t
27
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
DATA = SDIN
06588-045
Figure 45. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
Data Sheet AD7631
Rev. B | Page 29 of 32
HARDWARE CONFIGURATION
The AD7631 can be configured at any time with the dedicated
hardware pins BIPOLAR, TEN, D0/OB/2C, and PD for parallel
mode (MODE[1:0] = 0, 1, or 2) or serial hardware mode
(MODE[1:0] = 3, HW/SW = high). Programming the AD7631
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle, as indicated in
Figure 46. See Table 6 for pin descriptions. Note that these
inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[17:14] used for software
configuration are: HW/SW, SCIN, SCCLK, and SCCS. The
AD7631 is programmed using the dedicated write-only
serial configurable port (SCP) for conversion mode, input range
selection, output coding, and power-down using the serial
configuration register. See Table 11 for details of each bit in the
configuration register. The SCP can only be used in serial software
mode selected with MODE[1:0] = 3 and HW/SW = low because
the port is multiplexed on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 47 for timing details. SCIN is clocked into the
configuration register MSB first. The configuration register is
an internal shift register that begins with Bit 8, the START bit.
The 9th SCCLK edge updates the register and allows the new
settings to be used. As indicated in the timing diagram, at least one
acquisition time is required from the 9th SCCLK edge. Bits [1:0] are
reserved bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7631 is not busy
converting, as detailed in Figure 47. In this mode, the full
670 kSPS is not attainable because the time required for SCP
access is (t31 + 9 × 1/SCCLK + t8) minimum. If the full
throughput is required, the SCP can be written to during
conversion; however, it is not recommended to write to the SCP
during the last 600 ns of conversion (BUSY = high) or performance
degradation can result. In addition, the SCP can be accessed in
both serial master and serial slave read during and read after
convert modes.
Note that at power-up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), therefore placing the configuration to 0 V to 5 V input,
normal mode, and twos complemented output.
Table 11. Configuration Register Description
Bit Mnemonic Description
8 START START bit. With the SCP enabled (SCCS = low),
when START is high, the first rising edge of
SCCLK (INVSCLK = low) begins to load the
register with the new configuration.
7 BIPOLAR Input Range Select. Used in conjunction with
Bit 6, TEN, per the following.
Input Range (V) BIPOLAR TEN
0 to 5 Low Low
0 to 10 Low High
±5 High Low
±10 High High
6 TEN Input Range Select. See Bit 7, BIPOLAR.
5 PD Power Down.
PD = low, normal operation.
PD = high, power down the ADC. The SCP is
accessible while in power down. To power up
the ADC, write PD = low on the next
configuration setting.
4 RSV Reserved.
3 RSV Reserved.
2 OB/2C Output coding.
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
1 RSV Reserved.
0 RSV Reserved.
D0/OB/2C,
PD
BUSY
HW/SW = 1
CNVST
BIPOLAR,
TEN
t8
PD = 0
t8
0
6588-046
Figure 46. Hardware Configuration Timing
AD7631 Data Sheet
Rev. B | Page 30 of 32
SCIN
SCCL
K
X
START TEN
123 67
BUSY
HW/SW = 0
INVSCLK = 0
CNVST
SCCS
t
8
t
36
t
35
t
37
4
PD
5
BIPOLAR
X
OB/2C X
89
MODE[1:0] = 3
BIPOLAR = 0 OR 1
TEN = 0 OR 1 PD = 0
t
33
t
34
t
31
X
t
31
06588-047
Figure 47. Serial Configuration Port Timing
MICROPROCESSOR INTERFACING
The AD7631 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The
AD7631 is designed to interface with a parallel 8-bit or 18-bit wide
interface, or with a general-purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used with
the AD7631 to prevent digital noise from coupling into the ADC.
SPI Interface
The AD7631 is compatible with SPI and QSPI digital hosts and
DSPs, such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x.
Figure 48 shows an interface diagram between the AD7631 and
the SPI-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7631 acts as a slave device, and data must
be read after conversion. This mode also allows the daisy-chain
feature. The convert command could be initiated in response to
an internal timer interrupt.
The reading process can be initiated in response to the end-of-
conversion signal (BUSY going low) using an interrupt line of
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable
(TIMOD) = 0 by writing to the SPI control register (SPICLTx).
It should be noted that to meet all timing requirements, the SPI
clock should be limited to 17 Mbps allowing it to read an ADC
result in less than 1 µs. When a higher sampling rate is desired,
use one of the parallel interface modes.
BUSY
CS
SDOUT
SDCLK
CNVST
AD7631*
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x*
*ADDITIONAL PINS OMITTED FOR CLARITY.
DVDD
MODE[1:0]
EXT/INT
RD
INVSCLK
06588-048
Figure 48. Interfacing the AD7631 to SPI Interface
Data Sheet AD7631
Rev. B | Page 31 of 32
APPLICATION INFORMATION
LAYOUT GUIDELINES
While the AD7631 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7631 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7631, or as close as possible to the AD7631. If the AD7631 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at
one point only, a star ground point, established as close as
possible to the AD7631.
To prevent coupling noise onto the die, avoid radiating noise,
and reduce feedthrough:
Do not run digital lines under the device.
Do run the analog ground plane under the AD7631.
Do shield fast switching signals, such as CNVST or clocks,
with digital ground to avoid radiating noise to other sections
of the board and never run them near analog signal paths.
Avoid crossover of digital and analog signals.
Run traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough through
the board.
The power supply lines to the AD7631 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the impedance of the supplies presented
to the AD7631 and to reduce the magnitude of the supply
spikes. Decoupled ceramic capacitors, typically 100 nF, should
be placed on each of the power supplies pins, AVDD, DVDD,
OVDD, VCC, and VEE. The capacitors should be placed close
to, and ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 µF capacitors should be
located near the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7631 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present and no
separate supply is available, it is recommended to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. See
Figure 27 for an example of this configuration. When DVDD is
powered from the system supply, it is useful to insert a bead to
further reduce high frequency spikes.
The AD7631 has four different ground pins: REFGND, AGND,
DGND, and OGND.
REFGND senses the reference voltage and, because it carries
pulsed currents, should be a low impedance return to the
reference.
AGND is the ground to which most internal ADC analog
signals are referenced; it must be connected with the least
resistance to the analog ground plane.
DGND must be tied to the analog or digital ground plane
depending on the configuration.
OGND is connected to the digital system ground.
The layout of the decoupling of the reference voltage is important.
To minimize parasitic inductances, place the decoupling capacitor
close to the ADC and connect it with short, thick traces.
EVALUATING PERFORMANCE
A recommended layout for the AD7631 is outlined in the
EVAL-AD7631EDZ evaluation board documentation. The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CED1Z.
AD7631 Data Sheet
Rev. B | Page 32 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 49. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.80 MAX
0.65 TYP
5.50 REF
COPLANARITY
0.08
0.20 REF
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1
INDICATOR 0.50
REF
PIN 1
INDICATOR
0.25 MIN
7.10
7.00 SQ
6.90
6.85
6.75 SQ
6.65
06-05-2012-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
Figure 50. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes Temperature Range Package Description Package Option
AD7631BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7631BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7631BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
AD7631BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
EVAL-AD7631EDZ 2 Evaluation Board
EVAL-CED1Z 3 Converter Evaluation and Development Board
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the ED designators.
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06588-0-12/12(B)
