DAC1267X - Samsung Electronics

GENERALDESCRIPTION

Thedac1267x isaCMOS9Bit D/Aconverter for

generalapplications.Itsmaximumconversion rate

is40MSPS and supply voltageis1.8Vsingle.

Anexternal0.7Vvoltagereference(VBIAS)and

asingleresistor (RSET)control thefull-scaleoutput

current.

TYPICALAPPLICATION

·High Definition Television (HDTV)

·HardDiskDrive

·High Resolution ColorGraphics

·CAE/CAD/CAM

FUNCTIONAL BLOCKDIAGRAM

12Bit30MSPSDAC DAC1233

SAMSUNG ELECTRONICSCo.LTD

FEATURES

· 40MSPS pipelineoperation

· 1.8V CMOSmonolithic construction

· ±0.3LSBdifferential linearityerror(typical)

· ±1.5LSBintegral linearityerror(typical)

·Externalvoltage reference

· 9-Bitvoltageparallel input

1.8V9Bit40MSPSDAC DAC1267X

Rev 2.4(Apr.2002)

Noresponsibilityisassumed by SECforitsusenor forany

infringementsofpatentsorother rightsofthird partiesthatmay

result fromitsuse.The contentofthisdatasheet is subject to

changewithoutany notice.

AVDD18A AVSS18A AVDD18D AVSS18D AVBB18A

CCOMP

Clock

Generator

1st

Latch

Decoder

Buffer

2nd

Latch

Current

Cell

Array

CK1 CK2

D[8:0]

IOB

CLK

CK1

CK2 Amp CM

Block

VBIAS IREF

CCOMP

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DAC1267X

1.8V9Bit40MSPSDAC

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NAMEI/OTYPEI/OPAD PIN DESCRIPTION

D[8:0]DIpicc_abb DigitalInput

CLK DIpicc_abb ClockInput

PD DIpicc_abb High=powersaving standby mode

(normally=gnd)

VBIASAIpia_abb ExternalBias(0.7V)

IREFAO poa_abb Full SaleAdjustControl

CCOMPAIpia_abb Using Compensation Capacitor

IO AO poa_abb Analog Output

(outputRange:0.66Vpp)

IOBAO poa_abb Analog Output

(outputRange:0.66Vpp)

AVDD18A APvdd1t_abb Analog Power

AVSS18A AG vss1t_abb Analog Ground

AVDD18D DPvdd1t_abb DigitalPower

AVSS18D DG vss1t_abb DigitalGround

AVBB18A AG vbb_abb Analog Ground (bulk bias)

COREPIN DESCRIPTION

CORECONFIGURATION

I/OTYPEABBR.

·AI:Analog Input

·DI:DigitalInput

·AO:Analog Output

·DO:DigitalOutput

·AP:Analog Power

·DP:DigitalPower

·AG:Analog Ground

·DG:DigitalGround

·AB:Analog Bidirection

·DB:DigitalBidirection

2/11

IREFVBIAS

D[8:0]

AVDD18A AVSS18A AVDD18D AVSS18D AVBB18A

dac1267x

CCOMP

IOB

CLK PD

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1.8V9Bit40MSPSDAC

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CHARACTERISTICS SYMBOLMINTYPMAX UNIT

Operating SupplyVoltageAVDD18A-AVSS18A

AVDD18D-AVSS18D1.6 1.8 2.0V

DigitalInputVoltageHigh VIH0.8×VDD - - V

DigitalInputVoltageLow VIL- - 0.2×VDD V

Operating TemperatureRangeTOPR0-70 °C

OutputLoad(effective)RL150 Ω

Reference VoltageVBIAS0.7V

ClockCycleTimeTclk 25 - - ns

ClockPulseWidthHigh Tpwh 12 - - ns

ClockPulseWidthLowTpwl12 - - ns

IREFCurrentIref291.6 uA

ABSOLUTE MAXIMUMRATINGS

RECOMMENDEDOPERATINGCONDITIONS

CHARACTERISTICS SYMBOLVALUEUNIT

SupplyVoltageAVDD18D,AVDD18A+2.5V

DigitalInputVoltageVinAVSS18D-0.2toAVDD18D+0.2V

Operating TemperatureRangeTopr0to+70 °C

StorageTemperatureRangeTstg-55 to+150 °C

NOTE:

1.Absolutemaximumrating valuesappliedindividuallywhile anotherparametersarewithinspecified operating condition.

Function operation underany ofthese conditionsisnot implied.

2.Applied voltagemustbe current limitedtospecifiedrange.

3.Absolutemaximumratingsarevaluebeyond whichthedevice may bedamaged permanently.

Normaloperation isnotguaranteed.

NOTE :

1.It is stronglyrecommendedthat toavoid powerlatch-up all thesupply pins(AVDD18A,AVDD18D)

bedrivenfromthesamesource.

2.Voltageon any digitalpinthatgoesbelow AVSS18D(DigitalGround)by less than 0.2Vcaninduce destructivelatch-up.

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DC ELECTRICALCHARACTERISTICS

AC ELECTRICALCHARACTERISTICS

CHARACTERISTICS SYMBOLMINTYPMAX UNIT

Resolution - - 9-Bits

DifferentialLinearityErrorDLE -0.3 ±1 LSB

IntegralLinearityError ILE -1.5 ±2 LSB

Monotonicity-Guaranteed-

ZerolevelVz0-3mV

Full ScaleFS 0.55 0.678 0.75 V

MaximumOutputCompliance VOC0-+0.8V

ExternalReference VoltageVBIAS-0.7-V

CHARACTERISTICS SYMBOLMINTYPMAX UNIT

ClockRatefc- - 40 MHz

DigitalDataSetup Timets2- - ns

DigitalDataHoldTimeth 2 - - ns

Analog OutputDelayTimeTd-3-ns

Analog OutputRiseTimeTr - 12 15 ns

Analog OutputFall TimeTf - 13 15 ns

Analog OutputSettling TimeTs-91 115 ns

Clockand DataFeedthrough FDTHR-29 -27 -25 dB

GlitchImpulseGI90 114 146 pv-sec

PipelineDelayTpd -2-Clocks

VDD SupplyCurrentIdd -6 8 mA

SpuriousFree DynamicRangeSFDR-45 -50 -60 dB

NOTE :

·The aboveparametersarenot testedthrough thetemperaturerange,but these areguaranteed

overthefull temperaturerange.

·Clockand datafeedthrough isafunction ofthe amountofovershootand undershooton the

digital inputs.Settling timedoesnot include clockand datafeedthrough.Glitchimpulseinclude

clockand datafeedthrough.

NOTES

1.ConverterSpecifications(unless otherwisespecified)

AVDD18A=1.8V AVDD18D=1.8V

AVSS18A=GND AVSS18D=GND AVBB18A=GND

Ta=25°C

RL=150Ω,VBIAS=0.7V

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TIMINGDIAGRAM

NOTES:

·Outputdelaymeasuredfromthe50%pointoftherising edgeofCLKtothefull scaletrasition

·Settling timemeasuredfromthe50%pointof full scaletransition totheoutputremaining within ±1,±2LSB.

·Outputrise/fall timemeasured betweenthe10%and 90%pointsof full scaletransition.

CLK

Tclk

TpwhTpwl

TsTh

dataD[8:0]

50%

1LSB

90%

10%

TrTf

50%

111111111

000000000

111111111

PowerDown

on time

typ=100usecPowerDown

off time

typ=200usec

Tset

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CORE EVALUATIONGUIDE

TESTPATH

dac1267x

IREF

PDVBIAS CLK

0.7V

D[8:0]

MAIN

PATH

SELECT

CCOMP

AVDD18A

1.8V

AVSS18A

AVDD18D

AVSS18D

AVBB18A

R3IOB

1.Testability

Whetheryou useMUX ortheinternal logicfortestability,it isrequiredto be abletoselect thevaluesofdigital

inputs(D[0]~D[8] ) See abovefigure.Onlyifit is,you cancheckthemainfunction (Linearity),and output

(IO,IOB),VBIAS,IREFand CCOMPpinsarereservedforexternaluse.

2.Analysis

Thevoltage appliedtoVBIASismeasuredatIREFnode.And thevoltagevalueisproportionedtothereference

currentvalueof resistorwhichisconnectedtoIREFnode.So you canestimatethefull scale currentvalueby

measuring thevoltage,and checktheDCcharacteristicsoftheOPAMP.For reference,asVREFappliedto

VBIASnodeisgivenatIREFnode,the currentflowing through RSET isgivenasVREF/RSET.Thefull scale

current isgivenasthedecimalvalue equivalent tothedigitalcode.

6/11

LOCATION DESCRIPTION

Cc0.1mF

Ct10mF

R1 2.4kΩ

R2,R3 150Ω

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1.8V9Bit40MSPSDAC

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PACKAGECONFIGURATION

LOCATION DESCRIPTION

Ct10µF TANTALUMCAPACITOR

Cc0.1µFCERAMIC CAPACITOR

L1,L2 FERRITE BEAD(0.1mh)

R1 2.4KΩ

R2,R3 150Ω

VDD

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

GND

CLK

AVSS18D

AVDD18D

AVSS18A

AVDD18A

AVBB

AVDD18A

CCOMP

IREF

VBIAS

IOB

AVSS18A

dac1267x

Fclk=40MHz

DC=0.7V

CtCc

Digital input

CtVDD

GND

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PACKAGEPIN DESCRIPTION

NAMEPIN NOI/OTYPEPIN DESCRIPTION

AVDD18A36,37,41,42 APAnalog Power

AVBB18A38,39 AG Analog Ground

AVSS18A27,28,43,44 AG Analog Ground

D[0]~D[8]6~14 DIDigitalInputData

PD20 DIDigitalInputData(Low)

AVDD18D22 DPDigitalPower

AVSS18D21 DG DigitalGround

CLK19 DIDigitalInputData

IOB29 AO

Analog VoltageOutput

Thischipwasdevelopedfor12bit DAC,but

finishedto develop with 9bit DAC.When you

maywant to probeIOB,Thischipwill havethe

offseterrorcorresponding to 7/8LSB.

IO30 AO Analog VoltageOutput

VBIAS31 AIVoltageReference(0.7V)

IREF32,33 AO Analog DCcurrentoutput

Needantermination resistor

CCOMP34,35 AICompensation capacitor

1,2,3,4,5,18,23,

24,25,26,40,45,46

47,48

DO NoConnection

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PCBOARD LAYOUTCONSIDERATIONS

1.PCBoardConsiderations

Tominimize NoiseOnThePowerLinesAnd TheGround Lines,TheDigitalInputsNeedToBeShieldedAnd

Decoupled.ThisTrace LengthBetweenGroupsOfVDD (AVDD18A,AVDD18D)pins shortaspossiblesoasto

minimize inductiveringing.

2.SupplyDecoupling and Planes

Forthedecoupling capacitorbetweenthepowerline and theground line,0.1µFceramic capacitorisusedin

parallelwitha10µFtantalumcapacitor.Thedigitalpowerplane(AVDD18D)and analog powerplane

(AVDD18A)are connectedthrough aferritebead,and alsothedigitalground plane(AVSS18D)and the analog

ground plane(AVSS18A).Thisferritebeadshould belocatedwithin 3inchesofthedac1267x.The analog power

planesuppliespowertothedac1267x ofthe analog outputpinand related devices.

3.Analog SignalInterconnection

Tominimized noisepickup and reflectionsduetoimpedance mismatch,thedac1267x should belocatedasclose

aspossibletotheoutputconnector.

ThelinebetweenDACoutputand monitorinputshouldalso beregardedasatransmission line.Duetothe

fact,it cancauseproblemsintransmission linemismatch.Asasolution totheseproblems,thedouble-termination

methodsused.By using this,bothendsofthetermination linesarematched,providing anideal,non-reflective

system.

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PHANTOMCELL INFORMATION

PinNamePin

UsagePropertyPinLayoutGuide

AVDD18AExternalAP1.It isrecommendedthatyou usethickanalog powermetal(morethan 10umeach).

WhenconnectedtoPAD,each pathshould bekeptas shortaspossible.

2.DigitalPowerand analog powermustbeusedseparately.

3.InPhantomcell incaseofmany portsofonepowername,you mustdragthe

portsindividuallytoPAD in parallel.

4.CustomermustusetwoPAD'sindividuallyforanalog powerportsbecauseofPAD's

current limitation.

AVSS18AExternalAG

AVDD18DExternal / InternalDP

AVSS18DExternal / InternalDG

AVBB18AExternal / InternalAG

D[8:0]External / InternalDI1.Digital inputSignal linesmusthavesamelengthtoreduce propagation delay.

PDExternal / InternalDI

IREFExternalAB1.Analog Bi-direction linemustbekeptas shortaspossible.

2.Any othershould notacross theselinesexceptpowermetal.

VBIASExternalAB

CCOMPExternalAB

IOExternalAO 1.Analog output lineshould bekeptas shortaspossible.

2.Theselinesmusthavethesamemetal length becauseofvoltagedrop through the

metal line

IOBExternalAO

CLKExternal / InternalDI1.Separatedfromthe analog cleansignalsifpossible.

2.Do notexceedthelength by 100um.-

10 /11

AVSS18A

AVDD18A

CCOMP

AVBB18A

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[1]

D[0]

DAC1267X

AVDD18D

AVSS18D

CLK

AVDD18D

AVSS18D

AVBB18A

AVSS18A

VBIAS

AVDD18A

IREF

AVDD18A

IOB

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1.8V9Bit40MSPSDAC

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FEEDBACKREQUEST

We appreciateyourinterest in outproducts.If you havemorequestions,pleasespecifyinthe attachedform.

Thank you verymuch.

-Do you want toPowerdownmode?

-Do you want toInternalReference Voltage(BGR)?

-Which do you want toSerialInputTYPEorparallelInputTYPE?

-Do you need 3.3v and 1.8Vpowersupplyin yoursystem?

DC /AC ELECTRICALCHARACTERISTIC

CharacteristicsMinTypMax UnitRemarks

SupplyVoltageV

Powerdissipation mW

Resolution Bits

Analog OutputVoltageV

Operating Temperature°C

OutputLoadCapacitorpF

OutputLoadResistorΩ

IntegralNon-LinearityErrorLSB

DifferentialNon-LinearityErrorLSB

MaximumConversion RateMHz

VOLTAGEOUTPUTDAC

Reference VoltageTOP

BOTTOMV

Analog OutputVoltageRangeV

DigitalInputFormatBinaryCodeor2'sComplementCode

CURRENTOUTPUTDAC

Analog OutputMaximumCurrentmA

Analog OutputMaximumSignalFrequencyMHz

Reference VoltageV

ExternalResistor forCurrentSetting(RSET)Ω

PipelineDelaysec

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HISTORY CARD

VersionDateModifiedItemsComments

Ver2.0 01.06.21

ModifiedVersion

DAC1267X wasdevelopedfor12bit 40MHzDAC,but testresult

didn'tmeet12bit performance.So,thespecificationsofDAC1267X

aremodifiedto 9bit 40MHzDACand datasheet isalsomodified.

Ver2.1 01.07.04 ModifiedVersion

Typo and wrong information are corrected.

Ver2.2 01.07.05 Typo correction.

Ver2.3 01.07.09 ModifiedVersion

NewlyUpdated

Ver2.4 02.04.22 PhantomCell information update