SEMICONDUCTOR
6-7
Features
• Complete 12-Bit A/D Con verter with Reference and Clock
• Full 8-Bit, 12-Bit or 16-Bit Micr opr ocessor Bus Interface
• Bus Access Time. . . . . . . . . . . . . . . . . . . . . . . . . .150ns
• No Missing Codes Over Temperature
• Minimal Setup Time for Control Signals
• Fast Conversion Times
- HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs
- HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs
- HI-774 (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9µs
• Digital Error Correction (HI-774)
• Low Noise, via Current-Mode Signal
Transmission Between Chips
• Byte Enable/Short Cycle (AO Input)
- Guaranteed Break-Before-Make Action, Eliminating
Bus Contention During Read Operation. Latched by
Start Convert Input (To Set the Con ver sion Length)
• Supply Voltage . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
Applications
• Military and Industrial Data Acquisition Systems
• Electronic Test and Scientific Instrumentation
• Process Control Systems
Description
The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state out-
puts and a digital interface for microprocessor control. Succes-
sive approximation conversion is performed by two monolithic
dice housed in a 28 lead package. The bipolar analog die fea-
tures the Harris Dielectric Isolation process, which provides
enhanced A C perf ormance and freedom from latch-up .
Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.
The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.
Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A/674A) and 390mW (HI-774) at
12V. All models are available in sidebrazed DIP, PDIP, and
CLCC . For additional HI-Rel screening including 160 hour b urn-
in, specify “-8” suffix. F or MIL-STD-883 compliant parts, request
HI-574A/883, HI-674A/883, and HI-774/883 data sheets.
Pinouts
(PDIP, SBDIP)
TOP VIEW (CLCC)
TOP VIEW
STATUS, STS
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DIG COMMON,
DIGITAL
DATA
OUTPUTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CHIP ENABLE, CE
+10V REF, REF OUT
REFERENCE INPUT
20V INPUT
ANALOG
COMMON, A C
+12V/+15V SUPPLY, VCC
BYTE ADDR/SHORT
CYCLE, A O
10V INPUT
+5V SUPPLY, VLOGIC
CHIP SEL, CS
D ATA MODE SEL, 12/8
READ/CONVERT, R/C
BIPOLAR OFFSET
BIP OFF
-12V/-15V SUPPLY, VEE
MSB
LSB
DC
14
13
12
11
10
9
8
7
17
16
15
25
30
35
39
38
37
36
33
34
32
31
29
4
6 3
ANALOG COMMON, AC
NC
NC
NC
REFERENCE INPUT,
REF IN
+10V REFERENCE,
REF OUT
BIPOLAR OFFSET,
BIP OFF
NC
NC
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
NC
NC
NC
STATUS, STS
DB11, MSB
DB10
BYTE ADDRESS/
NC
NC
1
10V
20V
NC
NC
NC
NC
NC
(LSB) DB0
DC
DIG
DB1
NC
CHIP SELECT, CS
CHIP ENABLE, CE
+15V SUPPLY, VCC
40414243
44
2827262524232221201918
DATA MODE
-15V SUPPLY, VEE
READ CONVERT, R/C
SHORT CYCLE, AO
+5V SUPPLY, VLOGI
C
SELECT, 12/8
COMMON,
August 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
HI-574A, HI-674A,
HI-774
Complete, 12-Bit A/D Converters
with Microprocessor Interface
File Number 3096.4
6-8
Ordering Information
PART NUMBER INL TEMPERATURE RANGE
(oC) PACKAGE PKG. NO .
HI3-574AJN-5 ±1.0 LSB 0 to 75 28 Ld PDIP E28.6
HI3-574AKN-5 ±0.5 LSB 0 to 75 28 Ld PDIP E28.6
HI3-574ALN-5 ±0.5 LSB 0 to 70 28 Ld PDIP E28.6
HI1-574AJD-5 ±1.0 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-574AKD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-574ALD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-574ASD-2 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574ATD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574AUD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574ASD/883 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574ATD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-574AUD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI4-574ASE/883 ±1.0 LSB -55 to 125 44 Ld CLCC J44.A
HI4-574ATE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI4-574AUE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI3-674AJN-5 ±1.0 LSB 0 to 75 28 Ld PDIP E28.6
HI3-674AKN-5 ±0.5 LSB 0 to 75 28 Ld PDIP E28.6
HI3-674ALN-5 ±0.5 LSB 0 to 75 28 Ld PDIP E28.6
HI1-674AJD-5 ±1.0 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-674AKD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-674ALD-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-674ASD-2 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674ATD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674AUD-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674ASD/883 ±1.0 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674ATD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-674AUD/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI4-674ASE/883 ±1.0 LSB -55 to 125 44 Ld CLCC J44.A
HI4-674ATE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI4-674AUE/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI3-774J-5 ±1.0 LSB 0 to 75 28 Ld PDIP E28.6
HI3-774K-5 ±0.5 LSB 0 to 75 28 Ld PDIP E28.6
HI1-774J-5 ±1.0 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-774K-5 ±0.5 LSB 0 to 75 28 Ld SBDIP D28.6
HI1-774U-2 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI1-774T/883 ±0.5 LSB -55 to 125 28 Ld SBDIP D28.6
HI4-774S/883 ±1.0 LSB -55 to 125 44 Ld CLCC J44.A
HI4-774T/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI4-774U/883 ±0.5 LSB -55 to 125 44 Ld CLCC J44.A
HI-574A, HI-674A, HI-774
6-9
Functional Block Diagram
BIT OUTPUTS
MSB LSB
NIBBLE B (NOTE) NIBBLE C (NOTE)NIBBLE A (NOTE)
POWER-UP RESET
THREE-STATE BUFFERS AND CONTROL
12 BITS
SAR
STROBE
DIGITAL CHIP
CONTROL
CLK
OSCILLATOR
LOGIC
ANALOG CHIP
DAC
10K
+10V
REF -
+5K
5K
5K
2.5K
10V
INPUT
20V
INPUT
BIP
OFF
ANALOG
COMMON
COMP
-
+
12/8
CS
AO
R/C
CE
VREF IN
VREF OUT
VLOGIC
DIGITAL
COMMON
STS
VCC
VEE
10K
NOTE: “Nibble” is a 4-bit digital word.
12 BITS
HI-574A, HI-674A, HI-774
6-10
Absolute Maximum Ratings Thermal Information
Supply Voltage
VCC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V
VEE to Digital Common. . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V
VLOGIC to Digital Common. . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Analog Common to Digital Common±1V
Control Inputs
(CE, CS , A O, 12/8, R/C) to Digital Common . . -0.5V to VLOGIC +0.5V
Analog Inputs
(REFIN, BIPOFF, 10VIN) to Analog Common. . . . . . . . . . ±16.5V
20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V
REFOUT . . . . Indefinite Short To Common, Momentary Short To VCC
Operating Conditions
Temperature Range
HI3-574AxN-5, HI1-574AxD-5 . . . . . . . . . . . . . . . . . .0oC to 75oC
HI3-674AxN-5, HI1-674AxD-5 . . . . . . . . . . . . . . . . . .0oC to 75oC
HI3-774xN-5, HI1-774xD-5. . . . . . . . . . . . . . . . . . . . .0oC to 75oC
HI1-574AxD-2, HI1-674AxD-2, HI1-774xD-2 . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CLCC Package . . . . . . . . . . . . . . . . . . 65 14
SBDIP Package. . . . . . . . . . . . . . . . . . 60 18
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5 65 N/A
Maximum Junction Temperature
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . . . . . . . . 150oC
HI1-574AxD-2, HI1-574AxD-5. . . . . . . . . . . . . . . . . . . . . . . 175oC
HI1-674AxD-2, HI1-674AxD-5. . . . . . . . . . . . . . . . . . . . . . . 175oC
HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . .-40oC to 85oC
HI1-574AxD-2, HI1-574AxD-5. . . . . . . . . . . . . . . .-65oC to 150oC
HI1-674AxD-2, HI1-674AxD-5. . . . . . . . . . . . . . . .-65oC to 150oC
HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Die Characteristics
Transistor Count
HI-574A, HI-674A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
HI-774 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117
DC and Transfer Accuracy Specifications Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified
PARAMETER
TEMPERATURE RANGE
-5 (0oC to 75oC)
UNITSJ SUFFIX K SUFFIX L SUFFIX
DYNAMIC CHARACTERISTICS
Resolution (Max) 12 12 12 Bits
Linearity Error
25oC (Max) ±1±1/2±1/2LSB
0oC to 75oC (Max) ±1±1/2±1/2LSB
Max Resolution For Which No Missing Codes Is Guaranteed
25oC HI-574A, HI-674A 12 12 12 Bits
HI-774 11 12 12 Bits
TMIN to TMAX HI-574A, HI-674A 11 12 12 Bits
HI-774 11 12 12 Bits
Unipolar Offset (Max)
Adjustable to Zero ±2±1.5 ±1 LSB
Bipolar Offset (Max)
VIN = 0V (Adjustable to Zero) ±4±4±3 LSB
VIN = -10V ±0.15 ±0.1 ±0.1 % of FS
Full Scale Calibration Error
25oC (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable to Zero) ±0.25 ±0.25 ±0.15 % of FS
TMIN to TMAX (No Adjustment At 25oC) ±0.475 ±0.375 ±0.20 % of FS
TMIN to TMAX (With Adjustment To Zero 25oC) ±0.22 ±0.12 ±0.05 % of FS
HI-574A, HI-674A, HI-774
6-11
Temperature Coefficients
Guaranteed Max Change, TMIN to TMAX (Using Internal Reference)
Unipolar Offset HI-574A, HI-674A ±2±1±1 LSB
HI-774 ±2±1±1 LSB
Bipolar Offset HI-574A, HI-674A ±2±1±1 LSB
HI-774 ±2±2±1 LSB
Full Scale Calibration HI-574A, HI-674A ±9±2±2 LSB
HI-774 ±9±5±2 LSB
Power Supply Rejection
Max Change In Full Scale Calibration
+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V ±2±1±1 LSB
+4.5V < VLOGIC < +5.5V ±1/2±1/2±1/2LSB
-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V ±2±1±1 LSB
ANALOG INPUTS
Input Ranges
Bipolar -5 to +5 V
-10 to +10 V
Unipolar 0 to +10 V
0 to +20 V
Input Impedance
10V Span 5K, ±25% Ω
20V Span 10K, ±25% Ω
POWER SUPPLIES
Operating Voltage Range
VLOGIC +4.5 to +5.5 V
VCC +11.4 to +16.5 V
VEE -11.4 to -16.5 V
Operating Current
ILOGIC 7 Typ, 15 Max mA
ICC +15V Supply 11 Typ, 15 Max mA
IEE -15V Supply 21 Typ, 28 Max mA
Power Dissipation
±15V, +15V 515 Typ, 720 Max mW
±12V, +5V 385 Typ mW
Internal Reference Voltage
TMIN to TMAX +10.00 ±0.05 Max V
Output Current, Available For External Loads (External Load Should
Not Change During Conversion). 2.0 Max mA
DC and Transfer Accuracy Specifications Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued)
PARAMETER
TEMPERATURE RANGE
-5 (0oC to 75oC)
UNITSJ SUFFIX K SUFFIX L SUFFIX
HI-574A, HI-674A, HI-774
6-12
DC and Transfer Accuracy Specifications Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified
PARAMETER
TEMPERATURE RANGE
-2 (-55oC to 125oC)
UNITSS SUFFIX T SUFFIX U SUFFIX
DYNAMIC CHARACTERISTICS
Resolution (Max) 12 12 12 Bits
Linearity Error
25oC±1±1/2±1/2LSB
-55oC to 125oC (Max) ±1±1±1 LSB
Max Resolution For Which No Missing Codes Is Guaranteed
25oC HI-574A, HI-674A 12 12 12 Bits
HI-774 11 12 12 Bits
TMIN to TMAX HI-574A, HI-674A 11 12 12 Bits
HI-774 11 12 12 Bits
Unipolar Offset (Max)
Adjustable to Zero HI-574A, HI-674A ±2±1.5 ±1 LSB
HI-774 ±2±2±1 LSB
Bipolar Offset (Max)
VIN = 0V (Adjustable to Zero) ±4±4±3 LSB
VIN = -10V ±0.15 ±0.1 ±0.1 % of FS
Full Scale Calibration Error
25oC (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable To Zero) ±0.25 ±0.25 ±0.15 % of FS
TMIN to TMAX (No Adjustment At 25oC) ±0.75 ±0.50 ±0.275 % of FS
TMIN to TMAX (With Adjustment To Zero At 25oC) ±0.50 ±0.25 ±0.125 % of FS
Temperature Coefficients
Guaranteed Max Change, TMIN to TMAX (Using Internal Reference)
Unipolar Offset ±2±1±1 LSB
Bipolar Offset ±2±2±1 LSB
Full Scale Calibration ±20 ±10 ±5 LSB
Power Supply Rejection
Max Change In Full Scale Calibration
+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V ±2±1±1 LSB
+4.5V < VLOGIC < +5.5V ±1/2±1/2±1/2LSB
-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V ±2±1±1 LSB
ANALOG INPUTS
Input Ranges
Bipolar -5 to +5 V
-10 to +10 V
Unipolar 0 to +10 V
0 to +20 V
HI-574A, HI-674A, HI-774
6-13
Input Impedance
10V Span 5K, ±25% Ω
20V Span 10K, ±25% Ω
POWER SUPPLIES
Operating Voltage Range
VLOGIC +4.5 to +5.5 V
VCC +11.4 to +16.5 V
VEE -11.4 to -16.5 V
Operating Current
ILOGIC 7 Typ, 15 Max mA
ICC +15V Supply 11 Typ, 15 Max mA
IEE -15V Supply 21 Typ, 28 Max mA
Power Dissipation
±15V, +15V 515 Typ, 720 Max mW
±12V, +5V 385 Typ mW
Internal Reference Voltage
TMIN to TMAX +10.00 ±0.05 Max V
Output current, available for external loads (External load should not
change during conversion). 2.0 Max mA
Digital Specifications All Models, Over Full Temperature Range
PARAMETER MIN TYP MAX
Logic Inputs (CE, CS, R/C, AO, 412/8)
Logic “1” +2.4V - +5.5V
Logic “0” -0.5V - +0.8V
Current - ±0.1µA±5µA
Capacitance - 5pF -
Logic Outputs (DB11-DB0, STS)
Logic “0” (ISINK - 1.6mA) - - +0.4V
Logic “1” (ISOURCE - 500µA) +2.4V - -
Logic “1” (ISOURCE - 10µA) +4.5V - -
Leakage (High-Z State, DB11-DB0 Only) - ±0.1µA±5µA
Capacitance - 5pF -
Timing Specifications (HI-574A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL PARAMETER MIN TYP MAX UNITS
CONVERT MODE
tDSC STS Delay from CE - - 200 ns
DC and Transfer Accuracy Specifications Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued)
PARAMETER
TEMPERATURE RANGE
-2 (-55oC to 125oC)
UNITSS SUFFIX T SUFFIX U SUFFIX
HI-574A, HI-674A, HI-774
6-14
tHEC CE Pulse Width 50 - - ns
tSSC CS to CE Setup 50 - - ns
tHSC CS Low During CE High 50 - - ns
tSRC R/C to CE Setup 50 - - ns
tHRC R/C Low During CE High 50 - - ns
tSAC AO to CE Setup 0 - - ns
tHAC AO Valid During CE High 50 - - ns
tCConversion Time 12-Bit Cycle TMIN to TMAX 15 20 25 µs
8-Bit Cycle TMIN to TMAX 10 13 17 µs
READ MODE
tDD Access Time from CE - 75 150 ns
tHD Data Valid After CE Low 25 - - ns
tHL Output Float Delay - 100 150 ns
tSSR CS to CE Setup 50 - - ns
tSRR R/C to CE Setup 0 - - ns
tSAR AO to CE Setup 50 - - ns
tHSR CS Valid After CE Low 0 - - ns
tHRR R/C High After CE Low 0 - - ns
tHAR AO Valid After CE Low 50 - - ns
tHS STS Delay After Data Valid 300 - 1200 ns
Timing Specifications (HI-674A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL PARAMETER MIN TYP MAX UNITS
CONVERT MODE
tDSC STS Delay from CE - - 200 ns
tHEC CE Pulse Width 50 - - ns
tSSC CS to CE Setup 50 - - ns
tHSC CS Low During CE High 50 - - ns
tSRC R/C to CE Setup 50 - - ns
tHRC R/C Low During CE High 50 - - ns
tSAC AO to CE Setup 0 - - ns
tHAC AO Valid During CE High 50 - - ns
tCConversion Time 12-Bit Cycle TMIN to TMAX 91215µs
8-Bit Cycle TMIN to TMAX 6810µs
READ MODE
tDD Access Time from CE - 75 150 ns
tHD Data Valid After CE Low 25 - - ns
tHL Output Float Delay - 100 150 ns
Timing Specifications (HI-574A) 25oC, Note 2, Unless Otherwise Specified (Continued)
SYMBOL PARAMETER MIN TYP MAX UNITS
HI-574A, HI-674A, HI-774
6-15
tSSR CS to CE Setup 50 - - ns
tSRR R/C to CE Setup 0 - - ns
tSAR AO to CE Setup 50 - - ns
tHSR CS Valid After CE Low 0 - - ns
tHRR R/C High After CE Low 0 - - ns
tHAR AO Valid After CE Low 50 - - ns
tHS STS Delay After Data Valid 25 - 850 ns
Timing Specifications (HI-774) 25oC, Into a load with RL = 3kΩ and CL = 50pF, Note 2, Unless Otherwise Specified
SYMBOL PARAMETER MIN TYP MAX UNITS
CONVERT MODE
tDSC STS Delay from CE - 100 200 ns
tHEC CE Pulse Width 50 30 - ns
tSSC CS to CE Setup 50 20 - ns
tHSC CS Low During CE High 50 20 - ns
tSRC R/C to CE Setup 50 0 - ns
tHRC R/C Low During CE High 50 20 - ns
tSAC AO to CE Setup 0 0 - ns
tHAC AO Valid During CE High 50 30 - ns
tCConversion Time 12-Bit Cycle TMIN to TMAX (-5) - 8.0 9 µs
8-Bit Cycle TMIN to TMAX (-5) - 6.4 6.8 µs
12-Bit Cycle TMIN to TMAX (-2) - 9 11 µs
8-Bit Cycle TMIN to TMAX (-2) - 6.8 8.3 µs
READ MODE
tDD Access Time from CE - 75 150 ns
tHD Data Valid After CE Low 25 35 - ns
tHL Output Float Delay - 70 150 ns
tSSR CS to CE Setup 50 0 - ns
tSRR R/C to CE Setup 0 0 - ns
tSAR AO to CE Setup 50 25 - ns
tHSR CS Valid After CE Low 0 0 - ns
tHRR R/C High After CE Low 0 0 - ns
tHAR AO Valid After CE Low 50 25 - ns
tHS STS Delay After Data Valid - 90 300 ns
NOTES:
1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
2. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load.
Timing Specifications (HI-674A) 25oC, Note 2, Unless Otherwise Specified (Continued)
SYMBOL PARAMETER MIN TYP MAX UNITS
HI-574A, HI-674A, HI-774
6-16
Definitions of Specifications
Linearity Error
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs 1/2 LSB (1.22mV for 10V span) before
the first code transition (all zeros to only the LSB “on”). “Full
scale” is defined as a level 11/2 LSB beyond the last code tr an-
sition (to all ones). The de viation of a code from the true straight
line is measured from the middle of each particular code.
The HI-X74(A)K and L grades are guaranteed for maximum
nonlinearity of ±1/2 LSB. For these grades, this means that an
analog value which falls exactly in the center of a given code
width will result in the correct digital output code. Values nearer
the upper or lower tr ansition of the code width may produce the
next upper or lower digital output code. The HI-X74(A)J is
guaranteed to ±1 LSB max error. For this grade, an analog
value which falls within a given code width will result in either
the correct code for that region or either adjacent one.
Note that the linearity error is not user-adjustable.
Differential Linearity Error (No Missing Codes)
A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increas-
ing sequence as the analog input level is increased. Thus
e v ery code must hav e a finite width. F or the HI-X74(A)K and L
grades, which guarantee no missing codes to 12-bit resolu-
tion, all 4096 codes must be present over the entire operating
temperature ranges. The HI-X74(A)J grade guarantees no
missing codes to 11-bit resolution over temperature; this
means that all code combinations of the upper 11 bits must be
present; in practice v ery few of the 12-bit codes are missing.
Unipolar Offset
The first transition should occur at a le v el 1/2 LSB abov e analog
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset tempera-
ture coefficient specifies the maximum change of the transition
point ov er temper ature, with or without external adjustment.
Bipolar Offset
Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value 1/2 LSB below analog common. The bipolar
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over tempera-
ture.
Full Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111
1111) should occur for an analog value 11/2 LSB below the
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 2 and 3. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.
Pin Descriptions
PIN SYMBOL DESCRIPTION
1V
LOGIC Logic supply pin (+5V)
2 12/8 Data Mode Select - Selects between
12-bit and 8-bit output modes.
3CS Chip Select - Chip Select high disables
the device.
4A
O
Byte Address/Short Cycle - See Table
1 for operation.
5R/
C Read/Convert - See Table 1 for
operation.
6 CE Chip Enable - Chip Enable low disables
the device.
7V
CC Positive Supply (+12V/+15V)
8 REF OUT +10V Reference
9 AC Analog Common
10 REF IN Reference Input
11 VEE Negative Supply (-12V/-15V).
12 BIP OFF Bipolar Offset
13 10V Input 10V Input - Used for 0V to 10V and -5V
to +5V input ranges.
14 20V Input 20V Input - Used for 0V to 20V and -10V
to +10V input ranges.
15 DC Digital Common
16 DB0 Data Bit 0 (LSB)
17 DB1 Data Bit 1
18 DB2 Data Bit 2
19 DB3 Data Bit 3
20 DB4 Data Bit 4
21 DB5 Data Bit 5
22 DB6 Data Bit 6
23 DB7 Data Bit 7
24 DB8 Data Bit 8
25 DB9 Data Bit 9
26 DB10 Data Bit 10
27 DB11 Data Bit 11 (MSB)
28 STS Status Bit - Status high implies a
conv ersion is in prog ress.
HI-574A, HI-674A, HI-774
6-17
Temperature Coefficients
The temperature coefficients for full-scale calibration, unipo-
lar offset, and bipolar offset specify the maximum change
from the initial (25oC) value to the value at TMIN or TMAX.
Power Supply Rejection
The standard specifications for the HI-X74A assume use of
+5.00V and ±15.00V or ±12.00V supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.
Code Width
A fundamental quantity for A/D converter specifications is
the code width. This is defined as the range of analog input
values for which a given digital output code will occur. The
nominal value of a code width is equivalent to 1 least signifi-
cant bit (LSB) of the full scale range or 2.44mV out of 10V f or
a 12-bit ADC.
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.
Left-justified Data
The data format used in the HI-X74(A) is left-justified. This
means that the data represents the analog input as a frac-
tion of full-scale, ranging from 0 to . This implies a
binary point to the left of the MSB.
Applying the HI-X74(A)
For each application of this converter, the ground
connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must be
optimized to assure maximum performance. These areas
are re viewed in the following sections, along with basic oper-
ating modes and calibration requirements.
Physical Mounting and Layout Considerations
Layout
Unwanted, parasitic circuit components, (L, R, and C) can
make 12-bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.
The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vector board, will have an unpredictable effect on
accuracy.
In general, sensitiv e analog signals should be routed betw een
ground traces and kept well away from digital lines. If analog
and digital lines must cross, they should do so at right angles.
Power Supplies
Supply voltages to the HI-X74(A) (+15V, -15V and +5V) must
be “quiet” and well regulated. Voltage spikes on these lines can
affect the conver ter’s accuracy, causing several LSBs to flicker
when a constant input is applied. Digital noise and spikes from
a switching power supply are especially troublesome. If switch-
ing supplies must be used, outputs should be carefully filtered
to assure “quiet” DC voltage at the con verter terminals.
Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (VLOGIC
supply), one from pin 7 to 9 (VCC to Analog Common) and
one from pin 11 to 9 (VEE to Analog Common). For each
capacitor pair, a 10µF tantalum type in parallel with a 0.1µF
ceramic type is recommended.
Ground Connections
Pins 9 and 15 should be tied together at the package to
guarantee specified performance for the converter. In
addition, a wide PC trace should run directly from pin 9 to
(usually) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the conv erter is located some distance from
the system’s “single point” ground, make only these connec-
tions to pins 9 and 15: Tie them together at the package, and
back to the system ground with a single path. This path
should have low resistance. (Code dependent currents flow in
the VCC, VEE and VLOGIC terminals, but not through the
HI-X74(A)’s Analog Common or Digital Common).
Analog Signal Source
HI-574A and HI-674A
The de vice chosen to drive the HI-X74A analog input will see a
nominal load of 5kΩ (10V range) or 10kΩ (20V range).
However, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in cur-
rent at the analog input. Thus, the signal source must maintain
its output voltage while furnishing these step changes in load
current, which occur at 1.6µs and 950ns intervals for the
HI-574A and HI-674A, respectively. This requires low output
impedance and f ast settling b y the signal source.
The output impedance of an op amp, for example, has an open
loop value which, in a closed loop, is divided by the loop gain
available at a frequency of interest. The amplifier should have
acceptable loop gain at 600KHz for use with the HI-X74A. To
check whether the output properties of a signal source are
suitable , monitor the HI-X74A’s input (pin 13 or 14) with an oscil-
loscope while a conversion is in progress. Each of the twelve
disturbances should subside in 1µs or less for the HI-574A and
500ns or less for the HI-674A. (The comparator decision is
made about 1.5µs and 850ns after each code change from the
SAR f or the HI-574A and HI-674A, respectively.)
If the application calls for a Sample/Hold to precede the
converter, it should be noted that not all Sample/Holds are
compatible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance . A simpler solution is to use the
Harris HA-5320 Sample/Hold, which was designed for use
with the HI-574A.
4095
4096
HI-574A, HI-674A, HI-774
6-18
HI-774
The de vice driving the HI-774 analog input will see a nominal
load of 5kΩ (10V range) or 10kΩ (20V range). However, the
other end of these input resistors may change as much as
±400mV with each bit decision. These input disturbances
are caused by the internal DAC changing codes which
causes a glitch on the summing junction. This creates abrupt
changes in current at the analog input causing a “kick back”
glitch from the input. Because the algorithm starts with the
MSB, the first glitches will be the largest and get smaller as
the conversion proceeds. These glitches can occur at 350ns
intervals so an op amp with a low output impedance and f ast
settling is desirable. Ultimately the input must settle to within
the window of Figure 1 at the bit decision points in order to
achieve 12-bit accuracy.
The HI-774 differs from the most high-speed successive
approximation type ADC’s in that it does not require a high
perf ormance buff er or sample and hold. With error correction
the input can settle while the conversion is underway, but
only during the first 4.8µs. The input must be within 10.76%
of the final value when the MSB decision is made. This
occurs approximately 650ns after the conversion has been
initiated. Digital error correction also loosens the bandwidth
requirements of the buffer or sample and hold. As long as
the input “kick back” disturbances settle within the window of
Figure 1 the device will remain accurate. The combined
effect of settling and the “kick back” disturbances must
remain in the Figure 1 window.
If the design is being optimized for speed, the input device
should have closed loop bandwidth to 3MHz, and a low out-
put impedance (calculated by dividing the open loop output
resistance by the open loop gain). If the application requires
a high speed sample and hold the Harris HA-5330 or
HA-5320 are recommended.
In any design the input (pin 13 or 14) should be checked
during a conversion to make sure that the input stays within
the correctable window of Figure 1.
Digital Error Correction
HI-774
The HI-774 features the smart successive approximation
register (SSAR) which includes digital error correction. This
has the advantage of allo wing the initial input to vary within a
+31 to -32 LSB window about the final value. The input can
move during the first 4.8µs, after which it must remain stable
within ±1/2 LSB. With this feature a conversion can start
before the input has settled completely; however, it must be
within the window as described in Figure 1.
The conversion cycle starts by making the first 8-bit decisions
very quickly, allowing the internal DAC to settle only to 8-bit
accuracy. Then the converter goes through two error correc-
tion cycles. At this point the input must be stable within ±1/2
LSB. These cycles correct the 8-bit w ord to 12-bit accuracy f or
any errors made (up to +16 or -32 LSBs). This is up one count
or down two counts at 8-bit resolution. The converter then
continues to make the 4 LSB decisions, settling out to 12-bit
accuracy. The last four bits can adjust the code in the positive
direction by up to 15 LSBs. This results in a total correction
range of +31 to -32 LSBs. When an 8-bit conversion is per-
f ormed, the input must settle to within ±1/2 LSB at 8-bit resolu-
tion (which equals ±8 LSBs at 12-bit resolution).
With the HI-774 a conversion can be initiated before the
input has completely settled, as long as it meets the con-
straints of the Figure 1 window. This allows the user to star t
conversion up to 4.8µs earlier than with a typical analog to
digital converter. A typical successive approximation type
ADC must have a constant input during a conversion
because once a bit decision is made it is locked in and can-
not change.
FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs TIME
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. UNIPOLAR CONNECTIONS
32
16
8
0
-8
-16
-31
ALLOWABLE INPUT CHANGE
(LSBs AT 12-BIT RESOLUTION)
BIT DECISION POINTS
8-BIT CONVERSION
±1/2 LSB
~ 4.8µs
LAST BIT
DECISION
(12-BIT)
END OF
CONVERSION
(12 BIT)
MSB BIT DECISION
~ 650ns 12-BIT CONVERSION
12345678
CONVERSION TIME (µs)
INITIATED
10 REF IN
8 REF OUT
12 BIP OFF
13 10VIN
14 20VIN†
9 ANA
16-19
LOW BITS
20-23
MIDDLE BITS
24-27
HIGH BITS
STS 28
2 12/8
3CS
4A
O
5R/C
6CE
+5V 1
+15V 7
-15V 11
DIG COM 15
-15V
OFFSET
R1
100K +15V
GAIN
R2
100Ω
100K
100Ω
0V TO +10V
ANALOG
INPUTS
0V TO +20V
COM
HI-574A, HI-674A, HI-774
6-19
Range Connections and Calibration Procedures
The HI-X74(A) is a “complete” A/D converter, meaning it is
fully operational with addition of the power supply voltages, a
Start Convert signal, and a few external components as
shown in Figure 2 and Figure 3. Nothing more is required for
most applications.
Whether controlled by a processor or operating in the stand-
alone mode, the HI-X74(A) off ers four standard input ranges:
0V to +10V, 0V to +20V, ±5V and ±10V. The maximum errors
f or gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Pow er supply and g round connections ha ve been dis-
cussed in an earlier section.
Unipolar Connections and Calibration
Refer to Figure 2. The resistors shown (see Note) are for
calibration of offset and gain. If this is not required, replace
R2 with a 50Ω, 1% metal film resistor and remove the net-
work on pin 12. Connect pin 12 to pin 9. Then, connect the
analog signal to pin 13 for the 0V to 10V range, or to pin 14
for the 0V to 20V range. Inputs to +20V (5V over the power
supply) are no problem - the converter operates nor mally.
Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the mid-
point of an increment of analog input, as denoted by two
adjacent code changes. Nominal value of an increment is
one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an
adjustment is complete. Therefore, calibration is performed
in terms of the observable code changes instead of the
midpoint between code changes.
For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all 0’s. To do
this, apply an input of +1/2 LSB (+1.22mV for the 10V range;
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.
Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 11/2 LSBs below the nominal full scale (+9.9963V for
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.
Bipolar Connections and Calibration
Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiome-
ters R1 and R2 (see Note). If this isn’t required, either or
both pots ma y be replaced b y a 50Ω, 1% metal film resistor.
Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 f or a ±10V range. Calibration of offset and gain is sim-
ilar to that for the unipolar ranges as discussed above. First
apply a DC input voltage 1/2 LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 f or flic k er between
output codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage 11/2 LSBs below positive full scale
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111.
NO TE: The 100Ω potentiometer R2 provides Gain Adjust f or the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these , replace R2 b y a 50Ω, 1% metal film resistor. Then, to pro-
vide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in
series with pin 13. For the 20.48V range, add a 500Ω potentiometer
in series with pin 14.
Controlling the HI-X74(A)
The HI-X74(A) includes logic for direct interface to most
microprocessor systems. The processor may take full con-
trol of each conversion, or the converter may operate in the
“stand-alone” mode, controlled only by the R/C input. Full
control consists of selecting an 8-bit or 12-bit conversion
cycle, initiating the conversion, and reading the output data
when ready-choosing either 12 bits at once or 8 f ollowed b y
4, in a left-justified format. The five control inputs are all
TTL/CMOS-compatible: (12/8, CS, AO, R/C and CE). Table
1 illustrates the use of these inputs in controlling the
converter’s operations. Also, a simplified schematic of the
internal control logic is shown in Figure 7.
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 3. BIPOLAR CONNECTIONS
16-19
LOW BITS
20-23
MIDDLE BITS
24-27
HIGH BITS
STS 28
+5V 1
+15V 7
-15V 11
DIG COM 15
GAIN
R2
100Ω
100Ω
±5V
ANALOG
INPUTS
±10V
OFFSET
10 REF IN
8 REF OUT
12 BIP OFF
13 10VIN
14 20VIN†
9 ANA
2 12/8
3CS
4A
O
5R/C
6CE
COM
R1
HI-574A, HI-674A, HI-774
6-20
“Stand-Alone Operation”
The simplest control interface calls for a singe control line
connected to R/C . Also, CE and 12/8 are wired high, CS and
AO are wired low, and the output data appears in words of
12 bits each.
The R/C signal may have any duty cycle within (and
including) the extremes shown in Figures 8 and 9. In gen-
eral, data may be read when R/C is high unless STS is also
high, indicating a conversion is in progress. Timing parame-
ters particular to this mode of operation are listed below
under “Stand-Alone Mode Timing”.
Conversion Length
A Convert Start transition (see Table 1) latches the state of
AO, which determines whether the conversion continues for
12 bits (A O lo w) or stops with 8 bits (AO high). If all 12 bits are
read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. AO is latched because it
is also involved in enabling the output buffers (see “Reading
the Output Data”). No other control inputs are latched.
Conversion Start
A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state star ts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-774 Timing Specifications, Convert Mode.
This variety of HI-X74(A) control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 4.
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high.
Reading the Output Data
The output data buffers remain in a high impedance state
until f our conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and AO. Timing constraints are
illustrated in Figure 5.
HI-574A STAND-ALONE MODE TIMING
SYMBOL PARAMETER MIN TYP MAX UNITS
tHRL Low R/C Pulse Width 50 - - ns
tDS STS Delay from R/C - - 200 ns
tHDR Data Valid after R/C Lo w 25 - - ns
tHS STS Delay after Data V alid 300 - 1200 ns
tHRH High R/C Pulse Width 150 - - ns
tDDR Data Access Time - - 150 ns
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
HI-674A STAND-ALONE MODE TIMING
SYMBOL PARAMETER MIN TYP MAX UNITS
tHRL Low R/C Pulse Width 50 - - ns
tDS STS Delay from R/C - - 200 ns
tHDR Data Valid after R/C Lo w 25 - - ns
tHS STS Delay after Data V alid 25 - 850 ns
tHRH High R/C Pulse Width 150 - - ns
tDDR Data Access Time - - 150 ns
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
HI-774 STAND-ALONE MODE TIMING
SYMBOL PARAMETER MIN TYP MAX UNITS
tHRL Low R/C Pulse Width 50 - - ns
tDS STS Delay from R/C - - 200 ns
tHDR Data Valid after R/C Lo w 20 - - ns
tHS STS Delay after Data V alid - - 850 ns
tHRH High R/C Pulse Width 150 - - ns
tDDR Data Access Time - - 150 ns
TABLE 1. TRUTH TABLE FOR HI-X74(A) CONTROL INPUTS
CE CS R/C 12/8A
OOPERATION
0XXXXNone
X 1 X X X None
↑0 0 X 0 Initiate 12-bit conversion
↑0 0 X 1 Initiate 8-bit conversion
1↓0 X 0 Initiate 12-bit conversion
1↓0 X 1 Initiate 8-bit conversion
10↓X 0 Initiate 12-bit conversion
10↓X 1 Initiate 8-bit conversion
1011XEnable 12-bit Output
10100Enable 8 MSBs Only
10101Enable 4 LSBs Plus 4 Trailing
Zeroes
HI-574A, HI-674A, HI-774
6-21
The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active sim ultaneously, f or interf ace to
a 12-bit or 16-bit data bus. The AO input is ignored.
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by AO. This allows an 8-bit data bus
to be connected as shown in Figure 6. AO is usually tied to
the least significant bit of the address bus, for storing the
HI-X74(A) output in two consecutive memory locations.
(With AO low, the 8 MSBs only are enabled. With AO high, 4
MSBs are disabled, bits 4 through 7 are f orced lo w, and the 4
LSBs are enabled). This two byte format is considered “left
justified data,” for which a decimal (or binary!) point is
assumed to the left of byte 1:
Further, AO may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 6 will never be enabled at the
same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (tDD + tHS)
before STS goes low. See Figure 5.
BYTE 1 BYTE 2
•XXXXXXXX XXXX0000
MSB LSB
See HI-774 Timing Specifications for more information.
FIGURE 4. CONVERT START TIMING
CE
CS
R/C
AO
STS
DB11-DB0
tSSC
tSRC
tHEC
tHSC
tSACtHAC
tDSC tC
HIGH IMPEDANCE
tHRC
See HI-774 Timing Specifications for more information.
FIGURE 5. READ CYCLE TIMING
FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS
CE
CS
R/C
AO
STS
DB11-DB0 HIGH IMPED ANCE
tSSR
tSRR
tSAR
tHS tHD
tHL
tDD
tHAR
tHRR
tHSR
DATA
VALID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STS
DB11 (MSB)
DB0 (LSB)
DIG.
COM.
HI-774
12/8
AO
AO
DATA
BUS
ADDRESS BUS
HI-574A, HI-674A, HI-774
6-22
FIGURE 7. HI-774 CONTROL LOGIC
FIGURE 8. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION
FIGURE 9. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z
D
CK
Q
Q
EOC13
EOC9
CE
R/C
AO
CS
12/8
INPUT BUFFERS
READ CONTROL
POWER UP
RESET
CONVERT
CONTROL
CURRENT
CONTROLLED
OSCILLATOR
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
NIBBLE C
STATUS
STROBE
CLOCK
RESET
AO LATCH
tHRL
tDS
tHDR
tC
tHS
R/C
STS
DB11-DB0 VALID
DATA VALID
DATA
tC
tHDR
tDDR
tHRH tDS
VALID
DATA
R/C
STS
DB11-DB0 HIGH-ZHIGH-Z
HI-574A, HI-674A, HI-774
6-23
Die Characteristics
DIE DIMENSIONS:
Analog: 3070mm x 4610mm
Digital: 1900mm x 4510mm
METALLIZATION:
Digital Type: Nitrox
Thickness: 10kű2kÅ
Metal 1: AlSiCu
Thickness: 8kű1kÅ
Metal 2: AlSiCu
Thickness: 16kű2kÅ
Analog Type: Al
Thickness: 16kű2kÅ
PASSIVATION:
Type: Nitride Over Silox
Nitride Thickness: 3.5kű0.5kÅ
Silox Thickness: 12kű1.5kÅ
WORST CASE CURRENT DENSITY:
1.3 x 105 A/cm2
Metallization Mask Layout
HI-574A, HI-674A, HI-774
ANALOG
COMMON
DB10
ANALOG
COMMON
ANALOG
COMMON
VREFIN
VEE
VREFOUT
VCC
CE
R/C
AO
CS
BIPOLAR
OFFSET
10V
IN
20V
IN
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB0
DB1
12/8
VLOGIC
STS
DB11
VLOGIC
DIGITAL
COMMON
HI-574A, HI-674A, HI-774
