SNJ54ACT573J - Texas Instruments High-Performance Analog

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D4.5-V to 5.5-V VCC Operation

DInputs Accept Voltages to 5.5 V

DMax tpd of 9.5 ns at 5 V

DInputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in a bus-organized system without need for

interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74ACT573N SN74ACT573N

SOIC DW

Tube SN74ACT573DW

ACT573

40°Cto85°C

SOIC − DW Tape and reel SN74ACT573DWR ACT573

−40°C to 85°CSOP − NS Tape and reel SN74ACT573NSR ACT573

SSOP − DB Tape and reel SN74ACT573DBR AD573

TSSOP − PW Tape and reel SN74ACT573PWR AD573

CDIP − J Tube SNJ54ACT573J SNJ54ACT573J

−55°C to 125°CCFP − W Tube SNJ54ACT573W SNJ54ACT573W

55 C

125 C

LCCC − FK Tube SNJ54ACT573FK SNJ54ACT573FK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

VCC

SN54ACT573 ...J OR W PACKAGE

SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

7Q 1Q

GND

VCC

SN54ACT573 . . . FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each latch)

INPUTS OUTPUT

OE LE D

OUTPUT

L H H H

LHL L

LLX Q

H X X Z

logic diagram (positive logic)

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through, VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54ACT573 SN74ACT573

UNIT

MIN MAX MIN MAX UNIT

VCC Supply voltage 4.5 5.5 4.5 5.5 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VIInput voltage 0 VCC 0 VCC V

VOOutput voltage 0 VCC 0 VCC V

IOH High-level output current −24 −24 mA

IOL Low-level output current 24 24 mA

Δt/ΔvInput transition rise or fall rate 8 8 ns/V

TAOperating free-air temperature −55 125 −40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25°C SN54ACT573 SN74ACT573

UNIT

PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT

I50 A

4.5 V 4.4 4.49 4.4 4.4

IOH = −50 μA5.5 V 5.4 5.49 5.4 5.4

I24 mA

4.5 V 3.86 3.7 3.76

VOH IOH = − 24 mA 5.5 V 4.86 4.7 4.76 V

IOH = −50 mA†5.5 V 3.85

IOH = −75 mA†5.5 V 3.85

I50 A

4.5 V 0.1 0.1 0.1

IOL = 50 μA5.5 V 0.1 0.1 0.1

I24 mA

4.5 V 0.36 0.44 0.44

VOL IOL = 24 mA 5.5 V 0.36 0.44 0.44 V

IOL = 50 mA†5.5 V 1.65

IOL = 75 mA†5.5 V 1.65

IOZ VO = VCC or GND 5.5 V ±0.25 ±5±2.5 μA

IIVI = VCC or GND 5.5 V ±0.1 ±1±1μA

ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA

ΔI‡

One input at 3.4 V,

55V

ΔICC‡

One

input

Other inputs at GND or VCC 5.5 V 0.6 1.5 1.5 mA

CiVI = VCC or GND 5 V 5 pF

†Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V

(unless otherwise noted) (see Figure 1)

TA = 25°C SN54ACT573 SN74ACT573

UNIT

MIN MAX MIN MAX MIN MAX UNIT

twPulse duration, LE high 3.5 5 4 ns

tsu Setup time, data before LE↓3 4.5 3.5 ns

thHold time, data after LE↓0 1 0 ns

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM TO TA = 25°C SN54ACT573 SN74ACT573

UNIT

PARAMETER

FROM

(INPUT)

(OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT

tPLH

2.5 6 10.5 1.5 13.5 2 12

tPHL

D Q 2.5 6 10.5 1.5 13.5 2 12 ns

tPLH

3 6 10.5 1.5 13 2.5 12

tPHL

LE Q 2.5 5.5 9.5 1.5 12 2 10.5 ns

tPZH

2 5.5 10 1.5 11.5 1.5 11

tPZL

OE Q1.5 5.5 9.5 1.5 11 1.5 10.5 ns

tPHZ

2.5 6.5 11 1.5 13.5 1.5 12.5

tPLZ

OE Q1.5 5 8.5 1.5 10.5 1 9.5 ns

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 25 pF

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

3 V

0 V

tsu

VOLTAGE WAVEFORMS

Data Input

tPLH tPHL

VOH

VOL

3 V

0 V

Input

Output

Timing Input

50% VCC

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

2 × VCC

500 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × VCC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50% VCC VOL + 0.3 V

50% VCC

≈0 V

Open

VOLTAGE WAVEFORMS

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2 × VCC

Open

TEST S1

3 V

0 V

VOLTAGE WAVEFORMS

Input

VOH − 0.3 V

3 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one input transition per measurement.

VOLTAGE WAVEFORMS

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-87664012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

87664012A

SNJ54ACT

573FK

5962-8766401RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8766401RA

SNJ54ACT573J

5962-8766401SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8766401SA

SNJ54ACT573W

SN74ACT573DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI -40 to 85

SN74ACT573DBR ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573DW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

SN74ACT573DWG4 ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

SN74ACT573DWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

SN74ACT573DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

SN74ACT573N ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ACT573N

SN74ACT573NE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ACT573N

SN74ACT573NSR ACTIVE SO NS 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

SN74ACT573NSRE4 ACTIVE SO NS 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

SN74ACT573NSRG4 ACTIVE SO NS 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ACT573

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN74ACT573PW ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85

SN74ACT573PWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SN74ACT573PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AD573

SNJ54ACT573FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

87664012A

SNJ54ACT

573FK

SNJ54ACT573J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8766401RA

SNJ54ACT573J

SNJ54ACT573W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8766401SA

SNJ54ACT573W

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 3

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ACT573, SN74ACT573 :

•Catalog: SN74ACT573

•Military: SN54ACT573

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74ACT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74ACT573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

SN74ACT573NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1

SN74ACT573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74ACT573DBR SSOP DB 20 2000 367.0 367.0 38.0

SN74ACT573DWR SOIC DW 20 2000 367.0 367.0 45.0

SN74ACT573NSR SO NS 20 2000 367.0 367.0 45.0

SN74ACT573PWR TSSOP PW 20 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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