AD9878BST - Analog Devices

Mixed-Signal Front End

for Broadband Applications

AD9878

FEATURES

Low cost 3.3 V CMOS MxFE™ for broadband

applications

DOCSIS, EURO-DOCSIS, DVB, DAVIC

compliant

232 MHz quadrature digital upconverter

12-bit direct IF DAC (TxDAC+™)

Up to 65 MHz carrier frequency DDS

Programmable sampling clock rates

Analog Tx output level adjust

Dual 12-bit, 29 MSPS direct IF ADCs

with video clamp input

10-bit, 29 MSPS sampling ADC

8-bit sigma-delta auxiliary DAC

Direct interface to AD8321/AD8323 or

AD8322/AD8327 PGA cable driver

APPLICATIONS

Cable set-top boxes

Cable and wireless modems

FUNCTIONAL BLOCK DIAGRAM

03277-0-001

–

TxDATA

Σ-∆_OUT

CA INT

MCLK

OSCIN

Rx10

Rx12B

VIDEO

Rx12A

CLAMP

LEVEL

SPORT

IF10[4:0]

IF12[11:0]

FLAG[2:1]

Tx 16

DDS

SINC

–1

Σ-∆

MUX

ADC

MUX

DAC

CONTROL REGISTERS

PLL

Figure 1. Functional Block Diagram

GENERAL DESCRIPTION

The AD9878 is a single-supply cable modem/set-top box

mixed-signal front end. The device contains a transmit path

interpolation filter, a complete quadrature digital upconverter,

and transmit DAC. The receive path contains dual 12-bit ADCs

and a 10-bit ADC. All internally required clocks and an output

system clock are generated by the PLL from a single crystal

oscillator or clock input.

The transmit path interpolation filter provides an upsampling

factor of 16× with an output signal bandwidth up to 5.8 MHz.

Carrier frequencies up to 65 MHz with 26 bits of frequency

tuning resolution can be generated by the direct digital

synthesizer (DDS). The transmit DAC resolution is 12 bits and

can run at sampling rates as high as 232 MSPS. Analog output

scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to

preserve SNR when reduced output levels are required.

The 12-bit ADCs provide excellent undersampling

performance, allowing this device to deliver better than 10

ENOBs with IF inputs up to 70 MHz. The 12-bit IF ADCs can

sample at rates up to 29 MHz, allowing them to process

wideband signals.

The AD9878 includes a programmable sigma-delta DAC, which

can be used to control an external component such as a variable

gain amplifier (VGA) or a voltage controlled tuner.

The AD9878 also integrates a CA port that enables a host

processor to interface with the AD8321/AD8323 or

AD8322/AD8327/AD8328 programmable gain amplifier (PGA)

cable drivers via the MxFE serial port (SPORT).

The AD9878 is available in a 100-lead LQFP package. The

AD9878 is specified over the extended industrial (–40°C to

+85°C) temperature range.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD9878

TABLE OF CONTENTS

SPECIFICATIONS ........................................................................... 3

ABSOLUTE MAXIMUM RATINGS............................................. 6

DEFINITIONS OF SPECIFICATIONS......................................... 7

TYPICAL PERFORMANCE CHARACTERISTICS................... 8

SERIAL INTERFACE FOR REGISTER CONTROL ................. 15

GENERAL OPERATION OF THE SERIAL INTERFACE... 15

INSTRUCTION BYTE .............................................................. 15

SERIAL INTERFACE PORT PIN DESCRIPTION ............... 15

MSB/LSB TRANSFERS ............................................................. 16

NOTES ON SERIAL PORT OPERATION............................. 16

THEORY OF OPERATION.......................................................... 17

TRANSMIT PATH..................................................................... 18

INTERPOLATION FILTER ..................................................... 18

DIGITAL UPCONVERTER..................................................... 19

CLOCK AND OSCILLATOR CIRCUITRY........................... 21

PROGRAMMABLE CLOCK OUTPUT REFCLK................ 22

RESET AND TRANSMIT POWER-DOWN......................... 23

RECEIVE PATH (Rx)................................................................ 24

PCB DESIGN CONSIDERATIONS........................................ 25

PIN CONFIGURATION AND PIN FUNCTION

DESCRIPTIOINS........................................................................... 27

OUTLINE DIMENSIONS ............................................................ 34

ORDERING GUIDE.................................................................. 34

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9878

SPECIFICATIONS

Table 1. ELECTRICAL CHARACTERISTICS

(VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC Clock Derived from OSCIN,

RSET = 4.02 kΩ, Max. Fine Gain, 75 Ω DAC Load.)

PARAMETER

Temp

Test

Level

Min

Typ

Max

Unit

OSCIN and XTAL CHARACTERISTICS

Frequency Range

Duty Cycle

Input Impedance

MCLK Cycle to Cycle Jitter (fMCLK derived from PLL)

Full

25ºC

III

100||3

MHz

MΩ||pF

ps rms

Tx DAC CHARACTERISTICS

Maximum Sample Rate

Resolution

Full-Scale Output Current

Gain Error (Using Internal Reference)

Offset Error

Reference Voltage (REFIO Level)

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

Output Capacitance

Phase Noise @ 1 kHz Offset, 42 MHz Carrier

Output Voltage Compliance Range

Wideband SFDR

5 MHz Analog Out, IOUT = 10 mA

65 MHz Analog Out, IOUT = 10 mA

Narrow-Band SFDR (±1 MHz Window)

5 MHz Analog Out, IOUT = 10 mA

65 MHz Analog Out, IOUT = 10 mA

Full

N/A

Full

25°C

Full

N/A

III

232

–2.5

–0.5

62.4

50.3

–1

±1.0

1.23

±2.5

±8

–110

53.5

+2.5

+1.5

MHz

Bits

% FS

LSB

dBc/Hz

Tx MODULATOR CHARACTERISTICS

I/Q Offset

Pass-Band Amplitude Ripple (f < fIQCLK/8)

Pass-Band Amplitude Ripple (f < fIQCLK/4)

Stop-Band Response (f > fIQCLK × 3/4)

Full

±0.1

±0.5

–63

Tx GAIN CONTROL

Gain Step Size

Gain Step Error

Settling Time, 1% (Full-Scale Step)

25°C

III

0.5

<0.05

1.8

µs

10-BIT ADC CHARACTERISTICS

Resolution

Maximum Conversion Rate

Pipeline Delay

Analog Input

Input Voltage Range

Differential Input Impedance

Full Power Bandwidth

Dynamic Performance (f = 5 MHz)

Signal-to-Noise and Distortion (SINAD)

Effective Number of Bits (ENOB)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

Reference Voltage Error, REFT10–REFB10 (1.0 V)

N/A

Full

N/A

Full

25°C

Full

N/A

III

57.6

9.2

65.7

4.5

4||2

59.7

9.6

–71.1

72.4

±4

–63.6

±200

Bits

MHz

ADC cycles

Vppd

kΩ||pF

MHz

Bits

Rev. 0 | Page 3 of 36

AD9878

PARAMETER

Temp

Test

Level

Min

Typ

Max

Unit

Dynamic Performance (f = 50 MHz)

Signal-to-Noise and Distortion (SINAD)

Effective Number of Bits (ENOB)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

Full

54.8

8.8

56.9

57.8

9.3

–63.3

63.7

–56.9

Bits

12-BIT ADC CHARACTERISTICS

Resolution

Maximum Conversion Rate

Pipeline Delay

Analog Input

Input Voltage Range

Differential Input Impedance

Aperture Delay

Aperture Uncertainty (Jitter)

Full Power Bandwidth

Input Referred Noise

Reference Voltage Error, REFT12–REFB12 (1 V)

Dynamic Performance (AIN = –0.5 dBFS, f = 5 MHz)

ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD)

Effective Number of Bits (ENOBs)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

ADC Sample Clock = PLL

Signal-to-Noise and Distortion (SINAD)

Effective Number of Bits (ENOBs)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

Dynamic Performance (AIN = –0.5 dBFS, f = 50 MHz)

ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD)

Effective Number of Bits (ENOB)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

Differential Phase

Differential Gain

N/A

Full

N/A

Full

25°C

Full

25ºC

N/A

III

–200

61.0

9.8

64.2

62.8

60.4

9.74

62.4

62.7

59.4

9.5

61.6

62.5

5.5

4||2

2.0

1.2

±16

10.8

–72.7

74.6

64.4

10.4

65.1

–72.7

74.6

62.9

10.1

63.7

–71.7

<0.1

+200

–61.7

–61.8

–61.5

Bits

MHz

ADC cycles

Vppd

kΩ||pF

ps rms

MHz

µV

Bits

Degrees

LSB

VIDEO ADC PERFORMANCE (f = 5 MHz)

ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

Full

46.7

54.3

45.9

63.2

–50.2

–45.9

Bits

Rev. 0 | Page 4 of 36

AD9878

Rev. 0 | Page 5 of 36

PARAMETER

Temp

Test

Level

Min

Typ

Max

Unit

CHANNEL-TO-CHANNEL ISOLATION

Tx DAC-to-ADC Isolation (5 MHz Analog Output)

Isolation between Tx and 10-Bit ADC

Isolation between Tx and 12-Bit ADCs

ADC-to-ADC Isolation

(AIN = –0.5 dBFS, f = 5 MHz)

Isolation between IF10 and IF12A/B

Isolation between IF12A and IF12B

25°C

III

>60

>80

>85

TIMING CHARACTERISTICS (10 pF LOAD)

Wake-Up Time

Minimum RESET Pulsewidth Low (tRL)

Digital Output Rise/Fall Time

Tx/Rx Interface

MCLK Frequency (fMCLK)

TxSYNC/TxIQ Setup Time (tSU)

TxSYNC/TxIQ Hold Time (tHD)

MCLK Rising Edge to RxSYNC Valid Delay (tMD)

OSCOUT Rising or Falling Edge to

RxSYNC Valid Delay (tOD)

OSCOUT Edge to MCLK Falling Edge (tEE)

N/A

Full

N/A

2.8

TOSC/4 – 2.0

–1.0

200

1.0

TOSC/4 + 3.0

+1.0

TMCLK cycles

tMCLK cycles

MHz

SERIAL CONTROL BUS

Maximum SCLK Frequency (fSCLK)

Minimum Clock Pulsewidth High (tPWH)

Minimum Clock Pulsewidth Low (tPWL)

Maximum Clock Rise/Fall Time

Minimum Data/Chip-Select Setup Time (tDS)

Minimum Data Hold Time (tDH)

Maximum Data Valid Time (tDV)

Full

MHz

µs

CMOS LOGIC INPUTS

Logic “1” Voltage

Logic “0” Voltage

Logic “1” Current

Logic “0” Current

Input Capacitance

25°C

III

VDRVDD – 0.7

0.4

µA

CMOS LOGIC OUTPUTS (1 mA Load)

Logic “1” Voltage

Logic “0” Voltage

25°C

VDRVDD – 0.6

0.4

POWER SUPPLY

Supply Current, IS (Full Operation)

Analog Supply Current IAS

Digital Supply Current IDS

Supply Current, IS

Standby (

PWRDN Pin Active)

Full Power-Down (Register 02 = 0xFF)

Power-Down Tx Path (Register 02 = 0x60)

Power-Down IF12 Rx Paths (Register 02 = 0x1B)

Power Supply Rejection (Differential Signal)

Tx DAC

10-Bit ADC

12-Bit ADC

25°C

III

184

105

124

131

<0.25

<0.0001

<0.0004

204

115

159

% FS

AD9878

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Power Supply (VAVDD, VDVDD, VDRVDD) 3.9 V

Digital Output Current 5 mA

Digital Inputs –0.3 V to VDRVDD + 0.3 V

Analog Inputs –0.3 V to VAVDD + 0.3 V

Operating Temperature –40°C to +85°C

Maximum Junction Temperature 150°C

Storage Temperature –65°C to +150°C

Lead Temperature (Soldering 10 sec) 300°C

Absolute maximum ratings are limiting values, to be applied

individually, and beyond which the serviceability of the circuit

may be impaired. Functional operability under any of these

conditions is not necessarily implied. Exposure to absolute

maximum rating conditions for extended periods of time may

affect device reliability.

EXPLANATION OF TEST LEVELS

I. Devices are 100% production tested at 25°C and guaranteed

by design and characterization testing for industrial operating

temperature range (–40°C to +85°C).

II. Parameter is guaranteed by design and/or characterization

testing.

III. Parameter is a typical value only.

N/A. Test level definition is not applicable.

THERMAL CHARACTERISTICS

Thermal Resistance:

100-Lead LQFP: θJA = 40.5°C/W

Rev. 0 | Page 6 of 36

AD9878

DEFINITIONS OF SPECIFICATIONS

Differential Nonlinearity Error (DNL, No Missing Codes)

An ideal converter exhibits code transitions that are exactly

1 LSB apart. DNL is the deviation from this ideal value.

Guaranteed no missing codes to 10-bit resolution indicates that

all 1,024 codes, respectively, must be present over all operating

ranges.

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code

from a line drawn from negative full scale through positive full

scale. The point used as negative full scale occurs ½ LSB before

the first code transition. Positive full scale is defined as a level

1½ LSB beyond the last code transition. The deviation is

measured from the middle of each particular code to the true

straight line.

Phase Noise

Single-sideband phase noise power is specified relative to the

carrier (dBc/Hz) at a given frequency offset (1 kHz) from the

carrier. Phase noise can be measured directly in single-tone

transmit mode with a spectrum analyzer that supports noise

marker measurements. It detects the relative power between the

carrier and the offset (1 kHz) sideband noise and takes the

resolution bandwidth (rbw) into account by subtracting 10 ×

log(rbw). It also adds a correction factor that compensates for

the implementation of the resolution bandwidth, log display,

and detector characteristic.

Output Compliance Range

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Spurious-Free Dynamic Range (SFDR)

The difference, in dB, between the rms amplitude of the DAC’s

output signal (or ADC’s input signal) and the peak spurious

signal over the specified bandwidth (Nyquist bandwidth, unless

otherwise noted).

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and

the associated output data being made available.

Offset Error

The first code transition should occur at an analog value ½ LSB

above negative full scale. Offset error is defined as the deviation

of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB

above negative full scale. The last transition should occur for an

analog value 1½ LSB below the nominal full scale. Gain error is

the deviation of the actual difference between first and last code

transitions and the ideal difference between first and last code

transitions.

Aperture Delay

The aperture delay is a measure of the Sample-and-Hold

Amplifier (SHA) performance that specifies the time delay

between the rising edge of the sampling clock input to when the

input signal is held for conversion.

Aperture Uncertainty (Jitter)

Aperture jitter is the variation in aperture delay for successive

samples and is manifested as noise on the input to the ADC.

Input Referred Noise

The rms output noise is measured using histogram techniques.

The ADC output codes’ standard deviation is calculated in LSB,

and converted to an equivalent voltage. This results in a noise

figure that can be directly referred to the input of the MxFE.

Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc. The

value for S/N+D is expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the

number of bits. Using the following formula, it is possible to get

a measure of performance expressed as

, the effective number

of bits:

= (

SINAD

– 1.76)

/6.02 Thus, the effective number

of bits for a device for sine wave inputs at a given input

frequency can be calculated directly from its measured SINAD.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal, and

is expressed as a percentage or in decibels.

Power Supply Rejection

Power supply rejection specifies the converter’s maximum full-

scale change when the supplies are varied from nominal to

minimum and maximum specified voltages.

Channel-to-Channel Isolation (Crosstalk)

In an ideal multichannel system, the signal in one channel will

not influence the signal level of another channel. The channel-

to-channel isolation specification is a measure of the change

that occurs in a grounded channel as a full-scale signal is

applied to another channel.

Rev. 0 | Page 7 of 36

AD9878

Rev. 0 | Page 8 of 36

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY – MHz

MAGNITUDE – dB

0 2 4 6 8 10 12 14 16 18

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-0-022

Figure 2. Dual Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,

RSET =10 kΩ (IOUT = 4 mA), RBW = 1 kHz

FREQUENCY – MHz

MAGNITUDE – dB

0 2 4 6 8 10 12 14 16 18

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-0-023

Figure 3. Dual Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,

RSET = 4 kΩ (IOUT = 10 mA), RBW=1 kHz

FREQUENCY – MHz

MAGNITUDE – dB

55 57 59 61 63 65 67 69 70 73

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-0-024

Figure 4. Dual Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz,

RSET =10 kΩ (IOUT = 4 mA), RBW = 1 kHz

FREQUENCY – MHz

MAGNITUDE – dB

55 57 59 61 63 65 67 69 71 73

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-0-025

Figure 5. Dual Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz,

RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz

FREQUENCY – MHz

MAGNITUDE – dB

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-0-026

Figure 6. Single Sideband @ 65 MHz, RBW = 2 kHz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA)

FREQUENCY – MHz

MAGNITUDE – dB

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-0-027

Figure 7. Single Sideband @ 65 MHz, RBW = 2 kHz, fC = 66 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA)

AD9878

FREQUENCY – MHz

MAGNITUDE – dB

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-0-028

Figure 8. Single Sideband @ 42 MHz, RBW = 2 kHz ,fC = 43 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA)

FREQUENCY – MHz

MAGNITUDE – dB

0 20406080100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-0-029

Figure 9. Single Sideband @ 42 MHz, RBW = 2 kHz, fC = 43 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA)

FREQUENCY – MHz

MAGNITUDE – dB

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-0-030

Figure 10. Single Sideband @ 5 MHz, RBW = 2 kHz, fC = 6 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA)

FREQUENCY – MHz

MAGNITUDE – dB

0 20406080100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-0-031

Figure 11. Single Sideband @ 5 MHz, RBW = 2 kHz, fC = 6 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA)

FREQUENCY – MHz

MAGNITUDE – dB

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

–90

–80

–70

–60

–50

–40

–30

–20

–10

2.5

03277-0-032

Figure 12. Single Sideband @ 65 MHz, RBW = 500 Hz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA)

FREQUENCY – MHz

MAGNITUDE – dB

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

–90

–80

–70

–60

–50

–40

–30

–20

–10

2.5

03277-0-033

Figure 13. Single Sideband @ 65 MHz, RBW = 500 Hz, fC = 66 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA)

Rev. 0 | Page 9 of 36

AD9878

FREQUENCY – MHz

MAGNITUDE – dB

–50 –40 –30 –20 –10 0 10 20 30 40

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-0-034

Figure 14. Single Sideband @ 65 MHz, RBW = 50 Hz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA)

MAGNITUDE – dB

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY – MHz

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

03277-0-035

Figure 15. Single Sideband @ 65 MHz, RBW = 10 Hz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA)

MAGNITUDE – dB

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY – MHz

0 5 10 15 20 25 30 35 40 45 50

03277-0-036

Figure 16. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz

MAGNITUDE – dB

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY – MHz

0 5 10 15 20 25 30 35 40 45 50

03277-0-037

Figure 17. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz

Rev. 0 | Page 10 of 36

AD9878

Rev. 0 | Page 11 of 36

Table 3. AD9878 Register Map

SDIO

Bidirectional LSB First Reset

OSC IN

Multiplier

M[4:0]

0x08

PLL

Lock

Detect

MCLK Divider

R[5:0]

0x00

Power Down

PLL

Power Down

DAC Tx

Power Down

Digital Tx

Power Down

ADC12A

Power Down

ADC12B

Power Down

ADC10

Power Down

Reference

ADC12A

Power Down

Reference

ADC12B

0x00

Video Input into

ADC12B Flag 2 Flag 1 Flag 0

Enable

0x00

Flag 0 Sigma-Delta Output Control Word [7:0]

0x00

Video Input

Enable

0x00

ADC Clocked

Direct from

OSCIN

Rx Port

Fast Edge Rate

Power Down

Rx Sync Gen

Power-Down

Reference

ADC10

Send

ADC12A Data

Only

Send

ADC12B Data

Only

0x80

0x00

Version [3:0]

0x00

Tx Frequency Tuning Word

Profile 1 LSBs [1:0]

Tx Frequency Tuning Word

Profile 0 LSBs [1:0]

0x00

DAC Fine Gain Control [3:0]

0x00

Tx Path

Select Profile 1

Tx Path

AD8321/3 Gain

Control Mode

Tx Path

Bypass

sinc–1 Filter

Tx Path

Spectral

Inversion

Tx Path

Transmit

Single Tone

0x00

Tx Path Frequency Tuning Word Profile 0 [9:2]

0x00

Tx Path Frequency Tunin g Word Profile 0 [17:10]

0x00

Tx Path Frequency Tuning Word Profile 0 [25:18]

0x00

Cable Driver Amplifier Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0]

0x00

Tx Path Frequency Tu ning Word Profile 1 [9:2]

0x00

Tx Path Frequency Tuning Word Profile 1 [17:10]

0x00

Tx Path Frequency Tuning Word Profile 1 [25:18]

0x00

Cable Driver Amplifier Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0]

0x00

Address

(hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default

(hex) Type

Read/Write00

Clamp Level for Vidio Input [6:0]

Read/Write

Read-Only

Read/Write

Bits 0 to 4: OSCIN Multiplier

This register field is used to program the on-chip multiplier

(PLL) that generates the chip’s high frequency system clock,

fSYSCLK. For example, to multiply the external crystal clock fOSCIN

by 16 decimal, program Register 0, Bits 4:0 as 0x10. The default

value of M is 0x08. Valid entries range from 1 to 31. When M is

chosen equal to 1, the PLL is disabled and all internal clocks are

derived directly from OSCIN. The PLL requires 200 MCLK

cycles to regain frequency lock after a change in M, the clock

multiplier value. After the recapture time of the PLL, the

frequency of fSYSCLK is stable.

AD9878

Rev. 0 | Page 12 of 36

Bit 5: Reset

Writing a 1 to this bit resets the registers to their default values

and restarts the chip. The Reset bit always reads back 0. The bits

in Register 0 are not affected by this software reset. However, a

low level at the RESET pin would force all registers, including

all bits in Register 0, to their default state.

Bit 6: LSB First

Active high indicates SPI serial port access of instruction byte

and data registers is least significant bit (LSB) first. Default low

indicates most significant bit (MSB) first format.

Bit 7: SDIO Bidirectional

Active high configures the serial port as a three signal port with

the SDIO pin used as a bidirectional input/output pin. Default

low indicates the serial port uses four signals with SDIO

configured as an input and SDO configured as an output.

Bits [5:0]: MCLK Divider.

This register determines the output clock on the OSCOUT pin.

At default 0 (R = 0), OSCOUT provides a buffered version of

the OSCIN clock signal for other chips. The register can also be

used to divide the chip’s master clock fMCLK by R, where R is an

integer number between 2 and 63. The generated reference

clock on OSCOUT pin can be used for external frequency

controlled devices.

Bit 7: PLL Lock Detect

When this bit is set low, the OSCOUT pin functions in its

default mode and provides an output clock with frequency

fMCKL/R as described above. If this bit is set to 1, the OSCOUT

pin is configured to indicate whether the PLL is locked to fOSCIN.

In this mode the OSCOUT pin should be low-pass filtered with

an RC filter of 1.0 kΩ and 0.1 µF. A high output on OSCOUT

indicates that the PLL has achieved lock with fOSCIN.

Sections of the chip that are not used can be powered down

when the corresponding bits are set high. This register has a

default value of 0x00; all sections active.

Bit 0: Power-Down ADC 12B Voltage Reference

Active high powers down the voltage reference circuit for

ADC12B.

Bit 1: Power-Down ADC12A Voltage Reference

Active high powers down the voltage reference circuit for

ADC12A.

Bit 2: Power-Down ADC10

Active high powers down the 10-bit ADC.

Bit 3: Power-Down ADC12B

Active high powers down the ADC12B.

Bit 4: Power-Down ADC12A

Active high powers down the ADC12A.

Bit 5: Power-Down Tx

Active high powers down the digital transmit section of the

chip, similar to the function of the PWRDN pin.

Bit 6: Power-Down DAC Tx

Active high powers down the DAC.

Bit 7: Power-Down PLL

Active high powers down the OSCIN multiplier.

Bit 0: Flag 0 Enable

Active high, the SDELTA pin will maintain a fixed logic level

determined directly by the MSB of the sigma-delta control word

of Register 4.

Bit 1: Flag 1

The logic level of this bit will be applied at the FLAG1 pin.

Bit 4: Flag 2

The logic level of this bit will be applied at the FLAG2 pin.

Bit 5: Video Input into ADC12B

If the video input is enabled, setting this bit high sends the

signal applied to the VIDEO IN pin to the ADC12B. Otherwise,

the signal applied to the VIDEO IN pin is sent to the ADC12A.

Bits [7:0]: Sigma-Delta Control Word

The sigma-delta control word is 8 bits wide and controls the

duty cycle of the digital output on the SIGDELT pin. Changes to

the sigma-delta control word take effect immediately for every

value of 0. The control words are in straight binary format with

0x00 corresponding to the bottom of scale or 0% duty cycle, and

0xFF corresponding to the top of scale or near 100% duty cycle.

AD9878

Rev. 0 | Page 13 of 36

ffse e

IBit 7: Flag 0 (Sigma-Delta Control Word MSB)

When the Flag 0 Enable bit (Register 3, Bit 0) is set, the logic

level of this bit will appear on the output of the SIGDELT pin.

Bits [6:0]: Clamp Level Control Value

The 7-bit clamp level control value is used to set an offset to the

automatic clamp level control loop. The actual ADC output will

have a clamp level offset equal to 16 times the clamp level

control value as shown:

Clamp Level O t Clamp L vel Control Value

= (x)16

The default value for the clamp level control value is 0x20. This

results in an ADC output clamp level offset of 512 LSBs. The

valid programming range for the clamp level control value is

from 0x16 to 0x127.

Bit 0: Send ADC12B Data Only

When this bit is set high, the device enters a nonmultiplexed

mode and only the data from the ADC12B will be sent to the

IF[11:0] digital output port.

Bit 1: Send ADC12A Data Only

When this bit is set high, the device enters a nonmultiplexed

mode and only the data from the ADC12A will be sent to the

IF[11:0] digital output port.

Note: If both the Send ADC12B Data Only and Send ADC12A

Data Only register bits are set high, the device will send both

ADC12A and ADC12B data in multiplexed mode.

Bit 3: Power-Down ADC10 Voltage Reference

Active high powers down the voltage reference circuit for

ADC10.

Bit 4: Power Down RxSYNC Generator

Setting this bit to 1 powers down the 10-bit ADC’s sampling

clock and makes the RxSYNC output pin stay low. It can be

used for additional power saving on top of the power-down

selections in Register 2.

Bit 5: Rx PORT Fast Edge Rate

Setting this bit to 1 increases the output drive strength of all

digital output pins except MCLK, REFCLK, SIGDELT, and

FLAG[2:1]. These pins always have high output drive capability.

Bit 7: ADC Clocked Directly from OSC N

When set high, the ADC sampling clock is derived directly from

the input clock at OSCIN. In this mode, the clock supplied to

the OSCIN pin should originate from an external crystal or low

jitter crystal oscillator. When this bit is low, the ADC sampling

clock is derived from the internal PLL and the frequency of the

clock is equal to fOSCIN × M/8.

Bits [3:0]: Version

The die version of the chip can be read from this register.

LSBS

This register accommodates the two least significant bits each

for both of the frequency tuning words. See the description of

the burst parameter below.

This register allows the user to program the DAC gain if the

TxGain Control Select Bit 3 in Register F is set to 0.

Bits [3:0] DAC Gain (dB)

0000 0.0 (default)

0001 0.5

0010 1.0

0011 1.5

… …

1110 7.0

1111 7.5

Bit 0: Single Tone Tx Mode

Active high configures the AD9878 for single-tone applications

(e.g., FSK). The AD9878 will supply a single frequency output as

determined by the frequency tuning word selected by the active

profile. In this mode, the TxIQ input data pins are ignored but

should be tied to a valid logic voltage level. Default value is 0

(inactive).

Bit 1: Spectral Inversion Tx

When set to 1, inverted modulation is performed:

MODULATOR_OUT

= [

cos (ω

) +

sin (ω

)].

Default is logic 0, non-inverted modulation:

MODULATOR_OUT

= [

cos (ω

) –

sin (ω

)].

AD9878

Rev. 0 | Page 14 of 36

Bit 2: Bypass Inv S nc Tx Filter i

Active high, configures the AD9878 to bypass the sin(x)/x

compensation filter. Default value is 0 (inverse sinc filter

enabled).

Bit 3: CA Interface Mode Select

This bit changes the manner in which transmit gain control is

performed. Typically either AD8321/AD8323 (default 0) or

AD8322/AD8327 (1) variable gain cable amplifiers are

programmed over the chip’s 3-wire CA interface. The Tx Gain

Control Select changes the interpretation of the bits in Registers

13, 17, 1B, and 1F. See the Cable Driver Gain Control section

below.

Bit 5: Profile Select

The AD9878 quadrature digital upconverter is capable of

storing two preconfigured modulation modes called profiles.

Each profile defines a transmit frequency tuning word and cable

driver amplifier gain (/DAC gain) setting. The Profile Select bit

or PROFILE pin programs the current register profile to be

used. The Profile Select bit should always be 0 if the PROFILE

pin is used to switch between profiles. Using the Profile Select

bit as a means of switching between different profiles requires

the PROFILE pin to be tied low.

REGISTERS 10 THROUGH 17: BURST PARAMETER

Tx Frequency Tun ng Words

The frequency tuning word (FTW) determines the DDS

generated carrier frequency (fC) and is formed via a

concatenation of register addresses.

The 26-bit FTW is spread over four register addresses. Bit 25 is

the MSB and Bit 0 is the LSB. The carrier frequency equation is

given as:

= (

FTW

fSYSCLK

)/226

where :

fSYSCLK = M × fOSCIN

, and

FTW <

0x2000

Changes to FTW bytes take effect immediately.

Cable Driver Gain Control

The AD9878 has a 3-pin interface to the AD832x family of

programmable gain cable driver amplifiers. This allows direct

control of the cable driver’s gain through the AD9878. In its

default mode, the complete 8-bit register value is transmitted

over the 3-wire cable amplifier (CA) interface. If Bit 3 of

determine the 8-bit word sent over the CA interface according

to the table below:

Bits [7:4] CA Interface Transmit Word

0000

0001

0010

0011

0100

0101

0110

0111

1000

0000 0000 (default)

0000 0001

0000 0010

0000 0100

0000 1000

0001 0000

0010 0000

0100 0000

1000 0000

In this mode the lower bits of Registers 0x13 and 0x17

determine the fine gain setting of the DAC output:

Bits [3:0] DAC Fine Gain (dB)

0000

0001

0010

0011

...

1110

1111

0.0 (default)

0.5

1.0

1.5

...

7.0

7.5

New data is automatically sent over the 3-wire CA interface

(and DAC gain adjust) whenever the value of the active gain

control register changes or a new profile is selected. The default

value is 0x00 (lowest gain).

The formula for the combined output level calculation of

AD9878 fine gain and AD8327 or AD8322 coarse gain is:

8327 =

9878(0) + (

fine

)/2 + (

coa e

) – 19

8322 =

9878(0) + (

fine

)/2 + (

coa e

) – 14

where:

fine

= decimal value of Bits [3:0]

coar

= decimal value of Bits [7:4]

9878(0): Level at AD9878 output in dBmV for

fine

= 0.

8327: Level at output of AD8327 in dBmV.

8322: Level at output of AD8322 in dBmV.

AD9878

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9878 serial port is a flexible, synchronous serial

communications port that allows easy interface to many

industry standard microcontrollers and microprocessors. The

interface allows read/write access to all registers that configure

the AD9878. Single or multiple byte transfers are supported.

Also, the interface can be programmed to read words either

MSB first or LSB first. The AD9878’s serial interface port I/O

can be configured to have one bidirectional I/O (SDIO) pin or

two unidirectional I/O (SDIO/SDO) pins.

General Operation of the Serial Interface

There are two phases to a communication cycle with the

AD9878. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9878, coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9878 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication

cycle.

The Phase 1 instruction byte defines whether the upcoming

data transfer is read or write, the number of bytes in the data

transfer, and the starting register address for the first byte of the

data transfer. The first eight SCLK rising edges of each

communication cycle are used to write the instruction byte into

the AD9878.

The eight remaining SCLK edges are for Phase 2 of the

communication cycle. Phase 2 is the actual data transfer

between the AD9878 and the system controller. Phase 2 of the

communication cycle is a transfer of 1 to 4 data bytes as

determined by the instruction byte. Normally, using one multi-

byte transfer is the preferred method. However, single-byte data

transfers are useful to reduce CPU overhead when register

access requires one byte only. Registers change immediately

upon writing to the last bit of each transfer byte.

Instruction Byte

The instruction byte contains the following information:

MSB

16 15 14 13 12 11

LSB

R/W N1 N0 A4 A3 A2 A1 A0

The R/W bit of the instruction byte determines whether a read

or a write data transfer will occur after the instruction byte

write. Logic high indicates a read operation. Logic low indicates

a write operation. The [N1:N0] bits determine the number of

bytes to be transferred during the data transfer cycle. The bit

decodes are shown in Table 4. The timing diagrams are shown

in Figure 18 and Figure 19.

Table 4.

N1 N0 Description

0 0 Transfer 1 Byte

0 1 Transfer 2 Bytes

1 0 Transfer 3 Bytes

1 1 Transfer 4 Bytes

The Bits [A4:A0] determine which register is accessed during

the data transfer portion of the communications cycle. For

multibyte transfers, this address is the starting byte address. The

remaining register addresses are generated by the AD9878.

SCLK

INSTRUCTION BIT 7 INSTRUCTION BIT 6

SCLK

PWL

PWH

SDIO

03277-0-005

Figure 18. Timing Diagram for Register Write

SCLK

SDIO

SDO

DATA BIT N DATA BIT N

03277-0-006

Figure 19. Timing Diagram for Register Read

Serial Interface Port Pin Description

SCLK—Serial C ock

. The serial clock pin is used to synchronize

data transfers from the AD9878 and to run the serial port state

machine. The maximum SCLK frequency is 15 MHz. Input data

to the AD9878 is sampled on the rising edge of SCLK. Output

data changes on the falling edge of SCLK.

CS—Chip Select

. Active low input starts and gates a

communication cycle. It allows multiple devices to share a

common serial port bus. The SDO and SDIO pins go to a high

impedance state when CS

is high. Chip select should stay low

during the entire communication cycle.

SDIO—Seri l Da a I O

. Data is always written into the AD9878

on this pin. However, this pin can be used as a bidirectional data

line. The configuration of this pin is controlled by Bit 7 of

pin as unidirectional.

a t /

tSDO—Serial Da a Out

. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9878 operates in a single bidirectional I/O

mode, this pin does not output data and is set to a high

impedance state.

Rev. 0 | Page 15 of 36

AD9878

Rev. 0 | Page 16 of 36

MSB/LSB Transfers

The AD9878 serial port can support most significant bit (MSB)

first or least significant bit (LSB) first data formats (see Figure

20 and Figure 21). This functionality is controlled by the LSB

First bit in Register 0. The default mode is MSB First. When this

bit is set active high, the AD9878 serial port is in LSB First

format. In LSB First mode, the instruction byte and data bytes

must be written from the least significant bit to the most

significant bit. In LSB First mode, the serial port internal byte

address generator increments for each byte of the multibyte

communication cycle.

R/W N1 N0 A4 A3 A2 A1 A0 D7nD6nD20D10D00

D7nD6nD20D10D00

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO

SDO

03277-0-003

Figure 20. Serial Register Interface Timing, MSB First

D00D10D20D6nD7n

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO

SDO

A0 A1 A2 A3 A4 N0 N1 R/W D00D10D20D6nD7n

03277-0-004

Figure 21. Serial Register Interface Timing, LSB First

When this bit is set default low, the AD9878 serial port is in

MSB First format. In MSB First mode, the instruction byte and

data bytes must be written from the most significant bit to the

least significant bit. In MSB First mode, the serial port internal

byte address generator decrements for each byte of the

multibyte communication cycle.

When incrementing from 0x1F, the address generator changes

to 0x00. When decrementing from 0x00, the address generator

changes to 0x1F.

Notes on Serial Port Operation

The AD9878 serial port configuration bits reside in Bits 6 and 7

of Register Address 0x00. It is important to note that the

configuration changes immediately upon writing to the last bit

of the register. For multibyte transfers, writing to this register

may occur during the middle of the communication cycle.

Measures must be taken to compensate for this new

configuration for the remaining bytes of the current

communication cycle.

The same considerations apply when setting the Reset bit in

values, but the software reset does not affect the bits in Register

Address 0x00. It is recommended to use only single-byte

transfers when changing serial port configurations or initiating

a software reset. A write to Bits 1, 2, and 3 of Address 0x00 with

the same logic levels as Bits 7, 6, and 5 (bit pattern: XY1001YX

binary) allows the user to reprogram a lost serial port

configuration and to reset the registers to their default values. A

second write to Address 0x00 with the Reset bit low and the

serial port configuration as specified above (XY), reprograms

the OSCIN multiplier setting. A changed fSYSCLK frequency is

stable after a maximum of 200 fMCLK cycles (wake-up time).

AD9878

Rev. 0 | Page 17 of 36

THEORY OF OPERATION

For a general understanding of the AD9878, refer to Figure 22, a

block diagram of the device architecture. The device consists of

a transmit path, receive path, and auxiliary functions, such as a

PLL, a sigma-delta DAC, a serial control port, and a cable

amplifier interface.

The transmit path contains an interpolation filter, a complete

quadrature digital up-converter, an inverse sinc filter, and a

12-bit current output DAC.

The receive path contains a 10-bit ADC and a dual 12-bit ADC.

All internally required clocks and an output system clock are

generated by the PLL from a single crystal or clock input.

The 12-bit and 10-bit IF ADCs can convert direct IF inputs up

to 70 MHz and run at sample rates up to 33 MSPS. A video

input with an adjustable signal clamping level along with the

10-bit ADC allow the AD9878 to process an NTSC and a QAM

channel simultaneously.

The programmable sigma-delta DAC can be used to control

external components, such as variable gain amplifiers (VGAs)

or voltage controlled tuners. The CAPORT provides an

interface to the AD8321/AD8323 or AD8322/AD8327

programmable gain amplifier (PGA) cable drivers, enabling

host processor control via the MxFE serial port (SPORT).

TxIQ

TxSYNC

MCLK

REFCLK

A_POR

PROFILE

SPORT

IF10[4:0]

RxSYNC

IF12[11:0]

FSADJ

XTAL

OSCIN

Σ-∆_OUT

FLAG1

F10 INPUT

IF12B INPUT

VIDEO INPUT

AD9878

DATA

ASSEMBLER

QUADRATURE

MODULATOR

FIR LPF CIC LPF

COS

SIN

DAC GAIN CONTROL

PLL

OSCIN ×M

DDS

MUX

INTERFACE

PROFILE

SELECT

SERIAL

INTERFACE

÷4

SINC–1 MUX DAC

IF10

IF12

ADC

Rx PORT

Σ-∆INPUT REG

SINC–1

BYPASS

(

OSCIN

)

(

OSCIN

)

(

MCLK

)

MUX

12 ADC MUX IF12A INPUT

DAC

+–

CLAMP LEVEL

Σ-∆

÷R÷4

÷8

÷2÷2

÷2

(

IQCLK

)

(

SYSCLK

)

(

OSCIN

)

03277-0-007

Figure 22. AD9878 Block Diagram

AD9878

Rev. 0 | Page 18 of 36

MCLK

TxSYNC

TxIQ TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6]' TxI[5:0]' TxQ[11:6]' TxQ[5:0]' TxI[11:6]'' TxI[5:0]''

03277-0-008

Figure 23. Tx Timing Diagram

Transmit Path

The transmit path contains an interpolation filter, a complete

quadrature digital up-converter, an inverse sinc filter, and a

12-bit current output DAC. The maximum output current of

the DAC is set by an external resistor. The Tx output PGA

provides additional transmit signal level control. The transmit

path interpolation filter provides an up-sampling factor of 16

with an output signal bandwidth as high as 5.8 MHz. Carrier

frequencies up to 65 MHz with 26 bits of frequency tuning

resolution can be generated by the direct digital synthesizer

(DDS). The transmit DAC resolution is 12 bits and it can run at

sampling rates up to 232 MSPS. Analog output scaling from

0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when

reduced output levels are required.

DATA ASSEMBLER

The AD9878 data path operates on two 12-bit words, the I and

Q components, that form a complex symbol. The data assembler

builds the 24-bit complex symbols from four consecutive 6-bit

words read over the TxIQ [5:0] bus. These words are strobed

into the data assembler synchronous to the master clock

(MCLK). A high level on TxSYNC signals the start of a transmit

symbol. The first two 6-bit words of the symbol form the I

component; the second two 6-bit words form the Q component.

Symbol components are assumed to be in twos complement

format. The timing of the interface is fully described in the

Transmit Timing section. The I/Q sample rate fIQCLK puts a

bandwidth limit on the maximum transmit spectrum. This is

the familiar Nyquist limit (hereafter referred to as fNYQ) and is

equal to one-half fIQCLK.

TRANSMIT TIMING

The AD9878 provides a master clock MCLK and expects 6-bit

multiplexed TxIQ data on each rising edge (see Figure 23).

Transmit symbols are framed with the TxSYNC input. TxSYNC

high indicates the start of a transmit symbol. Four consecutive

6-bit data packages form a symbol (I MSB, I LSB, Q MSB, and

Q LSB).

INTERPOLATION FILTER

Once through the Data Assembler, the IQ data streams are fed

through a 4× FIR low-pass filter and a 4× Cascaded Integrator

Comb (CIC) low-pass filter. The combination of these two

filters results in the sample rate increasing by a factor of 16×. In

addition to the sample rate increase, the half-band filters

provide the low-pass filtering characteristic necessary to

suppress the spectral images between the original sampling

frequency and the new (16× higher) sampling frequency.

HALF-BAND FILTERS (HBFs)

HBF 1 and HBF 2 are both interpolating filters, each of which

doubles the sampling rate. Together, HBF 1 and HBF 2 have 26

taps and provide a factor of four increase in the sampling rate

(4 × fIQCLK or 8 × fNYQ).

In relation to phase response, both HBFs are linear phase filters.

As such, virtually no phase distortion is introduced within the

pass band of the filters. This is an important feature, as phase

distortion is generally intolerable in a data transmission system.

CASCADED INTEGRATOR COMB (CIC) FILTER

The CIC filter is configured as a programmable interpolator

and provides a sample rate increase by a factor of 4. The

frequency response of the CIC filter is given by:

))4(2(

)sin(

)4sin(

)( 

































−













−

COMBINED FILTER RESPONSE

The combined frequency response of the HBF and CIC filters

puts a limit on the input signal bandwidth that can be

propagated through the AD9878.The usable bandwidth of the

filter chain puts a limit on the maximum data rate that can be

propagated through the AD9878. A look at the pass-band detail

of the combined filter response (Figure 24) indicates that in

order to maintain an amplitude error of no more than 1 dB,

signal bandwidth is restricted to no more than about 60% of

fNYQ. Thus, in order to keep the bandwidth of the data in the flat

portion of the filter pass band, the user must oversample the

AD9878

Rev. 0 | Page 19 of 36

baseband data by at least a factor of two prior to presenting it to

the AD9878. Note that without oversampling, the Nyquist

bandwidth of the base-band data corresponds to fNYQ. As such,

the upper end of the data bandwidth will suffer 6 dB or more of

attenuation due to the frequency response of the digital filters.

Furthermore, if the baseband data applied to the AD9878 has

been pulse shaped, there is an additional concern. Typically,

pulse shaping is applied to the baseband data via a filter having

a raised cosine response. In such cases, an α value is used to

modify the bandwidth of the data where the value of α is such

that:

0 <

< 1.

A value of 0 causes the data bandwidth to correspond to the

Nyquist bandwidth. A value of 1 causes the data bandwidth to

be extended to twice the Nyquist bandwidth. Thus, with 2×

oversampling of the baseband data and α = 1, the Nyquist

bandwidth of the data will correspond with the I/Q Nyquist

bandwidth. As stated earlier, this results in problems near the

upper edge of the data bandwidth due to the frequency

response of the filters. The maximum value of α that can be

implemented is 0.45. This is because the data bandwidth

becomes:

NYQNYQ

725.0)1(2/1

+⋅

which puts the data bandwidth at the extreme edge of the flat

portion of the filter response.

If a particular application requires an α value between 0.45 and

1, then the user must oversample the baseband data by at least a

factor of four. Over the frequency range of the data to be

transmitted, the combined HB1, HB2, and CIC filter introduces

a worst-case droop of less than 0.2 dB.

FREQUENCY RELATIVE TO I/Q NYQ BW

MAGNITUDE – dB

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

–6

–5

–4

–3

–2

–1

1.0

03277-0-009

Figure 24. Cascaded Filter Pass Band

DIGITAL UPCONVERTER

The digital quadrature modulator stage following the CIC filters

is used to frequency shift (upconvert) the baseband spectrum of

the incoming data stream up to the desired carrier frequency.

The carrier frequency is controlled numerically by a direct

digital synthesizer (DDS). The DDS uses the internal system

clock (fSYSCLK) to generate the desired carrier frequency with a

high degree of precision. The carrier is applied to the I and Q

multipliers in quadrature fashion (90° phase offset) and

summed to yield a data stream that is the modulated carrier.

The modulated carrier becomes the 12-bit sample sent to the

DAC.

Tx SIGNAL LEVEL CONSIDERATIONS

The quadrature modulator itself introduces a maximum gain of

3 dB in signal level. To visualize this, assume that both the I data

and Q data are fixed at the maximum possible digital value,

Then the output of the modulator,

[

]

)sin()cos(

txtxz

−

03277-0-010

Figure 25. 16-Quadrature Modulation

It can be shown that |

| assumes a maximum value of

xxxz

=+=

(a gain of +3 dB). However, if the same

number of bits were used to represent the |

| values that were

used to represent the

values, an overflow would occur. To

prevent this possibility, an effective –3 dB attenuation is

internally implemented on the I and Q data path:

x//z

=+= 2121

The following example assumes a PK/rms level of 10 dB:

Maximum Symbol Componen Input Value =

±2047

LSBs –

0.2

±2000

LSBs

Maximum Complex Input RMS Value

2000

LSBs

–

Pk rms

(

)

= 1265 LSBs rms

The maximum complex input rms value calculation uses both I

and Q symbol components that add a factor of 2 (= 6 dB) to the

formula. Table 5 shows typical I-Q input test signals with

amplitude levels related to 12-bit full scale (FS).

AD9878

Table 5. I–Q Input Test Signals

Analog

Output Digital Input Input Level

Modulator

Output

Level

Single Tone

(fC – f)

I = cos(f)

Q = cos(f + 90°)

= –sin(f)

FS – 0.2 dB

FS – 3.0 dB

Single Tone

(fC + f)

I = cos(f)

Q = cos(f + 270°)

= +sin(f)

FS – 0.2 dB

FS – 3.0 dB

Dual Tone

(fC ± f)

I = cos(f) FS – 0.2 dB FS

Q = cos(f + 180°)

= –cos(f) or Q = +cos(f)

FS – 0.2 dB

Tx THROUGHPUT AND LATENCY

Data inputs affect the output fairly quickly but remain effective

due to the AD9878’s filter characteristics. Data transmit latency

through the AD9878 is easiest to describe in terms of fSYSCLK

clock cycles (4 × fMCLK). The numbers quoted are when an effect

is first seen after an input value change.

Latency of I/Q data entering the data assembler (AD9878 input)

to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles).

DC values applied to the data assembler input will take up to

176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle

at the DAC output.

Frequency hopping is accomplished via changing the PROFILE

input pin. The time required to switch from one frequency to

another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).

D/A CONVERTER

A 12-bit digital-to-analog converter (DAC) is used to convert

the digitally processed waveform into an analog signal. The

worst-case spurious signals due to the DAC are the harmonics

of the fundamental signal and their aliases (see the Analog

Devices DDS Tutorial at www.analog.com/dds). The conversion

process will produce aliased components of the fundamental

signal at

fSYSCLK ± fCARRIER

(

= 1, 2, 3). These are typically

filtered with an external RLC filter at the DAC output. It is

important for this analog filter to have a sufficiently flat gain

and linear phase response across the bandwidth of interest so as

to avoid modulation impairments. A relatively inexpensive

seventh order elliptical low-pass filter is sufficient to suppress

the aliased components for HFC network applications.

The AD9878 provides true and complement current outputs.

The full-scale output current is set by the RSET resistor at Pin 49

and the DAC Gain register. Assuming maximum DAC gain, the

value of RSET for a particular full-scale IOUT is determined using

the equation:

RSET

= 32

VDACRSET

IOUT

= 39.4/

IOUT

For example, if a full-scale output current of 20 mA is desired,

then RSET = (39.4/0.02), or approximately 2 kΩ.

The following equation calculates the full-scale output current

including the programmable DAC gain control.

IOUT

= 39.4/

RSET

× 10(–7.5 + 0.5

NGAIN

)/20

where

NGAIN

is the value of DAC Fine Gain Control[3:0].

The full-scale output current range of the AD9878 is 4 mA to

20 mA. Full-scale output currents outside of this range will

degrade SFDR performance. SFDR is also slightly affected by

output matching; that is, the two outputs should be terminated

equally for best SFDR performance. The output load should be

located as close as possible to the AD9878 package to minimize

stray capacitance and inductance. The load may be a simple

resistor to ground, an op amp current-to-voltage converter, or a

transformer-coupled circuit. It is best not to attempt to directly

drive highly reactive loads, such as an LC filter. Driving an LC

filter without a transformer requires that the filter be doubly

terminated for best performance; that is, the filter input and

output should both be resistively terminated with the

appropriate values. The parallel combination of the two

terminations will determine the load that the AD9878 sees for

signals within the filter pass band. For example, a 50 Ω

terminated input/output low-pass filter will look like a 25 Ω

load to the AD9878. The output compliance voltage of the

AD9878 is –0.5 V to +1.5 V. Any signal developed at the DAC

output should not exceed +1.5 V; otherwise signal distortion

will result. Furthermore, the signal may extend below ground as

much as 0.5 V without damage or signal distortion. The

AD9878 true and complement outputs can be differentially

combined for common-mode rejection using a broadband 1:1

transformer.

Using a grounded center tap results in signals at the AD9878

DAC output pins that are symmetrical about ground. As

previously mentioned, by differentially combining the two

signals, the user can provide some degree of common-mode

signal rejection.

A differential combiner might consist of a transformer or an op

amp. The object is to combine or amplify only the difference

between two signals and to reject any common—usually

undesirable—characteristic, such as 60 Hz hum or clock feed-

through that is equally present on both individual signals.

AD832x

AD9878

VARIABLE GAIN

CABLE DRIVER

AMPLIFIER

DAC

Ω

LOW-PASS

FILTER

CA_EN

CA_DATA

CA_CLK

03277-0-011

Figure 26. Cable Amplifier Connection

Rev. 0 | Page 20 of 36

AD9878

Connecting the AD9878 true and complement outputs to the

differential inputs of the programmable gain cable drivers

AD8321/AD8323 or AD8322/AD8327 (see Figure 26) provides

an optimized solution for the standard compliant cable modem

upstream channel. The cable driver’s gain can be programmed

through a direct 3-wire interface using the AD9878’s profile

registers.

PROGRAMMING THE AD8321/AD8323 OR

AD8322/AD8327 CABLE DRIVER AMPLIFIER

Programming the gain of the AD832x family of cable driver

amplifiers can be accomplished via the AD9878 cable amplifier

control interface. Two 8-bit registers within the AD9878 (one

per profile) store the gain value to be written to the serial 3-wire

port. Typically, either the AD8321/AD8323 or AD8322/AD8327

variable gain cable amplifiers are connected to the chip’s 3-wire

cable amplifier interface. The Tx Gain Control Select bit in

0x13, 0x17, 0x1B, and 0x1F. See Figure 27 and Cable Driver

Gain Control Register description.

CA ENABLE

CA_CLK

CA_DATA MSB

MCLK

LSB

03277-0-012

Figure 27. Cable Amplifier Interface Timing

Data transfers to the programmable gain cable driver amplifier

are initiated by four conditions:

1. Power-Up and Hardware Reset—Upon initial power-up and

every hardware reset, the AD9878 clears the contents of the

Gain Control registers to 0, which defines the lowest gain

setting of the AD832x. Thus, the AD9878 writes all 0s out of the

3-wire cable amplifier control interface.

2. Software Reset—Writing a 1 to Bit 5 of Address 0x00 initiates

a software reset. On a software reset, the AD9878 clears the

contents of the Gain Control registers to 0 for the lowest gain

and sets the Profile Select to 0. The AD9878 writes all 0s out of

the 3-wire cable amplifier control interface if the gain was on a

different setting (different from 0) before.

3. Change in Profile Selection—The AD9878 samples the

PROFILE input pin together with the two Profile Select bits and

writes to the AD832x Gain Control registers when a change in

profile and gain is determined. The data written to the cable

driver amplifier comes from the AD9878 Gain Control register

associated with the current profile.

4. Write to the AD9878 Cable Driver Amplifier Control

Registers—The AD9878 will write gain control data associated

with the current profile to the AD832x whenever the selected

AD9878 cable driver amplifier gain setting is changed. Once a

new stable gain value has been detected (48 to 64 MCLK cycles

after initiation) data write starts with CA_EN going low. The

AD9878 will always finish a write sequence to the cable driver

amplifier once it is started. The logic controlling data transfers

to the cable driver amplifier uses up to 200 MCLK cycles and

has been designed to prevent erroneous write cycles from ever

occurring.

OSCIN CLOCK MULTIPLIER

The AD9878 can accept either an input clock into the OSCIN

pin or a fundamental mode crystal across the OSCIN and XTAL

pins as the device’s main clock source. The internal PLL then

generates the fSYSCLK signal from which all other internal signals

are derived. The DAC uses fSYSCLK as its sampling clock. For DDS

applications, the carrier is typically limited to about 30% of

fSYSCLK. For a 65 MHz carrier, the system clock required is above

216 MHz. The OSCIN multiplier function maintains clock

integrity as evidenced by the AD9878 system’s excellent phase

noise characteristics and low clock-related spur in the output

spectrum.

External loop filter components consisting of a series resistor

(1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero

for the OSCIN multiplier PLL loop. The overall loop

performance has been optimized for these component values.

CLOCK AND OSCILLATOR CIRCUITRY

The AD9878’s internal oscillator generates all sampling clocks

from a simple, low cost, parallel resonance, fundamental

frequency quartz crystal. Figure 28 shows how the quartz

crystal is connected between OSCIN (Pin 61) and XTAL (Pin

60) with parallel resonant load capacitors as specified by the

crystal manufacturer. The internal oscillator circuitry can also

be overdriven by a TTL level clock applied to OSCIN with

XTAL left unconnected.

OSCIN = fMCLK × M

An internal phase-locked loop (PLL) generates the DAC

sampling frequency, fSYSCLK, by multiplying the OSCIN

frequency by M. The MCLK signal (Pin 23), fMCLK, is derived by

dividing fSYSCLK by 4.

SYSCLK = fOSCIN × M

MCLK = fOSCIN × M

An external PLL loop filter (Pin 57) consisting of a series

resistor and ceramic capacitor (Figure 28: R1 = 1.3 kΩ, C12 =

0.01 µF) is required for stability of the PLL. Also, a shield

surrounding these components is recommended to minimize

external noise coupling into the PLL’s voltage controlled

oscillator input (guard trace connected to AVDDPLL).

Rev. 0 | Page 21 of 36

AD9878

Figure 22 shows that ADCs are either sampled directly by a low

jitter clock at OSCIN or by a clock that is derived from the PLL

output. Operating modes can be selected in Register 8. Sampling

the ADCs directly with the OSCIN clock requires MCLK

programmed to be twice the OSCIN frequency.

PROGRAMMABLE CLOCK OUTPUT REFCLK

The AD9878 provides an auxiliary output clock on Pin 69,

REFCLK. The value of the MCLK divider bit field,

determines its output frequency as shown in the equations

REFCLK

fMCLK

, for

= 2 to 63

REFCLK

fOSCIN

, for

= 0

In its default setting (0x00 in Register 1), the REFCLK pin

provides a buffered output of

fOSCIN

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77

AVDD

AGND

VIDEO IN

AGND

IF12A+

IF12A–

AGND

AVDD

REFT12A

REFB12A

AVDD

AGND

IF12B+

IF12B–

AGND

AVDD

REFT12B

REFB12B

AVDD

AGND

AVDD10

AGND10

IF10+

IF10–

AGND

REFT10

REFB10

AGND10

AVDD10

DRVDD

DRGND

REFCLK

SIGDELT

FLAD(0)

FLAG(1)

CA_EN

CA_DATA

CA_CLK

DVDDOSC

C10

20pF

C11

20pF

C12

0.01µF

GUARD TRACE

1.3kΩ

OSCIN

XTAL

DGNDOSC

AGNDPLL

PLLFILT

AVDDPLL

DVDDPLL

DGNDPLL

AVDDTx

Tx+

Tx–

C13

0.1µFR

SET

4.02Ω

TxSYNC

(MSB) TxIQ(5)

TxIQ(4)

TxIQ(3)

TxIQ(2)

TxIQ(1)

TxIQ(0)

DVDD

DGND

DVDD

DGND

PROFILE

RESET

DVDD

DGND

SCLK

SDIO

SDO

DGNDTx

DVDDTx

PWRDN

REFIO

FSADJ

AGNDTx

DRGND

DRVDD

(MSB) IF12(11)

IF12(10)

IF12(9)

IF12(8)

IF12(7)

IF12(6)

IF12(5)

IF12(4)

IF12(3)

IF12(2)

IF12(1)

IF12(0)

(MSB) IF10(4)

IF10(3)

IF10(2)

IF10(1)

IF10(0)

RxSYNC

DRGND

DRVDD

MCLK

DVDD

DGND

AD9878

TOP VIEW

(Not to Scale)

0.1µF

CP2

10µF

0.1µF

CP1

10µF

0.1µF

CP1

10µF

03277-0-013

Figure 28. Basic Connection Diagram

Rev. 0 | Page 22 of 36

AD9878

RESET AND TRANSMIT POWER-DOWN

POWER-UP SEQUENCE

On initial power-up, the RESET pin should be held low until the

power supply is stable (see Figure 29). Once RESET is

deasserted, the AD9878 can be programmed over the serial

port. The on-chip PLL requires a maximum of 1 ms after the

rising edge of RESET or a change of the multiplier factor (M) to

completely settle. It is recommended that the PWRDN pin be

held low during the reset and PLL settling time. Changes to

ADC Clock Select (Register 0x08) or Sys Clock Divider N

(Register 0x01) should be programmed before the rising edge of

PWRDN. Once the PLL is frequency locked and after the

PWRDN

pin is brought high, transmit data can be sent reliably.

If the PWRDN pin cannot be held low throughout the reset and

PLL settling time period, then the Power-Down Digital Tx bit

or the PWRDN

pin should be pulsed after the PLL has settled.

This will ensure correct transmit filter initialization.

03277-0-014

1ms MIN.

5MCLK MIN.

RESET

PWRDN

Figure 29. Power-Up Sequence for Tx Data Path

RESET

To initiate hardware reset, the RESET

pin should be held low for

at least 100 ns. All internally generated clocks except OSCOUT

stop during reset. The rising edge of RESET resets the PLL clock

multiplier and reinitializes the programmable registers to their

default values. The same sequence as described above in the

Power-Up Sequence section should be followed after a reset or

change in M.

A software reset (writing a 1 into Bit 5 of Register 0x00) is

functionally equivalent to the hardware reset but does not force

TRANSMIT POWER-DOWN

A low level on the PWRDN pin stops all clocks linked to the

digital transmit data path and resets the CIC filter. Deasserting

PWRDN reactivates all clocks. The CIC filter is held in a reset

state for 80 MCLK cycles after the rising edge of PWRDN to

allow for flushing of the half-band filters with new input data.

Transmit data bursts should be padded with at least 20 symbols

of null data directly before the PWRDN pin is deasserted.

Immediately after the PWRDN pin is deasserted, the transmit

burst should start with a minimum of 20 null data symbols (see

Figure 30). This avoids unintended DAC output samples caused

by the transmit path latency and filter settling time.

Software Power-Down Digital Tx (Bit 5 in Register 0x02) is

functionally equivalent to the hardware PWRDN pin and takes

effect immediately after the last register bit has been written

over the serial port.

PWRDN

TxIQ

TxSYNC

20 NULL SYMBOLS DATA SYMBOLS 20 NULL SYMBOLS

00 00 00 00

5MCLK MIN.

03277-0-015

Figure 30. Timing Sequence to Flush Tx Data Path

SIGMA-DELTA OUTPUTS

The AD9878 contains an on-chip sigma-delta output that

provides a digital logic bit stream with an average duty cycle

that varies between 0% and (4095/4096)%, depending on the

programmed code, as shown in Figure 31.

000h

8 tMCLK

001h

002h

800h

FFFh

4096 ×8 tMCLK

8 tMCLK

4096 ×8 tMCLK

03277-0-016

Figure 31. Sigma-Delta Output Signals

This bit stream can be low-pass filtered to generate a

programmable dc voltage of:

= [(

Sigma-Delta Code

/4096) ×

where:

DRVDD

– 0.6 V

= 0.4 V

In cable modem set-top box applications, the output can be

used to control external variable gain amplifiers or RF tuners.

A simple single-pole RC low-pass filter provides sufficient

filtering (see Figure 32).

Rev. 0 | Page 23 of 36

AD9878

MCLK

DAC

CONTROL

WORD

TYPICAL: R = 50kΩ

C = 0.01µF

–3dB

= 1/(2πRC) = 318Hz

÷8

Σ-∆R

DC (V

TO V

)

03277-0-017

INPUT SIGNAL RANGE AND DIGITAL OUTPUT

CODES

The IF ADCs have differential analog inputs labeled IF+ and

IF–. The signal input, VAIN, is the voltage difference between the

two input pins, VAIN = VIF+ – VIF–. The full-scale input voltage

range is determined by the internal reference voltages, REFT

and REFB, which define the top and bottom of the scale. The

peak input voltage to the ADC is the difference between REFT

and REFB, which is 1 VPD. This results in the ADC full scale

input voltage range of 2 VPPD. The digital output code is straight

binary and is illustrated in Table 6.

Figure 32. Sigma-Delta RC Filter

In more demanding applications where additional gain, level

shift, or drive capability is required, a first or second order

active filter might be considered (see Figure 33). Table 6

IF12[11:0] Input Signal Voltage

111...111

111...110

...

100...001

100...000

011...111

...

000...001

000...000

VAIN ≥ +1.0 V

VAIN = +1.0 V – (1 LSB)

VAIN = +1.0 V – (2 LSB)

…

VAIN = 0 V + 1 LSB

VAIN = 0.0 V

VAIN = 0 V – 1 LSB

…

VAIN = –1.0 V + (2 LSB)

VAIN = –1.0 V

VAIN < –1.0 V

AD9878

SIGMA-DELTA

Σ-∆

OUT

OFFSET

OP250

TYPICAL: R = 50kΩ

C = 0.01µF

–3dB

= 1/(2πRC) = 318Hz

OUT

= (V

+ V

OFFSET

) (1 + R/R1)/2

03277-0-018

Figure 33. Sigma-Delta Active Filter with Gain and Offset

DRIVING THE INPUT

RECEIVE PATH (Rx) The IF ADCs have differential switched capacitor sample-and-

hold amplifier (SHA) inputs. The nominal differential input

impedance is 4.0 kΩ||3 pF. This impedance can be used as the

effective termination impedance when calculating filter transfer

characteristics and voltage signal attenuation from nonzero

source impedances. It should be noted, however, that for best

performance, additional requirements must be met by the signal

source. The SHA has input capacitors that must be recharged

each time the input is sampled. This results in a dynamic input

current at the device input, and demands that the source has

low (<50 Ω) output impedance at frequencies up to the ADC

sampling frequency. Also, the source must have settling to better

than 0.1% in <1/2 ADC CLK period.

The AD9878 includes three high speed, high performance

ADCs. The 10-bit and dual 12-bit direct IF ADCs deliver

excellent undersampling performance with input frequencies as

high as 70 MHz. The sampling rate can be as high as 33 MSPS.

The ADC sampling frequency can be derived directly from the

OSCIN signal or from the on-chip OSCIN multiplier. For

highest dynamic performance, it is recommended to choose an

OSCIN frequency that can be directly used as the ADC

sampling clock. Digital 12-bit ADC outputs are multiplexed to

one 12-bit bus, clocked by a frequency (fMCLK) of four times the

sampling rate. The IF ADCs use a multiplexer to a 12-bit

interface with an output word rate of fMCLK.

Another consideration for getting the best performance from

the ADC inputs is the dc biasing of the input signal. Ideally, the

signal should be biased to a dc level equal to the midpoint of the

ADC reference voltages, REFT12 and REFB12. Nominally, this

level will be 1.2 V. When ac-coupled, the ADC inputs will self-

bias to this voltage and require no additional input circuitry.

Figure 34 illustrates a recommended circuit that eases the

burden on the signal source by isolating its output from the

ADC input. The 33 Ω series termination resistors isolate the

amplifier outputs from any capacitive load, which typically

improves settling time. The series capacitors provide ac signal

coupling which ensures that the ADC inputs operate at the

IF10 AND IF12 ADC OPERATION

The IF10 and IF12 ADCs have a common architecture and

share many of the same characteristics from an applications

standpoint. Most of the information in the section below will be

applicable to both IF ADCs. Differences, where they exist, will

be highlighted.

Rev. 0 | Page 24 of 36

AD9878

optimal dc bias voltage. The shunt capacitor sources the

dynamic currents required to charge the SHA input capacitors,

removing this requirement from the ADC buffer. The values of

CC and CS should be calculated to get the correct HPF and LPF

corner frequencies.

AINP

AINN

33ΩC

33Ω

03277-0-019

Figure 34. Simple ADC Drive Configuration

RECEIVE TIMING

The AD9878 sends multiplexed data to the IF10 and IF12

outputs on every rising edge of MCLK. RxSYNC frames the

start of each IF10 data symbol. 10-bit and 12-bit ADCs are

completely read on every second MCLK cycle. RxSYNC is high

for every second 10-bit ADC data (if 10-bit ADC is not in

power-down mode).The Rx timing diagram is shown in Figure

35.

OSCOUT

MCLK

IF10 DAT

IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]

M/N = 2

IF10[9:5] IF10[4:0]

IF12A IF12B IF12B IF12B IF12A IF12B

RxSYNC

IF12 DAT

Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA)

M/N = 2

OSCOUT

IF12A OR IF12B IF12A OR IF12B

IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]

IF12A OR IF12B

MCLK

IF10 DAT

RxSYNC

IF DATA

Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC)

03277-0-020

Figure 35. Rx Port Timing

ADC VOLTAGE REFERENCES

The AD9878 has three independent internal references for its

10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are

designed for 2 V p-p input voltages with each of them having its

own internal reference. Figure 28 shows the proper connections

of the reference pins REFT and REFB. External references may

be necessary for systems that require high accuracy gain

matching between ADCs or for improvements in temperature

drift and noise characteristics. External references REFT and

REFB need to be centered at AVDD/2 with offset voltages as

specified:

REFT-10, -12: AVDD/2 + 0.5 V

REFB-10, -12: AVDD/2 – 0.5 V

A differential level of 1 V between the reference pins results in a

2 V p-p ADC input level AIN. Internal reference sources can be

powered down when external references are used (Register

Address 0x02).

VIDEO INPUT

For sampling video-type waveforms, such as NTSC and PAL

signals, the Video Input channel provides black level clamping.

Figure 36 shows the circuit configuration for using the Video

Channel input (Pin 98). An external blocking capacitor is used

with the on-chip video clamp circuit to level-shift the input

signal to a desired reference point. The clamp circuit

automatically senses the most negative portion of the input

signal, and adjusts the voltage across the input capacitor. This

forces the black level of the input signal to be equal to the value

programmed into the Clamp Level register (Register Address

0x07).Video Input can be multiplexed to the IF12A ADC

(default) or to the IF12B ADC by programming Register

Address 0x03.

2mA

IDEO INPU

0.1µF

CLAMP LEVEL +FS/2

CLAMP LEVEL

AD9878

OFFSET

BUFER

+–

DAC

ADC

LPF

CLAMP

LEVEL

03277-0-021

Figure 36. Video Clamp Circuit Input

PCB DESIGN CONSIDERATIONS

Although the AD9878 is a mixed-signal device, the part should

be treated as an analog component. The digital circuitry on-

chip has been specially designed to minimize the impact that

the digital switching noise will have on the operation of the

analog circuits. Following the power, grounding, and layout

recommendations in this section will help the user get the best

performance from the MxFE.

COMPONENT PLACEMENT

If the three following guidelines of component placement are

followed, chances for getting the best performance from the

MxFE are greatly increased.

Rev. 0 | Page 25 of 36

AD9878

Rev. 0 | Page 26 of 36

• First, manage the path of return currents flowing in the

ground plane so that high frequency switching currents from

the digital circuits do not flow on the ground plane under the

MxFE or analog circuits.

• Second, keep noisy digital signal paths and sensitive receive

signal paths as short as possible.

• Third, keep digital (noise generating) and analog (noise

susceptible) circuits as far away from each other as possible.

In order to best manage the return currents, pure digital circuits

that generate high switching currents should be closest to the

power supply entry. This will keep the highest frequency return

current paths short, and prevent them from traveling over the

sensitive MxFE and analog portions of the ground plane. Also,

these circuits should be generously bypassed at each device to

further reduce the high frequency ground currents. The MxFE

should be placed adjacent to the digital circuits, such that the

ground return currents from the digital sections will not flow in

the ground plane under the MxFE. The analog circuits should

be placed furthest from the power supply. The AD9878 has

several pins that are used to decouple sensitive internal nodes.

These pins are REFIO, REFB12A, REFT12A, REFB12B,

REFT12B, REFB10, and REFT10. The decoupling capacitors

connected to these points should have low ESR and ESL. The

capacitors should be placed as close to the MxFE as possible

and be connected directly to the analog ground plane. The

resistor connected to the FSADJ pin and the RC network

connected to the PLLFILT pin should also be placed close to the

device and connected directly to the analog ground plane.

POWER PLANES AND DECOUPLING

The AD9878 evaluation board (Figure 38 and Figure 39)

demonstrates a good power supply distribution and decoupling

strategy. The board has four layers: two signal layers, one

ground plane, and one power plane. The power plane is split

into a 3 VDD section that is used for the 3 V digital logic

circuits, a DVDD section that is used to supply the digital

supply pins of the AD9878, an AVDD section that is used to

supply the analog supply pins of the AD9878, and a VANLG

section that supplies the higher voltage analog components on

the board. The 3 VDD section will typically have the highest

frequency currents on the power plane and should be kept the

furthest from the MxFE and analog sections of the board.

The DVDD portion of the plane carries the current used to

power the digital portion of the MxFE to the device. This

should be treated similarly to the 3 VDD power plane and be

kept from going underneath the MxFE or analog components.

The MxFE should largely sit above the AVDD portion of the

power plane. The AVDD and DVDD power planes may be fed

from the same low noise voltage source; however, they should

be decoupled from each other to prevent the noise generated in

the DVDD portion of the MxFE from corrupting the AVDD

supply. This can be done by using ferrite beads between the

voltage source and DVDD, and between the source and AVDD.

Both DVDD and AVDD should have a low ESR, bulk

decoupling capacitor on the MxFE side of the ferrite as well as

low ESR, ESL decoupling capacitors on each supply pin (i.e., the

AD9878 requires 17 power supply decoupling capacitors). The

decoupling capacitors should be placed as close to the MxFE

supply pins as possible. An example of proper decoupling is

shown in the AD9878 evaluation board schematic (Figure 38

and Figure 39).

GROUND PLANES

In general, if the component placing guidelines discussed earlier

can be implemented, it is best to have at least one continuous

ground plane for the entire board. All ground connections

should be made as short as possible. This will result in the

lowest impedance return paths and the quietest ground

connections. If the components cannot be placed in a manner

that would keep the high frequency ground currents from

traversing under the MxFE and analog components, it may be

necessary to put current steering channels into the ground

plane to route the high frequency currents around these

sensitive areas. These current steering channels should be made

only when and where necessary.

SIGNAL ROUTING

The digital Rx and Tx signal paths should be kept as short as

possible. Also, these traces should have a controlled impedance

of about 50 Ω. This will prevent poor signal integrity and the

high currents that can occur during undershoot or overshoot

caused by ringing. If the signal traces cannot be kept shorter

than about 1.5 inches, then series termination resistors (33 Ω to

47 Ω) should be placed close to all signal sources. It is a good

idea to series terminate all clock signals at their source

regardless of trace length. The receive signals are the most

sensitive signals on the entire board. Careful routing of these

signals is essential for good receive path performance. The

IF+/IF– signals form a differential pair and should be routed

together as a pair. By keeping the traces adjacent to each other,

noise coupled onto the signals will appear as common mode

and will be largely rejected by the MxFE receive input. Keeping

the driving point impedance of the receive signal low and

placing any low-pass filtering of the signals close to the MxFE

will further reduce the possibility of noise corrupting these

signals.

AD9878

Rev. 0 | Page 27 of 36

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIOINS

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77

AVDD

AGND

VIDEO IN

AGND

IF12A+

IF12A–

AGND

AVDD

REFT12A

REFB12A

AVDD

AGND

IF12B+

IF12B–

AGND

AVDD

REFT12B

REFB12B

AVDD

AGND

AVDD10

AGND10

IF10+

IF10–

AGND

REFT10

REFB10

AGND10

AVDD10

DRVDD

DRGND

REFCLK

SIGDELT

FLAD(0)

FLAG(1)

CA_EN

CA_DATA

CA_CLK

DVDDOSC

OSCIN

XTAL

DGNDOSC

AGNDPLL

PLLFILT

AVDDPLL

DVDDPLL

DGNDPLL

AVDDTx

Tx+

Tx–

TxSYNC

TxIQ(5)

TxIQ(4)

TxIQ(3)

TxIQ(2)

TxIQ(1)

TxIQ(0)

DVDD

DGND

DVDD

DGND

PROFILE

RESET

DVDD

DGND

SCLK

SDIO

SDO

DGNDTx

DVDDTx

PWRDN

REFIO

FSADJ

AGNDTx

DRGND

DRVDD

IF12(11)

IF12(10)

IF12(9)

IF12(8)

IF12(7)

IF12(6)

IF12(5)

IF12(4)

IF12(3)

IF12(2)

IF12(1)

IF12(0)

IF10(4)

IF10(3)

IF10(2)

IF10(1)

IF10(0)

RxSYNC

DRGND

DRVDD

MCLK

DVDD

DGND

AD9878

100-LEAD LQFP

TOP VIEW

(Not to Scale)

03277-0-002

Figure 37. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Pin Function

1, 21, 70

2, 22, 71

3–14

15–19

24, 35, 39

25, 34, 36, 40

27:32

DRGND

DRVDD

IF12[11:0]

IF10[4:0]

RxSYNC

MCLK

DVDD

DGND

TxSYNC

TxIQ[5:0]

PROFILE

RESET

SCLK

SDIO

SDO

DGNDTx

DVDDTx

PWRDN

REFIO

FSADJ

Pin Driver Digital Ground

Pin Driver Digital 3.3 V Supply

12-Bit ADCs Digital Ouput

10-Bit ADC Digital Ouput

Sync Output, 10- and 12-Bit ADCs

Master Clock Output

Digital 3.3 V Supply

Digital Ground

Sync Input for Transmit Port

Digital Input for Transmit Port

Profile Selection Input

Chip Reset Input

SPORT Clock

SPORT Chip Select

SPORT Data I/O

SPORT Data Output

Tx Path Digital Ground

Tx Path Digital 3.3 V Supply

Power-Down Transmit Path

TxDAC Decoupling (to AGND)

DAC Output Adjust (External Res.)

AD9878

Rev. 0 | Page 28 of 36

Pin No. Mnemonic Pin Function

51, 52

66, 67

72, 80

73, 79

76, 81, 86, 89, 94, 97, 99

77, 78

82, 85, 90, 93, 100

87, 88

95, 96

AGNDTx

Tx–, Tx+

AVDDTx

DGNDPLL

DVDDPLL

AVDDPLL

PLLFILT

AGNDPLL

DGNDOSC

XTAL

OSCIN

DVDDOSC

CA_CLK

CA_DATA

CA_EN

FLAG[2:1]

SIGDELT

REFCLK

AVDD10

AGND10

REFB10

REFT10

AGND

IF10-, IF10+

AVDD

REFB12B

REFT12B

IF12B–, IF12B+

REFB12A

REFT12A

IF12A–, IF12A+

VIDEO IN

Tx Path Analog Ground

Tx Path Complementary Outputs

Tx Path Analog 3.3 V Supply

PLL Digital Ground

PLL Digital 3.3 V Supply

PLL Analog 3.3 V Supply

PLL Loop Filter Connection

PLL Analog Ground

Oscillator Digital Ground

Crystal Oscillator Inverted Output

Oscillator Clock Input

Oscillator Digital 3.3 V Supply

Serial Clock to Cable Driver

Serial Data to Cable Driver

Serial Enable to Cable Driver

Programmable Flag Outputs

Sigma-Delta DAC Output

Reference Clock Output

10-Bit ADC Analog 3.3 V Supply

10-Bit ADC Analog Ground

10-Bit ADC Ref Decoupling Node

12-Bit ADC Analog Ground

Differential Input to 10-bit ADC

12-Bit ADC Analog 3.3 V Supply

ADC12B Ref Decoupling Node

Differential Input to ADC12B

ADC12A Ref Decoupling Node

Differential Input to ADC12A

Video Clamp Input

AD9878

Rev. 0 | Page 29 of 36

10K

RC0805

SMA200UP

CC0805

RC0805

SMAEDGE

AGND;3,4,5

RC07CUP

RC0805

CC0603

RC0805

LC1210 LC1210

RC0805

CC0603

LC1210

RC0805

LC1210

CC0603

CC0805 CC0805

TOKOB5F

CC0603

CC0805

VCC

GND1

GND2

VIN+

VIN-

GND3

DATAEN

SDATA

CLKGND4

SLEEP

BYP

VOUT-

VOUT+

RAMP

TXEN

VCC1

GND5 GND

AD8328

CC0603 C C0603

RC0805

SMAEDGE

AGND;3,4,5

CC0603

RC0805

VAL

BCASE CC0805

CC 0805

CC0805

RC0805

SMAEDGE

AGND;3,4,5

DIP06RCUP

SMAEDGE

AGND;3,4,5

SMAEDGE

AGND;3,4,5

CC0805

RC0805

CC0603

DIP06RCUP

CC0603

RC0805

CC0603

RC0805RC0805

CC0603

RC0805

CC0805BCASE

RC0805

DIP06RCUP

CC1206

CC0805

RC0805

CC0805BCASE

CC1206

CC0603

AGND;5

SMAEDGE

AGND;3,4,5

RC0805

RIBBON

HEADER RA RIBBON

RCOM

RC0805

SMAEDGE

AGND;3,4,5

RC0805

CC0603

VCC

GND

RESET

ADM1818-10ART

CC0603 CC0603

BCASE

CC0603CC0603

CC0603 CC0603 BCASE CC0603

CC0603 CC0603 CC0603

BCASE

RC0805

CC0603

RC0805

CC0603

CC0805

CC0603 CC 0603

CC0805

AD9878LQFP

DGND1

DGND2

DGND3

DGND4

DGNDTX

DVDD1

DVDD2

DVDD3

DVDD4

DVDDTX

FSADJ

IF0

IF1

IF10

IF2

IF3

IF4

IF5

IF6

IF7

IF8

IF9

IFB0

IFB1

IFB2

IFB3

MCLK

PROFILE

REFIO

RXSYNC

SCLK

SDIO

SDO

TXIQ0

TXIQ1

TXIQ2

TXIQ3

TXIQ5

TXSYNC

PWRDN

RESET

DRVDD1

IF11

DRGND1

AGND1

TXIQ4

IFB4

AGND10

AGND10-A

AGND2

AGND3

AGND4

AGND5

AGND6

AGND7

AGNDPLL

AGNDTX

AVDD1

AVDD10

AVDD10-A

AVDD2

AVDD3

AVDD4

AVDD5

AVDDPLL

AVDDTX

CACLK

CADATA

DGNDOSC

DGNDPLL

DRGND

DRVDD

DRGND2

DRVDD2

DVDDOSC

DVDDPLL

FLAG1

FLAG2

IF10B+

IF10B-

IF12A+

IF12A-

IF12B+

IF12B-

OSCIN

PLLFILT

REFB10

REFCLK

REFB12B

REFB12A

REFT12A

REFT12B

REFT10

SIGDELT

TX-

TX+

VIDEOIN

CAEN

XTAL

AD8138

-IN

+INVEE

VCC

VOC

VO+

VO-

RC0805

OSC_IN_CLK

VIDEO IN

TRANSF AD8328

AD8328TRANSF

EXT_CLK

TRANSFAD8138

TRANSF

IF-12A

RESET

AD8138

TRANSF

AD8138 TRANSF

IF-12B

IF-10

AD8138

DIGITAL TRANSMIT

TX_OUT

AD8328

TRANSF

TX_OUT

DUTY CYCLE

POT1

10K

500

TX+

DVDDPLLOSCAVDDTX

TX-

SDO,SDIO,CS,SCLK

SCLK

SDO

SDIO

IF[0:11]

IF11

IF1

IF0

IF6

IF5

IF2

IF3

IF4

IF7

IF8

IF9

IF10

IFB[0:4]

IFB4

IFB2

IFB3

IFB1

IFB0

IF12B-

IF12B+

IF10-

IF10+

SDELTA0

IF12A-

IF12A+

100

3962

55 46

C98

20PF

C24

0.1UF

C23

C20

18PF

0.1UF

C69

WHT

TP4

0.01UF C16 R4 1.3K

C15

0.01UF

WHT

TP3

100K

WHT

TP15 TP6

WHT WHT

TP5

10V

10UF

0.1UF0.1UF

C3C2

0.1UF

C12

C14

16V

10UF

C13

0.1UF

C11

0.1UF

TP1

WHT WHT

TP2

0.1UF 0.1UF

10UF

10V

10K

R10

0.1UF

C22

0.1UF

C21

0.1UF

R22

499 1

J11

R20

49.9

RP1

11 12

13 14

15 16

17 18

21 22

23 24

25 26

R2133

R19

J12

JP31

JP25

JP26

JP4

SW1

0.1UF C101

C94

0.1UF

C88

47PF

C91

10UF

16V

C90

0.1UF

49.9 R33

C108

20PF

C95

JP23

JP21

R18

499

523

R23

10UF

16V

C96

0.1UF

C97

R15

10K

R13

49.9

R24 0.1UF C86

499

R17

R14

C87

C112

0.1UF

JP22

49.9 R27

R26

R25

C102

0.1UF

JP24

JP30

JP32

0.1UF C111

R32

R31

C92

20PF

J15

J13

JP1

500

0.1UF

C84

C17

18PF

18PF C18

U13

AGND;3

V_CLK;5

C110

0.1UF

C83

16V

10UF

37.5

R12

R11

37.5

8138-

A_BUFF-

VCML

8138+

8138-

DRVDD

C66

0.1UF

R39

43.3

R40

86.6

0.1UF

C115

C116

0.1UF

1011

20 1

0.1UF

C72

C117

0.1UF

JP8

JP7

18PF

C58

33PF

C57

0.01UF

C114

L15

220

R38

220

L16

C113

0.01UF

R36

220

L14L13

220

R37

CAENABLE

CADATA

CACLK

PWRDOWN

RXSYNC

MCLK

DVDDTX

DVDD

DRVDD

AVDD

REFCLK

FLAG1

FLAG2

CAENABLE

CADATA

CACLK

TXIQ1

TXIQ2

TXIQ3

TXIQ5

TXSYNC

0.1UF

C10

33OHM

75OHM

V_CLK

XTAL

OSCIN

RESET

49.9

C19

0.1UF

AGND;3,4,5

47PF

VCML

A_BUFF+

RC0805

R29

JP9

TXIQ0

PROFILE1

TXIQ4

CA_SLEEP

R28

5V_AD8328 5V_AD8328

CC0805

RC 0805

8138+

5.11K

R16

0.1UF

RC0805

DRVDD PWRDOWN

NC7SZ04

RC0805

03277-0-038

Figure 38. AD9878 Evaluation PCB Schematic (page1)

AD9878

Rev. 0 | Page 30 of 36

100

RJ45

SMAEDGE

AGND;3,4,5

74LVXC3245

TSSOP24

GND1

GND2 GND3

VCCB

VCCA

T/R

GND1

GND2 GND3

NCT/R

VCCA VCCB

74LVXC3245

TSSOP24

NC7SZ04

74LVXC3245

TSSOP24

GND1

GND2 GND3

VCCB

VCCA

T/R

HDR040RA

GND1

GND2 GND3

NCT/R

VCCA VCCB

74LVXC3245

TSSOP24

DCN25RPT

INVERT CLK

DIGITAL RECEIVE

MCLK

DEL_CLK

PC PARALLEL PORT

MCLK

RXSYNC

DEL_CLK

IFB[0:4]

IFB4

IFB2

IFB1

IFB0

IFB3

JP13

DBUFF3-5V

DBUFF5V

SDOPC

SSDIO

SDO

12 13

124

RIBBON

116 RP5

11 6

RP5

12 13

RP4 22

710

22RP4

611

RP4 22

512

22RP4

413

RP4 22

314

22RP4

215

RP4 22

116

22RP4

AGND;3

DBUFF5V;5

JP5

R35

1JP6

89 RP322

710 22 R P3

611 RP322

512 22 R P3

413 RP322

314 22 R P3

215 RP322

116 22 R P3

89 RP222

710 22 R P2

611 RP222

512 22 R P2

413 RP222

314 22 R P2

215 RP222

116 22 R P2

241

1312

RP7

710 RP6

RP6

1312

54 RP7

RP7

72 RP7

710 RP5

512 RP5

13 4

RP5

314 RP5

15 2

RP5

11 6

RP6

512 RP6

13 4

RP6

314 RP6

15 2

RP6

116 RP6

DEL_CLK

SDOPC

SDIO

SCLK

R34

DVDD

CA_SLEEP

9101112

SSCLK

SCS

IF0

IF2

IF3

IF1

IF4

IF5

IF6

IF7

IF8

IF9

IF10

IF11

IF[0:11]

RC0603

JP3

RC0603

0.1UF

VAL

10UF

16V

CC0805

LC1210

BCASE

CLR

CC0603CC0603 CC0603 CC0603

CC0603 CC0603 CC0603 CC0603

CC0603 CC0603 CC0603

CC0603

CC0603CC0603CC0603CC0603CC0603CC0603

CC0603CC0603 C C0603

CC0603CC0603CC0603CC0603

CLR

LC1210

CC0805

LC1210

CC0805

LC1210

CC0805

LC1210

CC0805BCASE

LC1210

CC0805

LC1210

CC0805BCASE

LC1210

CC0805

LC1210

CC0805

LC1210

BCASE

LC1210

BCASE

LC1210

BCASE

CC0805

BCASE

CLR

CC0603

CC0603 CC0603 CC0603 CC0603

CC0603

AD8328

C53

0.1UF

C48

0.1UF

C51

0.1UF

C54

0.1UF

C56

0.1UF

C33

0.1UF

TP19

TP18

TP17

TP16

JP2

C78

16V

10UF

C81

0.1UF

C79

16V

10UF

16V

C77

10UF

16V

C60

C61

16V

10UF

16V

C59

L12 VAL

C25

16V

10UF

C40

16V

10UF

16V

C26

VALL6

10UF

16V

C27

VALL3

0.1UF

C30

C43

0.1UF

L4 VAL

C28

0.1UF

L1 VAL

C41

16V

10UF

C44

0.1UF

L5 VAL

0.1UF

C29

VALL2

10UF

16V

C42

0.1UF

C45

L9 VAL

C64

0.1UF

VALL7

0.1UF

C62

VALL8

0.1UF

C63

C82

0.1UF

L11 VAL

0.1UF

C80

VALL10

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

0.1UF

C67 C70

0.1UF 0.1UF

C73 C75

0.1UF

C46

0.1UF

C52

0.1UF

C49

0.1UF

C85

0.1UF 0.1UF

C74 C71

0.1UF 0.1UF

C68 C65

0.1UF

C36

0.1UF

C37C34

0.1UF0.1UF

C31

0.1UF

C39C38

0.1UF0.1UF

C35C32

0.1UF

DVDDTX

AVDD

A_BUFF+

ABUFF+

ABUFF-

3_3VA

DBUFF5V

5V_AD8328

A_BUFF-

DVDDPLLOSC

AVDDTX

C55

0.1UF

C50

0.1UF

C47

0.1UF

C100

0.1UF

DBUFF3-5V

LC1210

AVDDPLL

V_CLK

TP20

C93

C89

L17

C76

DVDD

DRVDD

3_3VD

03277-0-039

Figure 39. AD9878 Evaluation PCB Schematic (page2)

AD9878

Rev. 0 | Page 31 of 36

03277-0-040

Figure 40. AD9878 Evaluation PCB—Top Assembly

03277-0-041

Figure 41. AD9878 Evaluation PCB—Bottom Assembly

AD9878

Rev. 0 | Page 32 of 36

03277-0-042

Figure 42. AD9878 Evaluation PCB Layout—Top Layer

03277-0-043

Figure 43. AD9878 Evaluation PCB Layout—Bottom Layer

AD9878

Rev. 0 | Page 33 of 36

03277-0-044

Figure 44. AD9878 Evaluation PCB—Power Plane

Figure 45. AD9878 Evaluation PCB—Ground Plane

AD9878

Rev. 0 | Page 34 of 36

OUTLINE DIMENSIONS

TOP VIEW

(PINS DOWN)

76100

14.00 BSC SQ

0.50 BSC 0 .27

0 .22

0 .17

1.60 MAX

SEATING

PLANE

12°

TYP

0.75

0.60

0.45

VIEW A

16.00 BSC SQ

12.00

REF

0.20

0.09

1.45

1.40

1.35

0.08 MAX

COPLANARITY

VIEW A

ROT A T ED 9 0 ° CCW

SEAT IN G

PLANE

10°

6°

2°

7°

3.5°

0°

0.15

0.05

PIN 1

COMPLIANT TO JEDEC STANDARDS MS-02 6 BED

Figure 46. 100-Lead Low Profile Quad FlapPackage [LQFP]

(ST-100)

Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9878BST –40°C to +85°C 100-LQFP ST-100

AD9878BSTRL –40°C to +85°C 100-LQFP ST-100

AD9878

Rev. 0 | Page 35 of 36

NOTES

AD9878

Rev. 0 | Page 36 of 36

NOTES

registered trademarks are the property of their respective companies.

C03277-0-5/03(0)