Nios Embedded Processor Development Board March 2001, ver. 1.1 Data Sheet Introduction This data sheet describes the features and functionality of the NiosTM CPU development board that is included in the ExcaliburTM Development Kit, featuring the Nios embedded processor. Development Board Features Functional Overview Altera Corporation A-MNL-NIOS-01 An APEXTM 20K200E device 1 MByte (512 K x 16-bit) of flash memory - pre-configured with 32-bit Nios reference design and software 256 KBytes of SRAM (in 2 64K x 16-bit chips) On-board logic for configuring APEX device from flash memory 3.3-V expansion/prototype headers (access to 40 user I/Os) 5-V-tolerant expansion/prototype headers (access to 40 user I/Os) A SODIMM) socket, compatible with standard SDRAM modules Two IEEE-1386 peripheral component interconnect (PCI) mezzanine connectors One RS-232 serial port One user-definable 8-bit dual in-line package (DIP) switch block Four user-definable push-button switches Dual 7-segment LED display Two user-definable LEDs Joint Test Action Group (JTAG) connector for ByteBlasterMVTM and MasterBlasterTM programmers Oscillator and zero-skew clock distribution circuitry Power-on reset circuitry Power-supply circuitry (Input: 9-V unregulated, center-negative) The Nios development board provides a hardware platform to immediately start developing embedded systems based on Altera APEXTM devices. The Nios development board is pre-loaded with a 32-bit Nios embedded processor system reference design. A QuartusTM II project directory containing the reference design example is installed with the Nios hardware development kit (HDK). The reference design and software are pre-loaded in flash memory, and boot on power-up. The reference design software includes a monitor that can be used to download and debug programs. 1 Nios Embedded Processor Development Board Nios Development Board Components 2 This section contains a brief overview of several important components on the Nios development board. A more complete list of components appears in Table 3 on page 18. A complete set of schematics, a physical layout database, and GERBER files for the Nios development board are installed as documentation for the Nios HDK. Altera Corporation Nios Embedded Processor Development Board Figure 1. Nios Development Board 1 Altera Corporation See Table 3 on page 18 for a complete list of the Nios development board components. 3 Nios Embedded Processor Development Board The APEX 20K200EFC484 Device U1 is an APEX 20K200E device in a 484-pin fineline ball-grid array (BGA) package. A useful Nios system module (CPU and peripherals) typically occupies between 25% and 35% of the logic on this device. Table 1 .APEX20K200E Device Features Maximum system gates 526,000 Typical gates 211,000 LEs 8,320 ESBs Maximum RAM bits 52 106,496 Maximum macrocells 832 Maximum user I/O pins 382 The development board provides two separate methods for configuring the APEX device: Flash Memory Chip 1. A JTAG connection (JP3) that can be used with Quartus II software via a ByteBlaster or MasterBlaster programming cable. 2. A configuration controller (U4) that configures the APEX device at power-up from hexout files stored in the flash memory (U3). See "Configuration Controller" on page 14 for more information. (U3) is an advanced micro-devices (AMD) AM29LV800BB 1Mbyte flash memory chip. It is connected to the APEX device so that it can be used for two purposes simultaneously: 1. A Nios processor implemented on the APEX device can use the flash as general-purpose readable, writable non-volatile memory. 2. The flash memory can hold an APEX device configuration file that is used by the configuration controller to load the APEX device at power-up. See "Configuration Controller" on page 14 for more information. A hexout configuration file that implements the 32-bit Nios reference design is pre-loaded in this flash memory. The 32-bit reference design, once loaded, can identify the 1 MB flash in its address space, and includes monitor software that can download files (either new APEX device configurations, Nios software, or both) into flash memory. The Nios SDK includes subroutines for writing and erasing this specific type of AMD flash memory. 4 Altera Corporation Nios Embedded Processor Development Board Dual SRAM Chips U14 and U15 are 256 Kbyte (64K x 16-bit) asynchronous SRAM chips. They are connected to the APEX device so that they can be used by a Nios processor as general-purpose zero-wait-state memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem. The pre-loaded Nios reference design identifies these SRAM chips in its address space as a contiguous 256 Kbyte, 32-bit-wide, zero-wait-state main memory. SODIMM Connector J2 is a 144-pin SODIMM socket that is compatible with standard single-data-rate, 64-bit-wide SDRAM modules. J2 is connected to the APEX device so that user logic can access SDRAM. The pre-loaded reference design does not make use of this connector. Altera Corporation 5 Nios Embedded Processor Development Board Figure 2. SODIMM Connector 6 Altera Corporation Nios Embedded Processor Development Board Expansion Prototype Connector Header: 3.3-V Headers JP8, JP9, and JP10 collectively form a standard-footprint, mechanically-stable connection that can be used (for example) as an interface to a special-function daughter card. Contact your Altera sales representative for a list of expansion daughter cards that can be used with the Nios board. The 3.3-V expansion prototype connector interface includes: 40 APEX device general-purpose I/O signals. A buffered, zero-skew copy of the on-board OSC output (from U5). A buffered, zero-skew copy of the APEX's PLL-output (from U5). An APEX device clock-input (for daughter cards that drive a clock to the programmable logic device (PLD). A logic-negative power-on-reset signal. Two regulated 3.3-V power-supply pins (500 mA total max load). Unregulated power-supply pin (connects directly to J1 power-input plug). Numerous ground connections. 1 The pre-loaded Nios reference design does not use the 3.3-V expansion prototype connector. Figure 3. 3.3-V Expansion Prototype Connector - JP8 Altera Corporation 7 Nios Embedded Processor Development Board Figure 4. 3.3-V Expansion Prototype Connector - JP9 Figure 5. 3.3-V Expansion Prototype Connector - JP 10 Expansion Prototype Connector Header: 5 Vtolerant. Headers JP11, JP12, and JP13 collectively form a standard-footprint, mechanically-stable connection that can be used (for example) as an interface to a special-function daughter card. The pre-loaded Nios reference design uses JP12 as an interface to the two-line LCD character display included with the Nios kit. The 5-V-tolerant expansion connector is similar to the 3.3-V expansion connector, except as indicated herein below: 8 JP11 (pin 38) is used as a global card-enable signal. All 40 I/O connections pass through analog switches (U8, U9, U11, and U12) to protect the APEX device from 5-V logic levels. These analog switches are globally enabled (switched-on) by APEX device I/O pin V7 (logic-0 on V7 enables switches). Altera Corporation Nios Embedded Processor Development Board A low-current 5-V power supply (50 mA max load) is presented on pin 2 of JP12 (the corresponding pin on the 3.3-V expansion connector is not connected). An RC-filtered connection to APEX device I/O pin U7. This circuit is suitable for producing a high-impedance, low-precision analog output if U7 is driven with a duty-cycle-modulated waveform by user-logic. The corresponding pin on the 3.3-V expansion connector is not connected. The Vref-voltage for the analog switches (3.3-V plus one diode-drop) is presented on pin 3 of JP13. The corresponding pin on the 3.3-V expansion connector is not connected. The pre-loaded Nios reference design uses JP12 as an interface to the twoline LCD character display included with the Nios Development Kit, featuring the Nios embedded processor. Figure 6. 5-V Expansion Prototype Connector - JP11 Altera Corporation 9 Nios Embedded Processor Development Board Figure 7. 5-V Expansion Prototype Connector - JP12 Figure 8. 5-V Expansion Prototype Connector - JP13 PCI Mezzanine Connectors (PMC) 10 PMCJN1 and PMCJN2 are IEEE1386-compliant PMC connectors. User logic in the APEX device can access PMC daughter cards through these connectors. The pre-loaded Nios reference design does not use the PCI mezzanine connector (PMC) connectors. Altera Corporation Nios Embedded Processor Development Board Figure 9. PCI Mezzanine Connectors (PMC) Altera Corporation 11 Nios Embedded Processor Development Board Serial Port Connector J3 is a standard DB-9 serial connector. This connector is typically used for host communication with a desktop workstation using a standard 9-pin serial cable connected to (for example) a COM-port. The transmit (TXD) receive (RXD) clear to send (CTS), and ready to send (RTS) signals use standard high-voltage RS-232 logic levels. U13 is a level-shifting buffer that presents or accepts 3.3-V versions of these signals to and from the APEX device. Figure 10. Serial Port Connector JTAG Connector JP3 is a 10-pin JTAG interface connector compatible with Altera ByteBlaster and MasterBlaster programming cables. The JTAG connection can be used for any of three purposes: 1. Quartus II software can configure the APEX device (U1) with a new bitstream (e.g., .sof) file via a MasterBlaster or ByteBlaster programming cable. 2. Quartus II or MAX+PLUS II software can re-program the EPM7064 device (U4) with a new .pof file via a MasterBlaster or ByteBlaster programming cable. 3. User-provided host software can conduct JTAG serial communication with a card plugged-in to the PMC connectors (PMCJN1 andPMCJN2) if the card makes use of the JTAG signals that are part of the IEEE-1386 standard. The JTAG chain on the Nios development board can include all, some, or none of the following three devices, in order: 12 1. (SW8) The APEX device (U1) 2. (SW9) The EPM7064 configuration controller (U4) 3. (SW10) A card plugged-in to the PMC connectors PMCJN1 and PMCJN2, if present. Altera Corporation Nios Embedded Processor Development Board Figure 11. JTAG Chain 1 Refer to the development board schematic for precise and complete connections information. For each device the indicated two-position connect/bypass switch determines whether the device is included in the JTAG chain (connect) or excluded (bypass). Figure 12. Two-Position Switches The JTAG connection is most commonly used to download user configuration (e.g., .sof) files to the APEX device chip during logic development and debugging. In this case, it is usually most convenient to leave SW8 in the connect position, and both SW9 and SW10 in the bypass position. The EPM7064 device (U4) comes factory-programmed as a configuration controller. See Factory and User Configurations on page 14. MAX PLUS+ II projects that include the design, implementation, and programming files for the configuration-controller logic are included with the Nios HDK. Most users will never need to re-program the configuration controller(U4). Altera Corporation 13 Nios Embedded Processor Development Board 1 Configuration Controller Re-programming U4 may result in an inoperable development board. Altera recommends that users leave SW9 and SW10 set to bypass. The configuration controller (U4), is an Altera EPM7064 PLD. It comes factory-programmed with logic that configures the APEX device (U1) from data stored in flash (U3) on power-up. At power-up (or when the reset switch SW2 is pressed), the configuration controller begins reading data out of the flash memory. The flash memory, APEX device, and configuration controller are connected so that data from the flash configures the APEX device in passive-parallel mode. Configuration Data The Quartus II software can (optionally) produce hexout configuration files, that are directly suitable for download and storage in the flash memory as configuration data. A hexout configuration file for the APEX20K200E device (U1) is a little less than 256Kbytes, and thus occupies about 1/4 of the flash memory (U3). New exult-files can be stored in the flash memory (U3) by software running on a Nios processor. The preloaded 32-bit Nios reference design includes the GERMS monitor program, that supports downloading exult files from a host (e.g., desktop workstation) into flash memory. f See the Nios Embedded Processor Software Development User Guide for a detailed description of the GERMS monitor program. Factory and User Configurations The configuration controller can manage two separate APEX device configurations stored in flash memory. These two configurations (hexoutfiles) are conventionally referred to as the user configuration and the factory configuration. Upon reset (or when the reset switch (SW2) is pressed) the configuration controller will attempt to load the APEX device with user configuration data. If this process fails (either because the userconfiguration is invalid or not present) the configuration controller will then load the APEX device with factory configuration data. The configuration controller expects user-configuration and factoryconfiguration files to be stored at fixed locations (offsets) in flash memory. Table 2 on page 15 shows how the configuration controller expects flash memory contents to be arranged 14 Altera Corporation Nios Embedded Processor Development Board . Table 2.Flash Memory Allocation 0x100000 - 0x17FFFF 512 Kbytes Nios instruction and nonvolatile data space. 0x180000 - 0x1BFFFF 256 Kbytes User-defined APEX device configuration data. 0x1C0000 - 0x1FFFFF 256 Kbytes Factory-default APEX device configuration. See "Configuration Controller" on page 14. The 32-bit Nios reference design is pre-loaded into the factoryconfiguration region of the flash memory. Altera recommends that users avoid overwriting the factory configuration data. The jumper (JP2) changes the behavior of the configuration controller. If a shorting block is present on JP2, the configuration controller will ignore the user-configuration and always configure the APEX device from the factory configuration. By shorting JP2, you can "escape" from the situation where a valid-but-nonfunctional user configuration is present in flash memory. In the pre-loaded Nios reference design, the 1 MB flash memory is mapped at base-address 0x100000. Thus, user hexout-files should be downloaded to address 0x180000 (= flash-base-address + userconfiguration offset). f Two-Digit 7-segment display (D1) Refer to the Software Reference Manual for detailed information about downloading and relocating files using the GERMS monitor. D1 is connected to the APEX device so that each segment is individually controlled by a general-purpose I/O pin. Figure 13. Dual-Digit Display The pre-loaded Nios reference design includes parallel input/output (PIO) registers and logic for driving this display. Altera Corporation 15 Nios Embedded Processor Development Board Switches, Buttons, and LEDs SW1 is an 8-DIP-switch block with each switch connected to an APEX general-purpose I/O and a pull-up resistor. The APEX device will see a logic-1 when each switch is open, and a logic-0 when each switch is closed. Figure 14. Eight Dip Switch Block SW4, SW5, SW6, and SW7 are momentary-contact push-button switches, each connected to an APEX device general-purpose I/O and a pull-up resistor. The APEX device will see a logic-0 when each switch is pressed. Discrete LEDs LED1 and LED2 are each controlled by an APEX device general-purpose I/O. Each LED will light-up when the APEX device drives a logic-1 on its controlling output. Figure 15. Switches and LEDs The Nios development board uses dedicated switches SW2 and SW3 for the following fixed functions: 16 Altera Corporation Nios Embedded Processor Development Board SW2: Reset When SW3 is pressed, a logic-0 value is driven to U7, the power-on reset controller. Pressing SW3 is equivalent to a power-on reset. When SW3 is pressed (or when the board is power-cycled), the configuration controller will load the APEX device from flash memory. See "Configuration Controller" on page 14 for more information. When the development board is delivered from the factory, the APEX device will be configured with the 32-bit reference design at power-up (or when SW3 is pressed). The reference design will then begin executing the GERMS monitor, a serial debug/download utility. SW3: Clear When SW2 is pressed, a logic-0 is driven onto the APEX devices' DEV_CLRn pin (and user I/O F12). The result of pressing SW2 depends on how the APEX device is currently configured. The pre-loaded Nios reference design treats SW2 as a CPU-reset pin: The reference Nios CPU will reset and start executing code from its boot-address (0) when SW2 is pressed. Power-supply circuitry The Nios development board runs from a 9-V, unregulated, centernegative input. On-board circuitry generates 5-V, 3.3-V, and 1.8-V regulated power levels. Clock Circuitry Altera Corporation The 1.8-V supply is used only for the APEX device core power source and it is not available on any connector or header. The 3.3-V supply is used as the power source for all APEX device I/O pins. The 3.3-V supply is also available to daughter cards or other devices plugged-in to any of the expansion connectors, including the PMC connectors and the SDRAM SODIMM socket. The total load from all externally-connected 3.3-V devices may not exceed 500 mA. The 5-V supply is presented on Pin2 of JP12 for use by any devices plugged-in to the 5-V-tolerant expansion connectors. The total load may not exceed 50 mA. The Nios development board includes a 33.333MHz free-running oscillator and a zero-skew, point-to-point clock distribution network that drives both the APEX device and pins on the expansion connectors, PMC connectors, and SODIMM connector. The zero-skew buffer distributes both the free-running 33MHz clock and the clock-output from one of the APEX's device internal PLLs (CLKLK_OUT1). 17 Nios Embedded Processor Development Board Figure 16. Clock Circuitry Notes: Table 3 .Nios Development Board Components (Sheet 1 of 2) 18 D1 Dual-digit 7-segment LED J1 Power supply connector J2 SDRAM SODIMM socket J3 Serial port connector PMCJN1 PMC connector PMCJN2 PMC connector JP2 Jumper header for configuration controller JP3 JTAG header JP8 40-pin header for 3.3 volt daughter card JP9 14-pin header for 3.3 volt daughter card JP10 20-pin header for 3.3 volt daughter card JP11 40-pin header for 5 volt daughter card JP12 14-pin header for 5 volt daughter card JP13 20-pin header for 5 volt daughter card JP14 6-pin header for serial debug JP3 JTAG header LED1 User-defined LED LED2 User-defined LED LED3 Flash-byte LED LED 7 Power indication LED SW1 8-bit DIP switch block SW2 Resets the board--clears the APEX device and reloads from the configuration controller SW3 Clears the CPU Altera Corporation Nios Embedded Processor Development Board Table 3 .Nios Development Board Components (Sheet 2 of 2) Notes: Altera Corporation SW4 User-defined push-button SW5 User-defined push-button SW6 User-defined push-button SW7 User-defined push-button SW8 APEX device JTAG chain switch SW9 Configuration controller JTAG chain switch SW10 PMC JTAG chain switch TP1 Ground point providing a ground plane reference TP2 Ground point providing a ground plane reference TP3 Ground point providing a ground plane reference TP4 Ground point providing a ground plane reference U1 APEX EP20K200E device U3 Flash memory device U4 APEX device configuration controller U5 Clock distribution chip U7 Monitor reset U13 RS-232 level-shifter U14 SRAM U15 SRAM Y1 Programmable High-Frequency Oscillator 19 Nios Embedded Processor Development Board 20 Altera Corporation