NM27C512V90 - National Semiconductor

TL/D/10834

NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM

February 1994

NM27C512

524,288-Bit (64K x 8) High Performance CMOS EPROM

General Description

The NM27C512 is a high performance 512K UV Erasable

Electrically Programmable Read Only Memory (EPROM). It

is manufactured using National’s proprietary 0.8 micron

CMOS AMGTM EPROM technology for an excellent combi-

nation of speed and economy while providing excellent reli-

ability.

The NM27C512 provides microprocessor-based systems

storage capacity for portions of operating system and appli-

cation software. Its 90 ns access time provides no-

wait-state operation with high-performance CPUs. The

NM27C512 offers a single chip solution for the code storage

requirements of 100% firmware-based equipment. Fre-

quently-used software routines are quickly executed from

EPROM storage, greatly enhancing system utility.

The NM27C512 is configured in the standard JEDEC

EPROM pinout which provides an easy upgrade path for

systems which are currently using standard EPROMs.

The NM27C512 is one member of a high density EPROM

Family which range in densities up to 4 Megabit.

Features

YHigh performance CMOS

Ð 90 ns access time

YFast turn-off for microprocessor compatibility

YManufacturers identification code

YJEDEC standard pin configuration

Ð 28-pin DIP package

Ð 32-pin chip carrier

Block Diagram

TL/D/10834–1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

NSC800TM is a trademark of National Semiconductor Corporation.

AMGTM is a trademark of WSI, Inc.

C1995 National Semiconductor Corporation RRD-B30M65/Printed in U. S. A.

Connection Diagrams

27C080 27C040 27C020 27C010 27C256

A19 XX/VPP XX/VPP XX/VPP

A16 A16 A16 A16

A15 A15 A15 A15 VPP

A12 A12 A12 A12 A12

A7A7A7A7A7

A6A6A6A6A6

A5A5A5A5A5

A4A4A4A4A4

A3A3A3A3A3

A2A2A2A2A2

A1A1A1A1A1

A0A0A0A0A0

O0O0O0O0O0

O1O1O1O1O1

O2O2O2O2O2

GND GND GND GND GND

DIP

NM27C512

TL/D/10834–2

27C256 27C010 27C020 27C040 27C080

VCC VCC VCC VCC

XX/PGM XX/PGM A18 A18

VCC XX A17 A17 A17

A14 A14 A14 A14 A14

A13 A13 A13 A13 A13

A8A8A8A8A8

A9A9A9A9A9

A11 A11 A11 A11 A11

OE OE OE OE OE/VPP

A10 A10 A10 A10 A10

CE/PGM CE CE CE/PGM CE/PGM

O7O7O7O7O7

O6O6O6O6O6

O5O5O5O5O5

O4O4O4O4O4

O3O3O3O3O3

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C512 pins.

Commercial Temp Range (0§Ctoa

70§C)

Parameter/Order Number Access Time (ns)*

NM27C512 Q, N, V 90 90

NM27C512 Q, N, V 120 120

NM27C512 Q, N, V 150 150

NM27C512 Q, N, V 200 200

Military Temp Range (b55§Ctoa

125§C)

Parameter/Order Number Access Time (ns)*

NM27C512 QM 200 200

Extended Temp Range (b40§Ctoa

85§C)

Parameter/Order Number Access Time (ns)*

NM27C512 QE, NE, VE 90 90

NM27C512 QE, NE, VE 120 120

NM27C512 QE, NE, VE 150 150

NM27C512 QE, NE, VE 200 200

Note: Surface mount PLCC package available for commercial and extended

temperature ranges only.

*All versions are guaranteed to function for slower speeds.

Package Types: NM27C512 Q, N, V XXX

QeQuartz-Windowed Ceramic DIP Package

NePlastic OTP DIP Package

VePLCC Package

#All packages conform to the JEDEC standard.

Pin Names

A0– A15 Addresses

CE Chip Enable

OE Output Enable

O0– O7 Outputs

PGM Program

XX Don’t Care (During Read)

PLCC

TL/D/10834–3

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

All Input Voltages Except A9 with

Respect to Ground b0.6V to a7V

VPP and A9 with Respect to Ground b0.7V to a14V

VCC Supply Voltage with

Respect to Ground b0.6V to a7V

ESD Protection

(MIL Std. 883, Method 3015.2) l2000V

All Output Voltages with

Respect to Ground VCC a1.0V to GND b0.6V

Operating Range

Range Temperature VCC Tolerance

Comm’l 0§Ctoa

70§Ca5V g10%

Industrial b40§Ctoa

85§Ca5V g10%

Military b55§Ctoa

125§Ca5V g10%

Read Operation

DC Electrical Characteristics

Symbol Parameter Test Conditions Min Max Units

VIL Input Low Level b0.5 08 V

VIH Input High Level 2.0 VCC a1V

OL Output Low Voltage IOL e2.1 mA 0.4 V

VOH Output High Voltage IOH eb

2.5 mA 3.5 V

ISB1 VCC Standby Current (CMOS) CE eVCC g0.3V 100 mA

ISB2 VCC Standby Current CE eVIH 1mA

CC1 VCC Active Current CE eOE eVIL fe5 MHz 40 mA

ICC2 VCC Active Current CE eGND, f e5 MHz

CMOS Inputs Inputs eVCC or GND, I/O e0mA 35 mA

C, I Temp Ranges

IPP VPP Supply Current VPP eVCC 10 mA

VPP VPP Read Voltage VCb0.7 VCC V

ILI Input Load Current VIN e5.5V or GND b11mA

LO Output Leakage Current VOUT e5.5V or GND b10 10 mA

AC Electrical Characteristics

Symbol Parameter 90 120 150 200 Units

Min Max Min Max Min Max Min Max

tACC Address to Output 90 120 150 200

Delay

tCE CE to Output Delay 90 120 150 200

tOE OE to Output Delay 40 50 50 50

tDF Output Disable to 35 25 45 55

Output Float

tOH Output Hold from

Addresses, CE or OE,000

Whichever Occurred First

Capacitance TAea

25§C, f e1 MHz (Note 2)

Symbol Parameter Conditions Typ Max Units

CIN1 Input Capacitance VIN e0V 612pF

except OE/VPP

COUT Output Capacitance VOUT e0V 9 12 pF

CIN2 OE/VPP Input VIN e0V 20 25 pF

Capacitance

AC Test Conditions

Output Load 1 TTL Gate and

CLe100 pF (Note 8)

Input Rise and Fall Times s5ns

Input Pulse Levels 0.45V to 2.4V

Timing Measurement Reference Level (Note 9)

Inputs 0.8V and 2V

Outputs 0.8V and 2V

AC Waveforms (Notes 6, 7)

TL/D/10834–4

Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to tACC –t

OE after the falling edge of CE without impacting tACC.

Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATE, the measured VOH1 (DC) b0.10V;

Low to TRI-STATE, the measured VOL1 (DC) a0.10V.

Note 5: TRI-STATE may be attained using OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on

every device between VCC and GND.

Note 7: The outputs must be restricted to VCC a1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL e1.6 mA, IOH eb

400 mA.

CL: 100 pF includes fixture capacitance.

Note 9: Inputs and outputs can undershoot to b2.0V for 20 ns Max.

Programming Characteristics (Notes 1 and 2)

Symbol Parameter Conditions Min Typ Max Units

tAS Address Setup Time 1 ms

tOES OE Setup Time 1 ms

tDS Data Setup Time 1 ms

tVCS VCC Setup Time 1 ms

tAH Address Hold Time 0 ms

tDH Data Hold Time 1 ms

tCF Chip Enable to Output Float Delay OE eVIL 060ns

PW Program Pulse Width 95 100 105 ms

tOEH OE Hold Time 1 ms

tDV Data Valid from CE OE eVIL 250 ns

tPRT OE Pulse Rise Time 50 ns

during Programming

tVR VPP Recovery Time 1 ms

IPP VPP Supply Current during CE eVIL 30 mA

Programming Pulse OE eVPP

ICC VCC Supply Current 50 mA

TRTemperature Ambient 20 25 30 §C

VCC Power Supply Voltage 6 6.25 6.5 V

VPP Programming Supply Voltage 12.5 12.75 13 V

tFR Input Rise, Fall Time 5 ns

VIL Input Low Voltage 0 0.45 V

VIH Input High Voltage 2.4 4 V

tIN Input Timing Reference Voltage 0.8 2 V

tOUT Output Timing Reference Voltage 0.8 2 V

Programming Waveforms

TL/D/10834–5

Note 1: National’s standard product warranty applies to devices programmed to specifications described herein.

Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a

board with voltage applied to VPP or VCC.

Note 3: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP

supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VCC to GND to suppress spurious

voltage transients which may damage the device.

Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings.

Fast Programming Algorithm Flow Chart

TL/D/10834–6

FIGURE 1

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Ta-

ble I. It should be noted that all inputs for the six modes are

at TTL levels. The power supplies required are VCC and

OE/VPP. The OE/VPP power supply must be at 12.75V dur-

ing the three programming modes, and must be at 5V in the

other three modes. The VCC power supply must be at 6.25V

during the three programming modes, and at 5V in the other

three modes.

Read Mode

The EPROM has two control functions, both of which must

be logically active in order to obtain data at the outputs.

Chip Enable (CE/PGM) is the power control and should be

used for device selection. Output Enable (OE/VPP)isthe

output control and should be used to gate data to the output

pins, independent of device selection. Assuming that ad-

dresses are stable, address access time (tACC) is equal to

the delay from CE to output (tCE). Data is available at the

outputs tOE after the falling edge of OE, assuming that CE

has been low and addresses have been stable for at least

tACC–tOE.

Standby Mode

The EPROM has a standby mode which reduces the active

power dissipation by over 99%, from 385 mW to 0.55 mW.

The EPROM is placed in the standby mode by applying a

CMOS high signal to the CE/PGM input. When in standby

mode, the outputs are in a high impedance state, indepen-

dent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL

high signal to the OE input. When in output disable all cir-

cuitry is enabled, except the outputs are in a high imped-

ance state (TRI-STATE).

Output OR-Typing

Because the EPROM is usually used in larger memory ar-

rays, National has provided a 2-line control function that

accommodates this use of multiple memory connections.

The 2-line control function allows for:

a) the lowest possible memory power dissipation, and

b) complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recom-

mended that CE/PGM be decoded and used as the primary

device selecting function, while OE/VPP be made a com-

mon connection to all devices in the array and connected to

the READ line from the system control bus.

This assures that all deselected memory devices are in their

low power standby modes and that the output pins are ac-

tive only when data is desired from a particular memory de-

vice.

Programming

CAUTION: Exceeding 14V on pin 22 (OE/VPP) will damage

the EPROM.

Initially, and after each erasure, all bits of the EPROM are in

the ‘‘1’s’’ state. Data is introduced by selectively program-

ming ‘‘0’s’’ into the desired bit locations. Although only

‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre-

sented in the data word. The only way to change a ‘‘0’’ to a

‘‘1’’ is by ultraviolet light erasure.

The EPROM is in the programming mode when the OE/VPP

is at 12.75V. It is required that at least a 0.1 mF capacitor be

placed across VCC to ground to suppress spurious voltage

transients which may damage the device. The data to be

programmed is applied 8 bits in parallel to the data output

pins. The levels required for the address and data inputs are

TTL.

When the address and data are stable, an active low, TTL

program pulse is applied to the CE/PGM input. A program

pulse must be applied at each address location to be pro-

grammed.

The EPROM is programmed with the Fast Programming Al-

gorithm shown in

Figure 1

. Each Address is programmed

with a series of 100 ms pulses until it verifies good, up to a

maximum of 25 pulses. Most memory cells will program with

a single 100 ms pulse.

The EPROM must not be programmed with a DC signal ap-

plied to the CE/PGM input.

Programming multiple EPROM in parallel with the same

data can be easily accomplished due to the simplicity of

the programming requirements. Like inputs of the parallel

EPROM may be connected together when they are pro-

grammed with the same data. A low level TTL pulse applied

to the CE/PGM input programs the paralleled EPROM.

Program Inhibit

Programming multiple EPROMs in parallel with different

data is also easily accomplished. Except for CE/PGM all

like inputs (including OE/VPP) of the parallel EPROMs may

be common. A TTL low level program pulse applied to an

EPROM’s CE/PGM input with OE/VPP at 12.75V will pro-

gram that EPROM. A TTL high level CE/PGM input inhibits

the other EPROMs from being programmed.

Program Verify

A verify should be performed on the programmed bits to

determine whether they were correctly programmed. The

verify is accomplished with OE/VPP and CE at VIL. Data

should be verified TDV after the falling edge of CE.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window

to prevent unintentional erasure. Covering the window will

also prevent temporary functional failure due to the genera-

tion of photo currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid

in programming. When the device is inserted in an EPROM

programmer socket, the programmer reads the code and

then automatically calls up the specific programming algo-

rithm for the part. This automatic programming control is

only possible with programmers which have the capability of

reading the code.

The Manufacturer’s Identification code, shown in Table II,

specifically identifies the manufacturer and device type. The

code for NM27C512 is ‘‘8F85’’, where ‘‘8F’’ designates that

it is made by National Semiconductor, and ‘‘85’’ designates

a 512K part.

The code is accessed by applying 12V g0.5V to address

pin A9. Addresses A1– A8, A10– A16, and all control pins

Functional Description (Continued)

are held at VIL. Address pin A0 is held at VIL for the manu-

facturer’s code, and held at VIH for the device code. The

code is read on the eight data pins, O0–O7. Proper code

access is only guaranteed at 25§Cg5§C.

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that era-

sure begins to occur when exposed to light with wave-

lengths shorter than approximately 4000 Angstroms (Ð). It

should be noted that sunlight and certain types of fluores-

cent lamps have wavelengths in the 3000Ð–4000Ðrange.

The recommended erasure procedure for the EPROM is ex-

posure to short wave ultraviolet light which has a wave-

length of 2537Ð. The integrated dose (i.e., UV intensity c

exposure time) for erasure should be minimum of

15W-sec/cm2.

The EPROM should be placed within 1 inch of the lamp

tubes during erasure. Some lamps have a filter on their

tubes which should be removed before erasure. Table III

shows the minimum EPROM erasure time for various light

intensities.

An erasure system should be calibrated periodically. The

distance from lamp to device should be maintained at one

inch. The erasure time increase as the square of the dis-

tance from the lamp (if distance is doubled the erasure time

increases by factor of 4). Lamps lose intensity as they age.

When a lamp is changed, the distance has changed, or the

lamp has aged, the system should be checked to make cer-

tain full erasure is occurring. Incomplete erasure will cause

symptoms that can be misleading. Programmers, compo-

nents, and even system designs have been erroneously

suspected when incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require

careful decoupling of the devices. The supply current, ICC,

has three segments that are of interest to the system de-

signer: the standby current level, the active current level,

and the transient current peaks that are produced by volt-

age transitions on input pins. The magnitude of these tran-

sient current peaks is dependent of the output capacitance

loading of the device. The associated VCC transient voltage

peaks can be suppressed by properly selected decoupling

capacitors. It is recommended that at least a 0.1 mF ceramic

capacitor be used on every device between VCC and GND.

This should be a high frequency capacitor of low inherent

inductance. In addition, at least a 4.7 mF bulk electrolytic

capacitor should be used between VCC and GND for each

eight devices. The bulk capacitor should be located near

where the power supply is connected to the array. The pur-

pose of the bulk capacitor is to overcome the voltage drop

caused by the inductive effects of the PC board traces.

Mode Selection

The modes of operation of the NM27C512 are listed in Table I. A single 5V power supply is required in the read mode. All

inputs are TTL levels excepts for VPP and A9 for device signature.

TABLE I. Mode Selection

Pins CE/PGM OE/VPP VCC Outputs

Mode

Read VIL VIL 5.0V DOUT

Output Disable X VIH 5.0V High Z

(Note 1)

Standby VIH X 5.0V High Z

Programming VIL 12.75V 6.25V DIN

Program Verify VIL VIL 6.25V DOUT

Program Inhibit VIH 12.75V 6.25V High Z

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer’s Identification Code

Pins A0 A9 07 06 05 04 03 02 01 00 Hex

(10) (24) (19) (18) (17) (16) (15) (13) (12) (11) Data

Manufacturer Code VIL 12V100011118F

Device Code VIH 12V1000010185

Physical Dimensions inches (millimeters)

UV Window Cavity Dual-In-Line Cerdip Package (JQ)

Order Number NM27C512Q

NS Package Number J28CQ

28-Lead Plastic One-Time-Programmable Dual-In-Line

Order Number NM27C512N

NS Package Number N28B

NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM

Physical Dimensions inches (millimeters) (Continued)

32-Lead Plastic Leaded Chip Carrier (PLCC)

Order Number NM27C512V

NS Package Number VA32A

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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