Si5324 A NY - F R E QUE N C Y P RECISION C LOCK M ULTIPLIER / J I T T E R A TTENUATOR Features Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs as low as 290 fs rms (12 kHz-20 MHz), 320 fs rms (50 kHz-80 MHz) Integrated loop filter with selectable loop bandwidth (4- 525 Hz) Meets ITU-T G.8251 and Telcordia GR-253-CORE jitter specification Hitless input clock switching with phase build-out Freerun, Digital Hold operation Configurable signal format per output (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236, 239/237, 66/64, 239/238, 15/14, 253/221, 255/238) LOL, LOS, FOS alarm outputs I2C or SPI programmable On-chip voltage regulator with high PSNR Single supply 1.8 5%, 2.5 10%, or 3.3 V 10% Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS-compliant Ordering Information: See page 64. Pin Assignments Description CKOUT1- CKOUT1+ NC GND NC VDD 36 35 34 33 32 31 30 29 28 RST 1 27 SDI NC 2 26 A2_SS INT_C1B 3 C2B 4 VDD 5 XA 6 XB 7 GND 8 20 GND NC 9 19 GND 25 A1 24 A0 GND Pad 23 SDA_SDO 22 SCL 21 CS_CA Copyright (c) 2014 by Silicon Laboratories LOL CKIN1- RATE1 CKIN1+ NC CKIN2- CKIN2+ VDD RATE0 10 11 12 13 14 15 16 17 18 The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applications requiring sub 1 ps jitter performance with loop bandwidths between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its external reference as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5324 input clock frequency and clock multiplication ratio are programmable via an I2C or SPI interface. The Si5324 is based on Silicon Laboratories' 3rd-generation DSPLL(R) technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5324 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Rev. 1.1 1/14 CKOUT2- 1/2/4/8/10G Fibre Channel line cards GbE/10/40/100G Synchronous Ethernet (LAN/WAN) Data converter clocking Wireless base stations Test and measurement CKOUT2+ Broadcast video -3G/HD/SD-SDI, Genlock Packet Optical Transport Systems (P-OTS), MSPP OTN/OTU-1/2/3/4 Asynchronous Demapping (Gapped Clock) SONET OC-48/192/768, SDH/STM-16/64/256 line cards CMODE Applications Si5324 Si5324 Functional Block Diagram Xtal or Refclock CKIN1 / N31 CKIN2 / N32 (R) DSPLL Xtal/Refclock Loss of Signal/ Frequency Offset Loss of Lock 2 / NC1_LS CKOUT1 / NC2_LS CKOUT2 /N1_HS / N2 VDD (1.8, 2.5, or 3.3 V) Control Signal Detect GND I2C/SPI Port Clock Select Device Interrupt Rate Select Skew Adjust Rev. 1.1 Si5324 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2. Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10.1. Si5324 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Rev. 1.1 3 Si5324 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature TA Supply Voltage during Normal Operation VDD Test Condition Min Typ Max Unit -40 25 85 C 3.3 V Nominal 2.97 3.3 3.63 V 2.5 V Nominal 2.25 2.5 2.75 V 1.8 V Nominal 1.71 1.8 1.89 V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. SIGNAL + Differential I/Os VICM , VOCM V VISE , VOSE SIGNAL - (SIGNAL +) - (SIGNAL -) Differential Peak-to-Peak Voltage VID,VOD VICM, VOCM Single-Ended Peak-to-Peak Voltage t SIGNAL + VID = (SIGNAL+) - (SIGNAL-) SIGNAL - Figure 1. Differential Voltage Characteristics 80% CKIN, CKOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics 4 Rev. 1.1 Si5324 Table 2. DC Characteristics (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit IDD LVPECL Format 622.08 MHz Out Both CKOUTs Enabled -- 251 279 mA LVPECL Format 622.08 MHz Out 1 CKOUT Enabled -- 217 243 mA CMOS Format 19.44 MHz Out Both CKOUTs Enabled -- 204 234 mA CMOS Format 19.44 MHz Out 1 CKOUT Enabled -- 194 220 mA Disable Mode -- 165 -- mA 1.8 V 5% 0.9 -- 1.4 V 2.5 V 10% 1 -- 1.7 V 3.3 V 10% 1.1 -- 1.95 V CKNRIN Single-ended 20 40 60 k Single-Ended Input Voltage Swing (See Absolute Specs) VISE fCKIN < 212.5 MHz See Figure 1. 0.2 -- -- VPP fCKIN > 212.5 MHz See Figure 1. 0.25 -- -- VPP Differential Input Voltage Swing (See Absolute Specs) VID fCKIN < 212.5 MHz See Figure 1. 0.2 -- -- VPP fCKIN > 212.5 MHz See Figure 1. 0.25 -- -- VPP Supply Current1 CKINn Input Pins2 Input Common Mode Voltage (Input Threshold Voltage) Input Resistance VICM Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. Rev. 1.1 5 Si5324 Table 2. DC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit CKOVCM LVPECL 100 load lineto-line VDD - 1.42 -- VDD -1.25 V Differential Output Swing CKOVD LVPECL 100 load lineto-line 1.1 -- 1.9 VPP Single Ended Output Swing CKOVSE LVPECL 100 load lineto-line 0.5 -- 0.93 VPP Differential Output Voltage CKOVD CML 100 load line-toline 350 425 500 mVPP CKOVCM CML 100 load line-toline -- VDD-0.36 -- V CKOVD LVDS 100 load line-to-line 500 700 900 mVPP Low Swing LVDS 100 load line-to-line 350 425 500 mVPP CKOVCM LVDS 100 load line-toline 1.125 1.2 1.275 V CKORD CML, LVPECL, LVDS -- 200 -- Output Voltage Low CKOVOLLH CMOS -- -- 0.4 V Output Voltage High CKOVOHLH VDD = 1.71 V CMOS 0.8 x VDD -- -- V Output Clocks (CKOUTn)3,5 Common Mode Common Mode Output Voltage Differential Output Voltage Common Mode Output Voltage Differential Output Resistance Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6 Rev. 1.1 Si5324 Table 2. DC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Output Drive Current (CMOS driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT- shorted externally) CKOIO ICMOS[1:0] = 11 VDD = 1.8 V -- 7.5 -- mA ICMOS[1:0] = 10 VDD = 1.8 V -- 5.5 -- mA ICMOS[1:0] = 01 VDD = 1.8 V -- 3.5 -- mA ICMOS[1:0] = 00 VDD = 1.8 V -- 1.75 -- mA ICMOS[1:0] = 11 VDD = 3.3 V -- 32 -- mA ICMOS[1:0] = 10 VDD = 3.3 V -- 24 -- mA ICMOS[1:0] = 01 VDD = 3.3 V -- 16 -- mA ICMOS[1:0] = 00 VDD = 3.3 V -- 8 -- mA VDD = 1.71 V -- -- 0.5 V VDD = 2.25 V -- -- 0.7 V VDD = 2.97 V -- -- 0.8 V VDD = 1.89 V 1.4 -- -- V VDD = 2.25 V 1.8 -- -- V VDD = 3.63 V 2.5 -- -- V 2-Level LVCMOS Input Pins Input Voltage Low Input Voltage High VIL VIH Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. Rev. 1.1 7 Si5324 Table 2. DC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit 3-Level Input Pins4 Input Voltage Low VILL -- -- 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD -- 0.55 x VDD V Input Voltage High VIHH 0.85 x VDD -- -- V Input Low Current IILL See Note 4 -20 -- -- A Input Mid Current IIMM See Note 4 -2 -- +2 A Input High Current IIHH See Note 4 -- -- 20 A VOL IO = 2 mA VDD = 1.71 V -- -- 0.4 V IO = 2 mA VDD = 2.97 V -- -- 0.4 V IO = -2 mA VDD = 1.71 V VDD - 0.4 -- -- V IO = -2 mA VDD = 2.97 V VDD - 0.4 -- -- V LVCMOS Output Pins Output Voltage Low Output Voltage Low Output Voltage High Output Voltage High VOH Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 8 Rev. 1.1 Si5324 Table 3. AC Characteristics (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Reference Clock Input Pin XA (XB with cap to GND) Input Resistance XARIN RATE[1:0] = LM, ML, MH, or HM, ac coupled -- 12 -- k Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH, or HM, ac coupled 0.5 -- 1.2 VPP 0.5 -- 2.4 VPP 0.002 -- 710 MHz 40 -- 60 % 2 -- -- ns -- -- 3 pF -- -- 11 ns N1 6 0.002 -- 945 MHz N1 = 5 970 -- 1134 MHz N1 = 4 1.213 -- 1.4 GHz -- -- 212.5 MHz Differential Reference Clock Input Pins (XA/XB) Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH, or HM CKINn Input Pins Input Frequency Input Duty Cycle (Minimum Pulse Width) CKNF CKNDC Input Capacitance CKNCIN Input Rise/Fall Time CKNTRF Whichever is smaller (i.e., the 40% / 60% limitation applies only to high frequency clocks) 20-80% See Figure 2 CKOUTn Output Pins (See ordering section for speed grade vs frequency limits) Output Frequency (Output not configured for CMOS or Disabled) Maximum Output Frequency in CMOS Format CKOF CKOF Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT setting (see application note, "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs". Visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. 3. LOCKT = 3.3 ms Rev. 1.1 9 Si5324 Table 3. AC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Output Rise/Fall (20-80 %) @ 622.08 MHz output CKOTRF Output not configured for CMOS or Disabled See Figure 2 -- 230 350 ps Output Rise/Fall (20-80%) @ 212.5 MHz output CKOTRF CMOS Output VDD = 1.71 CLOAD = 5 pF -- -- 8 ns Output Rise/Fall (20-80%) @ 212.5 MHz output CKOTRF CMOS Output VDD = 2.97 CLOAD = 5 pF -- -- 2 ns Output Duty Cycle Uncertainty @ 622.08 MHz CKODC 100 Load Line-to-Line Measured at 50% Point (Not for CMOS) -- -- +/-40 ps LVCMOS Input Pins Minimum Reset Pulse Width tRSTMN Reset to Microprocessor Access Ready tREADY 1 s 10 ms LVCMOS Output Pins Rise/Fall Times tRF CLOAD = 20pf See Figure 2 -- 25 -- ns LOSn Trigger Window LOSTRIG From last CKINn to Internal detection of LOSn N3 1 -- -- 4.5 x N3 TCKIN Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Fold = Fnew Stable Xa/XB reference -- 10 -- ms Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT setting (see application note, "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs". Visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. 3. LOCKT = 3.3 ms 10 Rev. 1.1 Si5324 Table 3. AC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Output Clock Skew tSKEW of CKOUTn to of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format PHASEOFFSET = 0 CKOUT_ALWAYS_ON = 1 SQ_ICAL = 1 -- -- 100 ps Phase Change due to Temperature Variation1 tTEMP Max phase changes from -40 to +85 C -- 300 500 ps -- 1 1.5 s -- 0.8 1.0 -- 1.2 1.5 -- 4.2 5.0 -- 200 -- ps -- 0.05 0.1 dB 5000/BW -- -- ns pk-pk Device Skew PLL Performance (fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz) Lock Time2 Si5324E-C-GM3 tLOCKMP Start of ICAL to of LOL Si5324A/B/C/D-C-GM Settle Time2 Si5324E-C-GM tSETTLE Start of ICAL to Fout within 5 ppm of final value Si5324A/B/C/D-C-GM Output Clock Phase Change tP_STEP Closed Loop Jitter Peaking JPK Jitter Tolerance JTOL After clock switch f3 128 kHz Jitter Frequency Loop Bandwidth s Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT setting (see application note, "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs". Visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. 3. LOCKT = 3.3 ms Rev. 1.1 11 Si5324 Table 3. AC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Phase Noise fout = 622.08 MHz Symbol Test Condition Min Typ Max Unit CKOPN 100 Hz Offset -- -90 -- dBc/Hz 1 kHz Offset -- -106 -- dBc/Hz 10 kHz Offset -- -121 -- dBc/Hz 100 kHz Offset -- -132 -- dBc/Hz 1 MHz Offset -- -132 -- dBc/Hz Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Offset -- -88 -76 dBc Spurious Noise SPSPUR Max spur @ n x F3 (n 1, n x F3 < 100 MHz) -- -93 -70 dBc Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT setting (see application note, "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs". Visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. 3. LOCKT = 3.3 ms 12 Rev. 1.1 Si5324 Table 4. Microprocessor Control (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit I2C Bus Lines (SDA, SCL) Input Voltage Low VILI2C -- -- 0.25 x VDD V Input Voltage High VIHI2C 0.7 x VDD -- VDD V VDD = 1.8V 0.1 x VDD -- -- V VDD = 2.5 or 3.3 V 0.05 x VDD -- -- V VDD = 1.8 V IO = 3 mA -- -- 0.2 x VDD V VDD = 2.5 or 3.3 V IO = 3 mA -- -- 0.4 V Hysteresis of Schmitt trigger inputs Output Voltage Low VHYSI2C VOLI2C Rev. 1.1 13 Si5324 Table 4. Microprocessor Control (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Duty Cycle, SCLK tDC SCLK = 10 MHz 40 -- 60 % Cycle Time, SCLK tc 100 -- -- ns Rise Time, SCLK tr 20-80% -- -- 25 ns Fall Time, SCLK tf 20-80% -- -- 25 ns Low Time, SCLK tlsc 20-20% 30 -- -- ns High Time, SCLK thsc 80-80% 30 -- -- ns Delay Time, SCLK Fall to SDO Active td1 -- -- 25 ns Delay Time, SCLK Fall to SDO Transition td2 -- -- 25 ns Delay Time, SS Rise to SDO Tri-state td3 -- -- 25 ns Setup Time, SS to SCLK Fall tsu1 25 -- -- ns Hold Time, SS to SCLK Rise th1 20 -- -- ns Setup Time, SDI to SCLK Rise tsu2 25 -- -- ns Hold Time, SDI to SCLK Rise th2 20 -- -- ns Delay Time between Slave Selects tcs 25 -- -- ns SPI Specifications 14 Rev. 1.1 Si5324 Table 5. Jitter Generation Parameter Jitter Gen OC-192 Symbol JGEN Test Condition* Measurement Filter DSPLL BW2 0.02-80 MHz 120 Hz 4-80 MHz 0.05-80 MHz Jitter Gen OC-48 JGEN 0.12-20 MHz Min Typ Max GR-253Specification Unit -- 4.2 6.2 30 psPP -- .27 .42 N/A psrms -- 3.7 6.4 10 psPP -- .14 0.31 N/A psrms -- 4.4 6.9 10 psPP -- .26 0.41 1.0 ps rms -- 3.5 5.4 40.2 psPP -- .27 0.41 4.02 ps rms 120 Hz 120 Hz 120 Hz *Note: Test conditions: 1. fIN = fOUT = 622.08 MHz 2. Clock input: LVPECL 3. Clock output: LVPECL 4. PLL bandwidth: 120 Hz 5. 114.285 MHz 3rd OT crystal used as XA/XB input 6. VDD = 2.5 V 7. TA = 85 C Table 6. Thermal Characteristics (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient JA Still Air 32 C/W Thermal Resistance Junction to Case JC Still Air 14 C/W Rev. 1.1 15 Si5324 Table 7. Absolute Maximum Ratings* Parameter Symbol Test Condition Min Typ Max Unit -- 3.8 V VDD+0.3 V DC Supply Voltage VDD -0.5 LVCMOS Input Voltage VDIG -0.3 CKINn Voltage Level Limits CKNVIN 0 -- VDD V XA/XB Voltage Level Limits XAVIN 0 -- 1.2 V Operating Junction Temperature TJCT -55 -- 150 C Storage Temperature Range TSTG -55 -- 150 C 2 -- -- kV ESD MM Tolerance; All pins except CKIN+/CKIN- 150 -- -- V ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN- 750 -- -- V ESD MM Tolerance; CKIN+/CKIN- 100 -- -- V ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN- Latch-up Tolerance JESD78 Compliant *Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 16 Rev. 1.1 Si5324 2. Typical Application Circuits C4 1 F System Power Supply C1 0.1 F Ferrite Bead C2 0.1 F VDD = 3.3 V C3 0.1 F 130 CKIN1- 82 Input Clock Sources* GND PAD GND CKIN1+ VDD 130 + 100 - CKOUT1- 82 0.1 F 0.1 F Clock Outputs CKOUT2+ VDD = 3.3 V 130 0.1 F CKOUT1+ + 100 - CKOUT2- 130 0.1 F CKIN2+ CKIN2- 82 82 Si5324 Option 1: INT_C1B Interrupt/CKIN_1 Invalid Indicator C2B CKIN_2 Invalid Indicator LOL PLL Loss of Lock Indicator XA 114.285 MHz Crystal XB VDD 15 k Crystal/Ref Clk Rate A[2:0] RATE[1:0]2 15 k Option 2: 0.1 F Refclk+ Refclk- Control Mode (L) Reset XA 0.1 F Serial Port Address SDA Serial Data SCL Serial Clock I2C Interface XB CS_CA CMODE Clock Select/Clock Active RST Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). Figure 3. Si5324 Typical Application Circuit (I2C Control Mode) Rev. 1.1 17 Si5324 C4 1 F System Power Supply C1 0.1 F Ferrite Bead C2 0.1 F VDD = 3.3 V C3 0.1 F 130 82 Input Clock Sources* 82 GND PAD CKIN1+ GND VDD 130 0.1 F CKOUT1+ + 100 - CKOUT1- CKIN1- 0.1 F 0.1 F Clock Outputs CKOUT2+ VDD = 3.3 V 130 + 100 - CKOUT2- 130 0.1 F CKIN2+ 82 82 CKIN2- INT_C1B Si5324 Option 1: XA Interrupt/CLKIN_1 Invalid Indicator C2B CLKIN_2 Invalid Indicator LOL PLL Loss of Lock Indicator SS Slave Select 114.285 MHz Crystal XB VDD 15 k RATE[1:0]2 Crystal/Ref Clk Rate 15 k Option 2: SDO 0.1 F Refclk+ Refclk- Control Mode (H) Reset SDI XA 0.1 F SCLK XB CMODE CS_CA Serial Data Out Serial Clock Clock Select/Clock Active RST Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). Figure 4. Si5324 Typical Application Circuit (SPI Control Mode) 18 Rev. 1.1 SPI Interface Serial Data In Si5324 3. Functional Description Xtal or Refclock CKIN1 / N31 CKIN2 / N32 (R) DSPLL Xtal/Refclock Loss of Signal/ Frequency Offset Loss of Lock / NC1_LS CKOUT1 / NC2_LS CKOUT2 /N1_HS / N2 VDD (1.8, 2.5, or 3.3 V) Control Signal Detect GND I2C/SPI Port Clock Select Device Interrupt Rate Select Skew Adjust Figure 5. Si5324 Functional Block Diagram The Si5324 is a low loop bandwidth, jitter-attenuating clock multiplier for high performance applications. The Si5324 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5324 can also use its external reference as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5324 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5324 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from http://www.silabs.com/timing. The Si5324 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyfrequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5324 PLL loop bandwidth is digitally programmable and supports a range from 4 Hz to 525 Hz. A fast lock feature is available to reduce lock times inherent with low loop bandwidth PLLs. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5324 supports hitless switching between the two synchronous input clocks in compliance with Telcordia GR-253-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (maximum 200 ps phase change). Manual and automatic revertive and non-revertive input clock switching options are available. The Si5324 monitors both input clocks for loss-of-signal (LOS) and provides a LOS alarm when it detects missing pulses on either input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. Due to the low loop bandwidth of the part, the LOL indicator clears before the loop fully settles (see "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs" for additional details). The Si5324 also monitors frequency offset alarms (FOS), which indicate if an input clock is within a specified frequency ppm accuracy relative to the frequency of an XA/XB reference clock. Both Stratum 3/3E and SONET Minimum Clock (SMC) FOS thresholds are supported. The Si5324 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL generates an output frequency based on a historical average frequency that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. Rev. 1.1 19 Si5324 The Si5324 has two differential clock outputs. The signal format of each clock output is independently programmable to support LVPECL, LVDS, CML, or CMOS loads. When configured for CMOS, four clock outputs are available. If not required, the second clock output can be powered down to minimize power consumption. In addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. The resolution varies from 800 ps to 2.2 ns depending on the PLL divider settings. The DSPLLsim software utility determines the phase offset resolution for a given combination of input clock and multiplication ratio. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply with bestin-class PSNR. 3.2. Additional Documentation Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed information about the Si5324. Additional design support is available from Silicon Laboratories through your distributor. Silicon Laboratories offers a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from http://www.silabs.com/timing (see "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 AnyFrequency Jitter Attenuating Clock ICs" for additional details). 3.1. External Reference An external, high quality 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal or external reference is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Specific recommendations can be found in the Family Reference Manual. In digital hold, the DSPLL remains locked and tracks the external reference. Note that crystals can have temperature sensitivities. Due to the low bandwidth capabilities of this part, any low-frequency wander or instability on the external reference will transfer to the output clocks. To address this issue, a stable external reference, TXCO, OCXO, or thermally-isolated crystal is recommended. For example, with a 20 ppm oscillator as the reference on the XA/XB pins, temperature changes cause the oscillator to change frequency slightly. Although the Si5324 is locked to its input on CLKIN, it also uses the XA/XB as a reference. If there is a need to use a reference oscillator instead of a crystal, Silicon Labs does not recommend using MEMS based oscillators. Instead, Silicon Labs recommends the Si530EB121M109DG, which is a very low-jitter/wander, LVPECL, 2.5 V crystal oscillator. The very low loop BW of the Si5324 means that it can be susceptible to XAXB reference sources that have high wander. Experience has shown that in spite of having low jitter, some MEMs oscillators have high wander, and these devices should be avoided. Contact Silicon Labs for details. 20 Rev. 1.1 Si5324 3.3. Typical Phase Noise Performance Figure 6. Broadcast Video Table 8. Broadcast Video Jitter1 Jitter Bandwidth2 Jitter (Peak-Peak) Jitter (RMS) 10 Hz to 20 MHz 5.24 ps 484 fs Notes: 1. Number of samples: 8.91E9. 2. Jitter integration bands include low-pass (-20 dB/Dec) and hi-pass (-60 dB/Dec) rolloffs per Telecordia GR-253-CORE. Rev. 1.1 21 Si5324 Figure 7. OTN/SONET/SDH Phase Noise Note: Phase noise plot uses brick wall integration. Table 9. SONET Jitter Jitter Bandwidth* Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 266 fs SONET_OC192_A, 20 kHz to 80 MHz 283 fs SONET_OC192_B, 4 MHz to 80 MHz 155 fs SONET_OC192_C, 50 kHz to 80 MHz 275 fs Brick Wall_800 Hz to 80 MHz 287 fs *Note: Jitter integration bands include low-pass (-20 dB/Dec) and hi-pass (-60 dB/Dec) roll-offs per Telecordia GR-253-CORE. 22 Rev. 1.1 Si5324 Figure 8. Wireless Base Station Phase Noise Table 10. Wireless Base Station Jitter* Jitter Bandwidth Jitter (peak-peak) Jitter (RMS) 10 Hz to 20 MHz 7.28 ps 581 fs Note: Number of samples: 8.91E9 Rev. 1.1 23 Si5324 4. Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined device behavior. Registers not listed, e.g. Register 64, should never be written to. Register D7 0 D6 D5 D4 FREE_RUN CKOUT_ ALWAYS_ON D3 D2 D1 BYPASS_REG 1 CK_PRIOR2[1:0] 2 CK_PRIOR1[1:0] BWSEL_REG[3:0] 3 CKSEL_REG[1:0] 4 AUTOSEL_REG[1:0] 5 ICMOS[1:0] DHOLD SQ_ICAL HST_DEL[4:0] 6 SFOUT2_REG[2:0} SFOUT1_REG[2:0] 7 8 FOSREFSEL[2:0] HLOG_2[1:0] HLOG_1[1:0] 9 HIST_AVG[4:0] 10 DSBL2_ REG DSBL1_ REG 11 19 D0 PD_CK2 FOS_EN FOS_THR[1:0] 20 VALTIME[1:0] CK2_BAD_PIN PD_CK1 LOCK[T2:0] CK1_ BAD_ PIN LOL_PIN INT_PIN CK1_ACTV_PIN CKSEL_PIN CK_BAD_ POL LOL_POL INT_POL 23 LOS2_MSK LOS1_MSK LOSX_MSK 24 FOS2_MSK FOS1_MSK LOL_MSK 21 22 25 CK_ACTV_ POL N1_HS[2:0] 31 NC1_LS[19:16] 32 NC1_LS[15:8] 33 NC1_LS[7:0] 34 NC2_LS[19:16] 35 NC2_LS[15:8] 36 NC2_LS[7:0] 40 N2_HS[2:0] N2_LS[19:16] 41 N2_LS[15:8] 42 N2_LS[7:0] 43 N31[18:16] 44 N31[15:8] 45 N31[7:0] 46 24 N32[18:16] Rev. 1.1 Si5324 Register D7 D6 D5 D4 D3 47 N32[15:8] 48 N32[7:0] 55 D2 D1 CLKIN2RATE[2:0] CLKIN1RATE[2:0] 128 CK2_ACTV_REG CK1_ACTV_REG 129 130 DIGHOLDVALID 131 132 FOS2_FLG 134 LOS2_INT LOS1_INT LOSX_INT FOS2_INT FOS1_INT LOL_INT LOS2_FLG LOS1_FLG LOSX_FLG FOS1_FLG LOL_FLG PARTNUM_RO[11:4] 135 136 D0 PARTNUM_RO[3:0] RST_REG REVID_RO[3:0] ICAL 137 FASTLOCK 138 139 LOS2_EN[0:0] LOS1_EN[0:0] 142 INDEPENDENTSKEW1[7:0] 143 INDEPENDENTSKEW2[7:0] LOS2_EN [1:1] LOS1_EN [1:1] FOS2_EN FOS1_EN Table 11. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table CKOUT_ALWAYS_ON SQ_ICAL Results 0 0 CKOUT OFF until after the first ICAL 0 1 CKOUT OFF until after the first successful ICAL (i.e., when LOL is low) 1 0 CKOUT always ON, including during an ICAL 1 1 CKOUT always ON, including during an ICAL. Use these settings to preserve output-to-output skew Rev. 1.1 25 Si5324 5. Register Descriptions Register 0. Bit D7 Name Type D6 D5 FREE_RUN CKOUT_ ALWAYS_ON R/W R/W R D4 D3 D2 D1 D0 BYPASS_ REG R R R R/W R Reset value = 0001 0100 Bit Name 7 Reserved 6 FREE_RUN 5 Function Reserved. Free Run. Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB reference. 0: Disable 1: Enable CKOUT_ CKOUT Always On. ALWAYS_ON This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on and ICAL is not complete or successful. See Table 11 on page 25. 0: Squelch output until part is calibrated (ICAL). 1: Provide an output. Notes: 1. The frequency may be significantly off until the part is calibrated. 2. Must be 1 to control output to output skew. 26 4:2 Reserved Reserved. 1 BYPASS_ REG Bypass Register. This bit enables or disables the PLL bypass mode. Use only when the device is in digital hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks. 0: Normal operation 1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL. 0 Reserved Reserved. Rev. 1.1 Si5324 Register 1. Bit D7 D6 D5 D4 Name R Type R R D3 D2 D1 D0 CK_PRIOR2 [1:0] CK_PRIOR1 [1:0] R/W R/W R Reset value = 1110 0100 Bit Name Function 7:4 Reserved 3:2 CK_PRIOR2 [1:0] CK_PRIOR 2. Selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: CKIN1 is 2nd priority. 01: CKIN2 is 2nd priority. 10: Reserved 11: Reserved 1:0 CK_PRIOR1 [1:0] CK_PRIOR 1. Selects which of the input clocks will be 1st priority in the autoselection state machine. 00: CKIN1 is 1st priority. 01: CKIN2 is 1st priority. 10: Reserved 11: Reserved Reserved. Register 2. Bit D7 D6 D5 Name BWSEL_REG [3:0] Type R/W D4 D3 D2 D1 D0 R R R R Reset value = 0100 0010 Bit 7:4 3:0 Name Function BWSEL_REG BWSEL_REG. [3:0] Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After BWSEL_REG is written with a new value, an ICAL is required for the change to take effect. Reserved Reserved. Rev. 1.1 27 Si5324 Register 3. Bit D7 D6 D5 D4 Name CKSEL_REG [1:0] DHOLD SQ_ICAL Type R/W R/W R/W D3 D2 D1 D0 R R R R Reset value = 0000 0101 Bit 7:6 28 Name Function CKSEL_REG CKSEL_REG. [1:0] If the device is operating in register-based manual clock selection mode (AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA input pin continues to control clock selection and CKSEL_REG is of no consequence. 00: CKIN_1 selected. 01: CKIN_2 selected. 10: Reserved 11: Reserved 5 DHOLD 4 SQ_ICAL SQ_ICAL. This bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. See Table 11 on page 25. 0: Output clocks enabled during ICAL. 1: Output clocks disabled during ICAL. 3:0 Reserved Reserved. DHOLD. Forces the part into digital hold. This bit overrides all other manual and automatic clock selection controls. 0: Normal operation. 1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the input clocks. Rev. 1.1 Si5324 Register 4. Bit D7 D6 Name AUTOSEL_REG [1:0] Type R/W D5 D4 D3 D2 D1 D0 HIST_DEL [4:0] R R/W Reset value = 0001 0010 Bit Name 7:6 AUTOSEL_ REG [1:0] Function AUTOSEL_REG [1:0]. Selects method of input clock selection to be used. 00: Manual (either register or pin controlled, see CKSEL_PIN) 01: Automatic Non-Revertive 10: Automatic Revertive 11: Reserved 5 Reserved Reserved. 4:0 HIST_DEL [4:0] HIST_DEL [4:0]. Selects amount of delay to be used in generating the history information used for Digital Hold. Register 5. Bit D7 D6 Name ICMOS [1:0] Type R/W D5 D4 D3 D2 D1 D0 R R R R R R Reset value = 1110 1101 Bit Name Function 7:6 ICMOS [1:0] ICMOS [1:0]. When the output buffer is set to CMOS mode, these bits determine the output buffer drive strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation. These values assume CKOUT+ is tied to CKOUT-. 00: 8mA/2mA. 01: 16mA/4mA 10: 24mA/6mA 11: 32mA/8mA 5:0 Reserved Reserved. Rev. 1.1 29 Si5324 Register 6. Bit D7 D6 Name Type R R D5 D4 D3 D2 D1 SFOUT2_REG [2:0] SFOUT1_REG [2:0] R/W R/W D0 Reset value = 0010 1101 30 Bit Name Function 7:6 Reserved Reserved. 5:3 SFOUT2_ REG [2:0] SFOUT2_REG [2:0]. Controls output signal format and disable for CKOUT2 output buffer. Bypass mode is not supported for CMOS output clocks. 000: Reserved 001: Disable 010: CMOS 011: Low swing LVDS 100: Reserved 101: LVPECL 110: CML 111: LVDS 2:0 SFOUT1_ REG [2:0] SFOUT1_REG [2:0]. Controls output signal format and disable for CKOUT1 output buffer. Bypass mode is not supported for CMOS output clocks. 000: Reserved 001: Disable 010: CMOS 011: Low swing LVDS 100: Reserved 101: LVPECL 110: CML 111: LVDS Rev. 1.1 Si5324 Register 7. Bit D7 D6 D5 D4 D3 D1 D0 FOSREFSEL [2:0] Name Type D2 R R R R R R/W Reset value = 0010 1010 Bit Name 7:3 Reserved. 2:0 Function Reserved. FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for Frequency Off-Set (FOS) alarms. 000: XA/XB (External reference) 001: CKIN1 010: CKIN2 011: Reserved 100: Reserved 101: Reserved 110: Reserved 111: Reserved Rev. 1.1 31 Si5324 Register 8. Bit D7 D6 D5 D4 Name HLOG_2[1:0] HLOG_1[1:0] Type R/W R/W D3 D2 D1 D0 R R R R Reset value = 0000 0000 Bit Name Function 7:6 HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur without glitches or runt pulses. 10:Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur without glitches or runt pulses. 11: Reserved 5:4 HLOG_1 [1:0] HLOG_1 [1:0]. 00: Normal operation 01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur without glitches or runt pulses. 10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur without glitches or runt pulses. 11: Reserved 3:0 Reserved Reserved. Register 9. Bit D7 D6 D5 Name HIST_AVG [4:0] Type R/W D4 D3 D2 D1 D0 R R R Reset value = 1100 0000 32 Bit Name 7:3 HIST_AVG [4:0] 2:0 Reserved Function HIST_AVG [4:0]. Selects amount of averaging time to be used in generating the history information for Digital Hold. Reserved. Rev. 1.1 Si5324 Register 10. Bit D7 D6 D5 D4 Name R Type R R D3 D2 DSBL2_REG DSBL1_REG R/W R/W R D1 D0 R R Reset value = 0000 0000 Bit Name 7:4 Reserved Function Reserved. 3 DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2_LS output divider is also powered down. 0: CKOUT2 enabled. 1: CKOUT2 disabled. 2 DSBL1_REG DSBL1_REG. This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is selected, the NC1_LS output divider is also powered down. 0: CKOUT1 enabled. 1: CKOUT1 disabled. 1:0 Reserved Reserved. Register 11. Bit D7 D6 D5 D4 D3 D2 Name Type R R R R R R D1 D0 PD_CK2 PD_CK1 R/W R/W Reset value = 0100 0000 Bit Name Function 7:2 Reserved Reserved. 1 PD_CK2 PD_CK2. This bit controls the powerdown of the CKIN2 input buffer. 0: CKIN2 enabled. 1: CKIN2 disabled. 0 PD_CK1 PD_CK1. This bit controls the powerdown of the CKIN1 input buffer. 0: CKIN1 enabled. 1: CKIN1 disabled. Rev. 1.1 33 Si5324 Register 19. Bit D7 D6 D5 D4 D3 D2 D1 Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0] Type R/W R/W R/W R/W D0 Reset value = 0010 1100 Bit Name Function 7 FOS_EN FOS_EN. Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSx_EN, register 139). 0: FOS disable 1: FOS enabled by FOSx_EN 6:5 FOS_THR [1:0] FOS_THR [1:0]. Frequency Offset at which FOS is declared: 00: 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK 01: 48 to 49 ppm (SMC) 10: 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK. 11: 200 ppm 4:3 VALTIME [1:0] VALTIME [1:0]. Sets amount of time for input clock to be valid before the associated alarm is removed. 00: 2 ms 01: 100 ms 10: 200 ms 11: 13 seconds 2:0 LOCKT [2:0] LOCKT [2:0]. Sets retrigger interval for one shot monitoring phase detector output. One shot is triggered by phase slip in DSPLL. Refer to the Family Reference Manual for more details. To minimize lock time, the value 001 for LOCKT is recommended (see "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs" for additional details). 000: 106 ms 001: 53 ms 010: 26.5 ms 011: 13.3 ms 100: 6.6 ms 101: 3.3 ms 110: 1.66 ms 111: .833 ms 34 Rev. 1.1 Si5324 Register 20. Bit D7 D6 D5 D4 Name Type R R R R D3 D2 D1 D0 CK2_BAD_PIN CK1_BAD_PIN LOL_PIN INT_PIN R/W R/W R/W R/W Reset value = 0011 1110 Bit Name 7:4 Reserved Function Reserved. 3 CK2_BAD_PIN CK2_BAD_PIN. The CK2_BAD status can be reflected on the C2B output pin. 0: C2B output pin tristated 1: C2B status reflected to output pin 2 CK1_BAD_PIN CK1_BAD_PIN. The CK1_BAD status can be reflected on the C1B output pin. 0: C1B output pin tristated 1: C1B status reflected to output pin 1 LOL_PIN LOL_PIN. The LOL_INT status bit can be reflected on the LOL output pin. 0: LOL output pin tristated 1: LOL_INT status reflected to output pin 0 INT_PIN INT_PIN. Reflects the interrupt status on the INT_C1B output pin. 0: Interrupt status not displayed on INT_C1B output pin. If CK1_BAD_PIN = 0, INT_C1B output pin is tristated. 1: Interrupt status reflected to output pin. Instead, the INT_C1B pin indicates when CKIN1 is bad. Rev. 1.1 35 Si5324 Register 21. Bit D7 D6 D5 D4 D3 D2 Name Type R R R R R R D1 D0 CK1_ACTV_PIN CKSEL_ PIN R/W R/W Reset value = 1111 1111 Bit Name 7:2 Reserved 1 0 36 Function Reserved. CK1_ACTV_PIN CK1_ACTV_PIN. The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin controlled clock selection is not being used. 0: CS_CA output pin tristated. 1: Clock Active status reflected to output pin. CKSEL_PIN CKSEL_PIN. If manual clock selection is being used, clock selection can be controlled via the CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when AUTOSEL_REG = Manual. 0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection. 1: CS_CA input pin controls clock selection. Rev. 1.1 Si5324 Register 22. Bit D7 D6 D5 D4 Name Type R R R R D3 D2 D1 D0 CK_ACTV_POL CK_BAD_ POL LOL_POL INT_POL R/W R/W R/W R/W Reset value = 1101 1111 Bit Name Function 7:4 Reserved 3 CK_ACTV_ POL 2 CK_BAD_ POL 1 LOL_POL LOL_POL. Sets the active polarity for the LOL status when reflected on an output pin. 0: Active low 1: Active high 0 INT_POL INT_POL. Sets the active polarity for the interrupt status when reflected on the INT_C1B output pin. 0: Active low 1: Active high Reserved. CK_ACTV_POL. Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: Active low 1: Active high CK_BAD_POL. Sets the active polarity for the INT_C1B and C2B signals when reflected on output pins. 0: Active low 1: Active high Rev. 1.1 37 Si5324 Register 23. Bit D7 D6 D5 D4 D3 Name Type R R R R R D2 D1 D0 LOS2_ MSK LOS1_ MSK LOSX_ MSK R/W R/W R/W Reset value = 0001 1111 38 Bit Name Function 7:3 Reserved 2 LOS2_MSK LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOS2_FLG register. 0: LOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: LOS2_FLG ignored in generating interrupt output. 1 LOS1_MSK LOS1_MSK. Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOS1_FLG register. 0: LOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: LOS1_FLG ignored in generating interrupt output. 0 LOSX_MSK LOSX_MSK. Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOSX_FLG register. 0: LOSX alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: LOSX_FLG ignored in generating interrupt output. Reserved. Rev. 1.1 Si5324 Register 24. Bit D7 D6 D5 D4 D3 Name Type R R R R R D2 D1 D0 FOS2_MSK FOS1_MSK LOL_MSK R/W R/W R/W Reset value = 0011 1111 Bit Name Function 7:3 Reserved 2 FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this register do not change the value held in the FOS2_FLG register. 0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: FOS2_FLG ignored in generating interrupt output. 1 FOS1_MSK FOS1_MSK. Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the FOS1_FLG register. 0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: FOS1_FLG ignored in generating interrupt output. 0 LOL_MSK LOL_MSK. Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the LOL_FLG register. 0: LOL alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: LOL_FLG ignored in generating interrupt output. Reserved. Rev. 1.1 39 Si5324 Register 25. Bit D7 D6 Name N1_HS [2:0] Type R/W D5 D4 D3 D2 D1 D0 R R R R R Reset value = 0010 0000 Bit Name Function 7:5 N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider. 000: N1= 4 001: N1= 5 010: N1=6 011: N1= 7 100: N1= 8 101: N1= 9 110: N1= 10 111: N1= 11 4:0 Reserved Reserved. Register 31. Bit D7 D6 D5 D4 D3 D1 D0 NC1_LS [19:16] Name Type D2 R R R R R/W Reset value = 0000 0000 40 Bit Name Function 7:4 Reserved Reserved. 3:0 NC1_LS [19:16] NC1_LS [19:16]. Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Rev. 1.1 Si5324 Register 32. Bit D7 D6 D5 D4 D3 Name NC1_LS [15:8] Type R/W D2 D1 D0 Reset value = 0000 0000 Bit 7:0 Name Function NC1_LS [15:8] NC1_LS [15:8]. Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Register 33. Bit D7 D6 D5 D4 D3 Name NC1_LS [7:0] Type R/W D2 D1 D0 Reset value = 0011 0001 Bit Name Function 7:0 NC1_LS [19:0] NC1_LS [7:0]. Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Rev. 1.1 41 Si5324 Register 34. Bit D7 D6 D5 D4 D3 D2 D1 D0 NC2_LS [19:16] Name R Type R R R R/W Reset value = 0000 0000 Bit Name Function 7:4 Reserved Reserved. 3:0 NC2_LS [19:16] NC2_LS [19:16]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Register 35. Bit D7 D6 D5 D4 D3 Name NC2_LS [15:8] Type R/W D2 D1 D0 Reset value = 0000 0000 Bit 7:0 42 Name Function NC2_LS [15:8] NC2_LS [15:8]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Rev. 1.1 Si5324 Register 36. Bit D7 D6 D5 D4 D3 Name NC2_LS [7:0] Type R/W D2 D1 D0 Reset value = 0011 0001 Bit 7:0 Name Function NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 220 Valid divider values = [1, 2, 4, 6, ..., 220] Rev. 1.1 43 Si5324 Register 40. Bit D7 D6 Name N2_HS [2:0] Type R/W D5 D4 D3 D2 D1 N2_LS [19:16] R R/W Reset value = 1100 0000 44 Bit Name 7:5 N2_HS [2:0] 4 Reserved 3:0 N2_LS [19:16] Function N2_HS [2:0]. Sets value for N2 high speed divider which drives N2LS low-speed divider. 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111: 11 Reserved. N2_LS [19:16]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 220 Valid divider values = [2, 4, 6, ..., 220] Rev. 1.1 D0 Si5324 Register 41. Bit D7 D6 D5 D4 D3 Name N2_LS [15:8] Type R/W D2 D1 D0 D1 D0 Reset value = 0000 0000 Bit 7:0 Name Function N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 220 Valid divider values = [2, 4, 6, ..., 220] Register 42. Bit D7 D6 D5 D4 D3 Name N2_LS [7:0] Type R/W D2 Reset value = 1111 1001 Bit Name 7:0 N2_LS [7:0] Function N2_LS [7:0]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 220 Valid divider values = [2, 4, 6, ..., 220] Rev. 1.1 45 Si5324 Register 43. Bit D7 D6 D5 D4 D3 D2 D1 D0 N31 [18:16] Name R Type R R R R R/W Reset value = 0000 0000 Bit Name 7:3 Reserved 2:0 N31 [18:16] Function Reserved. N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 219 Valid divider values = [1, 2, 3, ..., 219] Register 44. Bit D7 D6 D5 D4 D3 Name N31_[15:8] Type R/W Reset value = 0000 0000 46 Bit Name 7:0 N31_[15:8] Function N31_[15:8]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 219 Valid divider values = [1, 2, 3, ..., 219] Rev. 1.1 D2 D1 D0 Si5324 Register 45. Bit D7 D6 D5 D4 D3 Name N31_[7:0] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 Function N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 219 Valid divider values = [1, 2, 3, ..., 219] Register 46. Bit D7 D6 D5 D4 D3 N32_[18:16] Name Type R R R R R R/W Reset value = 0000 0000 Bit Name 7:3 Reserved 2:0 N32_[18:16] Function Reserved. N32_[18:16]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 219 Valid divider values = [1, 2, 3, ..., 219] Rev. 1.1 47 Si5324 Register 47. Bit D7 D6 D5 D4 D3 Name N32_[15:8] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] Function N32_[15:8]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 219 Valid divider values = [1, 2, 3, ..., 219] Register 48. Bit D7 D6 D5 D4 D3 Name N32_[7:0] Type R/W Reset value = 0000 1001 48 Bit Name 7:0 N32_[7:0] Function N32_[7:0]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 219 Valid divider values = [1, 2, 3, ..., 219] Rev. 1.1 Si5324 Register 55. Bit D7 D6 Name Type R R D5 D4 D3 D2 D1 CLKIN2RATE_[2:0] CLKIN1RATE[2:0] R/W R/W D0 Reset value = 0000 0000 Bit Name Function 7:6 Reserved 5:3 CLKIN2RATE[2:0] 2:0 CLKIN1RATE [2:0] CLKIN1RATE[2:0]. CKINn frequency selection for FOS alarm monitoring. 000: 10-27 MHz 001: 25-54 MHz 002: 50-105 MHz 003: 95-215 MHz 004: 190-435 MHz 005: 375-710 MHz 006: Reserved 007: Reserved Reserved. CLKIN2RATE_[2:0]. CKINn frequency selection for FOS alarm monitoring. 000: 10-27 MHz 001: 25-54 MHz 002: 50-105 MHz 003: 95-215 MHz 004: 190-435 MHz 005: 375-710 MHz 006: Reserved 007: Reserved Rev. 1.1 49 Si5324 Register 128. Bit D7 D6 D5 D4 D3 D2 D1 D0 CK2_ACTV_REG CK1_ACTV_REG Name R Type R R R R R R R Reset value = 0010 0000 Bit Name Function 7:2 Reserved 1 CK2_ACTV_REG CK2_ACTV_REG. Indicates if CKIN2 is currently the active clock for the PLL input. 0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1. 1: CKIN2 is the active input clock. 0 CK1_ACTV_REG CK1_ACTV_REG. Indicates if CKIN1 is currently the active clock for the PLL input. 0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1. 1: CKIN1 is the active input clock. Reserved. Register 129. Bit D7 D6 D5 D4 D3 Name Type R R R R R D2 D1 D0 LOS2_INT LOS1_INT LOSX_INT R R R Reset value = 0000 0110 50 Bit Name Function 7:3 Reserved Reserved. 2 LOS2_INT LOS2_INT. Indicates the LOS status on CKIN2. 0: Normal operation. 1: Internal loss-of-signal alarm on CKIN2 input. 1 LOS1_INT LOS1_INT. Indicates the LOS status on CKIN1. 0: Normal operation. 1: Internal loss-of-signal alarm on CKIN1 input. 0 LOSX_INT LOSX_INT. Indicates the LOS status of the external reference on the XA/XB pins. 0: Normal operation. 1: Internal loss-of-signal alarm on XA/XB reference clock input. Rev. 1.1 Si5324 Register 130. Bit D7 D5 D4 D3 DIGHOLDVALID Name Type D6 R R R R D2 D1 D0 FOS2_INT FOS1_INT LOL_INT R R R R Reset value = 0000 0001 Bit Name Function 7 Reserved 6 DIGHOLDVALID 5:3 Reserved Reserved. 2 FOS2_INT CKIN2 Frequency Offset Status. 0: Normal operation. 1: Internal frequency offset alarm on CKIN2 input. 1 FOS1_INT CKIN1 Frequency Offset Status. 0: Normal operation. 1: Internal frequency offset alarm on CKIN1 input. 0 LOL_INT Reserved. Digital Hold Valid. Indicates if the digital hold circuit has enough samples of a valid clock to meet digital hold specifications. 0: Indicates digital hold history registers have not been filled. The digital hold output frequency may not meet specifications. 1: Indicates digital hold history registers have been filled. The digital hold output frequency is valid. PLL Loss of Lock Status. 0: PLL locked. 1: PLL unlocked. Rev. 1.1 51 Si5324 Register 131. Bit D7 D6 D5 D4 D3 D1 D0 LOS2_FLG LOS1_FLG LOSX_FLG Name Type D2 R R R R R R/W R/W R/W Reset value = 0001 1111 52 Bit Name Function 7:3 Reserved 2 LOS2_FLG CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to this bit. 1 LOS1_FLG CKIN1 Loss-of-Signal Flag. 0: Normal operation 1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to this bit. 0 LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag. 0: Normal operation 1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to this bit. Reserved. Rev. 1.1 Si5324 Register 132. Bit D7 D6 D5 D4 D2 FOS2_FLG FOS1_FLG Name Type D3 R R R R R/W R/W D1 D0 LOL_FLG R/W R Reset value = 0000 0010 Bit Name Function 7:4 Reserved 3 FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to this bit. 2 FOS1_FLG CLKIN_1 Frequency Offset Flag. 0: Normal operation 1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to this bit. 1 LOL_FLG PLL Loss of Lock Flag. 0: PLL locked 1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to this bit. 0 Reserved Reserved. Reserved. Rev. 1.1 53 Si5324 Register 134. Bit D7 D6 D5 D4 D3 Name PARTNUM_RO [11:4] Type R D2 D1 D0 D2 D1 D0 Reset value = 0000 0001 Bit Name Function 7:0 PARTNUM_RO [11:0] Device ID (1 of 2). 0000 0001 1000: Si5324 Others Reserved Register 135. Bit D7 D6 D5 D4 D3 Name PARTNUM_RO [3:0] REVID_RO [3:0] Type R R Reset value = 1000 0010 54 Bit Name 7:4 PARTNUM_RO [11:0] 3:0 REVID_RO [3:0] Function Device ID (2 of 2). 0000 0001 1000: Si5324 Others Reserved Indicates Revision Number of Device. 0010: Revision C Others Reserved. Rev. 1.1 Si5324 Register 136. Bit D7 D6 Name RST_REG ICAL Type R/W R/W D5 D4 D3 D2 D1 D0 R R R R R R Reset value = 0000 0000 Bit Name 7 RST_REG Function Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted. 0: Normal operation. 1: Reset of all internal logic. Outputs disabled or tristated during reset. 6 ICAL 5:0 Reserved Start an Internal Calibration Sequence. For proper operation, the device must go through an internal calibration sequence. ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be present to begin ICAL. Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take effect. 0: Normal operation. 1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibration, LOL will go low. Reserved. Rev. 1.1 55 Si5324 Register 137. Bit D7 D6 D5 D4 D3 D2 D1 D0 FASTLOCK Name R Type R R R R R R R/W Reset value = 0000 0000 Bit Name 7:1 Reserved 0 FASTLOCK Function Do not modify. This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by dynamically changing the loop bandwidth. Register 138. Bit D7 D6 D5 D4 D3 D2 Name Type R R R R R R D1 D0 LOS2_EN [1:1] LOS1_EN [1:1] R/W R/W Reset value = 0000 1111 Bit Name 7:2 Reserved 1 LOS2_EN [1:0] Function Reserved. Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA monitoring. 11: Enable LOS monitoring. LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual for details. 0 LOS1_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2). Note: LOS1_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA monitoring. 11: Enable LOS monitoring. LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual for details. 56 Rev. 1.1 Si5324 Register 139. Bit D7 D6 Name Type R D5 D4 LOS2_EN [0:0] LOS1_EN [0:0] R/W R/W R D3 D2 D1 D0 FOS2_EN FOS1_EN R R R/W R/W Reset value = 1111 1111 Bit Name 7:6 Reserved Function Reserved. 5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA monitoring. 11: Enable LOS monitoring. LOSA is a slower and less sensitive version of LOS. See the family reference manual for details. 4 LOS_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2). Note: LOS1_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA monitoring. 11: Enable LOS monitoring. LOSA is a slower and less sensitive version of LOS. See the family reference manual for details. 3:2 Reserved Reserved. 1 FOS2_EN Enables FOS on a Per Channel Basis. 0: Disable FOS monitoring. 1: Enable FOS monitoring. 0 FOS1_EN Enables FOS on a Per Channel Basis. 0: Disable FOS monitoring. 1: Enable FOS monitoring. Rev. 1.1 57 Si5324 Register 142. Bit D7 D6 D5 D4 D3 D2 Name INDEPENDENTSKEW1 [7:0] Type R/W D1 D0 Reset value = 0000 0000 Bit Name 7:0 INDEPENDENTSKEW1 [7:0] Function INDEPENDENTSKEW1. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. Default = 0. Register 143. Bit D7 D6 D5 D4 D3 D2 Name INDEPENDENTSKEW2 [7:0] Type R/W D1 D0 Reset value = 0000 0000 Bit 7:0 58 Name Function INDEPENDENTSKEW2 [7:0] INDEPENDENTSKEW2. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. Default = 0. Rev. 1.1 Si5324 5.1. ICAL The device's registers must be configured for the intended applications. After the part is configured, the part must perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after a successful calibration operation, changing any of the Registers indicated in Table 12 requires that a calibration be performed again by the same procedure (writing a "1" to bit D6 in register 136). Table 12. ICAL-Sensitive Registers Address Register 0 BYPASS_REG 0 CKOUT_ALWAYS_ON 1 CK_PRIOR1 1 CK_PRIOR2 2 BWSEL_REG 4 HIST_DEL 5 ICMOS 7 FOSREFSEL 9 HIST_AVG 10 DSBL1_REG 10 DSBL2_REG 11 PD_CK1 11 PD_CK2 19 FOS_EN 19 FOS_THR 19 LOCKT 19 VALTIME 25 N1HS 31 NC1_LS 34 NC2_LS 40 N2_HS 40 N2_LS 43 N31 46 N32 55 CLKIN1RATE 55 CLKIN2RATE Rev. 1.1 59 Si5324 CKOUT1- CKOUT1+ NC GND NC VDD CKOUT2- CKOUT2+ CMODE 6. Pin Descriptions 36 35 34 33 32 31 30 29 28 RST 1 27 SDI NC 2 26 A2_SS INT_C1B 3 25 A1 C2B 4 VDD 5 24 A0 XA 6 XB 7 21 CS_CA GND 8 20 GND NC 9 GND Pad 23 SDA_SDO 22 SCL 19 GND LOL CKIN1- CKIN1+ RATE1 NC CKIN2- CKIN2+ RATE0 VDD 10 11 12 13 14 15 16 17 18 Pin # Pin Name I/O Signal Level Description 1 RST I LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are disabled during reset. The part must be programmed after a reset or power-on to get a clock output. See Family Reference Manual for details. This pin has a weak pull-up. 2, 9, 14, 30, 33 NC 3 INT_C1B No Connection. Leave floating. Make no external connections to this pin for normal operation. O LVCMOS Interrupt/CKIN1 Invalid Indicator. This pin functions as a device interrupt output or an alarm output for CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. If used as an alarm output, the pin functions as a LOS (and optionally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and INT_PIN = 0. 0 = CKIN1 present. 1 = LOS (FOS) on CKIN1. The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. 60 Rev. 1.1 Si5324 Pin # Pin Name I/O Signal Level Description 4 C2B O LVCMOS CKIN2 Invalid Indicator. This pin functions as a LOS (and optionally FOS) alarm indicator for CKIN2 if CK2_BAD_PIN = 1. 0 = CKIN2 present. 1 = LOS (FOS) on CKIN2. The active polarity can be changed by CK_BAD_POL. If CK2_BAD_PIN = 0, the pin tristates. 5, 10, 32 VDD VDD Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following Vdd pins: 5 0.1 F 10 0.1 F 32 0.1 F A 1.0 F should also be placed as close to the device as is practical. 7 6 XB XA I Analog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. Refer to Family Reference Manual for interfacing to an external reference. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by RATE[1:0] pins. 8, 31, 20, 19 GND GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Grounding these pins does not eliminate the requirement to ground the GND PAD on the bottom of the package. 11 15 RATE0 RATE1 I 3-Level External Crystal or Reference Clock Rate. Three level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. Refer to the Family Reference Manual for settings. These pins have both a weak pull-up and a weak pull-down; they default to M. L setting corresponds to ground. M setting corresponds to VDD/2. H setting corresponds to VDD. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 16 17 CKIN1+ CKIN1- I Multi Clock Input 1. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. 12 13 CKIN2+ CKIN2- I Multi Clock Input 2. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Rev. 1.1 61 Si5324 Pin # Pin Name I/O Signal Level Description 18 LOL O LVCMOS PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator if the LOL_PIN register bit is set to 1. 0 = PLL locked. 1 = PLL unlocked. If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit (see "AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs" for additional details). 21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator. Input: In manual clock selection mode, this pin functions as the manual input clock selector if the CKSEL_PIN is set to 1. 0 = Select CKIN1. 1 = Select CKIN2. If CKSEL_PIN = 0, the CKSEL_REG register bit controls this function and this input tristates. If configured for input, must be tied high or low. Output: In automatic clock selection mode, this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both clocks, CK_ACTV will indicate the last active clock that was used before entering the digital hold state. The CK_ACTV_PIN register bit must be set to 1 to reflect the active clock status to the CK_ACTV output pin. 0 = CKIN1 active input clock. 1 = CKIN2 active input clock. If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will always be reflected in the CK_ACTV_REG read only register bit. 22 SCL I LVCMOS Serial Clock. This pin functions as the serial clock input for both SPI and I2C modes. This pin has a weak pull-down. 23 SDA_SDO I/O LVCMOS Serial Data. In I2C control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output. 25 24 A1 A0 I LVCMOS Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. The I2C address is 1101 [A2] [A1] [A0]. In SPI control mode (CMODE = 1), these pins are ignored. These pins have a weak pull-down. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. 62 Rev. 1.1 Si5324 Pin # Pin Name I/O Signal Level Description 26 A2_SS I LVCMOS Serial Port Address/Slave Select. In I2C control mode (CMODE = 0), this pin functions as a hardware controlled address bit [A2]. In SPI control mode (CMODE = 1), this pin functions as the slave select input. This pin has a weak pull-down. 27 SDI I LVCMOS Serial Data In. In I2C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. This pin has a weak pull-down. 29 28 CKOUT1- CKOUT1+ O Multi Output Clock 1. Differential output clock with a frequency range of 8 kHz to 1.4175 GHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 34 35 CKOUT2- CKOUT2+ O Multi Output Clock 2. Differential output clock with a frequency range of 8 kHz to 1.4175 GHz. Output signal format is selected by SFOUT2_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 36 CMODE I LVCMOS GND PAD GND GND Supply Control Mode. Selects I2C or SPI control mode for the Si5324. 0 = I2C Control Mode 1 = SPI Control Mode This pin must not be NC. Tie either high or low. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Rev. 1.1 63 Si5324 7. Ordering Guide Ordering Part Number1 Output Clock Frequency Range Package ROHS6, Pb-Free Temperature Range Si5324A-C-GM2 2 kHz-945 MHz 970-1134 MHz 1.213-1.417 GHz 36-Lead 6 x 6 mm QFN Yes -40 to 85 C Si5324B-C-GM2 2 kHz-808 MHz 36-Lead 6 x 6 mm QFN Yes -40 to 85 C Si5324C-C-GM2 2 kHz-346 MHz 36-Lead 6 x 6 mm QFN Yes -40 to 85 C Si5324D-C-GM2 2 kHz-150 MHz 36-Lead 6 x 6 mm QFN Yes -40 to 85 C Si5324E-C-GM3 2 kHz-945 MHz 970-1134 MHz 1.213-1.417 GHz 36-Lead 6 x 6 mm QFN Yes -40 to 85 C Notes: 1. Add an R at the end of the device to denote tape and reel options. 2. These OPNs are recommended for all new designs. Refer to AN803 for more information. 3. This OPN is intended for use in legacy designs in which the Si5324 device must retain the original lock time behavior as described in AN803 and Product Bulletin (PB-1312191): "Si5324, Si5374, Si5374 Loss of Lock (LOL) Time Behavior: New Applications Note and Ordering Options". 64 Rev. 1.1 Si5324 Table 13. Product Selection Guide Part Number Control Number of Input Output RMS Phase Jitter PLL Hitless Inputs and Frequency Frequency (12 kHz-20 MHz) Bandwidth Switching Outputs (MHz)* (MHz)* Free Run Mode Package 0.008-644 0.45 ps 60 Hz to 8 kHz 19-710 19-710 0.3 ps 60 Hz to 8 kHz 6x6 mm 36-QFN 1-710 1-710 0.3 ps 60 Hz to 8 kHz 6x6 mm 36-QFN 1PLL, 1 | 1 0.002-710 0.002-1417 0.3 ps 60 Hz to 8 kHz Pin 1PLL, 2 | 2 0.008-707 0.008-1050 0.3 ps 60 Hz to 8 kHz Si5324 I2C/SPI 1PLL, 2 | 2 0.002-710 0.002-1417 0.3 ps 4 Hz to 525 Hz 6x6 mm 36-QFN Si5326 I2C/SPI 1PLL, 2 | 2 0.002-710 0.002-1417 0.3 ps 60 Hz to 8 kHz 6x6 mm 36-QFN Si5327 I2C/SPI 1PLL, 2 | 2 0.002-710 0.002-808 0.5 ps 60 Hz to 8 kHz 6x6 mm 36-QFN Si5366 Pin 1PLL, 4 | 5 0.008-707 0.008-1050 0.3 ps 60 Hz to 8 kHz Si5368 I2C/SPI 1PLL, 4 | 5 0.002-710 0.002-1417 0.3 ps 60 Hz to 8 kHz 14x14 mm 100-TQFP Si5369 I2C/SPI 1PLL, 4 | 5 0.002-710 0.002-1417 0.3 ps 4 Hz to 525 Hz 14x14 mm 100-TQFP Si5374 I 2C 4PLL, 8 | 8 0.002-710 0.002-808 0.4 ps 4 Hz to 525 Hz 10x10 mm 80-BGA Si5375 I 2C 4PLL, 4 | 4 0.002-710 0.002-808 0.4 ps 60 Hz to 8 kHz 10x10 mm 80-BGA Si5315 Pin 1PLL, 2 | 2 0.008-644 Si5316 Pin 1PLL, 2 | 1 Si5317 Pin 1PLL, 1 | 2 Si5319 I2C/SPI Si5323 6x6 mm 36-QFN 6x6 mm 36-QFN 6x6 mm 36-QFN 14x14 mm 100-TQFP *Note: Maximum input and output rates may be limited by speed rating of device. See each device's data sheet for ordering information. Rev. 1.1 65 Si5324 1.8, 2.5 V Operation 1.8, 2.5, 3.3 V Operation 100 Lead 14 x 14 mm TQFP 36 Lead 6 mm x 6 mm QFN FSYNC Realignment LOL Alarm FOS Alarm Hitless Switching LOS Jitter Generation (12 kHz - 20 MHz) Max Output Frequency (MHz) Max Input Freq (MHz)1 P Control Clock Outputs Clock Inputs Device Table 14. Product Selection Guide (Si5322/25/65/67) Low Jitter Precision Clock Multipliers (Wideband) Si5322 2 2 Si5325 2 2 Si5365 4 5 Si5367 4 5 707 1050 0.6 ps rms typ 710 1400 0.6 ps rms typ 707 1050 0.6 ps rms typ 710 1400 0.6 ps rms typ Notes: 1. Maximum input and output rates may be limited by speed rating of device. See each device's data sheet for ordering information. 2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal or reference clock. 66 Rev. 1.1 Si5324 8. Package Outline: 36-Pin QFN Figure 9 illustrates the package details for the Si5324. Table 15 lists the values for the dimensions shown in the illustration. Figure 9. 36-Pin Quad Flat No-lead (QFN) Table 15. Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 -- -- 12 b 0.18 0.25 0.30 aaa -- -- 0.10 bbb -- -- 0.10 ccc -- -- 0.08 D D2 L 6.00 BSC 3.95 4.10 4.25 Min Nom Max 0.50 0.60 0.70 e 0.50 BSC ddd -- -- 0.10 E 6.00 BSC eee -- -- 0.05 E2 3.95 4.10 4.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 67 Si5324 9. PCB Land Pattern Figure 10. PCB Land Pattern Diagram Figure 11. Ground Pad Recommended Layout 68 Rev. 1.1 Si5324 Table 16. PCB Land Pattern Dimensions Dimension MIN MAX e 0.50 BSC. E 5.42 REF. D 5.42 REF. E2 4.00 4.20 D2 4.00 4.20 GE 4.53 -- GD 4.53 -- X -- 0.28 Y 0.89 REF. ZE -- 6.31 ZD -- 6.31 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 69 Si5324 10. Top Marking 10.1. Si5324 Top Marking (QFN) 10.2. Top Marking Explanation Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5324Q Customer Part Number Q = Speed Code: A, B, C, D See Ordering Guide for options. Line 2 Marking: C-GM C = Product Revision G = Temperature Range -40 to 85 C (RoHS6) M = QFN Package Line 3 Marking: YYWWRF YY = Year WW = Work Week R = Die Revision F = Internal code Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter Lower-Left Justified XXXX Internal Code 70 Rev. 1.1 Si5324 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Added reference to AN803 on pages 11,19,20,34,62. Added additional LOL and Settling Time Specs on page 11. Added new part numbers on page 64. Revision 0.1 to Revision 0.2 Updated Rise/Fall Time values. Updated minimum loop BW value. Revision 0.2 to Revision 0.25 Updated features and applications. Changed maximum loop bandwidth to 525 Hz (global). Updated PLL performance specifications in Table 1. Added Typical Video Phase Noise Plot and data. Removed references to Si5325. Added note to register CKOUT_ALWAYS_ON on how to control output to output skew. Added Product Selection Guide to Section "7. Ordering Guide". Corrected typographical errors in Table 1. Updated typical phase noise performance page. Updated functional description. Added additional phase noise plots to Section "3.3. Typical Phase Noise Performance". Updated Register Map. Revised Device Top Mark. Revision 0.25 to Revision 0.3 Changed Any-Rate to Any-Frequency Changed Table 2, "Absolute Maximum Ratings," on page 6. Added Table 11, "CKOUT_ALWAYS_ON and SQ_ICAL Truth Table," on page 25 Added "no bypass with CMOS outputs" Revision 0.3 to Revision 1.0 Expanded spec Tables 1 and 2 to include all specifications in the Reference Manual. Reordered sections to conform to data sheet quality convention. Added tSETTLE specification. Corrected minor register map typos. Minor changes to Table 2. Added maximum lock and settle times to Table 3. Added titles to Tables 8, 9, and 10. Updated/added selection guide Tables 13 and 14. Removed SLEEP from register map. Added warning about MEMS reference oscillators to "3.1. External Reference" on page 20. Rev. 1.1 71 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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