SI5324-EVB - Silicon Labs - Datasheet.Live

Si5324

Features

Applications

Description

The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier

for applications requiring sub 1 ps jitter performance with loop bandwidths

between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz

to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided

down separately from a common source. The Si5324 can also use its

external reference as a clock source for frequency synthesis. The device

provides virtually any frequency translation combination across this

operating range. The Si5324 input clock frequency and clock multiplication

ratio are programmable via an I2C or SPI interface. The Si5324 is based on

Silicon Laboratories' 3rd-generation DSPLL® technology, which provides

any-frequency synthesis and jitter attenuation in a highly integrated PLL

solution that eliminates the need for external VCXO and filter components.

The DSPLL loop bandwidth is digitally programmable, providing jitter

performance optimization at the application level. The Si5324 is ideal for

providing clock multiplication and jitter attenuation in high performance

timing applications.

Generates any frequency from

2 kHz to 945 MHz and select

frequencies to 1.4 GHz from an

input frequency of 2 kHz to

710 MHz

Ultra-low jitter clock outputs as low

as 290 fs rms (12 kHz–20 MHz),

320 fs rms (50 kHz–80 MHz)

Integrated loop filter with

selectable loop bandwidth

(4– 525 Hz)

Meets ITU-T G.8251 and Telcordia

GR-253-CORE jitter specification

Hitless input clock switching with

phase build-out

Freerun, Digital Hold operation

Configurable signal format per

output (LVPECL, LVDS, CML,

CMOS)

Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236, 239/237, 66/64, 239/238,

15/14, 253/221, 255/238)

LOL, LOS, FOS alarm outputs

I2C or SPI programmable

On-chip voltage regulator with high

PSNR

Single supply 1.8 ±5%, 2.5 ±10%,

or 3.3 V ±10%

Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS-compliant

Broadcast video –3G/HD/SD-SDI,

Genlock

Packet Optical Transport Systems

(P-OTS), MSPP

OTN/OTU-1/2/3/4 Asynchronous

Demapping (Gapped Clock)

SONET OC-48/192/768,

SDH/STM-16/64/256 line cards

1/2/4/8/10G Fibre Channel line

cards

GbE/10/40/100G Synchronous

Ethernet (LAN/WAN)

Data converter clocking

Wireless base stations

Test and measurement

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/

JITTER ATTENUATOR

Ordering Information:

See page 64.

Pin Assignments

2930313233343536

10 11 12 13 14 15 16 17

RST

C2B

INT_C1B

GND

VDD

RATE0

CKIN2+

CKIN2–

RATE1

CKIN1+

CKIN1–

CS_CA

SCL

SDA_SDO

A2_SS

SDI

CKOUT1–

GND

VDD

CKOUT2–

CKOUT2+

CMODE

GND

Pad

GND

LOL

GND

CKOUT1+

Si5324

2 Rev. 1.1

Functional Block Diagram

DSPLL

Loss of Signal/

Frequency Offset

Xtal or Refclock

CKOUT2

CKIN1

CKOUT1

CKIN2

÷ N31

÷ N2

÷ NC1_LS

÷ NC2_LS

Skew Adjust

Signal Detect

Device Interrupt

VDD (1.8, 2.5, or 3.3 V)

GND

÷ N32

Loss of Lock

Clock Select

I2C/SPI Port

Control

Rate Select

÷N1_HS

Xtal/Refclock

Si5324

Rev. 1.1 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.2. Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.3. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

8. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

10.1. Si5324 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Si5324

4 Rev. 1.1

1. Electrical Specifications

Figure 1. Differential Voltage Characteristics

Figure 2. Rise/Fall Time Characteristics

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA–40 25 85 °C

Supply Voltage during

Normal Operation

VDD 3.3 V Nominal 2.97 3.3 3.63 V

2.5 V Nominal 2.25 2.5 2.75 V

1.8 V Nominal 1.71 1.8 1.89 V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

ISE , VOSE

VID,VOD

Differential I/Os

VICM, VOCM

Single-Ended

Peak-to-Peak Voltage

Differential Peak-to-Peak Voltage

SIGNAL +

SIGNAL –

(SIGNAL +) – (SIGNAL –)

SIGNAL +

SIGNAL –

VID = (SIGNAL+) – (SIGNAL–)

ICM , VOCM

tFtR

80%

20%

CKIN, CKOUT

Si5324

Rev. 1.1 5

Table 2. DC Characteristics

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Supply Current1IDD LVPECL Format

622.08 MHz Out

Both CKOUTs Enabled

—251 279 mA

LVPECL Format

622.08 MHz Out

1 CKOUT Enabled

—217 243 mA

CMOS Format

19.44 MHz Out

Both CKOUTs Enabled

—204 234 mA

CMOS Format

19.44 MHz Out

1 CKOUT Enabled

—194 220 mA

Disable Mode — 165 — mA

CKINn Inp ut Pins 2

Input Common Mode

Voltage (Input Thresh-

old Voltage)

VICM 1.8 V ± 5% 0.9 — 1.4 V

2.5 V ± 10% 1 — 1.7 V

3.3 V ± 10% 1.1 — 1.95 V

Input Resistance CKNRIN Single-ended 20 40 60 kΩ

Single-Ended Input

Voltage Swing

(See Absolute Specs)

VISE fCKIN < 212.5 MHz

See Figure 1.

0.2 — — VPP

fCKIN > 212.5 MHz

See Figure 1.

0.25 — — VPP

Differential Input

Voltage Swing

(See Absolute Specs)

VID fCKIN < 212.5 MHz

See Figure 1.

0.2 — — VPP

fCKIN > 212.5 MHz

See Figure 1.

0.25 — — VPP

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5324

6 Rev. 1.1

Output Clocks (CKOUTn)3,5

Common Mode CKOVCM LVPECL 100  load line-

to-line

VDD –

1.42

—V

DD –1.25 V

Differential Output

Swing

CKOVD LVPECL 100  load line-

to-line

1.1 — 1.9 VPP

Single Ended Output

Swing

CKOVSE LVPECL 100  load line-

to-line

0.5 — 0.93 VPP

Differential Output

Voltage

CKOVD CML 100  load line-to-

line

350 425 500 mVPP

Common Mode Output

Voltage

CKOVCM CML 100  load line-to-

line

—V

DD-0.36 — V

Differential Output

Voltage

CKOVD LVDS

100  load line-to-line

500 700 900 mVPP

Low Swing LVDS

100  load line-to-line

350 425 500 mVPP

Common Mode Output

Voltage

CKOVCM LVDS 100 load line-to-

line

1.125 1.2 1.275 V

Differential Output

Resistance

CKORD CML, LVPECL, LVDS — 200 — 

Output Voltage Low CKOVOLLH CMOS — — 0.4 V

Output Voltage High CKOVOHLH VDD =1.71V

CMOS

0.8 x

VDD

——V

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5324

Rev. 1.1 7

Output Drive Current

(CMOS driving into

CKOVOL for output low

or CKOVOH for output

high. CKOUT+ and

CKOUT– shorted

externally)

CKOIO ICMOS[1:0] = 11

VDD =1.8V

—7.5 — mA

ICMOS[1:0] = 10

VDD =1.8V

—5.5 — mA

ICMOS[1:0] = 01

VDD =1.8V

—3.5 — mA

ICMOS[1:0] = 00

VDD =1.8V

—1.75 — mA

ICMOS[1:0] = 11

VDD =3.3V

—32 — mA

ICMOS[1:0] = 10

VDD =3.3V

—24 — mA

ICMOS[1:0] = 01

VDD =3.3V

—16 — mA

ICMOS[1:0] = 00

VDD =3.3V

—8 — mA

2-Level LVCMOS Input Pins

Input Voltage Low VIL VDD =1.71V — — 0.5 V

VDD =2.25V — — 0.7 V

VDD =2.97V — — 0.8 V

Input Voltage High VIH VDD =1.89V 1.4 — — V

VDD =2.25V 1.8 — — V

VDD =3.63V 2.5 — — V

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5324

8 Rev. 1.1

3-Level Input Pins4

Input Voltage Low VILL — — 0.15 x VDD V

Input Voltage Mid VIMM 0.45 x

VDD

—0.55xV

DD V

Input Voltage High VIHH 0.85 x

VDD

——V

Input Low Current IILL See Note 4 –20 — — µA

Input Mid Current IIMM See Note 4 –2 — +2 µA

Input High Current IIHH See Note 4 — — 20 µA

LVCMOS Output Pins

Output Voltage Low VOL IO = 2 mA

VDD =1.71V

—— 0.4 V

Output Voltage Low IO = 2 mA

VDD =2.97V

—— 0.4 V

Output Voltage High VOH IO = –2 mA

VDD =1.71V

VDD –

0.4

——V

Output Voltage High IO = –2 mA

VDD =2.97V

VDD –

0.4

——V

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5324

Rev. 1.1 9

Table 3. AC Characteristics

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance XARIN RATE[1:0] = LM, ML, MH,

or HM, ac coupled

—12— k

Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH,

or HM, ac coupled

0.5 — 1.2 VPP

Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH,

or HM

0.5 — 2.4 VPP

CKINn Input Pins

Input Frequency CKNF0.002 — 710 MHz

Input Duty Cycle

(Minimum Pulse Width)

CKNDC Whichever is smaller

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

40 — 60 %

2——ns

Input Capacitance CKNCIN —— 3 pF

Input Rise/Fall Time CKNTRF 20–80%

See Figure 2

——11 ns

CKOUTn Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not configured

for CMOS or

Disabled)

CKOFN1 60.002—945MHz

N1 = 5 970 — 1134 MHz

N1 = 4 1.213 — 1.4 GHz

Maximum Output

Frequency in CMOS

Format

CKOF— — 212.5 MHz

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

Si5324

10 Rev. 1.1

Output Rise/Fall

(20–80 %) @

622.08 MHz output

CKOTRF Output not configured for

CMOS or Disabled

See Figure 2

—230350 ps

Output Rise/Fall

(20–80%) @

212.5 MHz output

CKOTRF CMOS Output

VDD =1.71

CLOAD =5 pF

—— 8 ns

Output Rise/Fall

(20–80%) @

212.5 MHz output

CKOTRF CMOS Output

VDD =2.97

CLOAD =5 pF

—— 2 ns

Output Duty Cycle

Uncertainty @

622.08 MHz

CKODC 100  Load

Line-to-Line

Measured at 50% Point

(Not for CMOS)

——+/-40ps

LVCMOS Input Pins

Minimum Reset Pulse

Width

tRSTMN 1µs

Reset to Microproces-

sor Access Ready

tREADY 10 ms

LVCMOS Output Pins

Rise/Fall Times tRF CLOAD =20pf

See Figure 2

—25— ns

LOSn Trigger Window LOSTRIG From last CKINn to 

Internal detection of LOSn

N3 ≠1

— — 4.5 x N3 TCKIN

Time to Clear LOL after

LOS Cleared

tCLRLOL LOS to LOL

Fold = Fnew

Stable Xa/XB reference

—10—ms

Table 3. AC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

Si5324

Rev. 1.1 11

Device Skew

Output Clock Skew tSKEW  of CKOUTn to  of

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

PHASEOFFSET =0

CKOUT_ALWAYS_ON =1

SQ_ICAL =1

——100ps

Phase Change due to

Temperature Variation1

tTEMP Max phase changes from

–40 to +85 °C

—300500 ps

PLL Performance

(fin = fout = 622.08 MHz; BW = 7 Hz ; LVPECL, XAXB = 114.285 MHz)

Lock Time2

Si5324E-C-GM3

tLOCKMP Start of ICAL to of LOL — 1 1.5 s

Si5324A/B/C/D-C-GM — 0.8 1.0

Settle Time2

Si5324E-C-GM

tSETTLE Start of ICAL to Fout within

5 ppm of final value

—1.21.5 s

Si5324A/B/C/D-C-GM — 4.2 5.0

Output Clock Phase

Change

tP_STEP After clock switch

f3 128 kHz

—200— ps

Closed Loop Jitter

Peaking

JPK —0.050.1 dB

Jitter Tolerance JTOL Jitter Frequency Loop

Bandwidth

5000/BW — — ns pk-pk

Table 3. AC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

Si5324

12 Rev. 1.1

Phase Noise

fout = 622.08 MHz

CKOPN 100 Hz Offset — –90 — dBc/Hz

1 kHz Offset — –106 — dBc/Hz

10 kHz Offset — –121 — dBc/Hz

100 kHz Offset — –132 — dBc/Hz

1 MHz Offset — –132 — dBc/Hz

Subharmonic Noise SPSUBH Phase Noise @ 100 kHz

Offset

—–88–76dBc

Spurious Noise SPSPUR Max spur @ n x F3

(n 1, n x F3 < 100 MHz)

—–93–70dBc

Table 3. AC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

Si5324

Rev. 1.1 13

Table 4. Microprocessor Control

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

I2C Bus Lines (SDA, SCL)

Input Voltage Low VILI2C — — 0.25 x VDD V

Input Voltage High VIHI2C 0.7 x VDD —V

DD V

Hysteresis of Schmitt

trigger inputs

VHYSI2C VDD = 1.8V 0.1 x VDD —— V

VDD = 2.5 or 3.3 V 0.05 x VDD —— V

Output Voltage Low VOLI2C VDD =1.8V

IO = 3 mA

— — 0.2 x VDD V

VDD = 2.5 or 3.3 V

IO = 3 mA

—— 0.4 V

Si5324

14 Rev. 1.1

SPI Specifications

Duty Cycle, SCLK tDC SCLK = 10 MHz 40 — 60 %

Cycle Time, SCLK tc100 — — ns

Rise Time, SCLK tr20–80% — — 25 ns

Fall Time, SCLK tf20–80% — — 25 ns

Low Time, SCLK tlsc 20–20% 30 — — ns

High Time, SCLK thsc 80–80% 30 — — ns

Delay Time, SCLK Fall

to SDO Active

td1 —— 25 ns

Delay Time, SCLK Fall

to SDO Transition

td2 —— 25 ns

Delay Time, SS Rise

to SDO Tri-state

td3 —— 25 ns

Setup Time, SS to

SCLK Fall

tsu1 25 — — ns

Hold Time, SS to

SCLK Rise

th1 20 — — ns

Setup Time, SDI to

SCLK Rise

tsu2 25 — — ns

Hold Time, SDI to

SCLK Rise

th2 20 — — ns

Delay Time between

Slave Selects

tcs 25 — — ns

Table 4. Microprocessor Control (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Si5324

Rev. 1.1 15

Table 5. Jitter Generation

Parameter Symbol Test Condition*Min Typ Max GR-253-

Specification Unit

Measurement

Filter DSPLL

BW2

Jitter Gen

OC-192

JGEN 0.02–80 MHz 120 Hz — 4.2 6.2 30 psPP

—.27.42 N/A ps

rms

4–80 MHz 120 Hz — 3.7 6.4 10 psPP

— .14 0.31 N/A psrms

0.05–80 MHz 120 Hz — 4.4 6.9 10 psPP

— .26 0.41 1.0 ps rms

Jitter Gen

OC-48

JGEN 0.12–20 MHz 120 Hz — 3.5 5.4 40.2 psPP

— .27 0.41 4.02 ps rms

*Note: Test conditions:

1. fIN = fOUT = 622.08 MHz

2. Clock input: LVPECL

3. Clock output: LVPECL

4. PLL bandwidth: 120 Hz

5. 114.285 MHz 3rd OT crystal used as XA/XB input

6. VDD =2.5V

7. TA=85°C

Table 6. Thermal Characteristics

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Value Unit

Thermal Resistance Junction to Ambient JA Still Air 32 C°/W

Thermal Resistance Junction to Case JC Still Air 14 C°/W

Si5324

16 Rev. 1.1

Table 7. Absolute Maximum Ratings*

Parameter Symbol Test Condition Min Typ Max Unit

DC Supply Voltage VDD –0.5 — 3.8 V

LVCMOS Input Voltage VDIG –0.3 VDD+0.3 V

CKINn Voltage Level Limits CKNVIN 0—V

DD V

XA/XB Voltage Level Limits XAVIN 0—1.2V

Operating Junction Temperature TJCT –55 — 150 ºC

Storage Temperature Range TSTG –55 — 150 ºC

ESD HBM Tolerance

(100 pF, 1.5 k); All pins except

CKIN+/CKIN–

2——kV

ESD MM Tolerance; All pins

except CKIN+/CKIN–

150 — — V

ESD HBM Tolerance

(100 pF, 1.5 k); CKIN+/CKIN–

750 — — V

ESD MM Tolerance;

CKIN+/CKIN–

100 — — V

Latch-up Tolerance JESD78 Compliant

*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions specified in the operation sections of this data sheet. Exposure to absolute maximum rating

conditions for extended periods of time may affect device reliability.

Si5324

Rev. 1.1 17

2. Typical Application Circuits

Figure 3. Si5324 Typical Application Circuit (I2C Control Mode)

GND PAD

Si5324 INT_C1B

C2B

LOL

RST

CKOUT1+

CKOUT1–

VDD

GND

Ferrite

Bead

System

Power

Supply

Serial Data

Serial Clock

Reset

Interrupt/CKIN_1 Invalid Indicator

CKIN_2 Invalid Indicator

PLL Loss of Lock Indicator

Clock Outputs

CKOUT2+

CKOUT2–

SDA

SCL

I2C Interface

Serial Port Address

A[2:0]

CMODE

Control Mode (L)

100 

0.1 µF

–

100 

0.1 µF

–

0.1 µF

1 µF

Clock Select/Clock Active

CS_CA

1. Assumes differential LVPECL termination (3.3 V) on clock inputs.

2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).

Notes:

Refclk+

Option 2: 0.1 µF

Refclk–

0.1 µF

RATE[1:0]2

Crystal/Ref Clk Rate

VDD

15 k

114.285 MHz Crystal

Option 1:

Input

Clock

Sources*

CKIN2+

CKIN2–

130 130 

82 82 

VDD = 3.3 V

130 130 

82 82 

VDD = 3.3 V

CKIN1+

CKIN1–

GND PAD

Si5324

18 Rev. 1.1

Figure 4. Si5324 Typical Application Circuit (SPI Control Mode)

Si5324

RST

CKOUT1+

CKOUT1–

VDD

GND

Ferrite

Bead

System

Power

Supply

Reset

Clock Outputs

CKOUT2+

CKOUT2–

CMODEControl Mode (H)

CKIN2+

CKIN2–

100 

0.1 µF

–

100 

0.1 µF

–

0.1 µF

1 µF

CKIN1+

CKIN1–

INT_C1B

C2B

SPI Interface

LOL

Interrupt/CLKIN_1 Invalid Indicator

CLKIN_2 Invalid Indicator

PLL Loss of Lock Indicator

Serial Data Out

Serial Data In

SDO

SDI

Serial Clock

SCLK

Slave Select

Clock Select/Clock Active

CS_CA

GND PAD

1. Assumes differential LVPECL termination (3.3 V) on clock inputs.

2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).

Notes:

Input

Clock

Sources*

130 130 

82 82 

VDD = 3.3 V

130 130 

82 82 

VDD = 3.3 V

Refclk+

Option 2: 0.1 µF

Refclk–

0.1 µF

RATE[1:0]2

Crystal/Ref Clk Rate

VDD

15 k

114.285 MHz Crystal

Option 1:

Si5324

Rev. 1.1 19

3. Functional Description

Figure 5. Si5324 Functional Block Diagram

The Si5324 is a low loop bandwidth, jitter-attenuating

clock multiplier for high performance applications. The

Si5324 accepts two input clocks ranging from 2 kHz to

710 MHz and generates two output clocks ranging from

2 kHz to 945 MHz and select frequencies to 1.4 GHz.

The Si5324 can also use its external reference as a

clock source for frequency synthesis. The device

provides virtually any frequency translation combination

across this operating range. Independent dividers are

available for each input clock and output clock, so the

Si5324 can accept input clocks at different frequencies

and it can generate output clocks at different

frequencies. The Si5324 input clock frequency and

clock multiplication ratio are programmable through an

I2C or SPI interface. Silicon Laboratories offers a PC-

based software utility, DSPLLsim, that can be used to

determine the optimum PLL divider settings for a given

input frequency/clock multiplication ratio combination

that minimizes phase noise and power consumption.

This utility can be downloaded from

http://www.silabs.com/timing.

The Si5324 is based on Silicon Laboratories' 3rd-

generation DSPLL® technology, which provides any-

frequency synthesis and jitter attenuation in a highly

integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The Si5324

PLL loop bandwidth is digitally programmable and

supports a range from 4 Hz to 525 Hz. A fast lock

feature is available to reduce lock times inherent with

low loop bandwidth PLLs. The DSPLLsim software

utility can be used to calculate valid loop bandwidth

settings for a given input clock frequency/clock

multiplication ratio.

The Si5324 supports hitless switching between the two

synchronous input clocks in compliance with Telcordia

GR-253-CORE that greatly minimizes the propagation

of phase transients to the clock outputs during an input

clock transition (maximum 200 ps phase change).

Manual and automatic revertive and non-revertive input

clock switching options are available. The Si5324

monitors both input clocks for loss-of-signal (LOS) and

provides a LOS alarm when it detects missing pulses on

either input clock. The device monitors the lock status of

the PLL. The lock detect algorithm works by

continuously monitoring the phase of the input clock in

relation to the phase of the feedback clock. Due to the

low loop bandwidth of the part, the LOL indicator clears

before the loop fully settles (see “AN803: Lock and Settling

Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs” for additional details).

The Si5324 also monitors frequency offset alarms

(FOS), which indicate if an input clock is within a

specified frequency ppm accuracy relative to the

frequency of an XA/XB reference clock. Both Stratum

3/3E and SONET Minimum Clock (SMC) FOS

thresholds are supported.

The Si5324 provides a digital hold capability that allows

the device to continue generation of a stable output

clock when the selected input reference is lost. During

digital hold, the DSPLL generates an output frequency

based on a historical average frequency that existed a

fixed amount of time before the error event occurred,

eliminating the effects of phase and frequency

transients that may occur immediately preceding digital

hold.

DSPLL

Loss of Signal/

Frequency Offset

Xtal or Refclock

CKOUT2

CKIN1

CKOUT1

CKIN2

÷ N31

÷ N2

÷ NC1_LS

÷ NC2_LS

Skew Adjust

Signal Detect

Device Interrupt

VDD (1.8, 2.5, or 3.3 V)

GND

÷ N32

Loss of Lock

Clock Select

I2C/SPI Port

Control

Rate Select

÷N1_HS

Xtal/Refclock

Si5324

20 Rev. 1.1

The Si5324 has two differential clock outputs. The

signal format of each clock output is independently

programmable to support LVPECL, LVDS, CML, or

CMOS loads. When configured for CMOS, four clock

outputs are available. If not required, the second clock

output can be powered down to minimize power

consumption. In addition, the phase of one output clock

may be adjusted in relation to the phase of the other

output clock. The resolution varies from 800 ps to 2.2 ns

depending on the PLL divider settings. The DSPLLsim

software utility determines the phase offset resolution

for a given combination of input clock and multiplication

ratio. For system-level debugging, a bypass mode is

available which drives the output clock directly from the

input clock, bypassing the internal DSPLL. The device is

in-class PSNR.

3.1. External Reference

An external, high quality 38.88 MHz clock or a low-cost

114.285 MHz 3rd overtone crystal or external reference

is used as part of a fixed-frequency oscillator within the

DSPLL. This external reference is required for the

device to perform jitter attenuation. Specific

recommendations can be found in the Family Reference

Manual.

In digital hold, the DSPLL remains locked and tracks the

external reference. Note that crystals can have

temperature sensitivities.

Due to the low bandwidth capabilities of this part, any

low-frequency wander or instability on the external

reference will transfer to the output clocks. To address

this issue, a stable external reference, TXCO, OCXO, or

thermally-isolated crystal is recommended.

For example, with a 20 ppm oscillator as the reference

on the XA/XB pins, temperature changes cause the

oscillator to change frequency slightly. Although the

Si5324 is locked to its input on CLKIN, it also uses the

XA/XB as a reference.

If there is a need to use a reference oscillator instead of

a crystal, Silicon Labs does not recommend using

MEMS based oscillators. Instead, Silicon Labs

recommends the Si530EB121M109DG, which is a very

low-jitter/wander, LVPECL, 2.5 V crystal oscillator. The

very low loop BW of the Si5324 means that it can be

susceptible to XAXB reference sources that have high

wander. Experience has shown that in spite of having

low jitter, some MEMs oscillators have high wander, and

these devices should be avoided. Contact Silicon Labs

for details.

3.2. Additional Documentation

Consult the Silicon Laboratories Any-Frequency

Precision Clock Family Reference Manual (FRM) for

detailed information about the Si5324. Additional design

support is available from Silicon Laboratories through

your distributor.

Silicon Laboratories offers a PC-based software utility

called DSPLLsim to simplify device configuration,

including frequency planning and loop bandwidth

selection. The FRM and this utility can be downloaded

from http://www.silabs.com/timing (see “AN803: Lock and

Settling Time Considerations for Si5324/27/69/74 Any-

Frequency Jitter Attenuating Clock ICs” for additional details).

Si5324

Rev. 1.1 21

3.3. Typical Phase Noise Performance

Figure 6. Broadcast Video

Table 8. Broadcast Video Jitter1

Jitter Bandwidth2Jitter (Peak-Peak) Jitter (RMS)

10 Hz to 20 MHz 5.24 ps 484 fs

Notes:

1. Number of samples: 8.91E9.

2. Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-

offs per Telecordia GR-253-CORE.

Si5324

22 Rev. 1.1

Figure 7. OTN/SONET/SDH Phase Noise

Note: Phase noise plot uses brick wall integration.

Table 9. SONET Jitter

Jitter Bandw idth*Jitter, RMS

SONET_OC48, 12 kHz to 20 MHz 266 fs

SONET_OC192_A, 20 kHz to 80 MHz 283 fs

SONET_OC192_B, 4 MHz to 80 MHz 155 fs

SONET_OC192_C, 50 kHz to 80 MHz 275 fs

Brick Wall_800 Hz to 80 MHz 287 fs

*Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs

per Telecordia GR-253-CORE.

Si5324

Rev. 1.1 23

Figure 8. Wireless Base Station Phase Noise

Table 10. Wireless Base Station Jitter*

Jitter Bandwidth Jitter (peak-peak) Jitter (RMS)

10 Hz to 20 MHz 7.28 ps 581 fs

Note: Number of samples: 8.91E9

Si5324

24 Rev. 1.1

4. Register Map

All register bits that are not defined in this map should always be written with the specified Reset Values. The

writing to these bits of values other than the specified Reset Values may result in undefined device behavior.

Registers not listed, e.g. Register 64, should never be written to.

0 FREE_RUN CKOUT_

ALWAYS_ON

BYPASS_REG

1CK_PRIOR2[1:0] CK_PRIOR1[1:0]

2 BWSEL_REG[3:0]

3 CKSEL_REG[1:0] DHOLD SQ_ICAL

4 AUTOSEL_REG[1:0] HST_DEL[4:0]

5 ICMOS[1:0]

6 SFOUT2_REG[2:0} SFOUT1_REG[2:0]

7FOSREFSEL[2:0]

8 HLOG_2[1:0] HLOG_1[1:0]

9 HIST_AVG[4:0]

10 DSBL2_ REG DSBL1_ REG

11 PD_CK2 PD_CK1

19 FOS_EN FOS_THR[1:0] VALTIME[1:0] LOCK[T2:0]

20 CK2_BAD_PIN CK1_ BAD_ PIN LOL_PIN INT_PIN

21 CK1_ACTV_PIN CKSEL_PIN

22 CK_ACTV_ POL CK_BAD_ POL LOL_POL INT_POL

23 LOS2_MSK LOS1_MSK LOSX_MSK

24 FOS2_MSK FOS1_MSK LOL_MSK

25 N1_HS[2:0]

31 NC1_LS[19:16]

32 NC1_LS[15:8]

33 NC1_LS[7:0]

34 NC2_LS[19:16]

35 NC2_LS[15:8]

36 NC2_LS[7:0]

40 N2_HS[2:0] N2_LS[19:16]

41 N2_LS[15:8]

42 N2_LS[7:0]

43 N31[18:16]

44 N31[15:8]

45 N31[7:0]

46 N32[18:16]

Si5324

Rev. 1.1 25

47 N32[15:8]

48 N32[7:0]

55 CLKIN2RATE[2:0] CLKIN1RATE[2:0]

128 CK2_ACTV_REG CK1_ACTV_REG

129 LOS2_INT LOS1_INT LOSX_INT

130 DIGHOLD-

VALID

FOS2_INT FOS1_INT LOL_INT

131 LOS2_FLG LOS1_FLG LOSX_FLG

132 FOS2_FLG FOS1_FLG LOL_FLG

134 PARTNUM_RO[11:4]

135 PARTNUM_RO[3:0] REVID_RO[3:0]

136 RST_REG ICAL

137 FASTLOCK

138 LOS2_EN [1:1] LOS1_EN [1:1]

139 LOS2_EN[0:0] LOS1_EN[0:0] FOS2_EN FOS1_EN

142 INDEPENDENTSKEW1[7:0]

143 INDEPENDENTSKEW2[7:0]

Table 11. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table

CKOUT_ALWAYS_ON SQ_ICAL Results

0 0 CKOUT OFF until after the first ICAL

0 1 CKOUT OFF until after the first successful

ICAL (i.e., when LOL is low)

1 0 CKOUT always ON, including during an ICAL

1 1 CKOUT always ON, including during an ICAL.

Use these settings to preserve output-to-output

skew

Si5324

26 Rev. 1.1

5. Register Descriptions

Reset value = 0001 0100

BitD7 D6 D5 D4D3D2 D1 D0

Name FREE_RUN CKOUT_

ALWAYS_ON

BYPASS_

REG

Type R R/W R/W R R R R/W R

Bit Name Function

7 Reserved Reserved.

6FREE_RUNFree Run.

Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB

reference.

0: Disable

1: Enable

5CKOUT_

ALWAYS_ON

CKOUT Always On.

This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on

and ICAL is not complete or successful. See Table 11 on page 25.

0: Squelch output until part is calibrated (ICAL).

1: Provide an output.

Notes:

1. The frequency may be significantly off until the part is calibrated.

2. Must be 1 to control output to output skew.

4:2 Reserved Reserved.

1 BYPASS_

REG

Bypass Register.

This bit enables or disables the PLL bypass mode. Use only when the device is in digital

hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks.

0: Normal operation

1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.

0 Reserved Reserved.

Si5324

Rev. 1.1 27

Reset value = 1110 0100

Reset value = 0100 0010

BitD7D6D5D4D3 D2 D1 D0

Name CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]

Type RRRR R/W R/W

Bit Name Function

7:4 Reserved Reserved.

3:2 CK_PRIOR2

[1:0]

CK_PRIOR 2.

Selects which of the input clocks will be 2nd priority in the autoselection state machine.

00: CKIN1 is 2nd priority.

01: CKIN2 is 2nd priority.

10: Reserved

11: Reserved

1:0 CK_PRIOR1

[1:0]

CK_PRIOR 1.

Selects which of the input clocks will be 1st priority in the autoselection state machine.

00: CKIN1 is 1st priority.

01: CKIN2 is 1st priority.

10: Reserved

11: Reserved

BitD7D6D5D4D3D2D1D0

Name BWSEL_REG [3:0]

Type R/W RRRR

Bit Name Function

7:4 BWSEL_REG

[3:0]

BWSEL_REG.

Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After

BWSEL_REG is written with a new value, an ICAL is required for the change to take

effect.

3:0 Reserved Reserved.

Si5324

28 Rev. 1.1

Reset value = 0000 0101

BitD7D6D5D4D3D2D1D0

Name CKSEL_REG [1:0] DHOLD SQ_ICAL

Type R/W R/W R/W R R R R

Bit Name Function

7:6 CKSEL_REG

[1:0]

CKSEL_REG.

If the device is operating in register-based manual clock selection mode

(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock

will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA

input pin continues to control clock selection and CKSEL_REG is of no consequence.

00: CKIN_1 selected.

01: CKIN_2 selected.

10: Reserved

11: Reserved

5 DHOLD DHOLD.

Forces the part into digital hold. This bit overrides all other manual and automatic clock

selection controls.

0: Normal operation.

1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the

input clocks.

4 SQ_ICAL SQ_ICAL.

This bit determines if the output clocks will remain enabled or be squelched (disabled)

during an internal calibration. See Table 11 on page 25.

0: Output clocks enabled during ICAL.

1: Output clocks disabled during ICAL.

3:0 Reserved Reserved.

Si5324

Rev. 1.1 29

Reset value = 0001 0010

Reset value = 1110 1101

BitD7D6D5D4D3D2D1D0

Name AUTOSEL_REG [1:0] HIST_DEL [4:0]

Type R/W R R/W

Bit Name Function

7:6 AUTOSEL_

REG [1:0]

AUTOSEL_REG [1:0].

Selects method of input clock selection to be used.

00: Manual (either register or pin controlled, see CKSEL_PIN)

01: Automatic Non-Revertive

10: Automatic Revertive

11: Reserved

5 Reserved Reserved.

4:0 HIST_DEL

[4:0]

HIST_DEL [4:0 ].

Selects amount of delay to be used in generating the history information used for Digital

Hold.

BitD7D6D5D4D3D2D1D0

Name ICMOS [1:0]

Type R/W RRRRRR

Bit Name Function

7:6 ICMOS [1:0] ICMOS [1:0].

When the output buffer is set to CMOS mode, these bits determine the output buffer drive

strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation.

These values assume CKOUT+ is tied to CKOUT-.

00: 8mA/2mA.

01: 16mA/4mA

10: 24mA/6mA

11: 32mA/8mA

5:0 Reserved Reserved.

Si5324

30 Rev. 1.1

Reset value = 0010 1101

BitD7D6D5D4D3D2D1D0

Name SFOUT2_REG [2:0] SFOUT1_REG [2:0]

Type RR R/W R/W

Bit Name Function

7:6 Reserved Reserved.

5:3 SFOUT2_

REG [2:0]

SFOUT2_REG [2:0].

Controls output signal format and disable for CKOUT2 output buffer. Bypass mode is not

supported for CMOS output clocks.

000: Reserved

001: Disable

010: CMOS

011: Low swing LVDS

100: Reserved

101: LVPECL

110: CML

111: LVDS

2:0 SFOUT1_

REG [2:0]

SFOUT1_REG [2:0].

Controls output signal format and disable for CKOUT1 output buffer. Bypass mode is not

supported for CMOS output clocks.

000: Reserved

001: Disable

010: CMOS

011: Low swing LVDS

100: Reserved

101: LVPECL

110: CML

111: LVDS

Si5324

Rev. 1.1 31

Reset value = 0010 1010

BitD7D6D5D4D3D2D1D0

Name FOSREFSEL [2:0]

Type RRRRR R/W

Bit Name Function

7:3 Reserved. Reserved.

2:0 FOSREFSEL

[2:0]

FOSREFSEL [2:0].

Selects which input clock is used as the reference frequency for Frequency Off-Set

(FOS) alarms.

000: XA/XB (External reference)

001: CKIN1

010: CKIN2

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Si5324

32 Rev. 1.1

Reset value = 0000 0000

Reset value = 1100 0000

BitD7D6D5D4D3D2D1D0

Name HLOG_2[1:0] HLOG_1[1:0]

Type R/W R/W RRRR

Bit Name Function

7:6 HLOG_2 [1:0] HLOG_2 [1:0].

00: Normal operation

01: Holds CKOUT2 output at static logic 0.

Entrance and exit from this state will occur without glitches or runt pulses.

10:Holds CKOUT2 output at static logic 1.

Entrance and exit from this state will occur without glitches or runt pulses.

11: Reserved

5:4 HLOG_1 [1:0] HLOG_1 [1:0].

00: Normal operation

01: Holds CKOUT1 output at static logic 0.

Entrance and exit from this state will occur without glitches or runt pulses.

10: Holds CKOUT1 output at static logic 1.

Entrance and exit from this state will occur without glitches or runt pulses.

11: Reserved

3:0 Reserved Reserved.

BitD7D6D5D4D3D2D1D0

Name HIST_AVG [4:0]

Type R/W RRR

Bit Name Function

7:3 HIST_AVG

[4:0]

HIST_AVG [4:0 ].

Selects amount of averaging time to be used in generating the history information for

Digital Hold.

2:0 Reserved Reserved.

Si5324

Rev. 1.1 33

Reset value = 0000 0000

Reset value = 0100 0000

BitD7D6D5D4 D3 D2 D1D0

Name DSBL2_REG DSBL1_REG

Type RRRR R/W R/W R R

Bit Name Function

7:4 Reserved Reserved.

3 DSBL2_REG DSBL2_REG.

This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is

selected, the NC2_LS output divider is also powered down.

0: CKOUT2 enabled.

1: CKOUT2 disabled.

2 DSBL1_REG DSBL1_REG.

This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is

selected, the NC1_LS output divider is also powered down.

0: CKOUT1 enabled.

1: CKOUT1 disabled.

1:0 Reserved Reserved.

BitD7D6D5D4D3D2D1 D0

Name PD_CK2 PD_CK1

Type RRRRRRR/WR/W

Bit Name Function

7:2 Reserved Reserved.

1PD_CK2PD_CK2.

This bit controls the powerdown of the CKIN2 input buffer.

0: CKIN2 enabled.

1: CKIN2 disabled.

0PD_CK1PD_CK1.

This bit controls the powerdown of the CKIN1 input buffer.

0: CKIN1 enabled.

1: CKIN1 disabled.

Si5324

34 Rev. 1.1

Reset value = 0010 1100

BitD7D6D5D4D3D2D1D0

Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0]

Type R/W R/W R/W R/W

Bit Name Function

7FOS_ENFOS_EN.

Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOS-

x_EN, register 139).

0: FOS disable

1: FOS enabled by FOSx_EN

6:5 FOS_THR [1:0] FOS_THR [1:0].

Frequency Offset at which FOS is declared:

00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK

01: ± 48 to 49 ppm (SMC)

10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.

11: ± 200 ppm

4:3 VALTIME [1:0] VALTIME [1:0].

Sets amount of time for input clock to be valid before the associated alarm is removed.

00: 2 ms

01: 100 ms

10: 200 ms

11: 13 seconds

2:0 LOCKT [2:0] LOCKT [2:0 ].

Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-

gered by phase slip in DSPLL. Refer to the Family Reference Manual for more details.

To minimize lock time, the value 001 for LOCKT is recommended (see “AN803: Lock and

Settling Time Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs” for

additional details).

000: 106 ms

001: 53 ms

010: 26.5 ms

011: 13.3 ms

100: 6.6 ms

101: 3.3 ms

110: 1.66 ms

111: .833 ms

Si5324

Rev. 1.1 35

Reset value = 0011 1110

BitD7D6D5D4 D3 D2 D1 D0

Name CK2_BAD_PIN CK1_BAD_PIN LOL_PIN INT_PIN

Type R R R R R/W R/W R/W R/W

Bit Name Function

7:4 Reserved Reserved.

3 CK2_BAD_PIN CK2_BAD_PIN.

The CK2_BAD status can be reflected on the C2B output pin.

0: C2B output pin tristated

1: C2B status reflected to output pin

2 CK1_BAD_PIN CK1_BAD_PIN.

The CK1_BAD status can be reflected on the C1B output pin.

0: C1B output pin tristated

1: C1B status reflected to output pin

1LOL_PINLOL_PIN.

The LOL_INT status bit can be reflected on the LOL output pin.

0: LOL output pin tristated

1: LOL_INT status reflected to output pin

0INT_PININT_PIN.

Reflects the interrupt status on the INT_C1B output pin.

0: Interrupt status not displayed on INT_C1B output pin. If CK1_BAD_PIN = 0, INT_C1B

output pin is tristated.

1: Interrupt status reflected to output pin. Instead, the INT_C1B pin indicates when

CKIN1 is bad.

Si5324

36 Rev. 1.1

Reset value = 1111 1111

BitD7D6D5D4D3D2 D1 D0

Name CK1_ACTV_PIN CKSEL_ PIN

Type RRRRRR R/W R/W

Bit Name Function

7:2 Reserved Reserved.

1 CK1_ACTV_PIN CK1_ACTV_PIN.

The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the

CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin

controlled clock selection is not being used.

0: CS_CA output pin tristated.

1: Clock Active status reflected to output pin.

0 CKSEL_PIN CKSEL_PIN.

If manual clock selection is being used, clock selection can be controlled via the

CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when

AUTOSEL_REG = Manual.

0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.

1: CS_CA input pin controls clock selection.

Si5324

Rev. 1.1 37

Reset value = 1101 1111

BitD7D6D5D4 D3 D2 D1 D0

Name CK_ACTV_POL CK_BAD_ POL LOL_POL INT_POL

Type R R R R R/W R/W R/W R/W

Bit Name Function

7:4 Reserved Reserved.

3 CK_ACTV_ POL CK_ACTV_POL.

Sets the active polarity for the CS_CA signals when reflected on an output pin.

0: Active low

1: Active high

2 CK_BAD_ POL CK_BAD_POL.

Sets the active polarity for the INT_C1B and C2B signals when reflected on output

pins.

0: Active low

1: Active high

1 LOL_POL LOL_POL.

Sets the active polarity for the LOL status when reflected on an output pin.

0: Active low

1: Active high

0INT_POLINT_POL.

Sets the active polarity for the interrupt status when reflected on the INT_C1B out-

put pin.

0: Active low

1: Active high

Si5324

38 Rev. 1.1

Reset value = 0001 1111

BitD7D6D5D4D3 D2 D1 D0

Name LOS2_ MSK LOS1_ MSK LOSX_ MSK

Type RRRRR R/W R/W R/W

Bit Name Function

7:3 Reserved Reserved.

2LOS2_MSKLOS2_MSK.

Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOS2_FLG register.

0: LOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOS2_FLG ignored in generating interrupt output.

1LOS1_MSKLOS1_MSK.

Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOS1_FLG register.

0: LOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOS1_FLG ignored in generating interrupt output.

0LOSX_MSKLOSX_MSK.

Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOSX_FLG register.

0: LOSX alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOSX_FLG ignored in generating interrupt output.

Si5324

Rev. 1.1 39

Reset value = 0011 1111

BitD7D6D5D4D3 D2 D1 D0

Name FOS2_MSK FOS1_MSK LOL_MSK

Type RRRRR R/W R/W R/W

Bit Name Function

7:3 Reserved Reserved.

2 FOS2_MSK FOS2_MSK.

Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this

0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: FOS2_FLG ignored in generating interrupt output.

1 FOS1_MSK FOS1_MSK.

Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-

ister do not change the value held in the FOS1_FLG register.

0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: FOS1_FLG ignored in generating interrupt output.

0LOL_MSKLOL_MSK.

Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-

ter do not change the value held in the LOL_FLG register.

0: LOL alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOL_FLG ignored in generating interrupt output.

Si5324

40 Rev. 1.1

Reset value = 0010 0000

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name N1_HS [2:0]

Type R/W RRRRR

Bit Name Function

7:5 N1_HS [2:0] N1_HS [2:0].

Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.

000: N1= 4

001: N1= 5

010: N1=6

011: N1= 7

100: N1= 8

101: N1= 9

110: N1= 10

111: N1= 11

4:0 Reserved Reserved.

BitD7D6D5D4D3D2D1D0

Name NC1_LS [19:16]

Type RRRR R/W

Bit Name Function

7:4 Reserved Reserved.

3:0 NC1_LS

[19:16]

NC1_LS [19:16].

Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Si5324

Rev. 1.1 41

Reset value = 0000 0000

Reset value = 0011 0001

BitD7D6D5D4D3D2D1D0

Name NC1_LS [15:8]

Type R/W

Bit Name Function

7:0 NC1_LS [15:8] NC1 _L S [1 5: 8] .

Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

BitD7D6D5D4D3D2D1D0

Name NC1_LS [7:0]

Type R/W

Bit Name Function

7:0 NC1_LS [19:0] NC1_LS [7:0].

Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Si5324

42 Rev. 1.1

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name NC2_LS [19:16]

Type RRRR R/W

Bit Name Function

7:4 Reserved Reserved.

3:0 NC2_LS

[19:16]

NC2_LS [19:16].

Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.

00000000000000000000=1

00000000000000000001=2

00000000000000000011=4

00000000000000000101=6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

BitD7D6D5D4D3D2D1D0

Name NC2_LS [15:8]

Type R/W

Bit Name Function

7:0 NC2_LS [15:8] NC2_LS [15:8].

Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Si5324

Rev. 1.1 43

Reset value = 0011 0001

BitD7D6D5D4D3D2D1D0

Name NC2_LS [7:0]

Type R/W

Bit Name Function

7:0 NC2_LS [7:0] NC2_LS [7:0].

Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 220

Valid divider values = [1, 2, 4, 6, ..., 220]

Si5324

44 Rev. 1.1

Reset value = 1100 0000

BitD7D6D5D4D3D2D1D0

Name N2_HS [2:0] N2_LS [19:16]

Type R/W R R/W

Bit Name Function

7:5 N2_HS [2:0] N2_HS [2:0].

Sets value for N2 high speed divider which drives N2LS low-speed divider.

000: 4

001: 5

010: 6

011: 7

100: 8

101: 9

110: 10

111: 11

4 Reserved Reserved.

3:0 N2_LS [19:16] N2_LS [19:16].

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 220

Valid divider values = [2, 4, 6, ..., 220]

Si5324

Rev. 1.1 45

Reset value = 0000 0000

Reset value = 1111 1001

BitD7D6D5D4D3D2D1D0

Name N2_LS [15:8]

Type R/W

Bit Name Function

7:0 N2_LS [15:8] N2_LS [15:8].

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 220

Valid divider values = [2, 4, 6, ..., 220]

BitD7D6D5D4D3D2D1D0

Name N2_LS [7:0]

Type R/W

Bit Name Function

7:0 N2_LS [7:0] N2_LS [7:0].

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 220

Valid divider values = [2, 4, 6, ..., 220]

Si5324

46 Rev. 1.1

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name N31 [18:16]

Type RRRRR R/W

Bit Name Function

7:3 Reserved Reserved.

2:0 N31 [18:16] N31 [18:16].

Sets value for input divider for CKIN1.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 219

Valid divider values = [1, 2, 3, ..., 219]

BitD7D6D5D4D3D2D1D0

Name N31_[15:8]

Type R/W

Bit Name Function

7:0 N31_[15:8] N31_[15:8].

Sets value for input divider for CKIN1.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 219

Valid divider values = [1, 2, 3, ..., 219]

Si5324

Rev. 1.1 47

Reset value = 0000 1001

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name N31_[7:0]

Type R/W

Bit Name Function

7:0 N31_[7:0 N31_[7:0].

Sets value for input divider for CKIN1.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 219

Valid divider values = [1, 2, 3, ..., 219]

BitD7D6D5D4D3D2D1D0

Name N32_[18:16]

Type RRRRR R/W

Bit Name Function

7:3 Reserved Reserved.

2:0 N32_[18:16] N32_[18:16].

Sets value for input divider for CKIN2.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 219

Valid divider values = [1, 2, 3, ..., 219]

Si5324

48 Rev. 1.1

Reset value = 0000 0000

Reset value = 0000 1001

BitD7D6D5D4D3D2D1D0

Name N32_[15:8]

Type R/W

Bit Name Function

7:0 N32_[15:8] N32_[15:8].

Sets value for input divider for CKIN2.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 219

Valid divider values = [1, 2, 3, ..., 219]

BitD7D6D5D4D3D2D1D0

Name N32_[7:0]

Type R/W

Bit Name Function

7:0 N32_[7:0] N32_[7:0].

Sets value for input divider for CKIN2.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 219

Valid divider values = [1, 2, 3, ..., 219]

Si5324

Rev. 1.1 49

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name CLKIN2RATE_[2:0] CLKIN1RATE[2:0]

Type RR R/W R/W

Bit Name Function

7:6 Reserved Reserved.

5:3 CLKIN2RATE[2:0] CLKIN2RATE_[2:0].

CKINn frequency selection for FOS alarm monitoring.

000: 10–27 MHz

001: 25–54 MHz

002: 50–105 MHz

003: 95–215 MHz

004: 190–435 MHz

005: 375–710 MHz

006: Reserved

007: Reserved

2:0 CLKIN1RATE [2:0] CLKIN1RATE[2:0].

CKINn frequency selection for FOS alarm monitoring.

000: 10–27 MHz

001: 25–54 MHz

002: 50–105 MHz

003: 95–215 MHz

004: 190–435 MHz

005: 375–710 MHz

006: Reserved

007: Reserved

Si5324

50 Rev. 1.1

Reset value = 0010 0000

Reset value = 0000 0110

BitD7D6D5D4D3D2 D1 D0

Name CK2_ACTV_REG CK1_ACTV_REG

Type RRRRRR R R

Bit Name Function

7:2 Reserved Reserved.

1CK2_ACTV_REGCK2_ACTV_REG.

Indicates if CKIN2 is currently the active clock for the PLL input.

0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.

1: CKIN2 is the active input clock.

0CK1_ACTV_REGCK1_ACTV_REG.

Indicates if CKIN1 is currently the active clock for the PLL input.

0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.

1: CKIN1 is the active input clock.

BitD7D6D5D4D3 D2 D1 D0

Name LOS2_INT LOS1_INT LOSX_INT

Type RRRRR R R R

Bit Name Function

7:3 Reserved Reserved.

2 LOS2_INT LOS2_INT.

Indicates the LOS status on CKIN2.

0: Normal operation.

1: Internal loss-of-signal alarm on CKIN2 input.

1 LOS1_INT LOS1_INT.

Indicates the LOS status on CKIN1.

0: Normal operation.

1: Internal loss-of-signal alarm on CKIN1 input.

0 LOSX_INT LOSX_INT.

Indicates the LOS status of the external reference on the XA/XB pins.

0: Normal operation.

1: Internal loss-of-signal alarm on XA/XB reference clock input.

Si5324

Rev. 1.1 51

Reset value = 0000 0001

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name DIGHOLDVALID FOS2_INT FOS1_INT LOL_INT

Type RRRRRRRR

Bit Name Function

7 Reserved Reserved.

6DIGHOLDVALIDDigital Hold Valid.

Indicates if the digital hold circuit has enough samples of a valid clock to meet dig-

ital hold specifications.

0: Indicates digital hold history registers have not been filled. The digital hold

output frequency may not meet specifications.

1: Indicates digital hold history registers have been filled. The digital hold output

frequency is valid.

5:3 Reserved Reserved.

2 FOS2_INT CKIN2 Frequency Offset Status.

0: Normal operation.

1: Internal frequency offset alarm on CKIN2 input.

1 FOS1_INT CKIN1 Frequency Offset Status.

0: Normal operation.

1: Internal frequency offset alarm on CKIN1 input.

0 LOL_INT PLL Loss of Lock Status.

0: PLL locked.

1: PLL unlocked.

Si5324

52 Rev. 1.1

Reset value = 0001 1111

BitD7D6D5D4D3D2D1 D0

Name LOS2_FLG LOS1_FLG LOSX_FLG

Type RRRRRR/WR/WR/W

Bit Name Function

7:3 Reserved Reserved.

2LOS2_FLGCKIN2 Loss-of-Signal Flag.

0: Normal operation.

1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to

this bit.

1LOS1_FLGCKIN1 Loss-of-Signal Flag.

0: Normal operation

1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to

this bit.

0 LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag.

0: Normal operation

1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to

this bit.

Si5324

Rev. 1.1 53

Reset value = 0000 0010

BitD7D6D5D4D3 D2 D1D0

Name FOS2_FLG FOS1_FLG LOL_FLG

Type RRRRR/WR/WR/WR

Bit Name Function

7:4 Reserved Reserved.

3FOS2_FLGCLKIN_2 Frequ ency Offset Flag.

0: Normal operation.

1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to

this bit.

2FOS1_FLGCLKIN_1 Frequ ency Offset Flag.

0: Normal operation

1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to

this bit.

1LOL_FLGPLL Loss of Lock Flag.

0: PLL locked

1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to

this bit.

0 Reserved Reserved.

Si5324

54 Rev. 1.1

Reset value = 0000 0001

Reset value = 1000 0010

BitD7D6D5D4D3D2D1D0

Name PARTNUM_RO [11:4]

Type R

Bit Name Function

7:0 PARTNUM_RO [11:0] Device ID (1 of 2).

0000 0001 1000: Si5324

Others Reserved

BitD7D6D5D4D3D2D1D0

Name PARTNUM_RO [3:0] REVID_RO [3:0]

Type RR

Bit Name Function

7:4 PARTNUM_RO [11:0] Device ID (2 of 2).

0000 0001 1000: Si5324

Others Reserved

3:0 REVID_RO [3:0] Indicates Revision Number of Device.

0010: Revision C

Others Reserved.

Si5324

Rev. 1.1 55

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name RST_REG ICAL

Type R/WR/WRRRRRR

Bit Name Function

7 RST_REG Internal Reset (Same as Pin Reset).

Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.

0: Normal operation.

1: Reset of all internal logic. Outputs disabled or tristated during reset.

6ICALStart an Internal Calibration Sequence.

For proper operation, the device must go through an internal calibration sequence.

ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-

tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)

must be present to begin ICAL.

Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take

effect.

0: Normal operation.

1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-

bration, LOL will go low.

5:0 Reserved Reserved.

Si5324

56 Rev. 1.1

Reset value = 0000 0000

Reset value = 0000 1111

BitD7D6D5D4D3D2D1D0

Name FASTLOCK

Type RRRRRRRR/W

Bit Name Function

7:1 Reserved Do not modify.

0 FASTLOCK This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by

dynamically changing the loop bandwidth.

BitD7D6D5D4D3D2 D1 D0

Name LOS2_EN [1:1] LOS1_EN [1:1]

Type RRRRRR R/W R/W

Bit Name Function

7:2 Reserved Reserved.

1 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).

Note: LOS2_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual

for details.

0 LOS1_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).

Note: LOS1_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual

for details.

Si5324

Rev. 1.1 57

Reset value = 1111 1111

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name LOS2_EN [0:0] LOS1_EN [0:0] FOS2_EN FOS1_EN

Type R R R/W R/W R R R/W R/W

Bit Name Function

7:6 Reserved Reserved.

5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).

Note: LOS2_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the family reference manual

for details.

4 LOS_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).

Note: LOS1_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the family reference manual

for details.

3:2 Reserved Reserved.

1FOS2_ENEnables FOS on a Per Channel Basis.

0: Disable FOS monitoring.

1: Enable FOS monitoring.

0FOS1_ENEnables FOS on a Per Channel Basis.

0: Disable FOS monitoring.

1: Enable FOS monitoring.

Si5324

58 Rev. 1.1

Reset value = 0000 0000

BitD7D6D5D4D3D2D1D0

Name INDEPENDENTSKEW1 [7:0]

Type R/W

Bit Name Function

7:0 INDEPENDENTSKEW1 [7:0] INDEPENDENTSKEW1.

8 bit field that represents a twos complement of the phase offset in

terms of clocks from the high speed output divider. Default = 0.

BitD7D6D5D4D3D2D1D0

Name INDEPENDENTSKEW2 [7:0]

Type R/W

Bit Name Function

7:0 INDEPENDENTSKEW2 [7:0] INDEPENDENTSKEW2.

8 bit field that represents a twos complement of the phase offset in terms

of clocks from the high speed output divider. Default = 0.

Si5324

Rev. 1.1 59

5.1. ICAL

The device's registers must be configured for the intended applications. After the part is configured, the part must

perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process

is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after

a successful calibration operation, changing any of the Registers indicated in Table 12 requires that a calibration be

performed again by the same procedure (writing a "1" to bit D6 in register 136).

Table 12. ICAL-Sensitive Registers

Address Register

0 BYPASS_REG

0 CKOUT_ALWAYS_ON

1 CK_PRIOR1

1 CK_PRIOR2

2 BWSEL_REG

4HIST_DEL

5ICMOS

7FOSREFSEL

9HIST_AVG

10 DSBL1_REG

10 DSBL2_REG

11 PD_CK1

11 PD_CK2

19 FOS_EN

19 FOS_THR

19 LOCKT

19 VALTIME

25 N1HS

31 NC1_LS

34 NC2_LS

40 N2_HS

40 N2_LS

43 N31

46 N32

55 CLKIN1RATE

55 CLKIN2RATE

Si5324

60 Rev. 1.1

6. Pin Descriptions

Pin # Pin Name I/O Signal Level Description

1RST ILVCMOSExternal Reset.

Active low input that performs external hardware reset of device.

Resets all internal logic to a known state and forces the device reg-

isters to their default value. Clock outputs are disabled during reset.

The part must be programmed after a reset or power-on to get a

clock output. See Family Reference Manual for details.

This pin has a weak pull-up.

2, 9, 14,

30, 33

NC No Connection.

Leave floating. Make no external connections to this pin for normal

operation.

3 INT_C1B O LVCMOS Interru pt/CKIN1 Invalid Indicator.

This pin functions as a device interrupt output or an alarm output for

CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The

pin functions as a maskable interrupt output with active polarity con-

trolled by the INT_POL register bit.

If used as an alarm output, the pin functions as a LOS (and option-

ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and

INT_PIN =0.

0 = CKIN1 present.

1 = LOS (FOS) on CKIN1.

The active polarity is controlled by CK_BAD_POL. If no function is

selected, the pin tristates.

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

2930313233343536

10 11 12 13 14 15 16 17

RST

C2B

INT_C1B

GND

VDD

RATE0

CKIN2+

CKIN2–

RATE1

CKIN1+

CKIN1–

CS_CA

SCL

SDA_SDO

A2_SS

SDI

CKOUT1–

GND

VDD

CKOUT2–

CKOUT2+

CMODE

GND

Pad

GND

LOL

GND

CKOUT1+

Si5324

Rev. 1.1 61

4C2BOLVCMOSCKIN2 Invalid Indicator.

This pin functions as a LOS (and optionally FOS) alarm indicator for

CKIN2 if CK2_BAD_PIN = 1.

0 = CKIN2 present.

1 = LOS (FOS) on CKIN2.

The active polarity can be changed by CK_BAD_POL. If

CK2_BAD_PIN = 0, the pin tristates.

5, 10, 32 VDD VDD Supply Supply.

The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-

itors should be associated with the following Vdd pins:

50.1µF

10 0.1 µF

32 0.1 µF

A 1.0 µF should also be placed as close to the device as is practical.

IAnalogExternal Crystal or Reference Clock.

External crystal should be connected to these pins to use internal

oscillator based reference. Refer to Family Reference Manual for

interfacing to an external reference. External reference must be

from a high-quality clock source (TCXO, OCXO). Frequency of crys-

tal or external clock is set by RATE[1:0] pins.

8, 31, 20,

GND GND Supply Ground.

Must be connected to system ground. Minimize the ground path

impedance for optimal performance of this device. Grounding these

pins does not eliminate the requirement to ground the GND PAD on

the bottom of the package.

RATE0

RATE1

I 3-Level External Crystal or Reference Clock Rate.

Three level inputs that select the type and rate of external crystal or

reference clock to be applied to the XA/XB port. Refer to the Family

Reference Manual for settings. These pins have both a weak pull-up

and a weak pull-down; they default to M.

L setting corresponds to ground.

M setting corresponds to VDD/2.

H setting corresponds to VDD.

Some designs may require an external resistor voltage divider when

driven by an active device that will tri-state.

CKIN1+

CKIN1–

IMultiClock Input 1.

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

CKIN2+

CKIN2–

IMultiClock Input 2.

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Si5324

62 Rev. 1.1

18 LOL O LVCMOS PLL Loss of Lock Indicator.

This pin functions as the active high PLL loss of lock indicator if the

LOL_PIN register bit is set to 1.

0 = PLL locked.

1 = PLL unlocked.

If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by

the LOL_POL bit. The PLL lock status will always be reflected in the

LOL_INT read only register bit (see “AN803: Lock and Settling Time

Considerations for Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock

ICs” for additional details).

21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.

Input: In manual clock selection mode, this pin functions as the

manual input clock selector if the CKSEL_PIN is set to 1.

0 = Select CKIN1.

1 = Select CKIN2.

If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-

tion and this input tristates. If configured for input, must be tied high

or low.

Output: In automatic clock selection mode, this pin indicates which

of the two input clocks is currently the active clock. If alarms exist on

both clocks, CK_ACTV will indicate the last active clock that was

used before entering the digital hold state. The CK_ACTV_PIN reg-

ister bit must be set to 1 to reflect the active clock status to the

CK_ACTV output pin.

0 = CKIN1 active input clock.

1 = CKIN2 active input clock.

If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will

always be reflected in the CK_ACTV_REG read only register bit.

22 SCL I LVCMOS Serial Clock.

This pin functions as the serial clock input for both SPI and I2C

modes.

This pin has a weak pull-down.

23 SDA_SDO I/O LVCMOS Serial Data.

In I2C control mode (CMODE = 0), this pin functions as the bidirec-

tional serial data port.

In SPI control mode (CMODE = 1), this pin functions as the serial

data output.

ILVCMOSSerial Port Address.

In I2C control mode (CMODE = 0), these pins function as hardware

controlled address bits. The I2C address is 1101 [A2] [A1] [A0].

In SPI control mode (CMODE = 1), these pins are ignored.

These pins have a weak pull-down.

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Si5324

Rev. 1.1 63

26 A2_SSILVCMOSSerial Port Address/Slave Select.

In I2C control mode (CMODE = 0), this pin functions as a hardware

controlled address bit [A2].

In SPI control mode (CMODE = 1), this pin functions as the slave

select input.

This pin has a weak pull-down.

27 SDI I LVCMOS Serial Data In.

In I2C control mode (CMODE = 0), this pin is ignored.

In SPI control mode (CMODE = 1), this pin functions as the serial

data input.

This pin has a weak pull-down.

CKOUT1–

CKOUT1+

OMultiOutput Clock 1.

Differential output clock with a frequency range of 8 kHz to

1.4175 GHz. Output signal format is selected by SFOUT1_REG

compatible modes. For CMOS format, both output pins drive identi-

cal single-ended clock outputs.

CKOUT2–

CKOUT2+

OMultiOutput Clock 2.

Differential output clock with a frequency range of 8 kHz to

1.4175 GHz. Output signal format is selected by SFOUT2_REG

compatible modes. For CMOS format, both output pins drive identi-

cal single-ended clock outputs.

36 CMODE I LVCMOS Control Mode.

Selects I2C or SPI control mode for the Si5324.

0=I

2C Control Mode

1 = SPI Control Mode

This pin must not be NC. Tie either high or low.

GND PAD GND GND Supply

Ground Pad.

The ground pad must provide a low thermal and electrical

impedance to a ground plane.

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Si5324

64 Rev. 1.1

7. Ordering Guide

Ordering Part

Number1Output Clock Frequency

Range Package ROHS6,

Pb-Free Temperature Range

Si5324A-C-GM22kHz–945MHz

970–1134 MHz

1.213–1.417 GHz

36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Si5324B-C-GM22 kHz–808 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Si5324C-C-GM22 kHz–346 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Si5324D-C-GM22 kHz–150 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Si5324E-C-GM32kHz–945MHz

970–1134 MHz

1.213–1.417 GHz

36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Notes:

1. Add an R at the end of the device to denote tape and reel options.

2. These OPNs are recommended for all new designs. Refer to AN803 for more information.

3. This OPN is intended for use in legacy designs in which the Si5324 device must retain the original lock time behavior

as described in AN803 and Product Bulletin (PB-1312191): “Si5324, Si5374, Si5374 Loss of Lock (LOL) Time

Behavior: New Applications Note and Ordering Options”.

Si5324

Rev. 1.1 65

Table 13. Product Selection Guide

Part

Number Control Number of

Inputs and

Outputs

Input

Frequency

(MHz)*

Output

Frequency

(MHz)*

RMS Phase Jitter

(12kHz–20MHz) PLL

Bandwidth Hitless

Switching Free

Run

Mode

Package

Si5315 Pin 1PLL, 2 | 2 0.008–644 0.008–644 0.45 ps 60 Hz to

8kHz 6x6 mm

36-QFN

Si5316 Pin 1PLL, 2 | 1 19–710 19–710 0.3 ps 60 Hz to

8kHz

6x6 mm

36-QFN

Si5317 Pin 1PLL, 1 | 2 1–710 1–710 0.3 ps 60 Hz to

8kHz

6x6 mm

36-QFN

Si5319 I2C/SPI 1PLL, 1 | 1 0.002–710 0.002–1417 0.3 ps 60 Hz to

8kHz 6x6 mm

36-QFN

Si5323 Pin 1PLL, 2 | 2 0.008–707 0.008–1050 0.3 ps 60 Hz to

8kHz 6x6 mm

36-QFN

Si5324 I2C/SPI 1PLL, 2 | 2 0.002–710 0.002–1417 0.3 ps 4 Hz to

525 Hz 

6x6 mm

36-QFN

Si5326 I2C/SPI 1PLL, 2 | 2 0.002–710 0.002–1417 0.3 ps 60 Hz to

8kHz 

6x6 mm

36-QFN

Si5327 I2C/SPI 1PLL, 2 | 2 0.002–710 0.002–808 0.5 ps 60 Hz to

8kHz 

6x6 mm

36-QFN

Si5366 Pin 1PLL, 4 | 5 0.008–707 0.008–1050 0.3 ps 60 Hz to

8kHz 14x14 mm

100-TQFP

Si5368 I2C/SPI 1PLL, 4 | 5 0.002–710 0.002–1417 0.3 ps 60 Hz to

8kHz 

14x14 mm

100-TQFP

Si5369 I2C/SPI 1PLL, 4 | 5 0.002–710 0.002–1417 0.3 ps 4 Hz to

525 Hz 

14x14 mm

100-TQFP

Si5374 I2C 4PLL, 8 | 8 0.002–710 0.002–808 0.4 ps 4 Hz to

525 Hz 

10x10 mm

80-BGA

Si5375 I2C 4PLL, 4 | 4 0.002–710 0.002–808 0.4 ps 60 Hz to

8kHz 

10x10 mm

80-BGA

*Note: Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering

information.

Si5324

66 Rev. 1.1

Table 14. Product Selection Guide (Si5322/25/65/67)

Device

Clock Inputs

Clock Outputs

P Control

Max Input Freq (MHz)1

Max Output Frequency (MHz)

Jitter Generation

(12 kHz – 20 MHz)

LOS

Hitless Switching

FOS Alarm

LOL Alarm

FSYNC Realignment

36 Lead 6 mm x 6 mm QFN

100 Lead 14 x 14 mm TQFP

1.8, 2.5, 3.3 V Operation

1.8, 2.5 V Operation

Low Jitter Precision Clock Multipliers (Wideband)

Si5322 2 2 707 1050 0.6 ps rms typ 

Si5325 2 2 710 1400 0.6 ps rms typ   

Si5365 4 5 707 1050 0.6 ps rms typ   

Si5367 4 5 710 1400 0.6 ps rms typ   

Notes:

1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering

information.

2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal or reference clock.

Si5324

Rev. 1.1 67

8. Package Outline: 36-Pin QFN

Figure 9 illustrates the package details for the Si5324. Table 15 lists the values for the dimensions shown in the

illustration.

Figure 9. 36-Pin Quad Flat No-lead (QFN)

Table 15. Package Dimensions

Symbol Millimeters Symbol Millimeters

Min Nom Max Min Nom Max

A 0.80 0.85 0.90 L 0.50 0.60 0.70

A1 0.00 0.02 0.05 ——12º

b 0.18 0.25 0.30 aaa — — 0.10

D 6.00 BSC bbb — — 0.10

D2 3.95 4.10 4.25 ccc — — 0.08

e 0.50 BSC ddd — — 0.10

E 6.00 BSC eee — — 0.05

E2 3.95 4.10 4.25

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220, variation VJJD.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

Si5324

68 Rev. 1.1

9. PCB Land Pattern

Figure 10. PCB Land Pattern Diagram

Figure 11. Ground Pad Recommended Layout

Si5324

Rev. 1.1 69

Table 16. PCB Land Pattern Dimensions

Dimension MIN MAX

e 0.50 BSC.

E5.42 REF.

D5.42 REF.

E2 4.00 4.20

D2 4.00 4.20

GE 4.53 —

GD 4.53 —

X — 0.28

Y0.89 REF.

ZE — 6.31

ZD — 6.31

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the

center ground pad.

Card Assembly

10. A No-Clean, Type-3 solder paste is recommended.

11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

Si5324

70 Rev. 1.1

10. Top Marking

10.1. Si5324 Top Marking (QFN)

10.2. Top Marking Explanation

Mark Method: Laser

Font Size: 0.80 mm

Right-Justified

Line 1 Marking: Si5324Q Customer Part Number

Q = Speed Code: A, B, C, D

See Ordering Guide for options.

Line 2 Marking: C-GM C = Product Revision

G = Temperature Range –40 to 85 °C (RoHS6)

M = QFN Package

Line 3 Marking: YYWWRF YY = Year

WW = Work Week

R = Die Revision

F = Internal code

Assigned by the Assembly House. Corresponds to the year

and work week of the mold date.

Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter

Lower-Left Justified

XXXX Internal Code



Si5324

Rev. 1.1 71

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

Updated Rise/Fall Time values.

Updated minimum loop BW value.

Revision 0.2 to Revision 0.25

Updated features and applications.

Changed maximum loop bandwidth to 525 Hz

(global).

Updated PLL performance specifications in Table 1.

Added Typical Video Phase Noise Plot and data.

Removed references to Si5325.

Added note to register CKOUT_ALWAYS_ON on

how to control output to output skew.

Added Product Selection Guide to Section “7.

Ordering Guide”.

Corrected typographical errors in Table 1.

Updated typical phase noise performance page.

Updated functional description.

Added additional phase noise plots to Section “3.3.

Typical Phase Noise Performance”.

Updated Register Map.

Revised Device Top Mark.

Revision 0.25 to Revision 0.3

Changed Any-Rate to Any-Frequency

Changed Table 2, “Absolute Maximum Ratings,” on

page 6.

Added Table 11, “CKOUT_ALWAYS_ON and

SQ_ICAL Truth Table,” on page 25

Added “no bypass with CMOS outputs”

Revision 0.3 to Revision 1.0

Expanded spec Tables 1 and 2 to include all

specifications in the Reference Manual.

Reordered sections to conform to data sheet quality

convention.

Added tSETTLE specification.

Corrected minor register map typos.

Minor changes to Table 2.

Added maximum lock and settle times to Table 3.

Added titles to Tables 8, 9, and 10.

Updated/added selection guide Tables 13 and 14.

Removed SLEEP from register map.

Added warning about MEMS reference oscillators to

"3.1. External Reference" on page 20.

Revision 1.0 to Revision 1.1

Added reference to AN803 on pages 11,19,20,34,62.

Added additional LOL and Settling Time Specs on

page 11.

Added new part numbers on page 64.

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers

using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific

device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories

reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific

written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected

to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no

circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations

thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,

USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of

ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.

http://www.silabs.com

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing SW/HW

www.silabs.com/CBPro Quality

www.silabs.com/quality Support and Community

community.silabs.com