19-4623; Rev 0; 5/09
Product Specification
Crimzon® ZLR32300
Z8®
Low-Voltage ROM
MCU with Infrared Timers
Maxim Integrated Products Inc.
120 San Gabriel Drive, Sunnyvale CA 94086
PS022613-0409
Maxim Integrated Products
120 San Gabriel Drive
Sunnyvale, CA 94086
United States
408-737-7600
www.maxim-ic.com
Copyright © 2009 Maxim Integrated Products
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim pro duct. Maxim retains
the right to make changes to it s products or specifications to improve performance, reliability or manufacturability. All information in
this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to
change without notice at any time. While the information furnished herein is held to be accura te and reliable, no responsibilit y will be
assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic
devices any license under the patent right of any manufacturer.
Maxim is a registered trademark of Maxim Integrated Products, Inc.
All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their
respective holders.
Z8 is a registered trademark of Zilog, Inc.
Crimzon is a registered trademark of Universal Electronics Inc.
Crimzon® ZLR16300
Product Specification
PS022613-0409 Revision History
iii
Revision History
Each instance in the Revision History table reflects a change to this document from its
previous revision. For more details, refer to the corresponding pages and appropriate links
in the table below.
Date Revision
Level Description Page
Number
April 2009 13 Changed to Maxim product All
February
2008 12 Updated the Ordering Information section. 92
January
2008 11 Updated the Ordering Information section. 92
August
2007 10 Updated the Disclaimer se ction and
implemente d sty le gu i de . All
February
2007 09 Updated Low-Voltage Detection Register—
LVD(D)0CH.60
May
2006 08 Added Pin 22 to SMR Block input , Figure 32.54
December
2005 07 Updated section clock and Input/output port. 50, 14
Crimzon® ZLR16300
Product Specification
19-4623; Rev 0; 5/09 Table of Contents
iv
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . 62
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . 69
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Crimzon® ZLR16300
Product Specification
19-4623; Rev 0; 5/09 Table of Contents
v
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Architectural Overview
1
Architectural Overview
Maxim’s Crimzon® ZLR32300 is an ROM-based member of the MCU family of
infrared microcontrollers. With 237 B of gene ral-pu rpose RAM and 4 KB to 3 2 KB
of ROM, CMOS microcontrollers offer fast-executing, efficient use of memory,
sophisticated interrupts, input/o utput (I/O) bit manipulation capabilit ies, automated
pulse generation/reception, and internal key-scan pull-up transistors.
The Crimzon ZLR32300 architecture (see Figure 1 on p age 4) is based on Maxim’ s
8-bit microcontroller core with an Expanded Register File allowing access to
register-mapped peripherals, I/O circuit s, and powerful counter/timer circuitry. The
Z8® offers a flexible
I/O scheme, an efficient register and address space structure, and a number of
ancillary features that are useful in many consumer, automotive, computer
peripheral, and
battery-operated hand-held applications.
There are three basic address spaces available to support a wide range of
configurations:
1. Program Memory
2. Register File
3. Expanded Register File
The register file is composed of 256 bytes of RAM. It includes four I/O port
registers, 16 control and st atus re gisters, and 2 36 gen eral-purpose registe rs. The
Expanded Register File consists of two additional register groups (F and D).
To unburden the program from coping with such real-time problems as generating
complex waveforms or receiving and demodulating complex waveform/pulses, the
Crimzon ZLR32300 offers a new intelligent counter/timer architecture with 8-bit
and
16-bit counter/timers (see Figure 2 on p age 5). Also included are a la rge number of
user-selectable modes and two on-board comparators to process analog signals
with separate reference voltages.
All signals with an overline, “ ”, are active Low. For example,
B/W, in which WORD is active Low, and B/W, in which BYTE is
active Low.
Power connections use the conventional descriptions listed in Table 1.
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Architectural Overview
2
Development Features
Table 2 lists the features of Crimzon ZLR32300 family.
The development features of Crimzon ZLR32300 include:
•
Low power consumption–5 mW (typical)
•
Three standby modes:
–STOP—1.4 A (typical)
–HALT—0.5 mA (typical)
–Low voltage
•
Special architecture to automate generation and reception of complex pulses or signals:
–One programmable 8-bit counter/timer with two capture registers and two load
registers
–One programmable 16-bit counter/timer with one 16-bit capture register pair and
one 16-bit load register pair
–Programmable input glitch filter for pulse reception
•
Six priority interrupts
–Three external
–Two assigned to counter/timers
–One low-voltage detection interrupt
•
Low-voltage detection and high-voltage detection Flags
•
Programmable Watchdog Timer/Power-on reset (WDT/POR) circuits
•
Two independent comparators with programmable interrupt polarity
Table 1. Power Connections
Connection Circuit Device
Power VCC VDD
Ground GND VSS
Table 2. Crimzon ZLR32300 Family Features
Device ROM (KB) RAM* (Bytes) I/O Lines Voltage Range
Crimzon ZLR32300 4, 8, 16, 24, 32 237 32, 24 or 16 2.0–3.6 V
*General purpose
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Architectural Overview
3
•
Mask selectable pull-up transistors on ports 0, 1, 2, 3
•
ROM options
–Port 0: 0–3 pull-up transistors
–Port 0: 4–7 pull-up transistors
–Port 1: 0–3 pull-up transistors
–Port 1: 4–7 pull-up transistors
–Port 2: 0–7 pull-up transistors
–Port 3: 0–3 pull-up transistors
–WDT enabled at POR
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Architectural Overview
4
Functional Block Diagram
Figure 1 displays the ZLR32300 MCU functional block diagram.
Figure 1. Functional Block Diagram
Z8® Core
Port 2
Port 0
P21
P22
P23
P24
P25
P26
P27
P20
I/O Bit
Programmable
P04
P05
P06
P07
P00
P01
P02
P03
I/O Nibble
Programmable
Register File
256 x 8-Bit
Register Bus Internal
Address Bus
Internal
Data Bus
Expanded
Register
File
Expanded
Register Bus
Z8 Core
Counter/Timer 8
8-Bit Counter/Timer 16
16-Bit
V
DD
V
SS
XTAL
RESET
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
Port 3
Machine
Timing &
Instruction
Control
Power
4
4
ROM
Up to 32K x 8
Port 1
P14
P15
P16
P17
P10
P11
P12
P13
I/O Byt e
Programmable
8
Watchdog
Timer Low-Voltage
Detection High-Voltage
Detection
Power-On
Reset
Note: Refer to the specific package for available pins.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Architectural Overview
5
Figure 2. Counter/Timers Diagram
HI16 LO16
TC16H TC16L
HI8 LO8
TC8L
88
16
8
Input
SCLK
Timer 16
Timer 8/16
Timer 8
88
88
8
16-Bit
T16
Clock
Divider
Glitch
Filter Edge
Detect
Circuit 8-Bit
T8
TC8H
1248
And/OR
Logic
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
6
Pin Description
The pin configuration for the 20-pin PDIP/SOIC/SSOP is displayed in Figure 3 and
described in Table 3. The pin configuration for the 28-pin PDIP/SOIC/SSOP is dis-
played in Figure 4 on page 7 and described in Table 4 on page 7. The pin configu-
rations for the 48-pin SSOP versions are displayed in Figure 5 on page 8 and
described in Table 5 on page 8.
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration
Table 3. 20-Pin PDIP/SOIC/SSOP Pin Identification
Pin No Symbol Function Direction
1–3 P25–P2 7 Port 2, Bits 5,6,7 Input/Output
4 P07 Port 0, Bit 7 Input/Output
5V
DD Power Supply
6 XTAL2 Crystal Oscillator Clock Output
7 XTAL1 Crystal Oscillator Clock Input
8–10 P31–P33 Port 3, Bits 1,2,3 Input
11,12 P34, P36 Port 3, Bits 4,6 Output
13 P00/Pref1/P30 Port 0, Bit 0/Analog refere nce input
Port 3 Bit 0 Input/Output for P00
Input for Pref1/P30
14 P01 Port 0, Bit 1 Input/Output
15 VSS Ground
16–20 P20–P24 Port 2, Bits 0,1,2,3,4 Input/Output
P25
P26
P27
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P24
P23
P22
P21
P20
VSS
P01
P00/Pref1/P30
P36
P34
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-Pin
PDIP
SOIC
SSOP
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
7
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration
Table 4. 28-Pin PDIP/SOIC/SSOP Pin Identification
Pin Symbol Direction Description
1-3 P25-P27 Input/Output Port 2, Bits 5,6,7
4-7 P04-P07 Input/Output Port 0, Bits 4,5,6,7
8V
DD Power supply
9 XTAL2 Output Crystal, oscillator clock
10 XTAL1 Input Crystal, oscillator clock
11-13 P31-P33 Input Port 3, Bits 1,2,3
14 P34 Output Port 3, Bit 4
15 P35 Output Port 3, Bit 5
16 P37 Output Port 3, Bit 7
17 P36 Output Port 3, Bit 6
18 Pref1/P30
Port 3 Bit 0 Input Analog ref input; connect to VCC if not used
Input for Pref1/P30
19-21 P00-P02 Input/Output Port 0, Bits 0,1,2
22 VSS Ground
23 P03 Input/Output Port 0, Bit 3
24-28 P20-P24 Input/Output Port 2, Bits 0-4
P24
P23
P22
P21
P20
P03
V
SS
P02
P01
P00
Pref1/P30
P36
P37
P35
P25
P26
P27
P04
P05
P06
P07
V
DD
XTAL2
XTAL1
P31
P32
P33
P34
1
14
28
15
28-Pin
PDIP
SOIC
SSOP
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
8
Figure 5. 48-Pin SSOP Pin Configuration
Table 5. 48-Pin Configuration
48-Pin SSOP No Symbol
31 P00
32 P01
35 P02
41 P03
5P04
7P05
8P06
11 P07
33 P10
34 P11
NC
P25
P26
P27
P04
N/C
P05
P06
P14
P15
P07
VDD
VDD
N/C
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
NC
VSS
NC
NC
P24
P23
P22
P21
P20
P03
P13
P12
VSS
VSS
N/C
P02
P11
P10
P01
P00
N/C
PREF1/P30
P36
P37
P35
RESET
48-Pin
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
9
39 P12
40 P13
9P14
10 P15
15 P16
16 P17
42 P20
43 P21
44 P22
45 P23
46 P24
2P25
3P26
4P27
19 P31
20 P32
21 P33
22 P34
26 P35
28 P36
27 P37
23 NC
47 NC
1NC
25 RESET
18 XTAL1
17 XTAL2
12, 13 VDD
24, 37, 38 VSS
29 Pref1/P30
48 NC
6NC
Table 5. 48-Pin Configuration (Continued)
48-Pin SSOP No Symbol
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
10
14 NC
30 NC
36 NC
Table 5. 48-Pin Configuration (Continued)
48-Pin SSOP No Symbol
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
11
Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal or ceramic resonator, to the on-chip
oscillator input. Additionally, an optional ex ternal single-phase clock can be coded
to the on-chip oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant, crystal or ceramic resonant to the on-chip
oscillator output.
Input/Output Ports
The CMOS input buf fer for each Po rt 0, 1, or 2 pin is always
connected to the pin, even when the pin is configured as an
output. If the pin is configured as an open-drain output and
no external signal is applied, a High out put state can cause
the CMOS input buffer to float. This might lea d to excessive
leakage current of more than 100 A. To prevent this
leakage, connect the pin to an external signal with a
defined logic level or ensure its output state is Low,
especially during STOP mode.
Internal pull-ups are disabled on any given pin or group of
port pins when programmed into output mode.
Port 0, 1, and 2 have input and output capability. The input
logic is always present no matter whether the port is
configured as input or output. When doing a READ
instruction, the MCU reads the actual value at the input
logic but not from the output buffer. In addition, the
instructions of OR, AND, and XOR have the Read-Modify-
Write sequence. The MCU first reads the port, and then
modifies the value and load back to the port.
Precaution must be taken if the port is configured as open-
drain output or if the port is driving any circuit that makes
the voltage different from the desired output logic. For
example, pins P00–P07 are not connected to anything else.
If it is configured as open-drain output with output logic as
Caution:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
12
ONE, it is a floating port and reads back as ZERO. The
following instruction sets P00-P07 all LOW.
AND P0,#%F0
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are
configured under software control as a nibble I/O port. The output drivers are
push-pull or open-drain controlled by bit D2 in the PCON register.
If one or both nibbles are needed for I/O operation, they must be configured by
writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as
an input port.
An optional pull-up transistor is available as a mask option on all Port 0 bits with
nibble select.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
13
The Port 0 direction is reset to be input following an Stop Mode
Recovery.
Figure 6. Port 0 Configuration
Port 1 (P17–P10)
Port 1 (see Figure 7) can be configured for standard port input or output mode.
After POR, Port 1 is configured as an input port. The output drivers are either
push-pull or open-drain and are controlled by bit D1 in the PCON register.
Note:
ZLR32300
ROM
4
4Port 0 (I/O)
Open-Drain
I/O
Out
In
V
CC
Pad
Mask
Option Resistive
Transistor
Pull-up
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
14
The Port 1 direction is reset to be input following an SMR.
In 20- and 28-pin packages, Port 1 is reserved. A write to this register
will have no effect and will always read FF.
Figure 7. Port 1 Configuration
Port 2 (P27–P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 8 on page
15). These eight I/O lines ca n be independently configured under sof tware control
as inputs or outputs. Po rt 2 is always available for I/O operation . A mask option is
available to connect eight pull-up transistors o n this port. Bit s programme d as out-
puts are globally programmed as either push-pull or open-drain. The POR resets
with the eight bits of Port 2 configured as inputs.
Note:
ZLR32300
ROM 8Port 1 (I/O)
Open-Drain
OEN
Out
In
Mask
Option V
CC
Resistive
Transistor
Pull-up
Pad
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
15
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up
the part. P20 can be programmed to access the edge-detection circuitry in
DEMODULATION mode.
Figure 8. Port 2 Configuration
Port 3 (P37–P30)
Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 9 on p age 16). Port 3
consists of fou r fixed input (P33–P30) and four fixed o utput (P37–P34), which can
be configured under software control for interrupt and as output from the counter/
timers. P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and
P37 are push-pull outputs.
ZLR32300
ROM
Port 2 (I/O)
Pad
In
Out
I/O
Open-Drain Resistive
Transistor
Pull-up
V
CC
Mask
Option
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
16
Figure 9. Port 3 Configuration
Two on-board comparators process analog signals on P31 and P32, with
reference to the voltage on Pref1 and P33. The Analog function is enabled by
programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as
rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1
and P33 are the comparator reference voltage inputs. Access to the Counter
Timer edge-detection circuit is through P31 or P20 (see T8 and T16 Common Func-
-
ZLR32300
ROM Port 3 (I/O)
P32 (AN2)
P31 (AN1)
Pref1
From Stop Mode Recovery Source of SMR
P33 (REF2)
IRQ2, P 3 1 D a ta L atch
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
D1 1 = Analog
0 = Digital
R247 = P3M
+
-
+
IRQ0, P 3 2 D a ta L atch
I
RQ1, P33 Data Latch
Comp1
Comp2
Dig.
An.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
17
tions—CTR1(0D)01h on page 30). Other edge detect and IRQ modes are
described in Table 6.
Comparators are powered down by entering STOP mode. For
P31–P33 to be used in a SMR source, these inputs must be
placed into DIGITAL mode.
2
Port 3 also provides output for each of the counter/timers and the AND/OR Logic
(see Figure 10 on page 18). Control is performed by programming bits D5–D4 of
CTR1, bit 0 of CTR0, and bit 0 of CTR2.
Table 6. Port 3 Pin Function Summary
Pin I/O Counter/Timers Comparator Interrupt
Pref1/P30 IN RF1
P31 IN IN AN1 IRQ2
P32 IN AN2 IRQ0
P33 IN RF2 IRQ1
P34 OUT T8 AO1
P35 OUT T16
P36 OUT T8/16
P37 OUT AO2
P20 I/O IN
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
18
Figure 10. Port 3 Counter/Timer Output Configuration
Pad
P34
Comp1
VDD
MUX
PCON, D0
MUX
CTR0, D0
P31
P30 (Pref1)
P34 data
T8_Out
+
Pad
P35
VDD
MUX
CTR2, D0
Out 35
T16_Out
Pad
P36
VDD
MUX
CTR1, D6
Out 36
T8/T16_Out
Pad
P37
VDD
MUX
PCON, D0
P37 data
-
P31
P3M D1
Comp2
P32
P33 +
-
P32
P3M D1
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Pin Description
19
Comparator Inputs
In ANALOG mode, P31 and P32 have a comparator front end. The comparator
reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch
and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32,
and P33) as displayed in Figure 9 on page 16. In DIGITAL mode, P33 is used as
D3 of the Port 3 input register, which then generates IRQ1.
Comparators are powered down by entering STOP mode. For
P31–P33 to be used in a SMR source, these inputs must be
placed into DIGITAL mode.
Comparator Outputs
These channels can be programmed to be output on P34 and P37 through the
PCON register.
RESET (Input, Active Low)
Reset initializes the MCU and is accomplished either through Power-On, Watch-
dog Timer, Stop Mode Recovery, Low-Voltage detection, or e xternal re set. During
Power-On Reset and W atchdog T imer Reset, the internally generated reset drives
the reset pin Low for the POR time. Any devices driving the external reset line
must be open-drain to avoid damage from a possible conflict during reset condi-
tions. Pull-up is provided internally.
When the ZLR32300 asserts (Low) the RESET pin, the internal pull-up is dis-
abled. The ZLR32300 does not assert the RESET pin when under VBO.
The external Reset does not initiate an exit from STOP mode.
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
20
Functional Description
This device incorporates special funct ions to enhance the Z8® functionality in co n-
sumer and battery-operated applications.
Program Memory
This device addresses 32 KB of ROM memory. The first 12 bytes are reserved for
interrupt vectors. These locations cont ain the six 16-bit vectors that correspond to
the six available interrupts (see Figure 11on page 21).
RAM
This device features 256 B of RAM.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
21
Figure 11.Program Memory Map (32 K ROM)
Expanded Register File
The register file has been expanded to allow for additional system control regis-
ters and for mapping of additional peripheral devices into the register address
area. The Z8 register address sp ace (R0 th rough R15 ) has b een implemen ted as
16 banks, with 16 registers per bank. These register groups are known as the
On-Chip
ROM
Reset Start Address
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
12
11
10
9
8
7
6
5
4
3
2
1
0
32768
Location of
first byte of
instruction
executed
after RESET
Interrupt Vector
(Lower Byte)
Interrupt Vector
(Upper Byte)
Not Accessible
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
22
ERF (Expanded Register File). Bits 7–4 of register RP select the working register
group. Bits 3–0 of register RP select the expanded register file bank.
An expanded register ban k is also referred to as an e xpande d register group (see
Figure 12 on page 23).
Note:Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
23
Figure 12. Expanded Register File Architecture
UUUUUUU0
00000000
00000000
00000000
00
0F
7F
F0
FF
FF SPL
00000000
UUUUUUUU
00000000
UUUUUUUU
UUUUUUUU
UUUUUUUU
11111111
00000000
11001111
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
FE SPH
FD RP
FC FLAGS
FB IMR
FA IRQ
F9 IPR
F8 P01M
F7 P3M
F6 P2M
F5 Reserved
F4 Reserved
F3 Reserved
F2 Reserved
F1 Reserved
F0 Reserved
D7
D6 D5 D4D3D2D1D0
UU001101
U01000U0
11111110
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D SMR2
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
76543210
Expanded Register
Bank Pointer
Working Register
UUUUUUUU
UUUUUUUU
00000000
(D) 0C LVD
(D) 0B HI8
(D) 0A LO8
(D) 09 HI16
(D) 08 LO16
(D) 07 TC16H
(D) 06 TC16L
(D) 05 TC8H
(D) 04 TC8L
(D) 03 CTR3
(D) 02 CTR2
(D) 01 CTR1
(D) 00 CTR0
Group Pointer
Register File (Bank 0)**
00011111
*
*
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
U = Unknown
* Not reset with a Stop Mode Recovery. P1 reserved in 20 and 28-pin package.
** All addresses are i n hexadecimal
Is not reset with a Stop Mode Recovery, except Bit 0
 Bit 5 Is not reset with a Stop Mode Recovery
 Bits 5,4,3,2 not reset with a Stop Mode Recovery
 Bits 5 and 4 not reset with a Stop Mode Recovery
 Bits 5,4,3,2,1 not reset with a Stop Mode Recovery
Expanded Reg. Bank 0/Group (0)
*
(0) 03 P3
(0) 02 P2
(0) 01 P1
(0) 00 P0
0U
U
U
U




*
*
*
*
*
*
*
*
*
*
*
Expanded Reg. Bank F/Group 0**
Expanded Reg. Bank 0/Group 15**
Register Pointer
Z8® Standard Control Registers
Expanded Reg. Bank D/Group 0
Reset Condition
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
24
The upper nibble of the register pointer (see Figure 13) selects which working
register group of 16 bytes in the register file, is accessed out of the possible 256.
The lower nibble selects the expanded register file bank and, in the case of the
Crimzon ZLR32300 family, banks 0, F, and D are implemented. A 0h in the lower
nibble allows the normal register file (bank 0) to be addressed. Any other value
from 1h to Fh exchanges the lower 16 registers to an expanded register bank.
Figure 13. Register Pointer
Example: Crimzon ZLR32300 (see Figure 12 on page 23).
R253 RP = 00h
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0Dh
R0 = CTR0
R1 = CTR1
R2 = CTR2
R3 = CTR3
The counter/timers are mapped into ERF group D. Access is easily performed
using the following:
LD RP, #0Dh ; Select ERF D
for access to bank D
; (working
register group 0)
LD R0,#xx ; load CTR0
LD 1, #xx ; load CTR1
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register
File Pointer
Working Register
Pointer
Default Setting Afte r Reset = 0000 0000
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
25
LD R1, 2 ; CTR2CTR1
LD RP, #0Dh ; Select ERF D
for access to bank D
; (working
register group 0)
LD RP, #7Dh ; Select
expanded register bank D and working ; register
group 7 of bank 0 for access.
LD 71h, 2
; CTR2register 71h
LD R1, 2
; CTR2register 71h
Register File
The register file (ban k 0) consists of 4 I/O port registers, 237 general-p urpose reg-
isters, 16 control and status registers (R0–R3, R4–R239, and R240–R255,
respectively), and two expanded registers groups in Banks D (see Table 7 on
page 28) and F. Instructions can access registers directly or indirectly through an
8-bit address field, thereby allowing a short, 4-bit register address to use the Reg-
ister Pointer (see Figure 14 on page 26). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16 continuous locations.
The Register Pointer addresses the st arting location of th e active working register
group.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
26
Working register group E0–EF can only be accessed through
working registers and indirect addressing modes.
Figure 14. Register Pointer—Detail
Stack
The internal register file is used for the sta ck. An 8-bit S t ack Pointer SPL (R255) is
used for the internal stack that resides in the general-purpose registers (R4–
R239). SPH (R254) can be used as a general-purpose register.
Timers
T8_Capture_HI—HI8(D)0BH
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 1.
Field Bit Position Description
T8_Capture_HI [7:0] R/W Captured Data—No Effect
Note:
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
Specified Working
Register Group
Register Group 1
Register Group 0
I/O Ports
R253
The lower nibble of the
register file address provided
by the instruction points to
the specified register .
* RP = 00: Selects Register Bank 0, Working Register Group 0
R15 to R0
R15 to R4 *
R3 to R0 *
FF
F0
EF
E0
DF
D0
40
3F
30
2F
20
1F
10
0F
00
Register Group 2
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
27
T8_Capture_LO—L08(D)0AH
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 0.
T16_Capture_HI—HI16(D)09H
This register holds the captured data from the output of the 16-bit Counter/
Timer16. This register holds the MS-Byte of the data.
T16_Capture_LO—L016(D)08H
This register holds the captured data from the output of the 16-bit Counter/
Timer16. This register holds the LS-Byte of the data.
Counter/Timer2 MS-Byte Hold Register—TC16H(D)07H
Counter/Timer2 LS-Byte Hold Register—TC16L(D)06H
Field Bit Position Description
T8_Capture_L0 [7:0] R/W Captured Data—No Effect
Field Bit Position Description
T16_Captur e_ HI [7:0] R/W Capture d Data—No Effect
Field Bit Position Description
T16_Capture_LO [7:0] R/W Captured Data—No Effect
Field Bit Position Description
T16_Data_HI [7:0] R/W Data
Field Bit Position Description
T16_Data_LO [7:0] R/W Data
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
28
Counter/Timer8 High Hold Register—TC8H(D)05H
Counter/Timer8 Low Hold Register—TC8L(D)04H
CTR0 Counter/Timer8 Control Register—CTR0(D)00H
Table 7 lists and briefly describes the fields for this register.
Field Bit Position Description
T8_Level_HI [7:0] R/W Data
Field Bit Position Description
T8_Level_LO [7:0] R/W Data
Table 7. CTR0(D)00H Counter/Timer8 Control Register
Field Bit Position Value Description
T8_Enable 7------- R/W 0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------- R/W 0*
1Modulo-N
Single Pass
Time_Out --5------ R/W 0**
1
0
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
T8 _Clock ---43--- R/W 0 0**
0 1
1 0
1 1
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1 Disable Data Capture Interrupt
Enable Data Capture Interru p t
Counter_INT_Mask ------1- R/W 0**
1Disable Time-Out Interrupt
Enable Time-Out Interrupt
P34_Out -------0 R/W 0*
1P34 as Port Output
T8 Output on P34
*Indicates the value upon Power-on reset.
**Indicates the value upon Power-on reset. Not reset with a Stop Mode Recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
29
T8 Enable
This field enables T8 when set (written) to 1.
Single/Modulo-N
When set to 0 (Modulo-N), the counter reloads the initial value when the terminal
count is reached. When set to 1 (single-pass), the counter stops when the termi-
nal count is reached.
Timeout
This bit is set when T 8 times out (terminal co unt reached). To reset this bit, write a
1 to its location.
Writing a 1 is the only way to reset the Terminal Count
status condition. Reset this bit before using/enabling the
counter/timers.
The first clock of T8 might not have complete clock width
and can occur any time when enabled.
Ensure to manipulate CTR0, bit 5 and CTR1, bits 0 and 1
(DEMODULATION mode) when using the OR or AND
commands. These instructions use a Read-Modify-Write
sequence in which the current st atus from the CTR0 and CTR1
registers is ORed or ANDed with t he designated value and then
written back into the registers.
T8 Clock
These bits define the frequency of the input signal to T8.
Caution:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
30
Capture_INT_Mask
Set this bit to allow an interrupt when dat a is cap tured into either LO8 or HI8 upon
a positive or negative edge detection in DEMODULATION mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
T8 and T16 Common Functions—CTR1(0D)01h
This register controls the functions in common with the T8 and T16.
Table 8 lists and briefly describes the fields for this register.
Table 8. CTR1(0D)01H T8 and T16 Common Functions
Field Bit Position Value Description
Mode 7------- R/W 0*
1TRANSMIT mode
DEMODULATION mode
P36_Out/
Demodulator_Input -6------ R/W 0*
1
0*
1
TRANSMIT mode
Port Output
T8/T16 Output
DEMODULATION mode
P31
P20
T8/T16_Logic/
Edge _Detect --54---- R/W 00**
01
10
11
00**
01
10
11
TRANSMIT mode
AND
OR
NOR
NAND
DEMODULATION mode
Falling Edge
Rising Edge
Both Edges
Reserved
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
31
Mode
If the result is 0, the cou nter/timers are in TRANSMIT mode; otherwise, they are in
DEMODULATION mode.
P36_Out/Demodulator_Input
In TRANSMIT mode, this bit defines whether P36 is used as a normal output pin
or the combined output of T8 and T16.
In DEMODULATION mode, this bit defines whether the input signal to the
Counter/Timers is from P20 or P31.
If the input signal is from Port 31, a capture event may also generate an IRQ2
interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by
clearing its IMR bit D2 or use P20 as the input.
Transmit_Submode/
Glitch_Filter ----32-- R/W 00
01
10
11
00
01
10
11
TRANSMIT mode
Normal Operation
PING-PONG mode
T16_Out = 0
T16_Out = 1
DEMODULATION mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
Reserved
Initial_T8_Out/
Rising Edge ------1- R/W
R
W
0
1
0
1
0
1
TRANSMIT mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
DEMODULATION mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Initial_T16_Out/
Falling_Edge -------0 R/W
R
W
0
1
0
1
0
1
TRANSMIT mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
DEMODULATION mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
*Default at Power-On Reset.
**Default at Power-On Reset. Not reset with a Stop Mode Recovery.
Table 8. CTR1(0D)01H T8 and T16 Common Functions (Continued)
Field Bit Position Value Description
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
32
T8/T16_Logic/Edge _Detect
In TRANSMIT mode, this field defines how the outputs of T8 and T16 are com-
bined (AND, OR, NOR, NAND).
In DEMODULATION mode, this field defines which edge should be detected by
the edge detector.
Transmit_Submode/Glitch Filter
In TRANSMIT mode, this field defines whether T8 and T16 are in the PING-PONG
mode or in independent normal operation mode. Setting this field to ‘NORMAL
OPERATION mode’ terminates the ‘PING-PONG mode’ operation. When set to
10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1.
In DEMODULATION mode, this field defines the width o f the glitch that must b e fil-
tered out.
Initial_T8_Out/Rising_Edge
In TRANSMIT mode, if 0, the output of T8 is set to 0 when it starts to count. If 1,
the output of T8 is set to 1 when it st arts to cou nt. When the counter is not enabled
and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This
ensures that when the clock is enabled, a transition occurs to the initial state set
by CTR1, D1.
In DEMODULATION mode, this bit is set to 1 when a rising edge is detected in the
input signal. In order to reset the mode, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In TRANSMIT mode, if it is 0, the output of T16 is set to 0 when it st arts to count. If
it is 1, the output of T16 is set to 1 when it start s to count. Th is bit is effective only
in Normal or PING-PONG mode (CTR1, D3; D2). Wh en the counter is not enabled
and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures
that when the clock is enabled, a tran sition occu rs to the initial st a te set by CTR1,
D0.
In DEMODULATION mode, this bit is set to 1 when a falling edge is detected in
the input signal. In order to reset it, a 1 must be written to this location.
Modifying CTR1 (D1 or D0) while the counters are enabled
causes unpredictable output from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register—CTR2(D)02H
Table 9 on page 33 lists and briefly describes the fields for this register.
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
33
T16_Enable
This field enables T16 when set to 1.
Single/Modulo-N
In TRANSMIT mode, when set to 0, the counter reloads the initial value when it
reaches the terminal count. When set to 1, the counter stops when the terminal
count is reached.
Table 9. CTR2(D)02H: Counter/Timer16 Control Register
Field Bit Position Value Description
T16_Enable 7------- R
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------ R/W 0*
1
0
1
TRANSMIT mode
Modulo-N
Single Pass
DEMODULATION mode
T16 Recognizes Edge
T16 Does Not Recognize
Edge
Time_Out --5----- R
W
0**
1
0
1
No Counter Timeout
Counter Timeout
Occurred
No Effect
Reset Flag to 0
T16 _Clock ---43--- R/W 00**
01
10
11
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1Disable Data Capture In t.
Enable Data Capture Int.
Counter_INT_Mask ------1- R/W 0*
1Disable Timeout Int.
Enable Timeout Int.
P35_Out -------0 R/W 0*
1P35 as Port Output
T16 Output on P35
*Indicates the value upon Power-On Reset.
**Indicates the value upon Powe r-On Reset. Not reset with a Stop Mode Recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
34
In DEMODULATION mode, when set to 0, T16 ca ptures and reloads on detection
of all the edges. When set to 1, T16 captures and detects on the first edge but
ignores the subsequent edges. For details, see the description of T16
DEMODULATION mode on page 42.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write
a 1 to this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
Counter_INT_Mask
Set this bit to allow an interrupt when T16 times out.
P35_Out
This bit defines whether P35 is used as a normal output pin or T16 output.
CTR3 T8/T16 Control Register—CTR3(D)03H
Table 10 lists and briefly describes the fields for this register. This register allows
the T8 and T16 counters to be synchronized.
Table 10. CTR3 (D)03H: T8/T16 Control Register
Field Bit Position Value Description
T16 Enable 7------- R
R
W
W
0**
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
T8 Enable -6------ R
R
W
W
0**
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Sync Mode --5----- R/W 0*
1Disable Sync Mode
Enable Sync Mode
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
35
Counter/Timer Functional Blocks
Input Circuit
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–
D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is
detected. Glitches in the input signal that have a width less than specified (CTR1
D3, D2) are filtered out (see Figure 15).
Figure 15.Glitch Filter Circuitry
T8 TRANSMIT Mode
Before T8 is enabled, the output of T8 depen ds on CTR1, D1. If it is 0, T8_OUT is
1; if it is 1, T8_OUT is 0 (see Figure 16 on page 36).
Reserved ---43210 R
W1
xAlways reads 11111
No Effect
*Indicates the value upon Power-On Reset.
**Indicates the value upon Powe r-On Reset. Not reset with a Stop Mode Recovery.
Table 10. CTR3 (D)03H: T8/T16 Control Register (Continued)
Field Bit Position Value Description
MUX Glitch
Filter Edge
Detector
P31
P20
Pos
Edge
Neg
Edge
CTR1
D5,D4
CTR1
D6 CTR1
D3, D2
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
36
Figure 16.TRANSMIT Mode Flowchart
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
T8 (8-Bit)
Transmit Mode
No T8_Enable Bit Set
CTR0, D7
Yes
CTR1, D1
Value
Reset T8_Enable Bit
01
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
No T8_Timeout
Yes
Single Pass Single
Modulo-N
T8_OUT Value 0
Enable T8
No T8_Timeout
Yes
Pass?
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
1
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
37
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1).
If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In SINGLE-PASS mode (CTR0, D6), T8 counts down to 0 and stops,
T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt
can be generated if it is enabled (CTR0, D1). In MODULO-N mode, upon reaching
terminal count, T8_OUT is toggled, but n o in terrupt is gene rated. From that point,
T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout sta-
tus bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One
cycle is thus completed. T8 then loads from TC8H or TC8L according to the
T8_OUT level and repeats the cycle. See Figure 17.
Figure 17.8-Bit Counter/Timer Circuits
You can modify the values in TC8H or TC8L at any time. The new values take
effect when they are loaded.
To ensure known operation do not write these registers at
the time the values are to be loaded into the counter/timer.
CTR0 D1
Negative Edge
Positive Edge
Z8 Data Bus
IRQ4
CTR0 D2
SCLK
Z8 Data Bus
CTR0 D4, D3
Clock
T8_OUT
LO8
TC8H TC8L
Clock
Select 8-Bit
Counter T8
HI8
Caution:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
38
An initial count of 1 is not allowed (a non-function occurs). An
initial count of 0 causes TC8 to count from 0 to FFH to FEH.
The letter H denotes hexadecimal values.
Transition from 0 to FFH is not a timeout condition.
Using the same instructions for stopping th e counter/timers
and setting the status bits is not recommended.
Two successive commands are necessary. First, the counter/timers must be
stopped. Second, the status bits must be reset. These commands are required
because it takes one counter/timer clock interval for the initiated event to actually
occur. See Figure 18 and Figure 19.
Figure 18. T8_OUT in SINGLE-PASS Mode
Figure 19. T8_OUT in MODULO-N Mode
Note:
Caution:
TC8H
Counts
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
T8_OUT Toggles;
Timeout In terrupt
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
Timeout
Interrupt Timeout
Interrupt
T8_OUT
T8_OUT Toggles
TC8L TC8H TC8H TC8LTC8L ...
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
39
T8 DEMODULATION Mode
You must program TC8L and TC8H to FFh. After T8 is enabled, when the first
edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to
count down. When a subsequent edge (rising, falling, or both depending on
CTR1, D5; D4) is detected during counting, the current value of T8 is
complemented and put into one of the capture registers. If it is a positive edge,
data is put into LO8; if it is a negative edge, data is put into HI8. From that point,
one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be
generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts
counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an
interrupt can be generated if enabled (CTR0, D1). T8 then continues counting
from FFh (see Figure 20 and Figure 21).
Figure 20.DEMODULATION Mode Count Capture Flowchart
T8 (8-Bit)
Count Capture
T8 Enable
(Set by User)
No
Yes
Edge Present
What Kind
of Edge
T8 HI8
No
Yes
Negative
FFh
T8
Positive
T8 LO8
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
40
Figure 21. DEMODULATION Mode Flowchart
T8 (8-Bit)
Demodulation Mode
T8 Enable
CTR0, D7
No
Yes
FFh
TC8
First
Edge Present
Enable TC8
T8_Enable
Bit Set
Edge Present
T8 Timeout
Set Edge Present Status
Bit and Trigger Data
Capture Int. If Enabled
Set Timeout Status
Bit and Trigger
Timeout Int. If Enabled
Continue Counting
Disable TC8
No
Yes
No
Yes
Yes
Yes
No
No
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
41
T16 TRANSMIT Mode
In NORMAL or PING-PONG mode, the output of T16 when not enable d, is depe n-
dent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can
force the output of T16 to either a 0 or 1 whether it is enabled or not by program-
ming CTR1 D3; D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded , and T16_OUT is switched
to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled
(in NORMAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if
enabled), and a status bit (CTR2, D5) is set (see Figure 22).
Figure 22.16-Bit Counter/Timer Circuits
Global interrupts override this funct ion as described in Interrupts
on page 45.
If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 23 on page
42). If it is in MODULO-N mode, it is loaded with TC16H * 256 + TC16L, and the
counting continues (see Figure 24 on page 42).
You can modify the values in TC16H and TC16L at any time. The new values take
effect when they are loaded.
CTR2 D1
Negative Edge
Positive Edge
Z8 Data Bus
IRQ3
CTR2 D2
SCLK
Z8 Data Bus
CTR2 D4, D3
Clock
T16_OUT
LO16
TC16H TC16L
Clock
Select 16-Bit
Counter T16
HI16
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
42
Do not load these registers at the time the values are to be
loaded into the counter/timer to ensure known operation.
An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to FFFFH to FFFEH. Transition
from 0 to FFFFH is not a timeout condition.
Figure 23.T16_OUT in SINGLE-PASS Mode
Figure 24.T16_OUT in Modulo-N Mode
T16 DEMODULATION Mode
You must program TC16L and TC16H to FFH. After T16 is enabled, and the first
edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16 cap-
tures HI16 and LO16, reloads, and begins counting.
If D6 of CTR2 Is 0
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is
detected during counting, the current count in T16 is complemented and put into
HI16 and LO16. When dat a is captured, one of the edge dete ct status bit s (CTR1,
D1; D0) is set and an interrupt is generated if enabled (CTR2, D2). T16 is loaded
with FFFFH and starts again.
Caution:
TC16H*256+TC16L Counts
“Counter Enable” Command
T16_OUT Switches to Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Timeout Interrupt
TC16H*256+TC16L
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Toggles,
Timeout Interrupt
“Counter Enable” Command,
T16_OUT Switches to Its
Initial Value (CTR1 D0)
TC16_OUT ...
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
43
This T16 mode is generally used to measure space time, the length of time
between bursts of carrier signal (marks).
If D6 of CTR2 Is 1
T16 ignores the subsequent edges in the input signal and continues counting
down. A timeout of T8 causes T16 to capture its current value and generate an
interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues
counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16
captures and reloads on the next edge (rising, falling, or both depending on
CTR1, D5; D4), continuing to ignore subsequent edges.
This T16 mode generally measures mark time, the length of an active carrier sig-
nal burst.
If T16 reaches 0, T16 continues counting from FFFFH. Meanwhile, a status bit
(CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2
D1).
PING-PONG Mode
This operation mode is only valid in TRANSMIT mode. T8 and T16 must be
programmed in SINGLE-PASS mode (CTR0, D6; CTR2, D6), and PING-PONG
mode must be programmed in CTR1, D3; D2. You can begin the operation by
enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example , if T8 is enabled,
T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level,
TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is
disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1,
D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16
reaches the terminal count, it stops, T8 is enabled again, repeating the entire
cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0,
D1; CTR2, D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of
CTR1. See Figure 25.
Enabling Ping-Pong operation while the counter/timers are
running might cause intermittent counter/timer function. Disable
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
44
the counter/timers and reset the Status Flags before instituting
this operation.
Figure 25.PING-PONG Mode Diagram
Initiating PING-PONG Mode
First, make sure both counter/timers are not running. Set T8 into SINGLE-PASS
mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the
PING-PONG mode (CTR1, D2; D3). These instructions can be in random order.
Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2,
D7). See Figure 26.
Figure 26.Output Circuit
The initial value of T8 or T16 must not be 1. If you stop the timer and restart the
timer, reload the initial value to avoid an unknown previous value.
Enable
TC8
Enable
Timeout
TC16
Ping-Pong
CTR1 D3,D2
Timeout
T16_OUT
MUX
CTR1 D3
T8_OUT
P34
AND/OR/NOR/NAND
Logic MUX
MUX
MUX
P35
P36
P34_Internal
CTR1 D5, D4
P36_Internal
P35_Internal
CTR1, D2
CTR0 D0
CTR1 D6
CTR2 D0
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
45
During PING-PONG Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alter-
nately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the
counter/timers reach the terminal count.
Timer Output
The output logic for the time rs is displayed in Figure 26 on p age 44. P34 is used to
output T8-OUT when D0 of CTR0 is set. P35 is used to output the value of TI6-
OUT when D0 of CTR2 is set. When D6 of CTR1 is set, P36 outputs the logic
combination of T8-OUT and T16-OUT determined by D5 and D4 of CTR1.
Interrupts
The Crimzon ZLR32300 features six dif ferent interrupts (se e Table 1 1on p age 47).
The interrupts are maskable and prioritized (see Figure 27 on page 46). The six
sources are divided as follows: three sources are claimed by Port 3 lines P33–
P31, two by the counter/timers (see Table 11 on page 47) and one for Low-Volt-
age detection. The Interrupt Mask Register (globally or individually) enables or
disables the six interrupt requests.
The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). In
DIGITAL mode, Pin P33 is the source. In ANALOG mode the output of the Stop
Mode Recovery source logic is used as the source for the in terrupt. See Figure 32
on page 54.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
46
Figure 27. Interrupt Block Diagram
Low-Voltage
Detection
Timer 8
Timer 16
Interrupt Edge
Select
IMR
IPR
Priority
Logic
IRQ
5
IRQ2 IRQ0 IRQ1 IRQ3 IRQ4 IRQ5
P31 P32
IRQ Register
D6, D7
Global
Interrupt
Enable
Interrupt
Request
Vector Select
D1 of P3M Register
P33
01
Stop Mode Recovery Source
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
47
When more than one interrupt is pending, priorities are resolved by a
programmable priority encoder controlled by the Interrupt Priority Register. An
interrupt machine cycle activates when an interrupt requ est is granted. As a result,
all subsequent interrupt s are disabled, and the Prog ram Counter and Status Flags
are saved. The cycle then branches to the Program Memory vector location
reserved for that interrupt. All Crimzon ZLR32300 interrupts are vectored through
locations in the Program Memory. This memory location and the next byte cont ain
the 16-bit address of the interrupt service routine for that particular interrupt
request. To accommodate polled interrupt systems, interrupt inputs are masked,
and the Interrupt Request register is polled to determine which of the interrupt
requests require service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered. You can program these interrupts. The software can poll to identify the
state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register
(R250), bits D7 and D6. The configuration is indicated in Table 12.
Table 11. Interrupt Types, Sources, and Vectors
Name Source Vector Location Comments
IRQ0 P32 0,1 External (P32), Rising, Falling Edge Triggered
IRQ1 P33 2,3 External (P33), Falling Edge Triggered
IRQ2 P31, TIN 4,5 External (P31), Rising, Falling Edge Triggered
IRQ3 T16 6,7 Internal
IRQ4 T8 8,9 Internal
IRQ5 LVD 10,11 Internal
Table 12.IRQ Register
IRQ Interrupt Edge
D7 D6 IRQ2 (P31) IRQ0 (P32)
00 F F
01 F R
10 R F
11 R/F R/F
Note:
F = Falling Edge; R = Rising Edge
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
48
Clock
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for
connection to a crystal, ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz
maximum, with a series resistance (RS) less than or equal to 100 . The on-chip
oscillator can be driven with a suitable external clock source.
The crystal must be connected across XTAL1 and XTAL2 using the recommended
capacitors from each pin to ground. The typical capacitor value is 10 pF for 8
MHz. Also check with the crystal supplier for the optimum capacitance.
Figure 28.Oscillator Configuration
Maxim’s IR MCU support s crystal, resonat or, and oscillator. Most resonators have
a frequency tolerance of less than ±0.5%, which is enough for remote control
application. Resonator has a very fast startup time, which is around few hundred
microseconds. Most crystals have a frequency tolerance of less than 50 ppm
(±0.005%). However, crystal needs longer startup time than the resonator. The
large loading capacitance slows down the oscillation startup time. Maxim®
suggests not to use more than 10 pF loading capacitor for the crystal. If the stray
capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2
must be reduced further to ensure stable oscillation before the TPOR (Power-On
Reset time is typically 5–6 ms, see Table 20 on page 85).
For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the
Stop Mode Recovery delay, which is the TPOR. If Stop Mode Recovery delay is not
selected, the MCU executes instruction immediately after it wakes up from the
C1
C2
XTAL1
XTAL2
XTAL1
XTAL2
Crystal
C1, C2 = 10 pF *
f = 8 MHz
External Clock
*Note: preliminary value.
XTAL1
XTAL2
Ceramic Resonator f = 8 MHz
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
49
STOP mode. If resonator or crystal is used as a clock source then Stop Mode
Recovery delay has to be selected (bit 5 of SMR = 1).
For resonator and crystal oscillator, the oscillation ground must go directly to the
ground pin of the microcontroller. The oscillation ground must use the shortest dis-
tance from the microcontroller ground pin and it must be isolated from other con-
nections.
Power Management
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the
Power-on reset timer function. The POR time allo ws V DD an d the o scillator circuit
to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
Power Fail to Power OK status, including Waking up from VBO Standby
•
Stop Mode Recovery (if D5 of SMR = 1)
•
WDT Timeout
The POR timer is 2.5 ms minimum. Bit 5 of the Stop Mode Register determines
whether the POR timer is byp assed after S top Mode Recove ry (typical for external
clock).
HALT Mode
This instruction turns OFF the internal CPU clock, but not the XTAL oscillation.
The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and
IRQ5 remain active. The devices are recovered by interrupts, either externally or
internally generated. An interrupt request must be executed (enabled) to exit
HALT mode. After the interrupt service routine, the program continues from the
instruction after HALT mode.
STOP Mode
This instruction turns OFF the internal clock and extern al crystal oscillation, reduc-
ing the standby current to 10 A or less. STOP mode is terminated only by a reset,
such as WDT timeout, POR, SMR or external reset. This condition causes the
processor to rest art the application program at add ress 000CH. To enter ST OP (or
HALT) mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP (Opcode = FFH) immediately before the appropri-
ate sleep instruction, as follows:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
50
FF NOP ; clear the pipeline
6F STOP ; enter STOP mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT Mode
Port Configuration
Port Configuration Register
The Port Configuration (PCON) register (see Figure 29) configures the comp arator
output on Port 3. It is located in the expanded register 2 at Bank F, location 00.
PCON(FH)00h
Figure 29. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comp arator used in Port 3. A 1 in this location brings the comp ar-
ator outputs to P34 an d P37, and a 0 releases the Port to its st and ard I/O config u-
ration.
Port 1 Output Mode (D1)
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull*
Reserved (Must be 1)
*Default setting after reset.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
51
Bit 1 controls the output mode of port 1. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop Mode Recovery
Stop Mode Recovery Register
This register selects the clock divide value and determines the mode of Stop
Mode Recovery (see Figure 30). All bits are write only except bit 7, which is read
only. Bit 7 is a Flag bit that is hardware set on the condition of Stop recovery and
reset by a power-on cycle. Bit 6 controls whether a low level or a high level at the
XOR-gate input (see Figure 32 on page 54) is required from the recovery source.
Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4 of the SMR regis-
ter specify the source of the Stop Mode Re covery signal. Bits D0 determines if
SCLK/TCLK are divided by 16 or not. The SMR is located in Bank F of the
Expanded Register Group at address 0BH.
SMR(0F)0Bh
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
52
Figure 30. Stop Mode Recovery Register
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (see Figure 31).
This control selectively reduces device power consumption during normal proces-
sor execution (SCLK control) and/or HALT mode (where TCLK sources interrupt
logic). After Stop Mode Recovery, this bit is set to a 0.
Figure 31.SCLK Circuit
Stop Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
*Default setting after reset.
* *Default setting after reset and Stop Mode Recovery.
* * *At the XOR gate input.
* * * *Default setting after reset. Recommended to be set to 1 if using a crystal or resonator clock
source.
SCLK
TCLKSMR, D0
2
OSC
16
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
53
Stop Mode Recovery Source (D2, D3, and D4)
These three bit s of the SMR specify the wake-up source of the S top recovery (see
Figure 32 and Table 14).
Stop Mode Recovery Register 2—SMR2(F)0Dh
Table 13 lists and briefly describes the fields for this register.
Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2*
Field Bit Position Value Description
Reserved 7------- 0 Reserved (Must be 0)
Recovery Level -6------ W0
†
1Low
High
Reserved --5----- 0 Reserved (Must be 0)
Source ---432-- W 000†
001
010
011
100
101
110
111
A. POR Only
B. NAND of P23–P20
C. NAND of P27–P20
D. NOR of P33–P31
E. NAND of P33–P31
F. NOR of P33–P3 1, P0 0, P07
G. NAND of P33–P31, P00, P07
H. NAND of P33–P31, P22–P20
Reserved ------10 00 Reserved (Must be 0)
*Port pins configured as outputs are ig nored as an SMR source.
†Indicates the value upon Power-On Reset.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
54
Figure 32. Stop Mode Recovery Source
SMR2 D4 D3 D2
100
SMR2 D4 D3 D2
111
SMR D4D3D2
010
SMR D4D3D2
111
SMR D4D3D2
101
SMR D4D3D2
100
SMR D4D3D2
011
SMR D4D3D2
000
SMR D4D3D2
110
VCC
P31
P32
P33
P27
P20
P23
P20
P27
SMR2 D4 D3 D2
001
SMR2 D4 D3 D2
000
SMR2 D4 D3 D2
010
SMR2 D4 D3 D2
011
SMR2 D4 D3 D2
101
SMR2 D4 D3 D2
110
VCC
P20
P23
P20
P27
P31
P32
P33
P31
P32
P33
P31
P32
P33
P00
P31
P32
P33
P00
P31
P32
P33
P20
P21
SMR D6
SMR2 D6
To RESET and WDT
Circuitry (Active Low)
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
55
Any Port 2 bit defined as an output drives the corresponding
input to the default state. This condition allows the remaining
inputs to control the AND/OR function. See SMR2 register on
page 56 for other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if low, disables the TPOR delay after Stop Mode Recovery. The default
configuration of this bit is 1. If the ‘fast’ wake up is selected, the Stop Mode
Recovery source must be kept active for at least 10 TpC.
This bit must be set to 1 if using a crystal or resonator clock
source. The TPOR delay allows the clock source to stabilize
before executing instructions.
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery
sources wakes the Crimzon ZLR32300 from STOP mod e. A 0 indicates Low level
recovery. The default is 0 on POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from STOP mode.
The bit is set to 0 when the device reset is other than Stop Mode Recovery.
Table 14. Stop Mode Recovery Source
SMR:432 Operation
D4 D3 D2 Description of Action
0 0 0 POR and/or external reset recovery
001Reserved
010P31 transition
011P32 transition
100P33 transition
101P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
Note:
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
56
Stop Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop Mode Recovery for SMR2 (see
Figure 33).
SMR2(0F)Dh
Figure 33. Stop Mode Recovery Register 2 ((0F)DH:D2–D4, D6 Write Only)
If SMR2 is used in conjunction with SMR, either of the specified events causes a
Stop Mode Recovery.
Port pins configured as outputs are ignored as an SMR or
SMR2 recovery source. For example, if the NAND or P23–P20
is selected as the recovery source and P20 is configured as an
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0Low *
1 High
Reserved (Must be 0)
Note:
If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
*Default setting after reset.
**At the XOR gate input.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
57
output, the remaining SMR pins (P23–P21) form the NAND
equation.
Watchdog Timer Mode
Watchdog Timer Mode Register (WDTMR)
The Watchdog Timer is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be enabled by executing the
WDT instruction. On subsequent executions of the WDT instruction, the WDT is
refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT
instruction affects the Zero (Z), Sign (S), and Overflow (V) Flags.
The POR clock source the internal RC-o scillator. Bits 0 and 1 of the WDT registe r
control a tap circuit tha t determines the minimum timeout period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
S top. Bits 4 through 7 a re reserved (see Figure 34). This reg ister is accessible only
during the first 60 processor cycles (120 XTAL clocks) from the execution of the
first instruction after Power-on reset, Watchdog Reset, or a Stop Mode Recovery
(see Figure 33 on p age 56). Af ter this point, the register cannot be modified by any
means (intentional or otherwise). The WDTMR cannot be read. The register is
located in Bank F of the Expanded Register Group at address location 0Fh. It is
organized as displayed in Figure 34.
WDTMR(0F)0Fh
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 10 ms min.
01* 20 ms min.
10 40 ms min.
11 160 ms min.
WDT During HALT
0OFF
1ON *
WDT During Stop
0OFF
1ON *
Reserved (Must be 0)
*Default setting after reset.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
58
Figure 34. Watchdog Timer Mode Register (Write Only)
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in Table 15.
WDTMR During Halt (D2)
This bit determines whether or not the WDT is active during HALT mode. A 1 indi-
cates active during HALT. The default is 1. See Figure 35.
Table 15. Watchdog Timer Time Select
D1 D0 Timeout of Internal RC-Oscillator
0010 ms min.
0120 ms min.
1040 ms min.
1 1 160 ms min.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
59
Figure 35. Resets and WDT
WDTMR During STOP (D3)
This bit determines whether or not the WDT is active during ST OP mode. A 1 indi-
cates active during Stop. The default is 1.
ROM Selectable Options
There are seven ROM Selectable Options to choose from based on ROM code
requirements. These are listed in Table 16.
-
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High
input translation.
+
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
5 Clock Filter *CLR2 18 Clock RESET
CLK Generator RESET
WDT T AP SELECT
POR 10 ms 20 ms 40 ms 160
CLK
*CLR1 WDT/POR Counter Chain
Internal
RC
Oscillator.
WDT
VDD
Low Operating
Voltage Det.
VBO VDD
Internal
RESET
Active
High
12-ns Glitch Filter
XTAL
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
60
Volt age Brownout/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for
correct operation of the device. Reset is globally driven when VDD falls below VBO.
A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or
resonator clock. If the VDD is allowed to st ay above VRAM, the RAM content is pre-
served. When the power level is returned to above VBO, the device performs a
POR and fu nctions no rmally.
Low-Voltage Detection
Low-Voltage Detection Register—LVD(D)0CH
Voltage detection does not work at STOP mode.
Table 16. ROM Selectable Options
Port 00–03 Pull-Ups ON/OFF
Port 04–07 Pull-Ups ON/OFF
Port 10–13 Pull-Ups ON/OFF
Port 14–17 Pull-Ups ON/OFF
Port 20–27 Pull-Ups ON/OFF
Port 3 Pull-Ups ON/OFF
Watchdog Timer at Power-On Reset ON/OFF
Field Bit Position Description
LVD 76543--- Reserved
No Effect
-----2-- R 1
0* HVD Flag set
HVD Flag reset
------1- R 1
0* LVD Flag set
LVD Flag reset
-------0 R/W 1
0* Enable VD
Disable VD
*Default after POR.
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
61
Do not modify register P01M while checking a low-voltage
condition. Switching noise of both ports 0 and 1 together might
trigger the LVD Flag.
Voltage Detection and Flags
The Voltage Detection register (LVD, register 0Ch at the expanded register bank
0Dh) offers an option of monitoring the VCC voltage. The voltage detection is
enabled when bit 0 of LVD register is set. Once voltage detection is enabled, the
VCC level is monitored in real time. The Flags in t he LVD register valid 20 µs after
voltage detection is enabled. The HVD Flag (bit 2 of the LVD register) is set only if
VCC is higher than VHVD. The LVD Flag (bit 1 of the LVD register) is set only if VCC
is lower than the VLVD. When voltage detection is enabled, the LVD Flag also trig-
gers IRQ5. The IRQ bit 5 latches the low voltage condition until it is cleared by
instructions or reset. The IRQ5 interrupt is served if it is enabled in the IMR regis-
ter. Otherwise, bit 5 of IRQ register is latched as a Flag only.
If it is necessary to receive an LVD interrupt upon power-up at
an operating voltage lower than the low-battery detect
threshold, enable interrupts using the Enable Interrupt (EI)
instruction prior to enabling the voltage detection.
Note:
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
62
Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are displayed in Figure 36 on
page 63 through Figure 40 on page 68.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
63
Figure 36.TC8 Control Register ((0D)O0H: Read/Write Except Where Noted)
CTR0(0D)00h
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt**
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture
Interrupt**
1 Enable T8 Data Capture Interrupt
00 SCLK on T8**
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8
R 0 No T8 Counter Timeout**
R 1 T8 Counter Timeout Occurred
W 0 No Effect
W 1 Reset Flag to 0
0 Modulo-N*
1 Single Pass
R 0 T8 Disabled *
R1 T8 Enabled
W0 Stop T8
W 1 Enable T8
*Default setting after reset.
**Default setting after reset. Not reset with a Stop Mode Recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
64
CTR1(0D)01h
D7 D6 D5 D4 D3 D2 D1 D0
TRANSMIT Mode*
R/W 0 T16_OUT is 0 initially*
1 T16_OUT is 1 initially
DEMODULATION Mode
R 0 No Falling Edge Detection
R 1 Falling Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
TRANSMIT Mode*
R/W 0 T8_OUT is 0 initially*
1 T8_OUT is 1 initially
DEMODULATION Mode
R 0 No Rising Edge Detection
R 1 Rising Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
TRANSMIT Mode*
0 0 Normal Operation*
0 1 PING-PONG Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
DEMODULATION Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
11Reserved
TRANSMIT Mode/T8/T16 Logic
0 0 AND**
01OR
1 0 NOR
11NAND
DEMODULATION Mode
0 0 Falling Edge Detection
0 1 Rising Edge Detection
1 0 Both Edge Detection
11Reserved
TRANSMIT Mode
0 P36 as Port Output *
1 P36 as T8/T16_OUT
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
65
Figure 37.T8 and T16 Common Control Functions ((0D)01H: Read/Write)
Ensure differentiating the TRANSMIT mode from
DEMODULATION mode. Depending on which of these two
modes is operating, the CTR1 bit has different functions.
Changing from one mode to another cannot be performed
DEMODULATION Mode
0 P31 as Demodulato r In put
1 P20 as Demodulator Input
TRANSMIT/DEMODULATION Mode
0 TRANSMIT Mode *
1 DEMODULATION Mode
*Default setting after reset.
**Default setting after reset. Not reset with a S top Mode
Recovery.
CTR1(0D)01h
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
66
without disabling the
counter/timers.
CTR2(0D)02h
Figure 38. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)
D7 D6 D5 D4 D3 D2 D1 D0
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt*
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture
Interrupt**
1 Enable T16 Data Capture Interrupt
0 0 SCLK on T16**
0 1 SCLK/2 on T16
1 0 SCLK/4 on T16
1 1 SCLK/8 on T16
R 0 No T16 Timeout**
R 1 T16 Timeout Occurs
W 0 No Effect
W 1 Reset Flag to 0
TRANSMIT Mode
0 Modulo-N for T16*
0 Single Pass for T16
Demodulator Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
R 0 T16 Disabled *
R 1 T16 Enabled
W 0 Stop T16
W1Enable T16
*Default setting after reset.
**Default setting after reset. Not reset with a S top Mode
Recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
67
CTR3(0D)03h
Figure 39. T8/T16 Control Register (0D)03H: Read/Write (Except Where
Noted)
If Sync Mode is enabled, the first pulse of T8 (car rier) is always
synchronized with T16 (demodulated signal). It can always
provide a full carrier pulse.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
0 No Effect
1 Always reads 11111
Sync Mode
0** Disable Sync Mode
1 Enable Sync Mode
T8 Enable
0* Counter Disabled
1 Counter Enabled
0 Stop Counter
1 Enable Counter
T16 Enable
0* Counter Disabled
1 Counter Enabled
0 Stop Counter
1 Enable Counter
*Default setting after reset.
**Default setting after reset. Not reset with a S top Mode
Recovery.
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
68
LVD(0D)0Ch
Figure 40. Voltage Detection Register
Do not modify register P01M while checking a low-voltage
condition. Switching noise of both ports 0 and 1 together might
trigger the LVD Flag.
D7 D6 D5 D4 D3 D2 D1 D0
Voltage Detection
0: Disable *
1: Enable
LVD Flag (Read only)
0: LVD Flag reset *
1: LVD Flag set
HVD Flag (Read only)
0: HVD Flag reset *
1: HVD Flag set
Reserved (Must be 0)
*Default setting after reset.
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
69
Expanded Register File Control Registers (0F)
The expand ed register file control registers (0F) are displayed in Figure 41 on p age
69 through Figure 54 on page 79.
PCON(0F)00h
Figure 41. Port Configuration Register (PCON)(0F)00H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standar d Output *
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull *
Reserved (Must be 1)
*Default setting after reset.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
70
SMR(0F)0Bh
Figure 42. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only,
D7=Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only * *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low **
1 High
Stop Flag
0 POR * * * * *
1 Stop Recovery * *
*Default setting after reset.
* *Default setting after reset and Stop Mode Recovery.
* * *At the XOR gate input.
* * * *Default setting after reset. Recommended to be set to 1 if using a crystal or resonator clock
source.Not reset with Stop Mode Recovery.
* * * * *Default setting after Power-On Reset.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
71
SMR2(0F)0Dh
Figure 43. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4, D6 Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0Low
1 High
Reserved (Must be 0)
Note:
If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
*Default setting after reset. Not reset with a Stop Mode Recovery.
* *At the XOR gate input.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
72
WDTMR(0F)0Fh
Figure 44. Watchdog Timer Register ((0F) 0FH: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 10 ms min.
01* 20 ms min.
10 40 ms min.
11 160 ms min.
WDT During HALT
0OFF
1ON *
WDT During Stop
0OFF
1ON *
Reserved (Must be 0)
*Default setting after reset. Not reset wit a Stop Mode Recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
73
Standard Control Registers
The standard control registers are displayed in Figure 45 through Figure 54 on p age
79.
R246P2M(F6H)
Figure 45. Port 2 Mode Register (F6H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P27–P20 I/O Definition
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
*Default setting after reset. Not reset wit a Stop Mode Recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
74
R247P3M(F7H)
Figure 46. Port 3 Mode Register (F7H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
0: Port 2 Open Drain *
1: Port 2 Push-Pull
0= P31, P32 DIGITAL Mode*
1= P31, P32 ANALOG Mode
Reserved (Must be 0)
*Default setting after reset. Not reset wit a Stop Mode recovery.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
75
R248 P01M(F8H)
Figure 47.Port 0 and 1 Mode Register (F8H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
0: Output
1: Input *
Reserved (Must be 0)
Reserved (Must be 1)
P17–P10 Mode
0: Byte Output
1: Byte Input*
Reserved (Must be 0)
P07–P04 Mode
0: Output
1: Input *
Reserved (Must be 0)
*Default setting after reset; only P00, P01, and P07 are available on Crimzon ZLR32 300 20-pin
configurations.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
76
R249 IPR(F9H)
Figure 48.Interrupt Priority Register (F9H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4, Priority
(Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2, Priority
(Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5, Priority
(Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved; must be 0
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
77
R250 IRQ(FAH)
Figure 49.Interrupt Request Register (FAH: Read/Write)
R251 IMR(FBH)
Figure 50.Interrupt Mask Register (FBH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
IRQ5 = LVD
Inter Edge
P31P32 = 00
P31P32 = 01
P31P32 = 10
P31 P32 = 11
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ 5– IR Q0
(D0 = IRQ0)
Reserved (Must be 0)
0 Master Interrup t Disable *
1 Master Interrupt Enable * *
*Default setting after reset.
* *Only by using EI, DI instruction; DI is required before changing the IMR regi ster.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
78
R252 Flags(FCH)
Figure 51.Flag Register (FCH: Read/Write)
R253 RP(FDH)
Figure 52.Register Pointer (FDH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank Pointer
Working Register Pointer
Default setting after reset = 0000 0000
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Functional Description
79
R254 SPH(FEH)
Figure 53.Stack Pointer High (FEH: Read/Write)
R255 SPL(FFH)
Figure 54.Stack Pointer Low (FFH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
General-Purpose Register
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Low
Byte (SP7–SP0)
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Electrical Characteristics
80
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 17 might cause permanent damage to
the device. This rating is a stress rating only. Functional operation of the device at
any condition above those indicate d in th e op erational se ctions of these specifica-
tions is not implied. Exposure to absolute maximum rating conditions for an
extended period might affect device reliability.
Table 17.Absolute Maximum Ratings
Parameter Minimum Maximum Units Notes
Ambient temperature under bias 0 +70 C
Storage temperature –65 +150 C
Voltage on any pin with respect to VSS –0.3 +4.0 V 1
Voltage on VDD pin with respect to VSS –0.3 +3.6 V
Maximum current on input and/or inactive output pin –5 +5 µA
Maximum output current from active output pin –25 +25 mA
Maximum current into VDD or out of VSS 75 mA
1This voltage applies to all pins except the following: VDD and RESET.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Electrical Characteristics
81
Standard Test Conditions
The characteristics listed in this product specification apply for standard test con-
ditions as noted. All voltages are referenced to GND. Positive current flows into
the referenced pin (see Figure 55 on page 81).
Figure 55.Test Load Diagram
Capacitance
Table 18 lists the capacitances.
Table 18.Cap ac itance
Parameter Maximum
Input capacitance 12 pF
Output capacitance 12 pF
I/O capacitance 12 pF
Note:
TA = 25 °C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND
From Output
Under Test
150 pF
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Electrical Characteristics
82
DC Characteristics
Table 19.DC Characteristics
TA= 0 °C to +70 °C
Symbol Parameter VCC Minimum Typ(7)
Maximum Units Conditions Notes
VCC Supply Voltage 2.0 3.6 V See not es 5 5
VCH Clock Input High
Voltage 2.0-3.6 0.8VCC VCC+0.3 V Driven by External
Clock Generator
VCL Clock Input Low
Voltage 2.0-3.6 VSS–0.3 0.5 V Driven by External
Clock Generator
VIH Input High Voltage 2.0-3.6 0.7VCC VCC+0.3 V
VIL Input Low Voltage 2.0-3.6 VSS–0.3 0.2 VCC V
VOH1 Output High Voltage 2.0-3.6 VCC–0.4 V IOH = –0.5 mA
VOH2 Output High Voltage
(P36, P37, P00,
P01)
2.0-3.6 VCC–0.8 V IOH = –7 mA
VOL1 Output Low Voltage 2.0-3.6 0.4 V IOL = 4.0 mA
VOL2 Output Low Voltage
(P00, P01, P36,
P37)
2.0-3.6 0.8 V IOL = 10 mA
VOFFSET Comparator Input
Offset Voltage 2.0-3.6 25 mV
VREF Comparator
Reference
Voltage
2.0-3.6 0 VDD
-1.75 V
IIL Input Leakag e 2.0 -3.6 – 1 1 AV
IN = 0 V, VCC
Pull-ups disabled
RPU Pull-Up Resistance 225 675 K VIN = 0 V; Pullup s
selected by mask
option
75 275 K
IOL Output Leakage 2.0-3.6 –1 1 AV
IN = 0 V, VCC
ICC Supply Current 2.0
3.6 1.2
2.2 3
5mA
mA at 8.0 MHz
at 8.0 MHz 1, 2
1, 2
ICC1 Standby Current
(HALT mode) 2.0
3.6 0.5
0.8 1.6
2.0 mA
mA VIN = 0 V, VCC at
8.0 MHz
Same as above
1, 2, 6
1, 2, 6
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Electrical Characteristics
83
ICC2 Standby Current
(STOP mode) 2.0
3.6
2.0
3.6
1.5
2.1
4.7
7.4
8
10
20
30
A
A
A
A
VIN = 0 V, VCC
WDT is not
Running
Same as above
VIN = 0 V, VCC
WDT is Running
Same as above
3
3
3
3
ILV Standby Current
(Low Voltage) 1.0 6 A Measured at 1.3 V 4
VBO VCC Low Voltage
Protection 1.8 2.0 V 8 MHz maximum
Ext. CLK Freq.
VLVD Vcc Low Voltage
Detection 2.4 V
VHVD Vcc High Voltage
Detection 2.7 V
Notes:
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (minimum 0.1 F), physically close to VDD and GND if
operating voltage fluctuations are anticipated, such as those resulting from driving an Infrared LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 °C.
Table 19.DC Characteristics (Continued)
TA= 0 °C to +70 °C
Symbol Parameter VCC Minimum Typ(7)
Maximum Units Conditions Notes
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Electrical Characteristics
84
AC Characteristics
Figure 56 on page 84 and Table 20 on page 85 describe the AC characteristics.
Figure 56. AC Timing Diagram
Clock
Stop
Mode
Recovery
Source
Clock
Setup
1
22
3
3
TIN
7
45
6
7
IRQN
89
11
10
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Electrical Characteristics
85
Table 20.AC Characteristics
TA=0 °C to +70 °C
8.0 MHz
No Symbol Parameter VCC Minimum Maximum Units Notes
Watchdog
Timer
Mode
Register
(D1, D0)
1 TpC Input Clock Period 2.0–3.6 121 DC ns 1
2 TrC,TfC Clock Input Rise and
Fall Times 2.0–3.6 25 ns 1
3 TwC Input Clock Width 2.0–3.6 37 ns 1
4 TwTinL Timer Input
Low Width 2.0
3.6 100
70 ns 1
5 TwTinH Timer Input High
Width 2.0–3.6 3TpC 1
6 TpTin Timer Input Period 2.0–3.6 8TpC 1
7 TrT in,TfT in T imer Input Rise and
Fall Timers 2.0–3.6 100 ns 1
8 TwIL Interrupt Request
Low Time 2.0
3.6 100
70 ns 1, 2
9 TwIH Interrupt Request
Input High Time 2.0–3.6 10TpC 1, 2
10 Twsm Stop Mode Recovery
Width Spec 2.0–3.6 12
10TpC
ns 3
4
11 Tost Oscillator
Start-Up Time 2.0–3.6 5TpC 4
12 Twdt Watchdog Timer
Delay Time 2.0–3.6
2.0–3.6
2.0–3.6
2.0–3.6
10
20
40
160
ms
ms
ms
ms
0, 0
0, 1
1, 0
1, 1
13 TPOR Power-On Reset 2.0–3.6 2.5 10 ms
Notes:
1.Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2.Interrupt request through Port 3 (P33–P31).
3.SMR – D5 = 1.
4.SMR – D5 = 0.
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Packaging
86
Packaging
Package information for all versions of Crimzon ZLR32300 is displayed in
Figure 57 through Figure 63 on page 91.
Figure 57.20-Pin PDIP Package Diagram
Figure 58.20-Pin SOIC Package Diagram
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Packaging
87
Figure 59. 20-Pin SSOP Package Diagram
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Packaging
88
Figure 60. 28-Pin SOIC Package Diagram
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Packaging
89
Figure 61. 28-Pin PDIP Package Diagram
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Packaging
90
Figure 62. 28-Pin SSOP Package Diagram
SYMBOL
A
A1
B
C
A2
e
MILLIMETER INCH
MIN MAX MIN MAX
1.73
0.05
1.68
0.25
5.20
0.65 TYP
0.09
10.07
7.65
0.63
1.86
0.0256 TYP
0.13
10.20
1.73
7.80
5.30
1.99
0.21
1.78
0.75
0.068
0.002
0.066
0.010
0.205
0.004
0.397
0.301
0.025
0.073
0.005
0.068
0.209
0.006
0.402
0.307
0.030
0.078
0.008
0.070
0.015
0.212
0.008
0.407
0.311
0.037
0.38
0.20
10.33
5.38
7.90
0.95
NOM NOM
D
E
H
L
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES .
H
C
DETAIL A
E
D
28 15
114
SEATING PLANE
A2
e
A
Q1
A1
B
L
0 - 8
DETAIL 'A'
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Packaging
91
Figure 63. 48-Pin SSOP Package Design
Contact Maxim® on the actual bonding diagram and coordinate
for chip-on-board assembly.
CONTROLLING DIMENSIONS : MM
LEADS ARE COPLANAR WITHIN .004 INCH
D
E H
1
A2 A
e
SEATING PLANE
b
48 25
c
Detail A
Detail A
0-8˚
L
1 24
Note:
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Ordering Information
92
Ordering Information
The following table provides part number, description, and memory size of Crim-
zon ZLR32300.
Memory Size Part Number Description
32 K ZLR32300H4832G 48-pin SSOP 32 K ROM
ZLR32300H2832G 28-pin SSOP 32 K ROM
ZLR32300P2832G 28-pin PDIP 32 K ROM
ZLR32300S2832G 28-pin SOIC 32 K ROM
ZLR32300H2032G 20-pin SSOP 32 K ROM
ZLR32300P2032G 20-pin PDIP 32 K ROM
ZLR32300S2032G 20-pin SOIC 32 K ROM
24 K ZLR32300H4824G 48-pin SSOP 24 K ROM
ZLR32300H2824G 28-pin SSOP 24 K ROM
ZLR32300P2824G 28-pin PDIP 24 K ROM
ZLR32300S2824G 28-pin SOIC 24 K ROM
ZLR32300H2024G 20-pin SSOP 24 K ROM
ZLR32300P2024G 20-pin PDIP 24 K ROM
ZLR32300S2024G 20-pin SOIC 24 K ROM
16 K ZLR32300H4816G 48-pin SSOP 16 K ROM
8 K ZLR32300H4808G 48-pin SSOP 8 K ROM
4 K ZLR32300H4804G 48-pin SSOP 4 K ROM
Development Tools
ZLP128ICE01ZEMG* In-Circuit Emulator
Note: *ZLP128ICE01ZEMG has been replaced by an improv ed
version, ZCRMZNICE01ZEMG.
ZLP323ICE01ZACG 40-PDIP/48-SSOP Accessory Kit
ZCRMZNICE01ZEMG Crimzon In-Circuit Emulator
ZCRMZN00100KITG Crimzon In-Circuit Emulator
Developm ent Kit
ZCRMZNICE01ZACG 20-Pin Accessory Kit
ZCRMZNICE02ZACG 40/48-Pin Accessory Kit
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Ordering Information
93
For fast results, contact your local Maxim sales office for assistance in ordering
the part desired.
Part Number Description
Maxim part numbers consist of a number of components, as displayed in
Figure 64. The example part number ZLR32300H2832G is a Crimzon masked
ROM product in a 28-pin SSOP package, with 32 KB of ROM and built with lead-
free solder.
Figure 64. Part Number Description Example
Note:
Contact www.maxim-ic.com for the die form.
Z LR32300H 2832G
Environmental Flow
G = Lead Free
Memory Size
32 = 32 KB
24 = 24 KB
16 = 16 KB
8 = 8 KB
4 = 4 KB
Number of Pins in Package
48 = 48 Pins
40 = 40 Pins
28 = 28 Pins
20 = 20 Pins
Package Type
H = SSOP
P = PDIP
S = SOIC
Product Number
32300
Product Line
Crimzon ROM
Maxim Product Prefix
Memory Size Part Number Description
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Index
94
Index
Numerics
16-bit counter/timer circuits 41
20-pin DIP package diagram 86
20-pin SSOP package diagram 87
28-pin DIP package diagram 89
28-pin SOICpackage diagram 88
28-pin SSOP package diagram 90
48-pin SSOP package diagram 91
8-bit counter/timer circuits 37
A
absolute maximum ratings 80
AC characteristics 84
timing diagram 84
address spaces, basic 1
architecture 1
expanded register file 23
B
basic address spaces 1
block diagram, ZLP32300 functional 4
C
capacitance 81
characteristics
AC 84
DC 82
clock 48
comparator inputs/outputs 19
configuration
port 0 13
port 1 14
port 2 15
port 3 16
port 3 counter/timer 18
counter/timer
16-bit circuits 41
8-bit circuits 37
brown-out voltage/standby 60
clock 48
demodulation mode count capture flowchart 39
demodulation mode flowchart 40
EPROM selectable options 60
glitch filter circuitry 35
halt instruction 49
input circuit 35
interrupt block diagram 46
interrupt types, sources and vectors 47
oscillator configuration 48
output circuit 44
ping-pong mode 43
port configuration register 50
resets and WDT 59
SCLK circuit 52
stop instruction 49
stop mode recovery register 52
stop mode recovery register 2 56
stop mode recovery source 54
T16 demodulation mode 42
T16 transmit mode 41
T16_OUT in modulo-N mode 42
T16_OUT in single-pass mode 42
T8 demodulation mode 39
T8 transmit mode 35
T8_OUT in modulo-N mode 38
T8_OUT in single-pass mode 38
transmit mode flowchart 36
voltage detection and flags 61
watchdog timer mode register 57
watchdog timer time select 58
CTR(D)01h T8 and T16 Common Functions 30
Customer Feedback Form 98
D
DC characteristics 82
demodulation mode
count capture flowchart 39
flowchart 40
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Index
95
T16 42
T8 39
description
pin 6
E
EPROM
selectable options 60
expanded register file 21
expanded register file architecture 23
expanded register file control registers 68
flag 78
interrupt mask register 77
interrupt priority register 76
interrupt request register 77
port 0 and 1 mode register 75
port 2 configuration register 73
port 3 mode register 74
port configuration register 73
register pointer 78
stack pointer high register 79
stack pointer low register 79
stop-mode recovery register 70
stop-mode recovery register 2 71
T16 control register 66
T8 and T16 common con trol functions register
65
T8/T16 control register 67
TC8 control register 62
watch-dog timer register 72
F
features
standby modes 2
functional description
counter/timer functional blocks 35
CTR(D)01h register 30
CTR0(D)00h register 28
CTR2(D)02h register 32
CTR3(D)03h register 34
expanded register file 21
expanded register file architecture 23
HI16(D)09h register 27
HI8(D)0Bh register 26
L08(D)0Ah register 27
L0I6(D)08h register 27
program memory map 21
RAM 20
register description 60
register file 25
register pointer 24
register pointer detail 26
SMR2(F)0D1h register 35
stack 26
TC16H(D)07h register 27
TC16L(D)06h register 27
TC8H(D)05h register 28
TC8L(D)04h register 28
G
glitch filter circuitry 35
H
halt instruction, counter/timer 49
I
input circuit 35
interrupt block diagram, counter/timer 46
interrupt types, sources and vectors 47
L
low-voltage detection register 60
M
memory, program 20
modulo-N mode
T16_OUT 42
T8_OUT 38
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Index
96
O
oscillator configuration 48
output circuit, counter/timer 44
P
package information
20-pin DIP package diagram 86
20-pin SSOP package diagram 87
28-pin DIP package diagram 89
28-pin SOIC package diagram 88
28-pin SSOP package diagram 90
48-pin SSOP package diagram 91
pin configuration
20-pin DIP/SOIC/SSOP 6
28-pin DIP/SOIC/SSOP 7
40- and 48-pin 8
48-pin SSOP 8
pin functions
port 0 (P07 - P00) 12
port 0 (P17 - P10) 13
port 0 configuratio n 13
port 1 configuratio n 14
port 2 (P27 - P20) 14
port 2 (P37 - P30) 15
port 2 configuratio n 15
port 3 configuratio n 16
port 3 counter/timer configuration 18
reset) 19
XTAL1 (time-based input 11
XTAL2 (time-based output) 11
ping-pong mo de 43
port 0 configuratio n 13
port 0 pin function 12
port 1 configuratio n 14
port 1 pin function 13
port 2 configuratio n 15
port 2 pin function 14
port 3 configuratio n 16
port 3 pin function 15
port 3counter/timer configuration 18
port configuration register 50
power connections 2
power supply 6
program memory 20
map 21
R
ratings, absolute maximum 80
register 56
CTR(D)01h 30
CTR0(D)00h 28
CTR2(D)02h 32
CTR3(D)03h 34
flag 78
HI16(D)09h 27
HI8(D)0Bh 26
interrupt priority 76
interrupt request 77
interruptmask 77
L016(D)08h 27
L08(D)0Ah 27
LVD(D)0Ch 60
pointer 78
port 0 and 1 75
port 2 configuration 73
port 3 mode 74
port configuration 50, 73
SMR2(F)0Dh 35
stack pointer high 79
stack pointer low 79
stop mode recovery 52
stop mode recovery 2 56
stop-mode recovery 70
stop-mode recovery 2 71
T16 control 66
T8 and T16 common control functions 65
T8/T16 control 67
TC16H(D)07h 27
TC16L(D)06h 27
TC8 control 62
TC8H(D)05h 28
TC8L(D)04h 28
voltage detection 68
watch-dog timer 72
register description
Counter/Timer2 LS-Byte Hold 27
Crimzon® ZLR32300
Product Specification
19-4623; Rev 0; 5/09 Index
97
Counter/Timer2 MS-Byte Hold 27
Counter/Timer8 Control 28
Counter/Timer8 High Hold 28
Counter/Timer8 Low Hold 28
CTR2 Counter/Timer 16 Control 32
CTR3 T8/T16 Control 34
Stop Mode Recovery2 35
T16_Capture_LO 27
T8 and T16 Common functions 30
T8_Capture_HI 26
T8_Capture_LO 27
register file 25
expanded 21
register pointer 24
detail 26
reset pin function 19
resets and WDT 59
S
SCLK circuit 52
single-pass mode
T16_OUT 42
T8_OUT 38
stack 26
standard test conditions 81
standby modes 2
stop instruction, counter/timer 49
stop mode recovery
2 register 56
source 54
stop mode recovery 2 56
stop mode recovery register 52
T
T16 transmit mode 41
T16_Capture_HI 27
T8 transmit mode 35
T8_Capture_HI 26
test conditions, standard 81
test load diagram 81
timing diagram, AC 84
transmit mode flowchart 36
V
VCC 6
voltage
brown-out/standby 60
detection and flags 61
voltage detection register 68
W
watchdog timer
mode register watchdog timer mode register 57
time select 58
X
XTAL1 6
XTAL1 pin function 11
XTAL2 6
XTAL2 pin function 11
19-4623; Rev 0; 5/09 Customer Support
Crimzon® ZLR32300
Product Specification
98
Customer Support
For any comments, detail technical questions, o r reporting problems, please v isit Maxim’s
Technical Support at https://support.maxim-ic.com/micro.