(OVATE INNOVATION and EXCELLENCE ADC-HS12B 12-Bit A/D Converter With Sample-Hold FEATURES * 12-Bit resolution Internal sample and hold * 6 Microseconds acquisition time * 9 Microseconds conversion time * Programmable input ranges Parallel output GENERAL DESCRIPTION The ADC-HS12B is a high performance 12-bit hybrid A/D converter with a self-contained sample-hold. It is specifically ess ices ow hes re hake designed for systems applications where the sampie-hold is MECHANICAL DIMENSIONS an integral part of the conversion process. The internal INCHES (mm) sample-hold has a 6 microseconds acquisition time for a full eee | iid 10V dc input change; the A/D converter has a fast 9 0035/0015 + F ogee microseconds conversion time. Five input voltage ranges (0,889/0,381) 7 PIN #1 INDEX are programmable by external pin connection; 0 to +5V, 0 oS to+t0V, +2.5V, +5V, and +10V. Input impedance to the 1 =e sample-hold is 100 megohms. Output coding is Qogioore J =e complementary binary for unipolar operation and = 172/169 mplimentary offset binary for bi ion. L=E |] ,9-045/0.035 (43,69/42,92) complimentary offse y polar operation 0.100 BSC J cma || (1.149/0,889) (2,54) = . . . . =m The ADC-HS12B uses a fast 12-bit monolithic DAC which 4 Sake includes a precision zener reference source. The circuit also 0110.09 P| contains a fast monolithic 12-bit successive approximation (2,80/2,28) lL tttos register, a clock and a monolithic sample-hoid. 0.200/0,175 L_ (28,20/27,43) (5,08/4,44) r SEATING PLANE 0.015/0.009 (0,381/0,228) |. 0.920/0.890 | (23,37/22,60) cy CONTROL OFSET OUT V de" ~15V de +5V dc H . +15V de ~ c+ Pp TPUT @ @@ Q INPUT/OUTPU CONNECTIONS 6.3K PRECISION, ANALOG (30) SAMPLE REFERENCE PIN FUNCTION PIN FUNCTION 1 BIT 12 QUT (LSB) 7 cy SH +} 2 BIT 11 OUT 18 REF OUT out GAIN a BIT 10 OUT 19 OO NOT CONNECT [2 ADJ. _ 12 BIT . 4 BIT 9 OUT 20 E.0.C. {STATUS) D/A CONVERTER 1) DIGITAL 5S BIT 8 OUT ay START CONVERT COMPARATOR T Ly com 6 | eir7ouT 22 COMPAR INPUT COMPAR l l 1 l I I l I ! I 7 BIT 6 OUT 23 BIPOLAR OFFSET @ IN | ___ @ sete 8 BIT 5 OUT 24 10V RANGE tov ASE RN aN fa 2 95... a BIT 4 OUT 25 20V RANGE RANGE REGISTER ) 10 BIT 3 OUT 26 ANALOG COM W BIT 2 OUT 27 GAIN ADJ. RANGE @ | 12 BIT 1 OUT (MSB) 28 + 15V POWER anaLoa@9} 13 DO NOT CONNECT 29 S.H. OUTPUT COM io 14 SHORT CYCLE 0 ANALOG IN WD ADOWDHDIOSOO OMI Od 5 DIGITAL COM at - 15V POWER & 721119 9 6 7 6 5 43 24 ze, 16 +5V POWER 32 SAMPLE CONTROL 33 3 se BIT NO mse, H&S no PARALLEL DATA OUTADC-HS12B S GYNEL ABSOLUTE MAXIMUM RATINGS Positive Supply, pin28 ........ Negative Supply, pin31........ Logic Supply Voltage, pin 16.... Digital Input Voltage, Pins 14, 21,32.............. Analog Input Voltage, pin 30 .... +5.5V + 15V PHYSICAL/ENVIRONMENTAL FUNCTIONAL SPECIFICATIONS Typical at 25C, +15V and +5V supplies unless otherwise noted. Operating Temp. Range, Case ...0C to 70C (BMC) .-55C to +125C (BMM, BMM-QL) INPUTS Analog Input Ranges, unipolar . . Analog Input Ranges, bipolar ... Input impedance............. Input Bias Current............ Start Conversion ............. Sample Control input .......... Oto +5V, Oto +10V +2.5V, +5V, +10V 100 megohms 50 nA typical, 200 nA max. 2V min. to +5.5V max. positive pulse with 100 nsec. duration min. Rise and fall times <30 nsec. Logic high to low transition resets converter and initiates next conversion. Loading: 2 TTL loads Logic high = hold Logic low = sample Loading: 1 TTL load Storage Temperature Range ..... -65C to +150C Package Type . 32 pin ceramic IMB eae . 0.010 x 0.018 inch Kovar Weight 0.0.0.0... . cece eee 0.5 ounces (14 grams) FOOTNOTES: 1, For sampie-hold input 2. All digital outputs can drive 2 TTL loads 3. For 1000 pF external hold capacitor OUTPUTS? Parallel Output Data........... Coding, unipolar.............. Coding, bipolar............... End of Conversion (status) ..... 12 parallel tines of data held until next conversion command. Vout (0) s +0.4V Vout (1")2 +2.4V Complementary Binary Complementary Offset Binary Conversion status signal. Output is logic high during reset and conversion and low when conversion is complete. SAMPLE-HOLD PERFORMANCE? input Offset Drift.............. Acquisition Time, 10V to 0.01% . Bandwidth ..........0..06055 Aperture Delay Time .......... Aperture Uncertainty Time ..... Sample to Hold Error Hold Mode Droop ..... Hold Mode Feedthrough ....... 25 uV/C 6 usec. 1M 2.5 mV max. 200 nV/ysec. max. 0.01% max. CONVERTER PERFORMANCE Resolution .............0006. Nonlinearity .............0005 Differential Nonlinearity ........ Temp. Coefficient of Gain ...... Temp. Coefficient of Zero, unipolar ..........-- ceca Temp. Coefficient of Oftset, Fee cece ences 12 bits (1 part in 4096) + % LSB max. +% LSB max. +20 ppm/C max. +5 ppm/C of FSR max. +10 ppm/C of FSR max. Differential Nonlinearity OMPCO..... cece eee +2 ppm/C of FSR Missing Codes ..............-. None over oper. temp. range Conversion Time ............- 9 usec. max. Power Supply Rejection........ 0.004%/% max. POWER REQUIREMENTS Power Suppy Voitage.......... +15V de +0.5V at 20 mA ~15V de +0.5V at 25 mA +5V de +0.25V at 85 mA TECHNICAL NOTES 1. It is recommended that the +15V power input pins both be bypassed to ground with a 0.01 uF ceramic capacitor in par- allel with a 1 F electrolytic capacitor and the +5V power in- put pin be bypassed to ground with a 1 uF electrolytic capac- itor as shown in the connection diagrams. In addition, pin 27 should be bypassed to ground with a 0.01 uF ceramic ca- pacitor. These precautions will assure noise free operation of the converter. 2. Digital Common (pin 15) and Analog Common (pin 26) are not connected together internally, and therefore must be connected as directly as possible externally. It is recom- mended that a ground plane be run underneath the case be- tween the two commons. Analog ground and +15V power ground should be run to pin 26 whereas digital ground and +5V dc ground should be run to pin 15. 3. External adjustment of zero or offset and gain are provided for by trimming potentiometers connected as shown in the connection diagrams. The potentiometer values can be be- tween 10K and 100K ohms and should be 100 ppm C, cer- met types. The adjustment range is +0.5% of FSR for zero or offset and +0.3% for gain. The trimming pots should be located as close as possible to the converter to avoid noise pickup. Calibration of the ADC-HS12B is performed with the sample-hold connected and operating dynamically. This re- sults in adjusting out the sample-hoid errors along with the A/D converter. For slow throughput applications it is recom- mended that a 0.01 pF hold capacitor be used for best accu- racy. With this value the acquisition time becomes 25 micro- seconds and the external timing must be adjusted accordingly. 4. The recommended timing shown in the Timing Diagram ai- lows 6 microseconds for the sample-hold acquisition and then 1 microsecond after the sample-hold goes into the hold mode to allow for output settling before the A/D begins its conversion cycle. 5. Short cycled operation results in shorter conversion times where the conversion can be truncated to less than 12 bits. This is done by connecting pin 14 to the output bit following the last bit desired. For example, for an 8-bit conversion, pin 14 is connected to bit 9 output. Maximum conversion times are given for short-cycled conversions in the Table. 6. Note that output coding is complementary coding. For uni- polar operation it is complementary binary and for bipolar operation it is complementary offset binary. In cases where bipolar coding of offset binary is required, this can be achieved by inverting the analog input to the converter (using an operational amplifier connected for gain of -1.0000). TheSy OVAVEL ADC-HS12B converter is then calibrated so that - FS analog input gives CONVERT (Pin 21). The rate of the external clock must be an output code of 0000 0000 0000, and +FS-1 LSB gives lower than the rate of the internal clock. The pulse width of 11411114 14191. the external clock should be between 100 nanoseconds and 300 nanoseconds. Each N bit conversion cycle requires a pulse train of N + 1 clock pulses for completion, .g., an 8-bit conversion requires 9 clock pulses for completion. A should be taken not to restrict air circulation in the vicinity of continuous pulse train may be used for consecutive conver- sions, resulting in an N bit conversion every N + 1 pulses, or the converter. . the E.0.C. output may be used to gate a continuous pulse 8. These converters can be operated with an external clock. To train for single conversions accomplish this, a negative pulse train is applied to START . 7. These converters dissipate 1.81 watts maximum of power. The case to ambient thermal resistance is approximately 25C per watt. For ambient temperatures above 50C, care TIMING DIAGRAM FOR ADC-HS12B TRIGGER {]- nsec. MIN SAMPLE ____ = CONTROL 8 usec START CONVERT j7 1 asec 7 +| he 60 nsec HM -.- EOC ) PARALLEL DATA (STATUS) 4 BBE MAK NOW VALID 7 : \ \ \ : : : ae 40 nsec. | ' ' ' 1 t ' i , ' 1 i 0 I ' I 1 1 1 T er 1 ' 1 \ 1 ' OUT (MsB) ' yoo ! i i ' ! ! | ; a a Te eee eee ' ' wow epee ee ee eet eee. are 1 T ' i i i 1 7 i 1 : 9 1 1 ' 1 OuT ) ' { I 1 1 ' I 1 F 1 T T T T T fi r Hi A a I - L 0 BIT3 ( ' 1 \ ' 1 : ( . out i ! 1 oe et i Moo. ' 1 1 7 fl V y Py poo Hl i ( ' 1 , t 1 ) 1 | 1 te eo arnt i 7 i ; ; 1 , . oo - OUT (LSB) 5 1 ' ' I \ ! ) Hood bbe bet e--! L 1 NOTE: TRIGGER, SAMPLE CONTROL. AND START CONVERT PULSES MUST BE EXTEANALLY GENERATED UNIPOLAR OPERATION, 0 TO + 10V BIPOLAR OPERATION, +5V -15V + 15V + -18V +15V0 0 +5 t 1aF 4 a QO | fi "I 3 a + +18 +15V 0.08 fi e 4 to n r a | ANALOG IN ANALOG IN (0 TO +10V) o4 30 153} o- (+54) o~} 30 ANALOG = 1,5 MEG soK 1 GND 26 22 0 "eset ANALOG o- 26 29) ADC-HS12B ADJ 29 ADC-HS128 2.8 MEG +18V 2.8 MEG 2a 27 +} 2 SOK 24 a7b 50K 23 GAIN GAIN 0.01 aF AD 1.5 MEG | 23 0.01 pF ADJ = 50K 4 22 = OFFSET ADJUST 17 32a 7 r bod aw LoL | SAMPLE 6 POLYSTYRENE OR - 15V Cy" + t cay TEFLON TY hoo pe LL SAMPLE START tho ors Sa CONTROL CONVERT $0000 pF [T CONTROL CONVERT = POLYSTYRENE OR TEFLON TYPEADC-HS12B (OVANEL CODING TABLES UNIPOLAR OPERATION BIPOLAR OPERATION COMP. COMP. INPUT RANGE BINARY CODING INPUT VOLTAGE RANGE OFFSET BINARY 0TO +10V 0TO +5V MSB LSB +10V +5V +2.5V | MSB LSB +9.9976V +4.9988V 0000 0000 0000 +9.9951V | +4.9976V | +2.4988V | 0000 0000 0000 +8.7500 + 4.3750 0001 1111 1111 +7.5000 | +3.7500 | +1.8750 | oot 1111 1111 +7.5000 + 3.7500 0011 1111 1114 +5.0000 | +2.5000 | +1.2500 | 0011 1111 1111 +5.0000 + 2.5000 O14 4144 11414 0.0000 0.0000 0.0000 | O111 1141 1111 +2.5000 + 1.2500 4011 1111 1111 -5.0000 |-25000 | -1.2500 | 1011 1111 1111 + 1.2500 + 0.6250 4101 1111 1114 -7.5000 | -3.7500 | -1.8750 | 1101 1111 1111 +0.0024 +0.0012 1144 1111 1110 -9.9951 |-4.9976 | -2.4988 | 1111 1111 1110 0.0000 0.0000 4444 4444 4114 10.0000 | -5.0000 | -2.5000 | 1111 1111 1111 CALIBRATION PROCEDURE CALIBRATION TABLE 1. Connect the ADC-HS12B as shown in one of the connection diagrams. The sample-hold and A/D converter should be UNIPOLAR RANGE ADJUST. INPUT VOLTAGE timed as shown in the timing diagram. The trigger pulse Oto +5V ZERO +0.6 mV should be applied at a rate of 70 kHz or less and should be GAIN +4.9982V 100 nanoseconds minimum width. Oto +10V ZERO +1.2 mV 2. Zero and Offset Adjustments GAIN +9.9963V Apply a precision voltage reference source between the BIPOLAR RANGE selected analog input and ground. Adjust the output of the reference source to the value shown in the Calibration Table 2.5V EAN To aceoy for the unipolar zero adjustment (zero + 1% LSB) or the +e. bipolar offset adjustment (-FS+% LSB). Adjust the trim- +5V OFFSET ~ 4.9988V ming potentiometer so that the output code flickers equally GAIN + 4.9963V between 1111 1111 1111 and 1111 1111 1110. +10V OFFSET 9.9976V 3. Full Scale Adjustment GAIN +9.9927V Change the output of the precision voltage reference source to the value shown in the Calibration Table for the unipolar or bipolar gain adjustment (+ FS-1'% LSB). Adjust the gain trimming potentiometer so that the output code flickers equally between 0000 0000 0001 and 0000 0000 0000. PIN 14 CONNECTION FOR SHORT CYCLE OPERATION SHORT CYCLE OPERATION RES. (BITS) | PIN 14TO | CONV. TIME 1 ON 10 oars 4 6) 7 3) Go) Gt) G2 3 PINa | 20 Dee sa 4 PIN 8 26 FOR CONVERSION TO N BITS S PINT | 33 eeecueuene 6 PIN 6 4 0 TERMINAL, PIN 14 7 PIN 5 46 8 PIN 4 53 9 PIN 3 60 10 PIN 2 66 1 PIN 1 73 12 PIN 16 9.0 INPUT CONNECTIONS INPUT VOLTAGE CONNECT THESE PINS RANGE TOGETHER ORDERING INFORMATION Oto +5V 29 & 24 22 & 25 23 & 26 Oto +10V 29 & 24 _ 23 & 26 MODEL TEMP. RANGE +2.5V 29 & 24 22 & 25 23 & 22 ADC-HS12BMC 0t0 470C +5V 29 & 24 = 23 & 22 ADC-HS12BMM -55 to +125 C +10V 29 & 25 _ 23 & 22 ADC-HS12BMM-QL -55 to +125 C DATEL makes no representation that the use of thasa products in the circuits described herein, or use of other technical information contained herein, will not infringe upon existing or future patent rights nor do the descriptions con- tained herein imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications subject to change without notice. DVNIEL For Applications Assistance, dial 1-800-233-2765, 8:30 a.m. to 4:30 p.m. EST DATEL, Inc. 11 CABOT BOULEVARD, MANSFIELD, MA 02048-1194 TEL. (508) 339-3000 / FAX (508) 339-6356 INTERNATIONAL: DATEL (UNITED KINGDOM) Basingstoke Tel. (256) 880-444 * DATEL (FRANCE) Tel. (1) 3460.0101 DATEL (GERMANY) Tel. (89) 54 4334-0 DATEL (JAPAN) Tokyo Tel. (3) 3779-1031 * Osaka Tel. (6) 354-2025 Printed in U.S.A. Copyright 1993 DATEL, Inc. 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