1
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Single 12-Bit 250Msps/
210Msps/170Msps ADCs
n Communications
n Cellular Basestations
n Software Defined Radios
n Medical Imaging
n High Definition Video
n Testing and Measurement Instruments
n 68.5dB SNR
n 90dB SFDR
n Low Power: 347mW/333mW/306mW Total
n Single 1.8V Supply
n DDR LVDS Outputs
n Easy-to-Drive 1.5VP-P Input Range
n 1.25GHz Full Power Bandwidth S/H
n Optional Clock Duty Cycle Stabilizer
n Low Power Sleep and Nap Modes
n Serial SPI Port for Configuration
n Pin-Compatible 14-Bit Versions
n 40-Lead (6mm × 6mm) QFN Package
The LT C
®
2152-12/LTC2151-12/LTC2150-12 are a family
of 250Msps/210Msps/170Msps 12-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals. They are perfect for demanding communications
applications with AC performance that includes 68.5dB
SNR and 90dB spurious free dynamic range (SFDR). The
1.25GHz input bandwidth allows the ADC to undersample
high input frequencies with good performance. The latency
is only six clock cycles.
DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.54LSBRMS.
The digital outputs are double-data rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L, LT, LT C , LTM , Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2152-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 250Msps
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 TA01b
100 120
–20
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC
CLOCK/DUTY
CYCLE
CONTROL
D10_11
•
•
•
D0_1
CLOCK
ANALOG
INPUT
21521012 TA01a
DDR
LVDS
VDD
GND
OVDD
OGND
LTC2152-12/
LTC2151-12/LTC2150-12
2
21521012fa
For more information www.linear.com/LTC2152-12
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD, OVDD ................................................ –0.3V to 2V
Analog Input Voltage
AIN+, AIN–, PAR/SER,
SENSE (Note 3) ........................ –0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC– (Note 3) ................ –0.3V to (VDD + 0.3V)
CS, SDI, SCK (Note 4) ........................... –0.3V to 3.9V
SDO (Note 4) ............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2152C, LTC2151C, LTC2150C ............. 0°C to 70°C
LTC2152I, LTC2151I, LTC2150I ............–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
PIN CONFIGURATION
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
GND
41
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
VDD
VDD
GND
AIN+
AIN–
GND
SENSE
VREF
VCM
GND
OVDD
D6_7+
D6_7–
CLKOUT+
CLKOUT–
D4_5+
D4_5–
D2_3+
D2_3–
OGND
PAR/SER
CS
SCK
SDI
SDO
GND
D10_11+
D10_11–
D8_9+
D8_9–
ENC+
ENC–
GND
OF–
OF+
NC
NC
D0_1–
D0_1+
OVDD
21
30
10
1
TJMAX = 150°C, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2152CUJ-12#PBF LTC2152CUJ-12#TRPBF LTC2152UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2152IUJ-12#PBF LTC2152IUJ-12#TRPBF LTC2152UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LTC2151CUJ-12#PBF LTC2151CUJ-12#TRPBF LTC2151UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2151IUJ-12#PBF LTC2151IUJ-12#TRPBF LTC2151UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LTC2150CUJ-12#PBF LTC2150CUJ-12#TRPBF LTC2150UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2150IUJ-12#PBF LTC2150IUJ-12#TRPBF LTC2150UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
LTC2152-12 LTC2151-12 LTC2150-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l12 12 12 Bits
Integral Linearity Error Differential Analog Input (Note 6) l–1.2 ±0.26 1.2 –1.2 ±0.30 1.2 –1.2 ±0.30 1.2 LSB
Differential Linearity Error Differential Analog Input l–0.6 ±0.16 0.6 –0.6 ±0.16 0.6 –0.6 ±0.16 0.6 LSB
Offset Error (Note 7) l–13 ±5 13 –13 ±5 13 –13 ±5 13 mV
Gain Error External Reference l–4 ±1 3 –4 ±1 3 –4 ±1 3 %FS
Offset Drift ±20 ±20 ±20 µV/°C
Full-Scale Drift Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Transition Noise 0.54 0.54 0.54 LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1.5 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) lVCM – 20mV VCM VCM + 20mV V
VSENSE External Reference Mode External Reference Mode l1.200 1.250 1.300 V
IIN1 Analog Input Leakage Current 0 < AIN+, AIN– < VDD, No Encode l–1 1 µA
IIN2 SENSE Input Leakage Current 1.2V < SENSE < 1.3V l–1 1 µA
IIN3 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–1 1 µA
tAP Sample-and-Hold Acquisition Delay Time 1 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS
CMRR Analog Input Common Mode Rejection Ratio 75 dB
BW-3B Full-Power Bandwidth 1250 MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2152-12 LTC2151-12 LTC2150-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 15MHz Input
70MHz Input
140MHz Input
l
67.1
68.5
68.4
68.0
67.1
68.5
68.3
67.9
67.3
68.5
68.3
67.8
dBFS
dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic
15MHz Input
70MHz Input
140MHz Input
l
72
90.6
88
80
74
90.1
89
81
76
90
88
80
dBFS
dBFS
dBFS
Spurious Free Dynamic Range
4th Harmonic or Higher
15MHz Input
70MHz Input
140MHz Input
l
81
98
95
85
82
98
95
85
83
98
95
84
dBFS
dBFS
dBFS
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
15MHz Input
70MHz Input
140MHz Input
l
66.5
68.5
68.4
67.7
66.6
68.4
68.3
67.7
66.7
68.4
68.3
67.7
dBFS
dBFS
dBFS
Crosstalk Crosstalk Between Channels Up to 315MHz Input –95 –95 –95 dB
LTC2152-12/
LTC2151-12/LTC2150-12
4
21521012fa
For more information www.linear.com/LTC2152-12
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.439 •
VDD – 18mV
0.439 •
VDD
0.439 •
VDD + 18mV
V
VCM Output Temperature Drift ±37 ppm/°C
VCM Output Resistance –1mA < IOUT < 1mA 4 Ω
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±30 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7 Ω
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC– )
VID Differential Input Voltage (Note 8) l0.2 1 1.9 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 8)
l
1.1
1.2
1.5
V
V
VIN Input Voltage Range ENC+, ENC– to GND l0.2 1.9 V
RIN Input Resistance (See Figure 2) 10 kΩ
CIN Input Capacitance (Note 8) 2 pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
IIN Input Current VIN = 0V to 1.8V l–10 10 µA
CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
COUT Output Capacitance (Note 8) 4 pF
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2152-12 LTC2151-12 LTC2150-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
VDD Analog Supply Voltage (Note 9) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage LVDS Mode (Note 9) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IVDD Analog Supply Current l166 185 158 175 145 159 mA
IOVDD Digital Supply Current 1.75mA LVDS Mode
3.5mA LVDS Mode
l
27
45
32
50
27
44
31
50
25
43
30
48
mA
mA
PDISS Power Dissipation 1.75mA LVDS Mode
3.5mA LVDS Mode
l
347
380
391
423
333
364
371
405
306
338
340
373
mW
mW
PNAP Nap Mode Power Clocked at fS(MAX) 105 99 93 mW
PSLEEP Sleep Mode Power Clocked at fS(MAX) <2 <2 <2 mW
5
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
mV
mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
V
V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2152-12 LTC2151-12 LTC2150-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Note 9) l10 250 10 210 10 170 MHz
tLENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
1.9
1.5
2
2
50
50
2.26
1.5
2.38
2.38
50
50
2.79
1.5
2.94
2.94
50
50
ns
ns
tHENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
1.9
1.5
2
2
50
50
2.26
1.5
2.38
2.38
50
50
2.79
1.5
2.94
2.94
50
50
ns
ns
DIGITAL DATA OUTPUTS
LTC215X-12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDENC to Data Delay CL = 5pF l1.7 2 2.3 ns
tCENC to CLKOUT Delay CL = 5pF l1.3 1.6 2 ns
tSKEW DATA to CLKOUT Skew tD – tCl0.3 0.4 0.55 ns
Pipeline Latency 6 6 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode, CSDO = 20pF
Readback Mode RPULLUP = 2k, CSDO = 20pF
40
250
ns
ns
tSCS to SCK Set-Up Time l5 ns
tHSCK to CS Hold Time l5 ns
tDS SDI Set-Up Time l5 ns
tDH SDI Hold Time l5 ns
tDO SCK Falling to SDO Valid Readback Mode RPULLUP = 2k, CSDO = 20pF l125 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V
DD
= OV
DD
= 1.8V, f
SAMPLE
= 250MHz (LTC2152),
210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential
ENC+/ENC– = 2V
P-P
sine wave, input range = 1.5V
P-P
with differential
drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
LTC2152-12/
LTC2151-12/LTC2150-12
6
21521012fa
For more information www.linear.com/LTC2152-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-12: Integral Nonlinearity
(INL)
LTC2152-12: Differential
Nonlinearity (DNL)
LTC2152-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point FFT,
fIN = 70MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point FFT,
fIN = 122MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point FFT,
fIN = 380MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point FFT,
fIN = 420MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point FFT,
fIN = 229MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point FFT,
fIN = 171MHz, –1dBFS, 250Msps
OUTPUT CODE
0
–2.0
–1.5
–1.0
–0.5
INL ERROR (LSB)
0
0.5
2.0
1.5
1.0
4095
21521012 G01
OUTPUT CODE
0
–0.50
–0.25
DNL ERROR (LSB)
0
0.25
0.50
4095
21521012 G02
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G03
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G04
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G05
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G06
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G07
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G08
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G09
100 120
–20
7
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
LTC2152-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 250Msps
LTC2152-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 250Msps
LTC2152-12: Shorted Input
Histogram
LTC2152-12: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2152-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2152-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 250Msps
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-12: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 250Msps
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
215210 G10
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G11
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G12
100 120
–20
OUTPUT CODE
2048
COUNT
12000
16000
20000
21521012 G13
8000
4000
10000
14000
18000
6000
2000
02052 2056
SAMPLE RATE (Msps)
0
IOVDD (mA)
35
45
40
50
200
21521012 G14
30
25
15
20
50 100 150 250
LVDS CURRENT 3.5mA
LVDS CURRENT 1.75mA
SAMPLE RATE (Msps)
0
IVDD (mA)
140
150
160
170
200
21521012 G15
130
120
110 50 100 150 250
AMPLITUDE (dBFS)
–90
0
SFDR (dBFS)
40
20
80
100
120
–70 –50 –40 0
21521012 G16
60
–80 –60 –30 –20 –10
dBFS
dBc
LTC2152-12: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
250Msps
LTC2152-12: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 250Msps
INPUT LEVEL (dBFS)
10
0
SNR (dBc AND dBFS)
20
30
40
50
70
60
–70 –50 –30–60 –40 –20 –10 0
21521012 G17
dBFS
dBc
INPUT FREQUENCY (MHz)
0
SFDR (dBFS)
50
40
60
70
800
21521012 G18
20
30
10
0200 400 500 1000
90
80
600
100 300 900
700
LTC2152-12/
LTC2151-12/LTC2150-12
8
21521012fa
For more information www.linear.com/LTC2152-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-12: Frequency Response
LTC2151-12: Integral Nonlinearity
INL
LTC2151-12: Differential Nonlinearity
DNL
LTC2151-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 210Msps
LTC2151-12: 32K Point FFT,
fIN = 71MHz, –1dBFS, 210Msps
LTC2151-12: 32K Point FFT,
fIN = 101MHz, –1dBFS, 210Msps
LTC2152-12: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
250Msps
LTC2151-12: 32K Point FFT,
fIN = 171MHz, –1dBFS, 210Msps
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
55
50
60
65
800
21521012 G19
45
40 200 400 500 1000
75
70
600
100 300 900
700
INPUT FREQUENCY (MHz)
–5.0
INPUT AMPLITUDE (dBFS)
–4.5
–3.5
–3.0
–2.5
1000
–0.5
21521012 G20
–4.0
100
–2.0
–1.5
–1.0
OUTPUT CODE
0
–2.0
–1.5
–1.0
–0.5
INL ERROR (LSB)
0
0.5
2.0
1.5
1.0
4095
21521012 G21
OUTPUT CODE
0
–0.50
–0.25
DNL ERROR (LSB)
0
0.25
0.50
4095
21521012 G22
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G23
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G24
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G25
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G26
100
–20
9
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
LTC2151-12: 32K Point FFT,
fIN = 227MHz, –1dBFS, 210Msps
LTC2151-12: 32K Point FFT,
fIN = 379MHz, –1dBFS, 210Msps
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G27
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G28
100
–20
LTC2151-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 210Msps
LTC2151-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 210Msps
LTC2151-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 210Msps
LTC2151-12: Shorted Input
Histogram
LTC2151-12: 32K Point FFT,
fIN = 417MHz, –1dBFS, 210Msps
LTC2151-12: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G29
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G30
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 G31
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80 100
21521012 G32
–20
OUTPUT CODE
2044 2048
COUNT
12000
16000
20000
21521012 G33
8000
4000
10000
14000
18000
6000
2000
02052 2056
SAMPLE RATE (Msps)
0
IOVDD (mA)
40
45
50
168
21521012 G34
30
35
20
25
15
42 84 128 210
LVDS CURRENT 3.5mA
LVDS CURRENT 1.75mA
LTC2151-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
SAMPLE RATE (Msps)
0
IVDD (mA)
150
160
168
21521012 G35
140
130
120
110 42 84 126 210
LTC2152-12/
LTC2151-12/LTC2150-12
10
21521012fa
For more information www.linear.com/LTC2152-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2151-12: SNR vs Input Level,
–1dBFS, 1.5V Range, 210Msps LTC2151-12: Frequency Response
LTC2151-12: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 210Msps
LTC2151-12: SFDR vs Input
Level, –1dBFS, 1.5V Range,
210Msps
LTC2151-12: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 210Msps
AMPLITUDE (dBFS)
0
SFDR (dBFS)
40
20
80
100
120
–70 –50 –40 0
21521012 G36
60
–80 –60 –30 –20 –10 10
dBFS
dBc
INPUT LEVEL (dBFS)
10
0
SNR (dBc AND dBFS)
20
30
40
50
70
60
–70 –50 –30–60 –40 –20 –10 0
21521012 G37
dBFS
dBc
INPUT FREQUENCY (MHz)
0
SFDR (dBFS)
50
40
60
70
800
21521012 G38
20
30
10
0200 400 500 1000
90
80
600
100 300 900
700
LTC2150-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 170Msps LTC2150-12: Integral Nonlinearity INL
LTC2150-12: Differential
Nonlinearity DNL
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
55
50
60
65
800
21521012 G39
45
40 200 400 500 1000
75
70
600
100 300 900
700
INPUT FREQUENCY (MHz)
–5.0
INPUT AMPLITUDE (dBFS)
–4.5
–3.5
–3.0
–2.5
1000
–0.5
21521012 G40
–4.0
100
–2.0
–1.5
–1.0
OUTPUT CODE
0
–2.0
–1.5
–1.0
–0.5
INL ERROR (LSB)
0
0.5
2.0
1.5
1.0
4095
21521012 G41
OUTPUT CODE
0
–0.50
–0.25
DNL ERROR (LSB)
0
0.25
0.50
4095
21521012 G42
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G43
80
–20
11
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2150-12: 32K Point FFT,
fIN = 121MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point FFT,
fIN = 176MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point FFT,
fIN = 225MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point FFT,
fIN = 70MHz, –1dBFS, 170Msps
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G44
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G45
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G46
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G47
80
–20
LTC2150-12: 32K Point FFT,
fIN = 380MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point FFT,
fIN = 420MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 170Msps
LTC2150-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 170Msps
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G48
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G49
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G50
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21521012 G51
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 3010 40 50 60 70 80
21521012 G52
–20
LTC2152-12/
LTC2151-12/LTC2150-12
12
21521012fa
For more information www.linear.com/LTC2152-12
LTC2150-12: IOVDD vs Sample
Rate, 15MHz Sine Wave Input,
–1dBFS
LTC2150-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2150-12: Shorted Input
Histogram
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2150-12: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 170Msps
LTC2150-12: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
170Msps
LTC2150-12: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
170Msps LTC2150-12: Frequency Response
LTC2150-12: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 170Msps
OUTPUT CODE
2056
COUNT
12000
16000
20000
21521012 G53
8000
4000
10000
14000
18000
6000
2000
02060 2064
SAMPLE RATE (Msps)
0
15
IOVDD (mA)
20
30
35
40
68 136 170
60
21521012 G54
25
34 102
45
50
55
LVDS CURRENT 3.5mA
LVDS CURRENT 1.75mA
SAMPLE RATE (Msps)
0
IVDD (mA)
135
140
136
21521012 G55
130
125
120
115
110
105
100 34 68 102 170
AMPLITUDE (dBFS)
0
SFDR (dBFS)
40
20
80
100
120
–70 –50 –40 0 10
21521012 G56
60
–80 –60 –30 –20 –10
dBFS
dBc
INPUT LEVEL (dBFS)
10
0
SNR (dBc AND dBFS)
20
30
40
50
70
60
–70 –50 –30–60 –40 –20 –10 0
21521012 G57
dBFS
dBc
INPUT FREQUENCY (MHz)
0
SFDR (dBFS)
50
40
60
70
800
21521012 G58
20
30
10
0200 400 500 1000
90
80
600
100 300 900
700
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
55
50
60
65
800
21521012 G59
45
40 200 400 500 1000
75
70
600
100 300 900
700
INPUT FREQUENCY (MHz)
–5.0
INPUT AMPLITUDE (dBFS)
–4.5
–3.5
–3.0
–2.5
1000
–0.5
21521012 G60
–4.0
100
–2.0
–1.5
–1.0
13
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
PIN FUNCTIONS
VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to
ground with 0.1µF ceramic capacitor. Pins 1, 2 can share
a bypass capacitor.
GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC
Power Ground. The exposed pad must be soldered to the
PCB ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
SENSE (Pin 7): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.75V
input range. An external reference between 1.2V and 1.3V
applied to SENSE selects an input range of ±0.6 • VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2µF ceramic capacitor. Nominally 1.25V.
VCM (Pin 9): Common Mode Bias Output; nominally equal
to 0.439•VDD. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
NC (Pins 16, 17): No Connection.
OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass
each pin to ground with separate 0.1µF ceramic capacitors.
OGND (Pin 21): LVDS Driver Ground.
SDO (Pin 36): In serial programming mode, (PAR/SER =
0V), SDO is the optional serial interface data output. Data
on SDO is read back from the mode control registers and
can be latched on the falling edge of SCK. SDO is an open-
drain N-channel MOSFET output that requires an external
2k pull-up resistor from 1.8V to 3.3V. If readback from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected.
SDI (Pin 37): In serial programming mode, (PAR/SER
= 0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
VDD), SDI selects 3.5mA or 1.75mA LVDS output current
(see Table 2).
SCK (Pin 38): In serial programming mode, (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
programming mode (PAR/SER = VDD), SCK controls the
sleep mode (see Table 2).
CS (Pin 39): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When CS
is low, SCK is enabled for shifting data on SDI into the
mode control registers. In parallel programming mode
(PAR/SER = VDD), CS controls the clock duty cycle stabi-
lizer (see Table 2).
PAR/SER (Pin 40): Programming Mode Selection Pin.
Connect to ground to enable the serial programming
mode. CS, SCK, SDI and SDO become a serial interface
that control the A/D operating modes. Connect to VDD to
enable the parallel programming mode where CS, SCK and
SDI become parallel logic inputs that control a reduced
set of the A/D operating modes. PAR/SER should be con-
nected directly to ground or the VDD of the part and not
be driven by a logic signal.
LTC2152-12/
LTC2151-12/LTC2150-12
14
21521012fa
For more information www.linear.com/LTC2152-12
PIN FUNCTIONS
LVDS Outputs (DDR LVDS)
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
D0_1–/D0_1+ to D10_11–/D10_11+ (Pins 18/19, 22/23, 24/25,
28/29, 31/32, 33/34): Double-Data Rate Digital Outputs.
Two data bits are multiplexed onto each differential output
pair. The even data bits (D0, D2, D4, D6, D8, D10) appear
when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7,
D9, D11) appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 26/27): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 14/15): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
This underflow is valid only when CLKOUT+ is low. In the
second half clock cycle, the overflow is set to 0.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
S/H
VCM
BUFFER
BUFFER
GND
VCM
0.1µF
CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC
CLOCK/DUTY
CYCLE CONTROL
1.25V
REFERENCE
RANGE
SELECT
CLOCK
ANALOG
INPUT
21521012 F01
DDR
LVDS
VDD
OVDD
OGND
CS
SPI
VREF
2.2µF
GND GND
SENSE
SCK
SDI
SDO
PAR/SER
D10_11
•
•
•
D0_1
15
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
TIMING DIAGRAMS
Double-Data Rate Output Timing, All Outputs Are Differential LVDS
tH
tC
tD
tL
tSKEW
D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4
D10N-6 D11N-6 D10N-5 D11N-5 D10N-4 D11N-4
OFN-6 INVALID OFN-5 INVALID OFN-4 INVALID
tAP
N + 1
N + 2
N + 3
N
ENC–
ENC+
D0_1+
D0_1–
D10_11+
D10_11–
CLKOUT–
CLKOUT+
OF+
OF–
21521012 TD01
LTM9003
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
21521012 TD02
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
LTC2152-12/
LTC2151-12/LTC2150-12
16
21521012fa
For more information www.linear.com/LTC2152-12
CONVERTER OPERATION
The LTC2152-12/LTC2151-12/LTC2150-12 are 12-
bit 250Msps/210Msps/170Msps A/D converters that
are powered by a single 1.8V supply. The analog
inputs must be driven differentially. The encode in-
puts should be driven differentially for optimal per-
formance. The digital outputs are double-data rate
LVDS. Additional features can be chosen by programming
the mode control registers through a serial SPI port.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). It must be driven differentially around a
common mode voltage set by the VCM output pin, which
is nominally 0.439•VDD. The inputs should swing from
VCM – 0.375V to VCM + 0.375V. There should be a 180°
phase difference between the inputs.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wide band noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC compo-
nent values should be chosen based on the application’s
input frequency.
T
ransformer-Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with the common mode supplied through a
pair of resistors via the VCM pin.
At higher input frequencies a transmission line balun
transformer (Figures 4 and 5) has better balance, resulting
in lower A/D distortion.
Figure 2. Equivalent Input Circuit for Differential Input Clock
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
APPLICATIONS INFORMATION
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 15MHz to 150MHz
2pF
RON
20Ω
RON
20Ω
VDD
VDD
LTC2152-12
AIN+
21521012 F02
2pF
VDD
AIN–
ENC–
ENC+
2pF
2pF
1.2V
5Ω
10k
5Ω
25Ω
25Ω 4.7Ω
4.7Ω
10Ω
0.1µF
10pF
0.1µF
LTC2152-12
IN
0.1µF T1
1:1
T1: MACOM ETC1-1T 21521012 F03
AIN+
AIN–
VCM
10Ω
0.1µF
0.1µF
IN
0.1µF
0.1µF T2
WBC1-1L
T1
MABA
007159-
000000
21521012 F04
LTC2152-12
AIN+
AIN–
VCM
45Ω
45Ω
100Ω
4.7Ω
4.7Ω
17
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
APPLICATIONS INFORMATION
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz Up to 900MHz
Figure 6. Front-End Circuit Using a High
Speed Differential Amplifier
Amplifier Circuits
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
3 and 5) should convert the signal to differential before
driving the A/D. The A/D cannot be driven single-ended.
Reference
The LTC2152-12/LTC2151-12/LTC2150-12 has an internal
1.25V voltage reference. For a 1.5V input range with in-
ternal reference, connect SENSE to VDD. For a 1.5V input
range with an external reference, apply a 1.25V reference
voltage to SENSE (Figure 7).
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
Figure 7. Reference Circuit Figure 8. Equivalent Encode Input Circuit
T1 45Ω
45Ω
10Ω
4.7Ω
0.1µF
0.1µF
IN
0.1µF
0.1µF
T1: MACOM ETC1-1-13 21521012 F05
LTC2152-12
AIN+
AIN–
VCM
4.7Ω
MABA
007159-
000000
100Ω
4.7Ω
4.7Ω
50Ω
50Ω
0.1µF
AIN+
AIN–
0.1µF
3pF
3pF
VCM
LTC2152-12
21521012 F06
INPUT
0.1µF
3pF
SCALER/
BUFFER
1.25V
SENSE
VREF
21521012 F07
5Ω
ADC
REFERENCE
SENSE
DETECTOR
2.2µF
VDD
LTC2152-12
21521012 F08
1.2V
10k 10k
ENC+
ENC–
LTC2152-12/
LTC2151-12/LTC2150-12
18
21521012fa
For more information www.linear.com/LTC2152-12
APPLICATIONS INFORMATION
the encode inputs directly. Otherwise, a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD + 0.1V or go below –0.1V.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
via SPI Register A2 (see SPI Control Register) or by CS
in parallel programming mode.
Figure 9. Sinusoidal Encode Drive
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
The digital outputs are double-data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are six LVDS output pairs (D0_1+/
D0_1– through D10_11–/D10_11+). Overflow (OF+/OF–)
and the data output clock (CLKOUT+/CLKOUT–) each have
an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage.
Figure 10. PECL or LVDS Encode Drive
LTC2152-12
T1
VDD
21521012 F09
1.2V
10k 10k
50Ω
100Ω
50Ω
0.1µF
0.1µF
0.1µF
T1: MACOM ETC1-1-13
VDD
LTC2152-12
PECL OR
LVDS INPUT
21521012 F10
1.2V
10k 10k
100Ω
0.1µF
0.1µF
ENC+
ENC–
19
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
APPLICATIONS INFORMATION
An external 100Ω differential termination resistor is re-
quired for each LVDS output pair. The termination resistors
should be located as close as possible to the LVDS receiver.
The outputs are powered by OVDD and OGND, which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 3). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In ad-
dition, an optional internal 100Ω termination resistor
can be enabled by serially programming mode control
register A3. The internal termination helps absorb any
reflections caused by imperfect termination at the re-
ceiver. When the internal termination is enabled, the
output driver current is doubled to maintain the same
output voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overflow bit has the same pipeline latency as the
data bits.
When CLKINV is set to 0 in the SPI register A2, OF signal
is valid when CLKOUT+ is low as shown in the Timing
Diagram.
Phase Shifting the Output Clock
To allow adequate setup and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have this
feature; this is generally the best place to adjust the timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature, the clock
duty cycle stabilizer must be turned on. Another con-
trol register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 11).
21
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LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
Figure 12. Functional Equivalent of Digital Output Randomizer
Figure 13. Unrandomizing for Randomized
Digital Output Signal
APPLICATIONS INFORMATION
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(1.5V Range) OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>0.75V
+0.75V
+0.7496337V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.0003662V
+0.000000V
–0.0003662V
–0.0007324V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.74963378V
–0.75V
< –0.75V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off-chip, these unwanted
tones can be randomized, which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT out-
puts are not affected. The output randomizer is enabled
by serially programming mode control register A4.
CLKOUT CLKOUT
OF
D11/D0
D10/D0
•
•
•
D1/D0
D0
21521012 F12
OF
D11
D10
D1
D0
RANDOMIZER
ON
D11
FPGA
PC BOARD
D10
•
•
•
D1
D0
21521012 F13
D0
D1/D0
D10/D0
D11/D0
OF
CLKOUT
LTC215X-12
LTC2152-12/
LTC2151-12/LTC2150-12
22
21521012fa
For more information www.linear.com/LTC2152-12
Alternate Bit Polarity
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output random-
izer—either both or neither function can be on at the same
time. The alternate bit polarity mode is enabled by serially
programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes (activate by setting
DTESTON) that force the A/D data outputs (OF, D11 to
D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs, includ-
ing OF and CLKOUT, are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
Sleep Mode
The A/D may be placed in a power-down mode to conserve
power. In sleep mode, the entire A/D converter is powered
down, resulting in < 2mW power consumption. If the en-
code input signal is not disabled, the power consumption
will be higher (up to 2mW at 250Msps). Sleep mode is
enabled by mode control register A1 (serial programming
mode), or by SCK (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF .
For the suggested values in Figure 1, the A/D will stabi-
lize after 0.1ms + 2500 • tp where tp is the period of the
sampling clock.
Nap Mode
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wakeup. Recovering from nap mode requires at least 100
clock cycles. Wake-up time from nap mode is guaranteed
only if the clock is kept running, otherwise sleep mode,
wake-up time conditions apply. Nap mode is enabled by
setting register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC215X-12 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
APPLICATIONS INFORMATION
23
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LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
Table 2. Parallel Programming Mode Control Bits)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Power-Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is neces-
sary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is WRITE-ONLY.
GROUNDING AND BYPASSING
The LTC215X-12 requires a printed circuit board with a
clean unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, OVDD, VCM and VREF pins. Bypass capacitors
must be located as close to the pins as possible. Size
0402 ceramic capacitors are recommended. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The analog inputs, encode signals and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC215X-12 is trans-
ferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
APPLICATIONS INFORMATION
LTC2152-12/
LTC2151-12/LTC2150-12
24
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For more information www.linear.com/LTC2152-12
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An “X” indicates an unused bit.
REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE-ONLY
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Bit 7 RESET Software Reset Bit
0 = Not Used
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0 Unused bit.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X SLEEP NAP 0 0
Bits 7-4 Unused, these bits are read back as 0.
Bit 3 SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2 NAP
0 = Normal Mode
1 = Low Power Mode
Bit 1-0 Must be set to 0.
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, these bits are read back as 0.
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
25
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LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF
Bits 7-5 Unused, these bits are read back as 0.
Bits 4-2 ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1 TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0 OUTOFF Digital Output Mode Control Bits
0 = LVDS DDR
1 = LVDS Tristate (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
OUTTEST2 OUTTEST1 OUTTEST0 ABP 0 DTESTON RAND TWOSCOMP
Bits 7-5 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D11-D0 alternate between 00000 0000 0000 and 11111 1111 1111
100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 01010 1010 1010 and 10101 0101 0101
Bit 4 ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3 Must be set to 0.
Bit 2 DTESTON Enable digital patterns (Bits 7-5)
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1 RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0 TWOSCOMP Tw o ’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Tw o ’s Complement Data Format
APPLICATIONS INFORMATION
27
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
TYPICAL APPLICATIONS
LTC2152-12
1
2
3
4
5
6
7
8
9
10
41
VDD
40
39
38
37
36
35
34
33
32
31
PAR/SER
CS
SCK
SDI
SDO
GND
D10_11+
D10_11–
D8_9+
D8_9–
D10_11+
D10_11–
D8_9+
D8_9–
11
12
13
14
15
16
17
18
19
20
CLK+
CLK–
GND
OF–
OF+
NC
NC
D0_1–
D0_1+
OVDD
30
29
28
27
26
25
24
23
22
21
OVDD
D6_7+
D6_7–
CLKOUT+
CLKOUT–
D4_5+
D4_5–
D2_3+
D2_3–
OGND
D6_7+
D6_7–
CLKOUT+
CLKOUT–
D4_5+
D4_5–
D2_3+
D2_3–
21521012 TA02
SENSE
SENSE
TP3 R9, 1k
C21
0.1µF
VCM
C16
2.2µF
C13
2.2µF
R19
10Ω
10Ω
R14
10Ω
R16
100Ω
VDD
VDD
GND
AINA+
AINA–
GND
SENSE
VREF
VCM
GND
GND
AINA+
AINA–
SDO
SDI
SCK
CS
PAR/SER
0.1µF 0.1µF
100Ω
CLK+CLK–
OF–
OF+
NC
NC
D0_1–
D0_1+
0.2µF 0.1µF
0.1µF
LTC2152-12 Schematic
LTC2152-12/
LTC2151-12/LTC2150-12
28
21521012fa
For more information www.linear.com/LTC2152-12
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
6.00 0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 ¥ 45
CHAMFER
0.40 0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 0.10
4.42 0.10
4.42 0.05
4.42 0.05
0.75 0.05 R = 0.115
TYP
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 0.05
4.50 0.05
(4 SIDES)
5.10 0.05
6.50 0.05
0.25 0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
29
21521012fa
LTC2152-12/
LTC2151-12/LTC2150-12
For more information www.linear.com/LTC2152-12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/14 Changed pipeline latency to 6
Updated G17, G37 and G57
5 and 15
7, 10 and 12
LTC2152-12/
LTC2151-12/LTC2150-12
30
21521012fa
For more information www.linear.com/LTC2152-12
LINEAR TECHNOLOGY CORPORATION 2011
LT1214 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2152-12
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88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply
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Frequency Range
LTC2152-12: 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 250Msps
TYPICAL APPLICATION
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21521012 TA03b
100 120
–20
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC
CLOCK/DUTY
CYCLE
CONTROL
D10_11
•
•
•
D0_1
CLOCK
ANALOG
INPUT
21521012 TA03a
DDR
LVDS
VDD
GND
OVDD
OGND
