To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.
2. Renesas Electronics does not assum e any liability for inf ringement of patents, co pyrights, or other int ellectual property rights
of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, m odify, copy, or otherw ise misappropriate an y Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technol ogy described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such law s and regulations. You should not use Renesas
Electronics products or the technology described in this docum ent for any purpose rela ting to military applications or use by
the military, including but not limited to the developm ent of weapons of ma ss destruction. Renesas Electronics products and
technology may not be used for or incor porated into any products or system s whose manufac ture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in prepa ring the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recom mended applicatio ns for each Renesas Electronics prod uct depends on the produc t’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Elec tronics product for any application cate gorized as “Spec ific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any applic ation for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intende d where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appli ances; mac hine tools; personal electronic equipm ent; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation
characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or
damages arising out of the use of Re nesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substa nces, including without lim itation, the EU R oHS
Directive. Renesas Electronics assum es no liability for damage s or losses occurring as a result of your noncom pliance with
applicable laws and regulatio ns.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions re garding the information conta ined in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.
H8S/2148 Group, H8S/2144 Group,
H8S/2148F-ZTAT™, H8S/2147N F-ZTAT™,
H8S/2144F-ZTAT™, H8S/2142F-ZTAT™
Hardware Manual
16
User’s Manual
Rev.4.00 2006.09
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2100 Series
H8S/2148 HD6432148S H8S/2147N HD64F2147N
HD6432148SW HD64F2147NV
HD64F2148 H8S/2144 HD6432144S
HD64F2148V HD64F2144
HD64F2148A HD64F2144V
HD64F2148AV HD64F2144A
H8S/2147 HD6432147S HD64F2144AV
HD6432147SW H8S/2143 HD6432143S
HD64F2147A H8S/2142 HD6432142
HD64F2147AV HD64F2142R
HD64F2142RV
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Rev. 4.00 Sep 27, 2006 page ii of xliv
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 4.00 Sep 27, 2006 page iii of xliv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through cu rrent f lows internally, and a malfunction may occur.
3. Processing befo re Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where th e states are
undefined, the register settings and the ou tput state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 4.00 Sep 27, 2006 page iv of xliv
Rev. 4.00 Sep 27, 2006 page v of xliv
Preface
The H8S/2148 Group, H8S/2144 Group, and H8S/2147N comprise high-performance
microcomputers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions
required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexib le response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR),
watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface
(SCI, IrDA), PS/2-compatible keyboard buffer controller, host interface (HIF), D/A converter
(DAC), A/D converter (ADC), and I/O ports. An I2C bus interface (IIC) can also be inco rporated
as an option.
An on-chip d a ta tr ansfer controller (DTC) is also provided, enabling high-speed data tran sf er
without CPU intervention.
The H8S/2148 Group has all the above on-chip supporting functions, and can also be provided
with an IIC module as an option. The H8S/2144 Group comprises reduced-function versions, with
fewer TMR channels, and no PWM, keyboard buffer controller, HIF, IIC, or DTC modules, and
the H8S/2147N with fewer TMR channels, no DTC and some other functions.
Use of the H8S/2148 Group, H8S/2144 Group, H8S/2147N enables compact, high-performance
systems to be implemented easily. The comprehensive PC-related interface functions and 16 × 8
matrix key-scan functions are ideal for applications such as notebook PC keyboard control and
intelligent battery and power supply control, while the various timer functions and their
interconnectability (timer connection), plus the interlinked operation of the I2C bus interface and
data transfer contr o ller (DTC), in particular, make th ese devices ideal for use in PC monitors. In
addition, the combination of F-ZTAT™* and reduced-function versions is ideal for applications
such as CD-ROM driv e units in which on-chip program memory is essential to meet perfo r mance
requirements, product start-up times are short, and program modifications may be necessary after
end-product assembly.
Rev. 4.00 Sep 27, 2006 page vi of xliv
This manual describes the hardware of the H8S/2148 Group, H8S/2144 Group, and H8S/2147N.
Refer to the H8S/2600 Series and H8S/2000 Series Software Manual for a detailed description of
the instruction set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp.
On-Chip Su pporting Modules
Group H8S/2148 Group H8S/2147N H8S/2144 Group
Product names H8S/2148,
H8S/2147 H8S/2147N H8S/2144,
H8S/2143,
H8S/2142
Bus controller (BSC) Available (16 bits) Available (16 bits) Available (16 bits)
Data transfer controller (DTC) Available — —
8-bit PWM timer (PWM) ×16 ×16 —
14-bit PWM timer (PWMX) ×2×2×2
16-bit free-running timer (FRT) ×1×1×1
8-bit timer (TMR) ×4×3×3
Timer connection Available — —
Watchdog timer (WDT) ×2×2×2
Serial communi cat ion interface (SCI) ×3×3×3
I2C bus interface (IIC) ×2 (option) ×2 (option) —
Keyboard buffer controller
(PS/2 compatible) ×3×3—
Host interface (HIF) ×4×4—
D/A converter ×2×2×2
A/D converter Analog inputs ×8×8×8
Expansion A/D inputs ×16 ×16 ×16
Rev. 4.00 Sep 27, 2006 page vii of xliv
Main Revisions for This Edition
Item Page Revision (See Manual for Details)
All — • Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8S/2148 Series → (After) H8S/2148 Group
(Before) H8S/2144 Series → (After) H8S/2144 Group
1.1 Overview
Table 1.1 Overview 4 Host interface specification in table 1.1 amended
• 8-bit host interface (ISA) port
6 Product lineup specification in table 1.1 amended
Product Code*
2
Group Mask ROM
Versions F-ZTAT
Versions ROM/RAM
(Bytes) Packages
H8S/2148 HD6432148S HD64F2148
HD64F2148V*
2
128 k/4 k
HD6432148SW*
1
HD64F2148A
HD64F2148AV*
2
FP-100B,
TFP-100B
HD6432147S HD64F2147A 64 k/2 k
HD6432147SW*
1
HD64F2147AV*
2
H8S/2147N —HD64F2147N
HD64F2147NV*
2
64 k/2 k
H8S/2144 HD6432144S HD64F2144
HD64F2144V*
2
HD64F2144A
HD64F2144AV*
2
128 k/4 k
HD6432143S —96 k/4 k
HD6432142 HD64F2142R
HD64F2142RV*
2
64 k/2 k
Notes: 1. W indicates the I2C bus option.
2. V indicates the 3-V version. Please refer to appendix F, Product
Code Lineup.
1.2 Internal Block
Diagram
Figure 1.1 (a) Internal
Block Diagram of
H8S/2148 Group
7 Figure 1.1 (a) amended
(Before) STBY → (After) STBY
Figure 1.1 (b) Internal
Block Diagram of
H8S/2147N
8 Figure 1.1 (b) amended
(Before) IIC × 2ch → (After) IIC × 2ch (option)
Rev. 4.00 Sep 27, 2006 page viii of xliv
Item Page Revision (See Manual for Details)
14 Mode 1 description of pin 35 amended
(Before) P67/TMOX/CIN/KIN7/IRQ7 →
(After) P67/TMOX/CIN7/KIN7/IRQ7
1.3.2 Pin Functions in
Each Operating Mode
Table 1.2 (a) Pin
Functions in Each
Operating Mode 17 Modes 2 and 3 in single chip modes of pin 95 amended
(Before) P82 → (After) P82/HIFSD
19 Mode 1 description of pin 35 amended
(Before) P67/CIN/KIN7/IRQ7 → (After) P67/CIN7/KIN7/IRQ7
Table 1.2 (b)
H8S/2147N Pin
Functions in Each
Operating Mode 21 Modes 2 and 3 in single chip modes of pin 95 amended
(Before) P82 → (After) P82/HIFSD
1.3.3 Pin Functions
Table 1.3 Pin Functions 30 Table 1.3 amended
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
Host
interface
(HIF)
HIRQ11
HIRQ1
HIRQ12
HIRQ3
HIRQ4
52
53
54
91
90
Output Host interrupt 11, 1, 12, 3, and 4: Output pins for
interrupt requests to the host.
33
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
I/O ports PA7 to
PA0 10, 11, 20,
21, 30, 31,
47, 48
Input/
output Port A: Eight input/output pins. The data direction
of each pin can be selected in the port A data
direction register (PADDR). These pins have built-in
MOS input pull-ups. These are the VCCB drive
pins. [H8S/2148 Group and H8S/2147N only]
2.6.1 Overview
Table 2.1 Instruction
Classification
52 Instruction in arithmetic operations amended
(Before) EG → (After) NEG
3.2.4 Serial Timer
Control Register (STCR) 89 Bit 3 bit table amended
Bit 3
FLSHE Description
0 Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register
and supporting module control register access (Initial value)
1 Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register
access (F-ZTAT version only)
4.5 Stack Status after
Exception Handling
Figure 4.5 (2) Stack
Status after Exception
Handling (Advanced
Mode)
111 Note * deleted from figu re 4.5 (2)
Rev. 4.00 Sep 27, 2006 page ix of xliv
Item Page Revision (See Manual for Details)
5.2.8 Address Break
Control Register
(ABRKCR)
124 Read/Write description amended
Bit 7 (Before) R/W → (After) R
5.5.3 Interrupt control
Mode 1
Figure 5.9 Example of
State Transitions in
Interrupt control Mode 1
140 Figure 5.9 amended
(Before) Only NMI interrupts enabled and address break →
(After) Only NMI interrupts and address break enabled
8.1 Overview
Table 8.1 H8S/2148
Group Port Functions
213 Table 8.1 amended
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port A •8-bit I/O port PA7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8),
expansion A/D
converter input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
expansion A/D
converter input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC, PS2AD,
PS2AC)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8),
expansion A/D converter
input (CIN15 to CIN8), and
keyboard buffer controller
input/output (PS2CD,
PS2CC, PS2B D, PS2BC,
PS2AD, PS2AC)
Table 8.2 H8S/2147N
Port Functions 216 Table 8.2 amended
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port A •8-bit I/O port PA7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8),
expansion A/D
converter input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
expansion A/D
converter input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC, PS2AD,
PS2AC)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8), expansion
A/D converter input (CIN15
to CIN8), and keyboard
buffer controller
input/output (PS2CD,
PS2CC, PS2B D, PS2BC,
PS2AD, PS2AC)
Rev. 4.00 Sep 27, 2006 page x of xliv
Item Page Revision (See Manual for Details)
8.1 Overview
Table 8.3 H8S/2144 Port
Functions
220 Table 8.3 amended
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port A •8-bit I/O port PA7 to PA0 /
A23 to A16/
KIN15 to KIN8/
CIN15 to CIN8
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8), and
expansion A/D
converter input
(CIN15 to
CIN8)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
and expansion A/D
converter input
(CIN15 to CIN8)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8) and
expansion A/D converter
input (CIN15 to CIN8)
8.7.2 Register
Configuration
Table 8.14 Port 6
Registers
247 Table 8.14 amended
(Before) System control register → (After) System control
register 2
8.9.3 Pin Functions
Table 8.19 Port 8 Pin
Functions
258 P81/GA20/CS2 selection method and pin function de scription
amended
Pin Selection Method and Pin Functions
P81/GA20/CS2 The pin function is switched as shown below according to the combination of
operating mode, bit CS2E in SYSCR, bit FGA20E in HICR of the HIF, and bit
P81DDR.
Operating
mode Not slave mode Slave mode
FGA20E —01
CS2E —01—
P81DDR 0 1 0 1 —01
Pin function P81
input
pin
P81
output
pin
P81
input
pin
P81
output
pin
CS2
input
pin
P81
input
pin
GA20
output
pin
This pin should be used as the GA20 output pin or CS2 input pin only in mode
2 or 3 (EXPE = 0).
Rev. 4.00 Sep 27, 2006 page xi of xliv
Item Page Revision (See Manual for Details)
8.11.3 Pin Functions
Table 8.23 Port A Pin
Functions
270 Table 8.23 amended
Pin Selection Method and Pin Functions
PA1/A17/KIN9/
CIN9 The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA1DDR.
Operating
mode Modes 1,
2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
PA1DDR 0 1 0 1
IOSE ——— 01
Pin function PA1
input pin PA1
output pin PA1
input pin A17
output pin PA1
output pin
KIN9 input pin, CIN9 input pin
This pin can always be used as the KIN9 or CIN9 input pin.
PA0/A16/KIN8/
CIN8 The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA0DDR.
Operating
mode Modes 1,
2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
PA0DDR 0 1 0 1
IOSE ——— 01
Pin function PA0
input pin PA0
output pin PA0
input pin A16
output pin PA0
output pin
KIN8 input pin, CIN8 input pin
This pin can always be used as the KIN8 or CIN8 input pin.
9.3.1 Correspondence
between PWM Data
Register Contents and
Output Waveform
Table 9.4 Duty Cycle of
Basic Pulse
289 Description of upper 6 bits changed to of upper 4 bits
10.3 Bus Master
Interface 299 Description amended
... Example 2: Read DADRA
MOV.W @DADRA, R0 ; Transfer contents of DADRA to R0
10.4 Operation
Table 10.4 Settings and
Operation (Examples
when φ = 10 MHz)
303 Table 10.4 amended
Fixed DADR Bits
Bit Data
CKS
Resolution
T
(µs) CFS
Base
Cycle
(µs)
Conversion
Cycle
(µs)
T
L
(if OS = 0)
T
H
(if OS = 1) Precision
(Bits) 3210
Conversion
Cycle*
(µs)
0 0.1 0 6.4 1638.4 1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 1638.4
1 25.6 1638.4 1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 1638.4
1 0.2 0 12.8 3276.8 1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 3276.8
1 51.2 3276.8 1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 3276.8
Rev. 4.00 Sep 27, 2006 page xii of xliv
Item Page Revision (See Manual for Details)
16.1.1 Features 492 • Automatic switching from formatless mode to I2C bus format
(channel 0 only)
Description added
16.4 Usage Notes
Figure 16.19 Flowchart
and Timing of Start
Condition Instruction
Issuance for
Retransmission
548 Figure 16.19 amended
SCL
ACK
9
IRIC
[1] IRIC determination Determination
of SCL = low
[2]
[3] Start condition
instruction issuance
SDA
550 to
557 Description added
• Notes on WAIT Function
• Notes on ICDR Reads and ICCR Access in Slave Transmit
Mode
• Notes on TRS Bit Setting in Slave Mode
• Notes on Arbitration Lost in Master Mode
• Notes on Interrupt Occurrence after ACKB Reception
• Notes on TRS Bit Setting and ICDR Register Access
20.4.3 Input Sampling
and A/D Conversion Time
Figure 20.5 A/D
Conversion Time
628 Figure 20.5 amended
(1)
(2)
A
ddress
φ
Write signal
Rev. 4.00 Sep 27, 2006 page xiii of xliv
Item Page Revision (See Manual for Details)
22.4.2 Block Diagram
Figure 22.2 Block
Diagram of Flas h
Memory
643 Figure 22.2 amended
Module bus
Bus interface/controller
Flash memory
(128 kbytes/64 kbytes)
Operating
mode
FLMCR2
Internal address bus
Internal data bus (16 bits)
Mode pins
EBR1
EBR2
FLMCR1 *
*
*
*
22.5.3 Erase Block
Registers 1 and 2
(EBR1, EBR2)
653 Bit figure amended
Read/Write description of bits 7 to 2 (Before) *2 → (After)
22.10.1 Programmer
Mode Setting 671 Note amended
In programmer mode, ... Renesas Technology microcomputer
device types with 128-kbyte*1*3 or 64-kbyte*2*3 o n-chip flash
memory. ...
Note: 3. Use products other than the A-mask version of the
H8S/2148, H8S/2147N, H8S/2144, and H8S/2142 ...
22.10.4 Memory Read
Mode
Figure 22.17 Timing
Waveforms when
Entering Another Mo de
from Memory Read
Mode
675 Figure 22.17 amended
CE
FA17 to FA0
FO7 to FO0 H'XX
OE
WE
Other mode command writeMemory read mode
t
wep
t
ceh
t
dh
t
ds
t
nxtc
t
ces
Address stable
Data
t
f
t
r
Rev. 4.00 Sep 27, 2006 page xiv of xliv
Item Page Revision (See Manual for Details)
22.10.4 Memory Read
Mode
Figure 22.19 Timing
Waveforms for CE/OE
Clocked Read
676 Figure 22.19 amended
CE
FA17 to FA0
FO7 to FO0
VIH
OE
WE
t
ce
tacc
toe
toh toh
tdf
tce
tacc
toe
Address stable Address stable
Data Data
tdf
22.10.7 Status Read
Mode
Figure 22.22 Status
Read Mode Timing
Waveforms
681 Figure 22.22 amended
CE
OE
WE tces
tnxtc tnxtc
tdf
tces
twep twep
toe
tce tnxtc
tftrtftr
tceh
tceh
23.5.3 Erase Block
Registers 1 and 2
(EBR1, EBR2)
699 Bit figure amended
Read/Write description of bits 7 to 2 (Before) *2 → (After)
Bit 1 0
EBR1 EB9/—*
2
EB8/—*
2
Initial value 0 0
Read/Write R/W*
1
*
2
R/W*
1
*
2
Note 2 amended
Note: 2. Bits EB8 and EB9 are not present in the 64-kbyte
versions; they must not be set to1.
Table 23.5 Flash
Memory Er ase Blocks 700 64-kbyte description added to table 23.5
Block (Size)
128-kbyte Version 64-kbyte Version Address
EB0 (1 kbyte) EB0 (1 kbyte) H'(00)0000 to H'(00)03FF
EB1 (1 kbyte) EB1 (1 kbyte) H'(00)0400 to H'(00)07FF
EB2 (1 kbyte) EB2 (1 kbyte) H'(00)0800 to H'(00)0BFF
EB3 (1 kbytes) EB3 (1 kbytes) H'(00)0C00 to H'(00)0FFF
EB4 (28 kbytes) EB4 (28 kbytes) H'(00)1000 to H'(00)7FFF
EB5 (16 kbytes) EB5 (16 kbytes) H'(00)8000 to H'(00)BFFF
EB6 (8 kbytes) EB6 (8 kbytes) H'(00)C000 to H'(00)DFFF
EB7 (8 kbytes) EB7 (8 kbytes) H'00E000 to H'00FFFF
EB8 (32 kbytes) —H'010000 to H'017FFF
EB9 (32 kbytes) —H'018000 to H'01FFFF
Rev. 4.00 Sep 27, 2006 page xv of xliv
Item Page Revision (See Manual for Details)
23.6.1 Boot Mode 705 Description amended
H'(FF)E088 and above
23.7.2 Program-Verify
Mode
Figure 23.12
Program/Program-Verify
Flowcharts
710 Note *6 added to figure 23.12
Start
End of programming
End sub
Set SWE bit in FLMCR1
Wait (x) µs
n = 1
m = 0
Sub-routine-call See Note 7 for pulse width
Note 7: Write Pulse Width
Start of programming
Sub-routine write pulse
Set PSU bit in FLMCR1
Enable WDT
Set P bit in FLMCR1
Wait (y) µs
Clear P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Clear PSU bit in FLMCR2
Wait (α) µs
Disable WDT
Wait (β) µs
Write pulse application subroutine
NG
NG
NG NG
OK
OK
Wait (γ) µs
Wait (ε) µs
*2
*4
*6
*6
*6
*6
*6
*6
*6*6
*5
*6
*6
*6
*1
Wait (η) µs
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Program data =
verify data?
Transfer additional program data
to additional program data area
Additional program data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
End of 128-byte
data verification?
m = 0?
Increment address
Programming failure
OK
Write 128-byte data in RAM reprogram data
area consecutively to flash memory
Write pulse
(z1) µs or (z2) µs
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
.
998
999
1000
Write Time (z*
6
) µsec
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
.
.
.
z2
z2
z2
Reprogram data computation
Transfer reprogram data to reprogram data area
*4
*3
6 ≥ n? NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
Additional write pulse (z3) µs
Wait (θ) µs
*1
Note: Use a (z3) µs write pulse for additional
programming.
Additional program data
storage area (128 kbytes)
OK
OK NG
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*4
n ← n + 1
n ≥ 1000?
Clear SWE bit in FLMCR1
Wait (θ) µs
6 ≥ n?
23.10.4 Memory Read
Mode
Figure 23.17 Timing
Waveforms when
Entering Another Mo de
from Memory Read
Mode
721 Figure 23.17 amended
CE
FA17 to FA0
FO7 to FO0 H'XX
OE
WE
Other mode command write
t
wep
t
ceh
t
dh
t
ds
t
ces
Data
t
f
t
r
Memory read mode
Address stable
t
nxtc
Rev. 4.00 Sep 27, 2006 page xvi of xliv
Item Page Revision (See Manual for Details)
23.10.4 Memory Read
Mode
Figure 23.19 Timing
Waveforms for CE/OE
Clocked Read
722 Figure 23.19 amended
CE
FA17 to FA0
FO7 to FO0
VIH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
Address stable Address stable
Data Data
t
df
23.10.5 Auto-Program
Mode
Figure 23.20 Auto-
Program Mode Timing
Waveforms
724 Figure 23.20 amended
Data
CE
FA17 to FA0
FO7 to FO0
FO6
FO7
OE
WE
tnxtc
twsts
tnxtc
tces
tdstdh
twep
tas tah
tceh
Address
stable
Programming wait
Data transfer
1 byte to 128 bytes
H'40 Data
FO0 to FO5 = 0
t
f
t
r
t
spa
t
write (1 to 3000 ms)
Programming normal
end identification signal
Programming operation
end identification signal
23.10.6 Auto-Erase
Mode
Figure 23.21 Auto-
Erase Mode Timing
Waveforms
725 Figure 23.21 amended
CE
FA17 to FA0
FO7 to FO0
FO6
FO7
OE
WE
t
ests
t
nxtc
t
nxtc
t
ces
t
ceh
t
dh
CL
in
DL
in
t
wep
FO0 to FO5 = 0
H'20 H'20
Erase normal end
confirmation signal
t
f
t
r
t
ds
t
spa
t
erase
(100 to 40000 ms)
Erase end identification
signal
Rev. 4.00 Sep 27, 2006 page xvii of xliv
Item Page Revision (See Manual for Details)
23.10.7 Status Read
Mode
Figure 23.22 Status
Read Mode Timing
Waveforms
727 Figure 23.22 amended
CE
OE
WE t
ces
t
nxtc
t
nxtc
t
df
t
ces
t
dh
t
wep
t
wep
t
dh
t
oe
t
ce
t
nxtc
t
f
t
r
t
f
t
r
t
ceh
t
ds
t
ds
t
ceh
24.7 Subclock Input
Circuit 740 Note on Subclock Usage
Description added
25.12 Usage Notes 764 Section 25.12 added
799 Table 26.15 amended
Item Symbol Min Typ Max Unit Test
Condition
Reprogramming count N
WEC
100*
8
10000*
9
—Times
Data retention time*
10
t
DRP
10 — — Years
Programming Wait time after SWE-bit setting*
1
x10——µs
26.2.6 Flash Memory
Characteristics
Table 26.15 Flash
Memor y Charact eristics
(Programming/erasing
operating range) 800 Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.3.3 AC
Characteristics
Table 26.20 Clock
Timing
819 Table 26.20 amended
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Oscillation settling
time at reset
(crystal)
t
OSC1
10 —10 —20 —ms Figure 26.6
Oscillation settling
time in software
standby (crysta l)
t
OSC2
8 — 8 — 8 — ms Figure 26.7
Table 26.25 I2C Bus
Timing 829 Table 26.25 amended
Ratings
Item Symbol Min Typ Max Unit Test Conditions Notes
SCL, SDA input
fall time t
Sf
——300 ns Figure 26.28
SCL, SDA output
fall time t
of
20 + 0.1 Cb —250 ns
SCL, SDA input
spike pulse
elimination time
t
SP
——1t
cyc
Rev. 4.00 Sep 27, 2006 page xviii of xliv
Item Page Revision (See Manual for Details)
831 Note *4 added to table condition
Condition C: VCC = 3.0 V to 3.6V*4, AVCC = 3.0 V to 3.6 V*4,
AVref = 3.0 V to AVCC*4, VCCB = 3.0 V to 5.5 V*4, ...
26.3.4 A/D Conversion
Characteristics
Table 26.27 A/D
Conversion
Characteristics (CIN15 to
CIN0 Input: 134/266-
State Conversion)
Note 4 amended
Note: 4. When using CIN, the applicable range is VCC = 3.0 V to
3.6 V, ...
833 Table 26.29 amended
Item amended (Before) Wait time after dummy write → (After)
Wait time a fter H'FF dummy write
Symbol of wait time after SWE-bit clear (Before) Θ → (After) θ
Item Symbol Min Typ Max Unit Test
Condition
Reprogramming count N
WEC
100*
8
10000*
9
—Times
Data retention time*
10
t
DRP
10 — — Years
Programming Wait time after SWE-bit setting*
1
x1——µs
26.3.6 Flash Memory
Characteristics
Table 26.29 Flash
Memor y Charact eristics
(Programming/erasing
operating range)
834 Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.4.3 AC
Characteristics
Table 26.35 Control
Signal Timing
849 Unit of tNMIH amended
(Before) → (After) ns
Table 26.37 Timing of
On-Chip Supporting
Modules (1)
854,
855 Units of tPRS, tPRH, tFTIS, tFTCS, tTMRS, tTMCS amended
(Before) → (After) ns
Units of tFTCWL, tTMCWL, synchronous tScyc amended
(Before) → (After) tcyc
Unit of tSCKf amended
(Before) 1.5 → (After) tcyc
26.4.4 A/D Conversion
Characteristics
Table 26.41 A/D
Conversion
Characteristics (CIN15 to
CIN0 Input: 134/266-
State Conversion)
860 Table condition amended
Table condition A (Before) ..., Ta = −20 to +75°C (regular
specifications), Ta = −40 to +85°C (wide-range specifications)
→ (After) ... Ta = −20 to +75°C
Rev. 4.00 Sep 27, 2006 page xix of xliv
Item Page Revision (See Manual for Details)
862 Table 26.43 amended
Item Symbol Min Typ Max Unit Test
Condition
Reprogramming count N
WEC
100*
8
10000*
9
—Times
Data retention time*
10
t
DRP
10 — — Years
Programming Wait time after SWE-bit setting*
1
x10——µs
26.4.6 Flash Memory
Characteristics
Table 26.43 Flash
Memor y Charact eristics
(Programming/erasing
operating range) 863 Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.5.3 AC
Characteristics
Table 26.49 Control
Signal Timing
877 Unit of tNMIH amended
(Before) (blank) → (After) ns
885 Table 26.55 amended
Item Symbol Min Typ Max Unit Condition
Reprogramming count NWEC 100*810000*9—Times
Data retention time*10 tDRP 10 — — Years
Programming Wait time after SWE-bit setting*1x10——µs
26.5.6 Flash Memory
Characteristics
Table 26.55 Flash
Memor y Charact eristics
(Programming/erasing
operating range) 886 Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.6.3 AC
Characteristics
Table 26.61 Control
Signal Timing
900 Unit of tNMIH amended
(Before) (blank) → (After) ns
Rev. 4.00 Sep 27, 2006 page xx of xliv
Item Page Revision (See Manual for Details)
26.6.6 Flash Memory
Characteristics
Table 26.67 Flash
Memor y Charact eristics
(Programming/erasing
operating range)
908 Table 26.67 amended
Symbol of wait time after SWE-bit clear (Before) Θ → (After) θ
Item Symbol Min Typ Max Unit Test
Condition
Reprogramming count N
WEC
100*
8
10000*
9
—Times
Data retention time*
10
t
DRP
10 — — Years
Programming Wait time after SWE-bit setting*
1
x1——µs
909 Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.7.2 Clock Timing
Figure 26.6 Oscillation
Settling Timing
912 Figure 26.6 amended
t
OSC1
t
OSC1
EXTAL
V
CC
STBY
RES
φ
t
DEXT
t
DEXT
26.7.5 Timing of On-
Chip Supporting Modules
Figure 26.28 I2C Bus
Interface Input/Output
Timing (Option)
924 Figure 26.28 amended
SDA0,
SDA1 V
IL
V
IH
t
BUF
P*S*
t
STAH
t
SCLH
t
Sr
t
SCLL
t
SCL
t
Sf
t
of
t
SDAH
SCL0,
SCL1
Rev. 4.00 Sep 27, 2006 page xxi of xliv
Item Page Revision (See Manual for Details)
A.1 Instruction
Table A.1 Instruction
Set
930 Table A.1 amended
2. Arithmetic Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
EXTU
TAS
EXTU.W Rd
EXTU.L ERd
TAS @ERd
*3
0 → (<bits 15 to 8> of Rd16)
0 → (<bits 31 to 16> of ERd32)
@ERd-0 → CCR set, (1) →
(<bit 7> of @ERd)
W
L
B
2
2
1
1
4
Operation
Condition Code No. of
States*
1
Normal
Advanced
Size
4
——— 00
——— 00
——— 0
933 Table A.1 amended
4. Shift Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
SHLR SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
—
—
—
—
—
—
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
Size
0
C
MSB LSB
939 Table A.1 amended
6. Branch Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
JMP
BSR
JSR
RTS
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
PC←ERn
PC←aa:24
PC←@aa:8
PC→@-SP,PC←PC+d:8
PC→@-SP,PC←PC+d:16
PC→@-SP,PC←ERn
PC→@-SP,PC←aa:24
PC→@-SP,PC←@aa:8
PC←@SP+
—
—
—
—
—
—
—
—
—
2
2
4
4
—
—
—
—
—
—
—
—
—
2
3
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
4
3
4
3
4
4
4
5
4
5
4
5
6
5
A.2 Instruction Codes
Table A.2 Instruction
Codes
949 Table A.2 amended
LDC @aa:16,CCR
LDC @aa:16,EXR
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte
Instruc-
tion
LDC W
W
0
0
1
1
4
4
0
1
6
6
B
B
0
0
0
0
abs
abs
Rev. 4.00 Sep 27, 2006 page xxii of xliv
Item Page Revision (See Manual for Details)
B.3 Functions 1013 Subheading amended
KBCOMPH'FEE4 IrDA/Expansion A/D
1016 ISRH'FEEB Interrupt Controller
Figure amended
IRQ7 to IRQ0 flags
0 [Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high*
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)*
Note: * When a product, in which a DTC is incorporated, is
used in the following settings, the corresponding flag bit is not
automatically cleared even when exception handling, which is a
clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an inte rrupt source),
IRQ4F flag is not automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt
source), IRQ5F flag is not automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt
source), IRQ6F flag is not automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt
source), IRQ7F flag is not automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts
are used with the above combinations, clea r the interrupt flag
by software in the interrupt handling routine of the
corresponding IRQ.
1019 ABRKCRH'FEF4 Interrupt Controller
Read/Write description amended
Bit 7 (Before) R/W → (After) R
1021 FLMCR1H'FF80 Flash Memory
Initial value des cript ion am ende d
Bit 7 (Before) → (After) 1
Rev. 4.00 Sep 27, 2006 page xxiii of xliv
Item Page Revision (See Manual for Details)
B.3 Functions 1025 EBR1H'FF82 Flash Memory
EBR2H'FF83 Flash Memory
Figure amended
Read/Write description of bits 7 to 2 (Before) *2 → (After)
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
EB8/—*2
0
R/W*1*2
2
—
0
—
1
EB9/—*2
0
R/W*1*2
Bit
EBR1
Initial value
Read/Write
7
EB7
0
R/W*1
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit
EBR2
Initial value
Read/Write
1030 ICCR1H'FF88 IIC1
ICCR0H'FFD8 IIC0
Figure amended
I
2
C bus interface enable
0I
2
C bus interface module disabled, with
SCL and SDA signal pins set to port
function
SAR and SARX can be accessed
1I
2
C bus interface module enabled for
transfer operations (pins SCL and SDA
are driving the bus)
ICMR and ICDR can be accessed
1059 SYSCRH'FFC4 System
Figure amended
IOS enable
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,
the address range is from H'(FF)F000 to H'(FF)F7FF.
0The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
1 The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)*
Rev. 4.00 Sep 27, 2006 page xxiv of xliv
Item Page Revision (See Manual for Details)
B.3 Functions 1077 TICRRH'FFF2 TMRX
TICRFH'FFF3 TMRX
Figure amended
(Before) Stores TCNT value at fall of external trigger input →
(After) Stores TCNT value at fall of external reset input
1080 STR1H'FFF6 HIF
STR2H'FFFE HIF
Slave R/W description amended
Bit 0 (Before) R → (After) R/(W)
C.2 Port 2 Block
Diagrams
Figure C.4 Port 2 Block
Diagram (Pin P27)
1089 Figure C.4 amended
P27
Hardware
standby Mode 1
Appendix F Product
Code Lineup
Table F.1 H8S/2148
Group and H8S/2144
Group Product Code
Lineup
1128 Package code in table F.1 amended
HD64F2144ATE20 (Before) FP-100B → (After) TFP-100B
HD64F2144AVFA10 (Befor e) TFP-100B → (After) FP-100B
Appendix G Package
Dimensions
Figure G.1 Package
Dimensions (FP-100B)
1129 Figure G.1 replaced
Figure G.2 Package
Dimensions (TFP-100B) 1130 Figure G.2 replaced
Rev. 4.00 Sep 27, 2006 page xxv of xliv
Contents
Section 1 Overview............................................................................................................. 1
1.1 Overview........................................................................................................................... 1
1.2 Internal Block Diagram..................................................................................................... 7
1.3 Pin Arrangement and Functions........................................................................................ 10
1.3.1 Pin Arrangement.................................................................................................. 10
1.3.2 Pin Functions in Each Operating Mode............................................................... 13
1.3.3 Pin Functions ....................................................................................................... 26
Section 2 CPU...................................................................................................................... 35
2.1 Overview........................................................................................................................... 35
2.1.1 Features................................................................................................................ 35
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 36
2.1.3 Differences from H8/300 CPU ............................................................................ 37
2.1.4 Differences from H8/300H CPU.......................................................................... 37
2.2 CPU Operating Modes...................................................................................................... 38
2.3 Address Space................................................................................................................... 43
2.4 Register Configuration...................................................................................................... 44
2.4.1 Overview.............................................................................................................. 44
2.4.2 General Registers................................................................................................. 45
2.4.3 Control Registers ................................................................................................. 46
2.4.4 Initial Register Values.......................................................................................... 48
2.5 Data Formats..................................................................................................................... 49
2.5.1 General Register Data Formats............................................................................ 49
2.5.2 Memory Data Formats......................................................................................... 51
2.6 Instruction Set................................................................................................................... 52
2.6.1 Overview.............................................................................................................. 52
2.6.2 Instructions and Addressing Modes..................................................................... 53
2.6.3 Table of Instructions Classified by Function....................................................... 55
2.6.4 Basic Instruction Formats .................................................................................... 64
2.6.5 Notes on Use of Bit-Manipulation Instructions ................................................... 65
2.7 Addressing Modes and Effective Address Calculation..................................................... 65
2.7.1 Addressing Mode................................................................................................. 65
2.7.2 Effective Address Calculation ............................................................................. 69
2.8 Processing States............................................................................................................... 73
2.8.1 Overview.............................................................................................................. 73
2.8.2 Reset State............................................................................................................ 74
2.8.3 Exception-Handling State.................................................................................... 75
2.8.4 Program Execution State...................................................................................... 76
Rev. 4.00 Sep 27, 2006 page xxvi of xliv
2.8.5 Bus-Released State............................................................................................... 76
2.8.6 Power-Down State............................................................................................... 77
2.9 Basic Timing..................................................................................................................... 78
2.9.1 Overview.............................................................................................................. 78
2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 78
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 80
2.9.4 External Address Space Access Timing .............................................................. 81
2.10 Usage Note........................................................................................................................ 82
2.10.1 T AS Instruction .................................................................................................... 82
2.10.2 STM/LDM Instruction......................................................................................... 82
Section 3 MCU Operating Modes .................................................................................. 83
3.1 Overview........................................................................................................................... 83
3.1.1 Operating Mode Selection ................................................................................... 83
3.1.2 Register Configuration......................................................................................... 84
3.2 Register Descriptions........................................................................................................84
3.2.1 Mode Control Register (MDCR) ......................................................................... 84
3.2.2 System Control Register (SYSCR)...................................................................... 85
3.2.3 Bus Control Register (BCR)................................................................................ 87
3.2.4 Serial Timer Control Register (STCR) ................................................................ 88
3.3 Operating Mode Descriptions........................................................................................... 89
3.3.1 Mode 1................................................................................................................. 89
3.3.2 Mode 2................................................................................................................. 89
3.3.3 Mode 3................................................................................................................. 90
3.4 Pin Functions in Each Operating Mode............................................................................ 90
3.5 Memory Map in Each Operating Mode............................................................................ 91
Section 4 Exception Handling ......................................................................................... 103
4.1 Overview........................................................................................................................... 103
4.1.1 Exception Handling Types and Priority............................................................... 103
4.1.2 Exception Handling Operation............................................................................. 104
4.1.3 Exception Sources and Vector Table................................................................... 104
4.2 Reset.................................................................................................................................. 106
4.2.1 Overview.............................................................................................................. 106
4.2.2 Reset Sequence.................................................................................................... 106
4.2.3 Interrupts after Reset............................................................................................ 108
4.3 Interrupts........................................................................................................................... 109
4.4 Trap Instruction................................................................................................................. 110
4.5 Stack Status after Exception Handling.............................................................................. 111
4.6 Notes on Use of the Stack................................................................................................. 112
Rev. 4.00 Sep 27, 2006 page xxvii of xliv
Section 5 Interrupt Controller.......................................................................................... 113
5.1 Overview........................................................................................................................... 113
5.1.1 Features................................................................................................................ 113
5.1.2 Block Diagram..................................................................................................... 114
5.1.3 Pin Configuration................................................................................................. 115
5.1.4 Register Configuration......................................................................................... 116
5.2 Register Descriptions........................................................................................................ 117
5.2.1 System Control Register (SYSCR)...................................................................... 117
5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 118
5.2.3 IRQ Enable Register (IER).................................................................................. 119
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 119
5.2.5 IRQ Status Register (ISR).................................................................................... 120
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 122
5.2.7 Keyboard Matrix Interrupt Mask Register (KMIMRA)....................................... 122
5.2.8 Address Break Control Register (ABRKCR)....................................................... 124
5.2.9 Break Address Registers A, B, C (BARA, BARB, BARC)................................. 125
5.3 Interrupt Sources............................................................................................................... 126
5.3.1 External Interrupts ............................................................................................... 126
5.3.2 Internal Interrupts................................................................................................. 128
5.3.3 Interrupt Exception Vector Table ........................................................................ 128
5.4 Address Breaks ................................................................................................................. 132
5.4.1 Features................................................................................................................ 132
5.4.2 Block Diagram..................................................................................................... 132
5.4.3 Operation ............................................................................................................. 133
5.4.4 Usage Notes......................................................................................................... 133
5.5 Interrupt Operation............................................................................................................ 135
5.5.1 Interrupt Control Modes and Interrupt Operation................................................ 135
5.5.2 Interrupt Control Mode 0..................................................................................... 138
5.5.3 Interrupt Control Mode 1..................................................................................... 140
5.5.4 Interrupt Exception Handling Sequence .............................................................. 143
5.5.5 Interrupt Response Times.................................................................................... 145
5.6 Usage Notes ...................................................................................................................... 146
5.6.1 Contention between Interrupt Generation and Disabling..................................... 146
5.6.2 Instructions That Disable Interrupts..................................................................... 147
5.6.3 Interrupts during Execution of EEPMOV Instruction.......................................... 147
5.7 DTC Activation by Interrupt............................................................................................. 148
5.7.1 Overview.............................................................................................................. 148
5.7.2 Block Diagram..................................................................................................... 148
5.7.3 Operation ............................................................................................................. 149
Rev. 4.00 Sep 27, 2006 page xxviii of xliv
Section 6 Bus Controller ................................................................................................... 151
6.1 Overview........................................................................................................................... 151
6.1.1 Features................................................................................................................ 151
6.1.2 Block Diagram..................................................................................................... 152
6.1.3 Pin Configuration................................................................................................. 153
6.1.4 Register Configuration......................................................................................... 153
6.2 Register Descriptions........................................................................................................ 154
6.2.1 Bus Control Register (BCR)................................................................................ 154
6.2.2 Wait State Control Register (WSCR) .................................................................. 155
6.3 Overview of Bus Control.................................................................................................. 157
6.3.1 Bus Specifications................................................................................................ 157
6.3.2 Advanced Mode................................................................................................... 158
6.3.3 Normal Mode....................................................................................................... 158
6.3.4 I/O Select Signal.................................................................................................. 159
6.4 Basic Bus Interface........................................................................................................... 160
6.4.1 Overview.............................................................................................................. 160
6.4.2 Data Size and Data Alignment............................................................................. 160
6.4.3 Valid Strobes........................................................................................................ 162
6.4.4 Basic Timing........................................................................................................ 163
6.4.5 Wait Control ........................................................................................................ 171
6.5 Burst ROM Interface......................................................................................................... 173
6.5.1 Overview.............................................................................................................. 173
6.5.2 Basic Timing........................................................................................................ 173
6.5.3 Wait Control ........................................................................................................ 175
6.6 Idle Cycle.......................................................................................................................... 175
6.6.1 Operation ............................................................................................................. 175
6.6.2 Pin States in Idle Cycle........................................................................................ 176
6.7 Bus Arbitration.................................................................................................................. 177
6.7.1 Overview.............................................................................................................. 177
6.7.2 Operation ............................................................................................................. 177
6.7.3 Bus Transfer Timing............................................................................................ 178
Section 7 Data Transfer Controller (DTC)................................................................... 179
7.1 Overview........................................................................................................................... 179
7.1.1 Features................................................................................................................ 179
7.1.2 Block Diagram..................................................................................................... 180
7.1.3 Register Configuration......................................................................................... 181
7.2 Register Descriptions........................................................................................................ 182
7.2.1 DTC Mode Register A (MRA) ............................................................................ 182
7.2.2 DTC Mode Register B (MRB)............................................................................. 184
7.2.3 DTC Source Address Register (SAR).................................................................. 185
Rev. 4.00 Sep 27, 2006 page xxix of xliv
7.2.4 DTC Destination Address Register (DAR).......................................................... 185
7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 186
7.2.6 DTC Transfer Count Register B (CRB)............................................................... 186
7.2.7 DTC Enable Registers (DTCER)......................................................................... 187
7.2.8 DTC Vector Register (DTVECR)........................................................................ 188
7.2.9 Module Stop Control Register (MSTPCR).......................................................... 189
7.3 Operation .......................................................................................................................... 189
7.3.1 Overview.............................................................................................................. 189
7.3.2 Activation Sources............................................................................................... 191
7.3.3 DTC Vector Table................................................................................................ 193
7.3.4 Location of Register Information in Address Space............................................ 195
7.3.5 Normal Mode....................................................................................................... 196
7.3.6 Repeat Mode........................................................................................................ 197
7.3.7 Block Transfer Mode........................................................................................... 198
7.3.8 Chain Transfer ..................................................................................................... 200
7.3.9 Operation Timing................................................................................................. 201
7.3.10 Number of DTC Execution States........................................................................ 202
7.3.11 Procedures for Using the DTC............................................................................. 204
7.3.12 Examples of Use of the DTC............................................................................... 205
7.4 Interrupts........................................................................................................................... 207
7.5 Usage Notes ...................................................................................................................... 207
Section 8 I/O Ports.............................................................................................................. 209
8.1 Overview........................................................................................................................... 209
8.2 Port 1................................................................................................................................. 221
8.2.1 Overview.............................................................................................................. 221
8.2.2 Register Configuration......................................................................................... 222
8.2.3 Pin Functions in Each Mode................................................................................ 224
8.2.4 MOS Input Pull-Up Function............................................................................... 226
8.3 Port 2................................................................................................................................. 226
8.3.1 Overview.............................................................................................................. 226
8.3.2 Register Configuration......................................................................................... 228
8.3.3 Pin Functions in Each Mode................................................................................ 230
8.3.4 MOS Input Pull-Up Function............................................................................... 232
8.4 Port 3................................................................................................................................. 233
8.4.1 Overview.............................................................................................................. 233
8.4.2 Register Configuration......................................................................................... 234
8.4.3 Pin Functions in Each Mode................................................................................ 236
8.4.4 MOS Input Pull-Up Function............................................................................... 237
8.5 Port 4................................................................................................................................. 238
8.5.1 Overview.............................................................................................................. 238
Rev. 4.00 Sep 27, 2006 page xxx of xliv
8.5.2 Register Configuration......................................................................................... 238
8.5.3 Pin Functions ....................................................................................................... 239
8.6 Port 5................................................................................................................................. 243
8.6.1 Overview.............................................................................................................. 243
8.6.2 Register Configuration......................................................................................... 243
8.6.3 Pin Functions ....................................................................................................... 245
8.7 Port 6................................................................................................................................. 246
8.7.1 Overview.............................................................................................................. 246
8.7.2 Register Configuration......................................................................................... 247
8.7.3 Pin Functions ....................................................................................................... 250
8.7.4 MOS Input Pull-Up Function............................................................................... 252
8.8 Port 7................................................................................................................................. 253
8.8.1 Overview.............................................................................................................. 253
8.8.2 Register Configuration......................................................................................... 253
8.8.3 Pin Functions ....................................................................................................... 254
8.9 Port 8................................................................................................................................. 255
8.9.1 Overview.............................................................................................................. 255
8.9.2 Register Configuration......................................................................................... 255
8.9.3 Pin Functions ....................................................................................................... 256
8.10 Port 9................................................................................................................................. 259
8.10.1 Overview.............................................................................................................. 259
8.10.2 Register Configuration......................................................................................... 260
8.10.3 Pin Functions ....................................................................................................... 261
8.11 Port A................................................................................................................................ 265
8.11.1 Overview.............................................................................................................. 265
8.11.2 Register Configuration......................................................................................... 266
8.11.3 Pin Functions ....................................................................................................... 267
8.11.4 MOS Input Pull-Up Function............................................................................... 271
8.12 Port B..................................................................................................................... ........... 272
8.12.1 Overview.............................................................................................................. 272
8.12.2 Register Configuration......................................................................................... 273
8.12.3 Pin Functions ....................................................................................................... 275
8.12.4 MOS Input Pull-Up Function............................................................................... 278
Section 9 8-Bit PWM Timers........................................................................................... 279
9.1 Overview........................................................................................................................... 279
9.1.1 Features................................................................................................................ 279
9.1.2 Block Diagram..................................................................................................... 280
9.1.3 Pin Configuration................................................................................................. 281
9.1.4 Register Configuration......................................................................................... 281
9.2 Register Descriptions........................................................................................................ 282
Rev. 4.00 Sep 27, 2006 page xxxi of xliv
9.2.1 PWM Register Select (PWSL)............................................................................. 282
9.2.2 PWM Data Registers (PWDR0 to PWDR15)...................................................... 284
9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 284
9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB)................. 285
9.2.5 Peripheral Clock Select Register (PCSR)............................................................ 286
9.2.6 Port 1 Data Direction Register (P1DDR)............................................................. 286
9.2.7 Port 2 Data Direction Register (P2DDR)............................................................. 287
9.2.8 Port 1 Data Register (P1DR)................................................................................ 287
9.2.9 Port 2 Data Register (P2DR)................................................................................ 287
9.2.10 Module Stop Control Register (MSTPCR).......................................................... 288
9.3 Operation .......................................................................................................................... 289
9.3.1 Correspondence between PWM Data Register Contents
and Output Waveform.......................................................................................... 289
Section 10 14-Bit PWM Timer (PWMX)..................................................................... 291
10.1 Overview........................................................................................................................... 291
10.1.1 Features................................................................................................................ 291
10.1.2 Block Diagram..................................................................................................... 292
10.1.3 Pin Configuration................................................................................................. 293
10.1.4 Register Configuration......................................................................................... 293
10.2 Register Descriptions........................................................................................................ 294
10.2.1 PWM (D/A) Counter (DACNT).......................................................................... 294
10.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 295
10.2.3 PWM D/A Control Register (DACR).................................................................. 296
10.2.4 Module Stop Control Register (MSTPCR).......................................................... 298
10.3 Bus Master Interface......................................................................................................... 299
10.4 Operation .......................................................................................................................... 302
Section 11 16-Bit Free-Running Timer......................................................................... 307
11.1 Overview........................................................................................................................... 307
11.1.1 Features................................................................................................................ 307
11.1.2 Block Diagram..................................................................................................... 308
11.1.3 Input and Output Pins.......................................................................................... 309
11.1.4 Register Configuration......................................................................................... 310
11.2 Register Descriptions........................................................................................................ 311
11.2.1 Free-Running Counter (FRC) .............................................................................. 311
11.2.2 Output Compare Registers A and B (OCRA, OCRB)......................................... 311
11.2.3 Input Capture Registers A to D (ICRA to ICRD)................................................ 312
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF)............................... 313
11.2.5 Output Compare Register DM (OCRDM)........................................................... 314
11.2.6 T imer Interrupt Enable Register (TIER).............................................................. 314
Rev. 4.00 Sep 27, 2006 page xxxii of xliv
11.2.7 T imer Control/Status Register (TCSR)................................................................ 316
11.2.8 T imer Control Register (TCR)............................................................................. 319
11.2.9 T imer Output Compare Control Register (TOCR) .............................................. 321
11.2.10 Module Stop Control Register (MSTPCR).......................................................... 324
11.3 Operation .......................................................................................................................... 325
11.3.1 FRC Increment Timing........................................................................................ 325
11.3.2 Output Compare Output Timing.......................................................................... 326
11.3.3 FRC Clear Timing................................................................................................ 327
11.3.4 Input Capture Input Timing................................................................................. 327
11.3.5 T iming of Input Capture Flag (ICF) Setting ........................................................ 329
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)................................ 330
11.3.7 Setting of FRC Overflow Flag (OVF) ................................................................. 331
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF ......................................... 331
11.3.9 ICRD and OCRDM Mask Signal Generation...................................................... 332
11.4 Interrupts........................................................................................................................... 333
11.5 Sample Application........................................................................................................... 334
11.6 Usage Notes...................................................................................................................... 335
Section 12 8-Bit Timers..................................................................................................... 341
12.1 Overview........................................................................................................................... 341
12.1.1 Features................................................................................................................ 341
12.1.2 Block Diagram..................................................................................................... 342
12.1.3 Pin Configuration................................................................................................. 343
12.1.4 Register Configuration......................................................................................... 344
12.2 Register Descriptions........................................................................................................ 345
12.2.1 Timer Counter (TCNT)........................................................................................ 345
12.2.2 T ime Constant Register A (TCORA)................................................................... 346
12.2.3 Time Constant Register B (TCORB)................................................................... 347
12.2.4 T imer Control Register (TCR)............................................................................. 348
12.2.5 T imer Control/Status Register (TCSR)................................................................ 352
12.2.6 Serial/Timer Control Register (STCR) ................................................................ 356
12.2.7 System Control Register (SYSCR)...................................................................... 357
12.2.8 Timer Connection Register S (TCONRS) ............................................................ 357
12.2.9 I nput Capture Register (TICR) [TMRX Additional Function]............................ 358
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]................... 359
12.2.11 Input Capture Registers R and F (TICRR, TICRF)
[TMRX Additional Functions]............................................................................. 359
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]..................... 360
12.2.13 Module Stop Control Register (MSTPCR).......................................................... 361
12.3 Operation .......................................................................................................................... 362
12.3.1 T CNT Incrementation Timing............................................................................. 362
Rev. 4.00 Sep 27, 2006 page xxxiii of xliv
12.3.2 Compare-Match Timing....................................................................................... 363
12.3.3 T CNT External Reset Timing.............................................................................. 364
12.3.4 Timing of Overflow Flag (OVF) Setting............................................................. 365
12.3.5 Operation with Cascaded Connection.................................................................. 365
12.3.6 I nput Capture Operation ...................................................................................... 367
12.4 Interrupt Sources............................................................................................................... 369
12.5 8-Bit Timer Application Example..................................................................................... 370
12.6 Usage Notes...................................................................................................................... 371
12.6.1 Contention between TCNT Write and Clear........................................................ 371
12.6.2 Contention between TCNT Write and Increment................................................ 372
12.6.3 Contention between TCOR Write and Compare-Match...................................... 373
12.6.4 Contention between Compare-Matches A and B................................................. 374
12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 374
Section 13 Timer Connection........................................................................................... 377
13.1 Overview........................................................................................................................... 377
13.1.1 Features................................................................................................................ 377
13.1.2 Block Diagram..................................................................................................... 377
13.1.3 Input and Output Pins.......................................................................................... 379
13.1.4 Register Configuration......................................................................................... 380
13.2 Register Descriptions........................................................................................................ 380
13.2.1 Timer Connection Register I (TCONRI) ............................................................. 380
13.2.2 T imer Connection Register O (TCONRO).......................................................... 383
13.2.3 Timer Connection Register S (TCONRS) ............................................................ 385
13.2.4 E dge Sense Register (SEDGR)............................................................................ 387
13.2.5 Module Stop Control Register (MSTPCR).......................................................... 390
13.3 Operation .......................................................................................................................... 391
13.3.1 PWM Decoding (PDC Signal Generation) .......................................................... 391
13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)..................... 393
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 394
13.3.4 IHI Signal and 2fH Modification......................................................................... 396
13.3.5 IVI Signal Fall Modification and IHI Synchronization ....................................... 398
13.3.6 Internal Synchronization Signal Generation
(IHG/IVG/CL4 Signal Generation) ..................................................................... 400
13.3.7 HSYNCO Output................................................................................................. 403
13.3.8 VSYNCO Output................................................................................................. 404
13.3.9 CBLANK Output................................................................................................. 405
Section 14 Watchdog Timer (WDT).............................................................................. 407
14.1 Overview........................................................................................................................... 407
14.1.1 Features................................................................................................................ 407
Rev. 4.00 Sep 27, 2006 page xxxiv of xliv
14.1.2 Block Diagram..................................................................................................... 408
14.1.3 Pin Configuration................................................................................................. 409
14.1.4 Register Configuration......................................................................................... 410
14.2 Register Descriptions........................................................................................................ 410
14.2.1 Timer Counter (TCNT)........................................................................................ 410
14.2.2 T imer Control/Status Register (TCSR)................................................................ 411
14.2.3 System Control Register (SYSCR)...................................................................... 414
14.2.4 Notes on Register Access..................................................................................... 415
14.3 Operation .......................................................................................................................... 416
14.3.1 Watchdog Timer Operation ................................................................................. 416
14.3.2 I nterval Timer Operation ..................................................................................... 417
14.3.3 T iming of Setting of Overflow Flag (OVF)......................................................... 418
14.3.4 RESO Signal Output Timing ............................................................................... 419
14.4 Interrupts........................................................................................................................... 419
14.5 Usage Notes...................................................................................................................... 420
14.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 420
14.5.2 Changing Value of CKS2 to CKS0...................................................................... 420
14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 421
14.5.4 System Reset by RESO Signal............................................................................. 421
14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode,
and Watch Mode.................................................................................................. 421
14.5.6 OVF Flag Clear Condition................................................................................... 422
Section 15 Serial Communication Interface (SCI, IrDA)........................................ 423
15.1 Overview........................................................................................................................... 423
15.1.1 Features................................................................................................................ 423
15.1.2 Block Diagram..................................................................................................... 425
15.1.3 Pin Configuration................................................................................................. 426
15.1.4 Register Configuration......................................................................................... 426
15.2 Register Descriptions........................................................................................................ 428
15.2.1 Receive Shift Register (RSR) .............................................................................. 428
15.2.2 Receive Data Register (RDR).............................................................................. 428
15.2.3 Transmit Shift Register (TSR)............................................................................. 429
15.2.4 T ransmit Data Register (TDR)............................................................................. 429
15.2.5 Serial Mode Register (SMR)................................................................................ 430
15.2.6 Serial Control Register (SCR).............................................................................. 433
15.2.7 Serial Status Register (SSR) ................................................................................ 436
15.2.8 Bit Rate Register (BRR) ...................................................................................... 441
15.2.9 Serial Interface Mode Register (SCMR).............................................................. 449
15.2.10 Module Stop Control Register (MSTPCR).......................................................... 450
15.2.11 Keyboard Comparator Control Register (KBCOMP).......................................... 452
Rev. 4.00 Sep 27, 2006 page xxxv of xliv
15.3 Operation .......................................................................................................................... 453
15.3.1 Overview.............................................................................................................. 453
15.3.2 Operation in Asynchronous Mode....................................................................... 455
15.3.3 Multiprocessor Communication Function............................................................ 466
15.3.4 Operation in Synchronous Mode ......................................................................... 474
15.3.5 I rDA Operation.................................................................................................... 483
15.4 SCI Interrupts.................................................................................................................... 486
15.5 Usage Notes...................................................................................................................... 487
Section 16 I2C Bus Interface [Option]........................................................................... 491
16.1 Overview........................................................................................................................... 491
16.1.1 Features................................................................................................................ 491
16.1.2 Block Diagram..................................................................................................... 492
16.1.3 I nput/Output Pins................................................................................................. 494
16.1.4 Register Configuration......................................................................................... 495
16.2 Register Descriptions........................................................................................................ 496
16.2.1 I2C Bus Data Register (ICDR) ............................................................................. 496
16.2.2 Slave Address Register (SAR)............................................................................. 499
16.2.3 Second Slave Address Register (SARX) ............................................................. 500
16.2.4 I2C Bus Mode Register (ICMR)........................................................................... 501
16.2.5 I2C Bus Control Register (ICCR)......................................................................... 504
16.2.6 I2C Bus Status Register (ICSR)............................................................................ 511
16.2.7 Serial/Timer Control Register (STCR) ................................................................ 516
16.2.8 DDC Swi tch Register (DDCSWR)...................................................................... 518
16.2.9 Module Stop Control Register (MSTPCR).......................................................... 520
16.3 Operation .......................................................................................................................... 521
16.3.1 I2C Bus Data Format............................................................................................ 521
16.3.2 Master Transmit Operation.................................................................................. 523
16.3.3 Master Receive Operation.................................................................................... 525
16.3.4 Slave Receive Operation...................................................................................... 528
16.3.5 Slave Transmit Operation .................................................................................... 531
16.3.6 I RIC Setting Timing and SCL Control ................................................................ 533
16.3.7 Automatic Switching from Formatless Mode to I2C Bus Format ........................ 534
16.3.8 Operation Using the DTC.................................................................................... 535
16.3.9 Noise Canceler..................................................................................................... 536
16.3.10 Sample Flowcharts............................................................................................... 536
16.3.11 Initialization of Internal State .............................................................................. 541
16.4 Usage Notes...................................................................................................................... 542
Section 17 Keyboard Buffer Controller........................................................................ 559
17.1 Overview........................................................................................................................... 559
Rev. 4.00 Sep 27, 2006 page xxxvi of xliv
17.1.1 Features................................................................................................................ 559
17.1.2 Block Diagram..................................................................................................... 561
17.1.3 I nput/Output Pins................................................................................................. 562
17.1.4 Register Configuration......................................................................................... 562
17.2 Register Descriptions........................................................................................................ 563
17.2.1 Keyboard Control Register H (KBCRH)............................................................. 563
17.2.2 Keyboard Control Register L (KBCRL).............................................................. 565
17.2.3 Keyboard Data Buffer Register (KBBR)............................................................. 567
17.2.4 Module Stop Control Register (MSTPCR).......................................................... 567
17.3 Operation .......................................................................................................................... 568
17.3.1 Receive Operation................................................................................................ 568
17.3.2 T ransmit Operation.............................................................................................. 570
17.3.3 Receive Abort ...................................................................................................... 573
17.3.4 KCLKI and KDI Read Timing............................................................................. 576
17.3.5 KCLKO and KDO Write Timing......................................................................... 577
17.3.6 KBF Setting Timing and KCLK Control............................................................. 578
17.3.7 Receive Timing.................................................................................................... 579
17.3.8 KCLK Fall Interrupt Operation............................................................................ 580
17.3.9 Usage Note........................................................................................................... 581
Section 18 Host Interface.................................................................................................. 583
18.1 Overview........................................................................................................................... 583
18.1.1 Features................................................................................................................ 583
18.1.2 Block Diagram..................................................................................................... 584
18.1.3 Input and Output Pins.......................................................................................... 585
18.1.4 Register Configuration......................................................................................... 586
18.2 Register Descriptions........................................................................................................ 587
18.2.1 System Control Register (SYSCR)...................................................................... 587
18.2.2 System Control Register 2 (SYSCR2)................................................................. 588
18.2.3 Host Interface Control Register (HICR) .............................................................. 590
18.2.4 I nput Data Register 1 (IDR1)............................................................................... 592
18.2.5 Output Data Register 1 (ODR)............................................................................. 592
18.2.6 Status Register (STR) .......................................................................................... 593
18.2.7 Module Stop Control Register (MSTPCR).......................................................... 595
18.3 Operation .......................................................................................................................... 595
18.3.1 Host Interface Activation..................................................................................... 595
18.3.2 Control States....................................................................................................... 597
18.3.3 A20 Gate.............................................................................................................. 597
18.3.4 Host Interface Pin Shutdown Function................................................................ 599
18.4 Interrupts........................................................................................................................... 601
18.4.1 I BF1, IBF2, IBF3, IBF4....................................................................................... 601
Rev. 4.00 Sep 27, 2006 page xxxvii of xliv
18.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4................................................ 601
18.5 Usage Note........................................................................................................................ 603
Section 19 D/A Converter................................................................................................. 605
19.1 Overview........................................................................................................................... 605
19.1.1 Features................................................................................................................ 605
19.1.2 Block Diagram..................................................................................................... 606
19.1.3 Input and Output Pins.......................................................................................... 607
19.1.4 Register Configuration......................................................................................... 607
19.2 Register Descriptions........................................................................................................ 608
19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 608
19.2.2 D/A Control Register (DACR) ............................................................................ 608
19.2.3 Module Stop Control Register (MSTPCR).......................................................... 610
19.3 Operation .......................................................................................................................... 611
Section 20 A/D Converter................................................................................................. 613
20.1 Overview........................................................................................................................... 613
20.1.1 Features................................................................................................................ 613
20.1.2 Block Diagram..................................................................................................... 614
20.1.3 Pin Configuration................................................................................................. 615
20.1.4 Register Configuration......................................................................................... 616
20.2 Register Descriptions........................................................................................................ 616
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 616
20.2.2 A/D Control/Status Register (ADCSR) ............................................................... 617
20.2.3 A/D Control Register (ADCR) ............................................................................ 620
20.2.4 Keyboard Comparator Control Register (KBCOMP).......................................... 621
20.2.5 Module Stop Control Register (MSTPCR).......................................................... 622
20.3 Interface to Bus Master..................................................................................................... 623
20.4 Operation .......................................................................................................................... 624
20.4.1 Single Mode (SCAN = 0) .................................................................................... 624
20.4.2 Scan Mode (SCAN = 1)....................................................................................... 626
20.4.3 Input Sampling and A/D Conversion Time ......................................................... 628
20.4.4 External Trigger Input Timing............................................................................. 629
20.5 Interrupts........................................................................................................................... 629
20.6 Usage Notes...................................................................................................................... 630
Section 21 RAM .................................................................................................................. 635
21.1 Overview........................................................................................................................... 635
21.1.1 Block Diagram..................................................................................................... 635
21.1.2 Register Configuration......................................................................................... 636
21.2 System Control Register (SYSCR)................................................................................... 636
Rev. 4.00 Sep 27, 2006 page xxxviii of xliv
21.3 Operation .......................................................................................................................... 637
21.3.1 Expanded Mode (Modes 1, 2, 3 (EXPE = 1))...................................................... 637
21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0))................................................. 637
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT,
H8S/2147N F-ZTAT, H8S/2144 F-ZTAT,
and H8S/2142 F-ZTAT)............................................................................... 639
22.1 Overview........................................................................................................................... 639
22.1.1 Block Diagram..................................................................................................... 639
22.1.2 Register Configuration......................................................................................... 640
22.2 Register Descriptions........................................................................................................ 640
22.2.1 Mode Control Register (MDCR) ......................................................................... 640
22.3 Operation .......................................................................................................................... 641
22.4 Overview of Flash Memory.............................................................................................. 642
22.4.1 Features................................................................................................................ 642
22.4.2 Block Diagram..................................................................................................... 643
22.4.3 Flash Memory Operating Modes ......................................................................... 644
22.4.4 Pin Configuration................................................................................................. 648
22.4.5 Register Configuration......................................................................................... 648
22.5 Register Descriptions........................................................................................................ 649
22.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 649
22.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 651
22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 653
22.5.4 Serial/Timer Control Register (STCR) ................................................................ 654
22.6 On-Board Programming Modes........................................................................................ 655
22.6.1 Boot Mode ........................................................................................................... 656
22.6.2 User Program Mode............................................................................................. 661
22.7 Programming/Erasing Flash Memory............................................................................... 662
22.7.1 Program Mode ..................................................................................................... 662
22.7.2 Program-Verify Mode.......................................................................................... 663
22.7.3 E rase Mode.......................................................................................................... 665
22.7.4 Erase-Verify Mode .............................................................................................. 665
22.8 Flash Memory Protection.................................................................................................. 667
22.8.1 Hardware Protection ............................................................................................ 667
22.8.2 Software Protection.............................................................................................. 667
22.8.3 E rror Protection .................................................................................................... 668
22.9 Interrupt Handling when Programming/Erasing Flash Memory....................................... 670
22.10 Flash Memory Programmer Mode.................................................................................... 671
22.10.1 Programmer Mode Setting................................................................................... 671
22.10.2 Socket Adapters and Memory Map ..................................................................... 672
22.10.3 Programmer Mode Operation.............................................................................. 672
Rev. 4.00 Sep 27, 2006 page xxxix of xliv
22.10.4 Memory Read Mode............................................................................................ 673
22.10.5 Auto-Program Mode............................................................................................ 677
22.10.6 Auto-Erase Mode................................................................................................. 679
22.10.7 Status Read Mode................................................................................................ 680
22.10.8 Status Polling....................................................................................................... 681
22.10.9 Programmer Mode Transition Time .................................................................... 682
22.10.10 Notes on Memory Programming...................................................................... 683
22.11 Flash Memory Programming and Erasing Precautions..................................................... 683
22.12 Note on Switching from F-ZTAT Version to Mask ROM Version.................................. 684
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version,
H8S/2147 F-ZTAT A-Mask Version,
H8S/2144 F-ZTAT A-Mask Version)...................................................... 685
23.1 Overview........................................................................................................................... 685
23.1.1 Block Diagram..................................................................................................... 685
23.1.2 Register Configuration......................................................................................... 686
23.2 Register Descriptions........................................................................................................ 686
23.2.1 Mode Control Register (MDCR) ......................................................................... 686
23.3 Operation .......................................................................................................................... 687
23.4 Overview of Flash Memory.............................................................................................. 688
23.4.1 Features................................................................................................................ 688
23.4.2 Block Diagram..................................................................................................... 689
23.4.3 Flash Memory Operating Modes ......................................................................... 690
23.4.4 Pin Configuration................................................................................................. 694
23.4.5 Register Configuration......................................................................................... 694
23.5 Register Descriptions........................................................................................................ 695
23.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 695
23.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 697
23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 699
23.5.4 Serial/Timer Control Register (STCR) ................................................................ 700
23.6 On-Board Programming Modes........................................................................................ 701
23.6.1 Boot Mode ........................................................................................................... 702
23.6.2 User Program Mode............................................................................................. 707
23.7 Programming/Erasing Flash Memory............................................................................... 708
23.7.1 Program Mode ..................................................................................................... 708
23.7.2 Program-Verify Mode.......................................................................................... 709
23.7.3 E rase Mode.......................................................................................................... 711
23.7.4 Erase-Verify Mode .............................................................................................. 711
23.8 Flash Memory Protection.................................................................................................. 713
23.8.1 Hardware Protection ............................................................................................ 713
23.8.2 Software Protection.............................................................................................. 713
Rev. 4.00 Sep 27, 2006 page xl of xliv
23.8.3 E rror Protection .................................................................................................... 714
23.9 Interrupt Handling when Programming/Erasing Flash Memory....................................... 716
23.10 Flash Memory Programmer Mode.................................................................................... 717
23.10.1 Programmer Mode Setting................................................................................... 717
23.10.2 Socket Adapters and Memory Map ..................................................................... 718
23.10.3 Programmer Mode Operation.............................................................................. 718
23.10.4 Memory Read Mode............................................................................................ 719
23.10.5 Auto-Program Mode............................................................................................ 723
23.10.6 Auto-Erase Mode................................................................................................. 725
23.10.7 Status Read Mode................................................................................................ 726
23.10.8 Status Polling....................................................................................................... 727
23.10.9 Programmer Mode Transition Time .................................................................... 728
23.10.10 Notes on Memory Programming...................................................................... 729
23.11 Flash Memory Programming and Erasing Precautions..................................................... 729
23.12 Note on Switching from F-ZTAT Version to Mask ROM Version.................................. 730
Section 24 Clock Pulse Generator.................................................................................. 731
24.1 Overview........................................................................................................................... 731
24.1.1 Block Diagram..................................................................................................... 731
24.1.2 Register Configuration......................................................................................... 732
24.2 Register Descriptions........................................................................................................ 732
24.2.1 Standby Control Register (SBYCR) .................................................................... 732
24.2.2 L ow-Power Control Register (LPWRCR)........................................................... 733
24.3 Oscillator........................................................................................................................... 734
24.3.1 Connecting a Crystal Resonator ........................................................................... 734
24.3.2 External Clock Input............................................................................................ 736
24.4 Duty Adjustment Circuit................................................................................................... 739
24.5 Medium-Speed Clock Divider.......................................................................................... 739
24.6 Bus Master Clock Selection Circuit.................................................................................. 739
24.7 Subclock Input Circuit...................................................................................................... 739
24.8 Subclock Waveform Shaping Circuit................................................................................ 740
24.9 Clock Selection Circuit..................................................................................................... 741
Section 25 Power-Down State......................................................................................... 743
25.1 Overview........................................................................................................................... 743
25.1.1 Register Configuration......................................................................................... 747
25.2 Register Descriptions........................................................................................................ 747
25.2.1 Standby Control Register (SBYCR) .................................................................... 747
25.2.2 L ow-Power Control Register (LPWRCR)........................................................... 749
25.2.3 T imer Control/Status Register (TCSR)................................................................ 751
25.2.4 Module Stop Control Register (MSTPCR).......................................................... 752
Rev. 4.00 Sep 27, 2006 page xli of xliv
25.3 Medium-Speed Mode........................................................................................................ 753
25.4 Sleep Mode ....................................................................................................................... 754
25.4.1 Sleep Mode .......................................................................................................... 754
25.4.2 Clearing Sleep Mode............................................................................................ 754
25.5 Module Stop Mode ........................................................................................................... 755
25.5.1 Module Stop Mode .............................................................................................. 755
25.5.2 Usage Note........................................................................................................... 756
25.6 Software Standby Mode.................................................................................................... 757
25.6.1 Software Standby Mode....................................................................................... 757
25.6.2 Clearing Software Standby Mode........................................................................ 757
25.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode .......... 757
25.6.4 Software Standby Mode Application Example.................................................... 758
25.6.5 Usage Note........................................................................................................... 759
25.7 Hardware Standby Mode .................................................................................................. 759
25.7.1 Hardware Standby Mode ..................................................................................... 759
25.7.2 Hardware Standby Mode Timing......................................................................... 760
25.8 Watch Mode...................................................................................................................... 761
25.8.1 Watch Mode......................................................................................................... 761
25.8.2 Clearing Watch Mode.......................................................................................... 761
25.9 Subsleep Mode.................................................................................................................. 762
25.9.1 Subsleep Mode..................................................................................................... 762
25.9.2 Clearing Subsleep Mode...................................................................................... 762
25.10 Subactive Mode ................................................................................................................ 763
25.10.1 Subactive Mode ................................................................................................... 763
25.10.2 Clearing Subactive Mode ..................................................................................... 763
25.11 Direct Transition............................................................................................................... 764
25.11.1 Overview of Direct Transition............................................................................. 764
25.12 Usage Notes...................................................................................................................... 764
Section 26 Electrical Characteristics.............................................................................. 765
26.1 Voltage of Power Supply and Operating Range ............................................................... 765
26.2 Electrical Characteristics of H8S/2148 F-ZTAT............................................................... 768
26.2.1 Absolute Maximum Ratings ................................................................................ 768
26.2.2 DC Characteristics............................................................................................... 769
26.2.3 AC Characteristics............................................................................................... 784
26.2.4 A/D Conversion Characteristics........................................................................... 796
26.2.5 D/A Conversion Characteristics........................................................................... 798
26.2.6 Flash Memory Characteristics ............................................................................. 799
26.2.7 Usage Note........................................................................................................... 800
Rev. 4.00 Sep 27, 2006 page xlii of xliv
26.3 Electrical Characteristics of H8S/2148 F-ZTAT (A-mask version),
H8S/2147 F-ZTAT (A-mask version), and Mask ROM Versions of H8S/2148
and H8S/2147.................................................................................................................... 802
26.3.1 Absolute Maximum Ratings ................................................................................ 802
26.3.2 DC Characteristics............................................................................................... 804
26.3.3 AC Characteristics............................................................................................... 818
26.3.4 A/D Conversion Characteristics........................................................................... 830
26.3.5 D/A Conversion Characteristics........................................................................... 832
26.3.6 Flash Memory Characteristics ............................................................................. 832
26.3.7 Usage Note........................................................................................................... 835
26.4 Electrical Characteristics of H8S/2147N F-ZTAT............................................................ 836
26.4.1 Absolute Maximum Ratings ................................................................................ 836
26.4.2 DC Characteristics............................................................................................... 837
26.4.3 AC Characteristics............................................................................................... 847
26.4.4 A/D Conversion Characteristics........................................................................... 859
26.4.5 D/A Conversion Characteristics........................................................................... 861
26.4.6 Flash Memory Characteristics ............................................................................. 862
26.4.7 Usage Note........................................................................................................... 863
26.5 Electrical Characteristics of H8S/2144 F-ZTAT, H8S/2142 F-ZTAT,
and Mask ROM Version of H8S/2142.............................................................................. 864
26.5.1 Absolute Maximum Ratings ................................................................................ 864
26.5.2 DC Characteristics............................................................................................... 865
26.5.3 AC Characteristics............................................................................................... 875
26.5.4 A/D Conversion Characteristics........................................................................... 882
26.5.5 D/A Conversion Characteristics........................................................................... 884
26.5.6 Flash Memory Characteristics ............................................................................. 885
26.5.7 Usage Note........................................................................................................... 886
26.6 Electrical Characteristics of H8S/2144 F-ZTAT (A-mask version)
and Mask ROM Versions of H8S/2144 and H8S/2143 .................................................... 887
26.6.1 Absolute Maximum Ratings ................................................................................ 887
26.6.2 DC Characteristics............................................................................................... 888
26.6.3 AC Characteristics............................................................................................... 898
26.6.4 A/D Conversion Characteristics........................................................................... 905
26.6.5 D/A Conversion Characteristics........................................................................... 907
26.6.6 Flash Memory Characteristics ............................................................................. 907
26.6.7 Usage Note........................................................................................................... 910
26.7 Operational Timing........................................................................................................... 911
26.7.1 Test Conditions for the AC Characteristics.......................................................... 911
26.7.2 Clock Timing....................................................................................................... 911
26.7.3 Control Signal Timing ......................................................................................... 912
26.7.4 Bus Timing .......................................................................................................... 914
Rev. 4.00 Sep 27, 2006 page xliii of xliv
26.7.5 Timing of On-Chip Supporting Modules............................................................. 919
Appendix A Instruction Set.............................................................................................. 925
A.1 Instruction......................................................................................................................... 925
A.2 Instruction Codes.............................................................................................................. 943
A.3 Operation Code Map......................................................................................................... 957
A.4 Number of States Required for Execution ........................................................................ 961
A.5 Bus States during Instruction Execution........................................................................... 974
Appendix B Internal I/O Registers................................................................................. 990
B.1 Addresses.......................................................................................................................... 990
B.2 Register Selection Conditions........................................................................................... 997
B.3 Functions......................................................................................................................... 1004
Appendix C I/O Port Block Diagrams......................................................................... 1086
C.1 Port 1 Block Diagram ..................................................................................................... 1086
C.2 Port 2 Block Diagrams.................................................................................................... 1087
C.3 Port 3 Block Diagram ..................................................................................................... 1090
C.4 Port 4 Block Diagrams.................................................................................................... 1091
C.5 Port 5 Block Diagrams.................................................................................................... 1098
C.6 Port 6 Block Diagrams.................................................................................................... 1101
C.7 Port 7 Block Diagrams.................................................................................................... 1106
C.8 Port 8 Block Diagrams.................................................................................................... 1107
C.9 Port 9 Block Diagrams.................................................................................................... 1113
C.10 Port A Block Diagrams................................................................................................... 1118
C.11 Port B Block Diagram..................................................................................................... 1121
Appendix D Pin States..................................................................................................... 1124
D.1 Port States in Each Processing State............................................................................... 1124
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode............................................................................................ 1126
E.1 Timing of Transition to Hard ware Standby Mode.......................................................... 1126
E.2 Timing of Recovery from Hardware Standby Mode....................................................... 1126
Appendix F Product Code Lineup................................................................................ 1127
Appendix G Package Dimensions ................................................................................ 1129
Rev. 4.00 Sep 27, 2006 page xliv of xliv
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 1 of 1130
REJ09B0327-0400
Section 1 Overview
1.1 Overview
This LSI comp r ise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas
Technology proprietary architecture, and equipped with supporting modules on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU in structions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting modules required for system configuration include a data transfer controller
(DTC) bus master, ROM and RAM, a 16-bit free-running timer module (FRT), 8-bit timer module
(TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), serial
communication interface (SCI), PS/2-compatible keyboard buffer controller, host interface (HIF),
D/A converter (DAC), A/D converter (ADC), and I/O ports. An I2C bus interface (IIC) can also be
incorporated as an option.
The on-chip ROM is either f lash m emory (F-ZTAT™*) or mask ROM, with a capacity of 128, 96,
or 64 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word
data to be accessed in one state. Instruction fetching has been speeded up, and processing speed
increased.
Three operating modes, modes 1 to 3, are provided, and there is a choice of address space and
single-chip mode or externally expanded modes.
The features of this LSI are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 2 of 1130
REJ09B0327-0400
Table 1.1 Overview
Item Specifications
CPU • General-r egi ster arch ite ctur e
Sixteen 16-bit general registers (also usable as sixteen 8-bit
registers or eight 32-bit registers)
• High-speed operation suitable for real-time control
Maximum operating frequency: 20 MHz/5 V, 10 MHz/3 V
High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 50 ns (20-MHz operation)
16 × 16-bit register-register multiply: 1000 ns (20-MHz operation)
32 ÷ 16-bit register-register divide: 1000 ns (20-MHz operation)
• Instruction set suitable for high-speed operation
Sixty-five basic instructions
8/16/32-bit transfer/arithmetic and logic instructions
Unsigned/signed multiply and divide instructions
Powerful bit-manipu lati on instructions
• Two CPU operating modes
Normal mode: 64-kbyte address space
Advanced mode: 16-Mbyte address space
Operating modes • Three MCU operating modes
External Data Bus
Mode CPU Operating
Mode Description On-Chip
ROM Initial
Value Maximum
Value
1 Normal Expanded mode
with on-chip ROM
disabled
Disabled 8 bits 16 bits
2 Advanced Single-c hi p mode Enabled None None
Expanded mode
with on-chip ROM
enabled
Enabled 8 bi ts 16 bits
3 Normal Single-chip mode Enabled None None
Expanded mode
with on-chip ROM
enabled
Enabled 8 bi ts 16 bits
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 3 of 1130
REJ09B0327-0400
Item Specifications
Bus controller • 2-state or 3-state access space can be designated for external
expansion area s
• Number of program wait states can be set for external expansion areas
Data transfer
controller (DTC)
(H8S/2148 Group)
• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one
activat ion sour ce
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-bit free-running
timer module
(FRT: 1 channel)
• One 16-bit free-running counter (also usable for external event
counting)
• Two output compare out puts
• Four input capture inp uts (with buffer operati on cap abi lity)
8-bit timer module
(2 channels: TMR0,
TMR1)
Each channe l has:
• One 8-bit up-counter (also usable for external event counting)
• Two timer constant registers
• The two channels can be connected
Timer connection and
8-bit timer module
(TMR) (2 channels:
TMRX, TMRY)
(Timer connection and
TMRX provided in
H8S/2148 Group)
Input/output and FRT, TMR1, TMRX, TMRY can be interconnected
• Measurement of input signal or frequency-divided waveform pulse
width and cycle (FRT, TMR1)
• Output of waveform obtained by modification of input signal edge (FRT,
TMR1)
• Determinat ion of input signal duty cycle (TMRX)
• Output of waveform synchronized with input signal (FRT, TMRX,
TMRY)
• Automatic generation of cyclical waveform (FRT, TMRY)
Watchdog timer
module
(WDT: 2 channels)
• Watchdog timer or interval timer function selectable
• Subclock operation capability (channel 1 only)
8-bit PWM timer
(PWM)
(H8S/2148 Group and
H8S/2147N)
• Up to 16 outputs
• Pulse duty cycle settable from 0 to 100%
• Resolution: 1/256
• 1.25 MHz maximum carrier frequency (20-MHz operation)
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 4 of 1130
REJ09B0327-0400
Item Specifications
14-bit PWM timer
(PWMX) • Up to 2 outputs
• Resolution: 1/16384
• 312.5 kHz maximum carrier frequency (20-MHz operation)
Serial communi cat ion
interface
(SCI: 2 channels,
SCI0 and SCI1)
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
SCI with IrDA:
1 channel (SCI2) • Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Compatible with IrDA specification version 1.0
• TxD and RxD encoding /decoding in IrDA fo rmat
Keyboard buffer
controller (PS2:
3 channels)
(H8S/2148 Group,
H8S/2147N)
• Compatible with PS/2 interface
• Direct manipulation of transmission output by software
• Receive data input to 8-bit shift register
• Data receive com ple ted interr upt, pari ty error dete ctio n, stop bit
monitoring
Host interface (HIF)
(H8S/2148 Group,
H8S/2147N)
• 8-bit host interface (ISA) port
• Five host interrupt requests (HIRQ11, HIRQ1, HIRQ12, HIRQ3,
HIRQ4)
• Normal and fast A20 gate output
• Four register sets (eac h comprising two data registers and two status
registers)
Keyboard contr oll er • Matrix keyboard control using keyboard scan with wakeup interrupt and
sense port configuration
A/D converter • Resolution: 10 bits
• Input:
8 channels (dedicated analog pins)
16 channels (same pins as keyboard sense port)
• High-speed conversion: 6.7 µs minimum conversion time (20-MHz
operation)
• Single or scan mode selectable
• Sample-and-hold function
• A/D conversion can be activated by external trigger or timer trigger
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 5 of 1130
REJ09B0327-0400
Item Specifications
D/A converter • Resolution : 8 bits
• Output: 2 channels
I/O ports • 74 input/output pins (including 24 with LED drive capability)
• 8 input-only pins
• VCCB (separate power supply) drive pins among I/O pins (H8S/2148
Group and H8S/2147N)
Memory • Flash memory or mask ROM
• High-speed static RAM
Product Name ROM RAM
H8S/2144, H8S/ 2148 128 k bytes 4 kbytes
H8S/2143 96 kbytes 4 kbytes
H8S/2142, H8S/ 2147,
H8S/2147N 64 kbytes 2 kbytes
Interrupt controller • Nine external interr upt pin s (NMI, IRQ0 to IRQ7)
• 44 internal interrupt sources
• Three priority le vel s setta ble
Power-down state • Medium-speed mode
• Sleep mode
• Module stop mode
• Software standb y mode
• Hardware stan dby mode
• Subclock operation
Clock pulse generator • Built-in duty correcti on circuit
Packages • 100-pin plastic QFP (FP-100B)
• 100-pin plastic TQFP (TFP-100B)
I2C bus interface
(IIC: 2 channels)
(option in H8S/2148
Group and
H8S/2147N)
• Conforms to Philips I2C bus interfa ce stan dard
• Single master mode/slave mode
• Arbitration lost condition can be identified
• Supports two slave addresses
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 6 of 1130
REJ09B0327-0400
Item Specifications
Product Code*2
Product lineup
(preliminary)
Group Mask ROM
Versions F-ZTAT
Versions ROM/RAM
(Bytes) Packages
H8S/2148 HD6432148S HD64F2148
HD64F2148V*2128 k/4 k
HD6432148SW*1HD64F2148A
HD64F2148AV*2
FP-100B,
TFP-100B
HD6432147S HD64F2147A 64 k/2 k
HD6432147SW*1HD64F2147AV*2
H8S/2147N — HD64F2147N
HD64F2147NV*264 k/2 k
H8S/2144 HD6432144S HD64F2144
HD64F2144V*2
HD64F2144A
HD64F2144AV*2
128 k/4 k
HD6432143S — 96 k/4 k
HD6432142 HD64F2142R
HD64F2142RV*264 k/2 k
Notes: 1. W indicates the I2C bus option.
2. V indicates the 3-V version. Please refer to appendix F, Product
Code Lineup.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 7 of 1130
REJ09B0327-0400
1.2 Internal Block Diagram
An internal block diagram of the H8S/2148 Group is shown in figure 1.1 (a), an internal block
diagram of the H8S/2147N is shown in figure 1.1 (b), and an internal block diagram of the
H8S/2144 Group in figure 1.1 (c).
H8S/2000 CPU
DTC
WDT0, WDT1
ROM
RAM
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
P27/A15/PW15/CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
PA7/A23/KIN15/CIN15/PS2CD
PA6/A22/KIN14/CIN14/PS2CC
PA5/A21/KIN13/CIN13/PS2BD
PA4/A20/KIN12/CIN12/PS2BC
PA3/A19/KIN11/CIN11/PS2AD
PA2/A18/KIN10/CIN10/PS2AC
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
P37/D15/HDB7
P36/D14/HDB6
P35/D13/HDB5
P34/D12/HDB4
P33/D11/HDB3
P32/D10/HDB2
P31/D9/HDB1
P30/D8/HDB0
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
P97/WAIT/SDA0
P96/φ/EXCL
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG/ECS2
P67/TMOX/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4/CLAMPO
P63/FTIB/CIN3/KIN3/VFBACKI
P62/FTIA/CIN2/KIN2/VSYNCI/TMIY
P61/FTOA/CIN1/KIN1/VSYNCO
P60/FTCI/CIN0/KIN0/HFBACKI/TMIX
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12/CSYNCI
P44/TMO1/HIRQ1/HSYNCO
P43/TMCI1/HIRQ11/HSYNCI
P42/TMRI0/SCK2/SDA1
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P52/SCK0/SCL0
P51/RxD0
P50/TxD0
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P86/IRQ5/SCK1/SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82/HIFSD
P81/CS2/GA20
P80/HA0
AVref
AVCC
AVSS
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
RESO
VCC1
VCC2 (VCL)
VSS
VSS
VSS
VSS
VSS
Port 9Port 6Port 4Port 5
Port APort 2Port 1Port 3Port B
Clock pulse generator
Interrupt
controller
16-bit FRT
8-bit timer × 4ch
(TMR0, TMR1,
TMRX, TMRY)
Timer connection
SCI × 3ch
(IrDA × 1ch)
IIC × 2ch
(option)
Port 8 Port 7
Internal data bus
Internal address bus
Bus controller
Keyboard buffer
controller × 3ch
8-bit PWM
14-bit PWM
Host interface
10-bit A/D
8-bit D/A
Figure 1.1 (a) Internal Block Diagram of H8S/2148 Group
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 8 of 1130
REJ09B0327-0400
H8S/2000 CPU
WDT0, WDT1
ROM
RAM
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
P27/A15/PW15
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
PA7/A23/KIN15/CIN15/PS2CD
PA6/A22/KIN14/CIN14/PS2CC
PA5/A21/KIN13/CIN13/PS2BD
PA4/A20/KIN12/CIN12/PS2BC
PA3/A19/KIN11/CIN11/PS2AD
PA2/A18/KIN10/CIN10/PS2AC
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
P37/D15/HDB7
P36/D14/HDB6
P35/D13/HDB5
P34/D12/HDB4
P33/D11/HDB3
P32/D10/HDB2
P31/D9/HDB1
P30/D8/HDB0
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
P97/WAIT/SDA0
P96/φ/EXCL
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG/ECS2
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12
P44/TMO1/HIRQ1
P43/TMCI1/HIRQ11
P42/TMRI0/SCK2/SDA1
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P52/SCK0/SCL0
P51/RxD0
P50/TxD0
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P86/IRQ5/SCK1/SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82/HIFSD
P81/CS2/GA20
P80/HA0
AVref
AVCC
AVSS
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
RESO
VCC1
VCC2
VSS
VSS
VSS
VSS
VSS
Port 9Port 6Port 4Port 5
Port APort 2Port 1Port 3Port B
Clock pulse generator
Interrupt
controller
16-bit FRT
8-bit timer × 3ch
(TMR0, TMR1, TMRY)
SCI × 3ch
(IrDA × 1ch)
IIC × 2ch
(option)
Port 8 Port 7
Internal data bus
Internal address bus
Bus controller
Keyboard buffer
controller × 3ch
8-bit PWM
14-bit PWM
Host interface
10-bit A/D
8-bit D/A
Figure 1.1 (b) Internal Block Diagram of H8S/2147N
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 9 of 1130
REJ09B0327-0400
H8S/2000 CPU
WDT0, WDT1
ROM
RAM
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
PA7/A23/KIN15/CIN15
PA6/A22/KIN14/CIN14
PA5/A21/KIN13/CIN13
PA4/A20/KIN12/CIN12
PA3/A19/KIN11/CIN11
PA2/A18/KIN10/CIN10
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
P37/D15
P36/D14
P35/D13
P34/D12
P33/D11
P32/D10
P31/D9
P30/D8
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3
PB2/D2
PB1/D1
PB0/D0
P97/WAIT
P96/φ/EXCL
P95/AS/IOS
P94/HWR
P93/RD
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
P47/PWX1
P46/PWX0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SCK2
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P52/SCK0
P51/RxD0
P50/TxD0
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P86/IRQ5/SCK1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82
P81
P80
AVref
AVCC
AVSS
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
RESO
VCC1
VCC2 (VCL)
VSS
VSS
VSS
VSS
VSS
Port A
Clock pulse generator
Interrupt
controller
16-bit FRT
8-bit timer × 3ch
(TMR0, TMR1, TMRY)
SCI × 3ch
(IrDA × 1ch)
Internal data bus
Internal address bus
Bus controller
14-bit PWM
10-bit A/D
8-bit D/A
Port 9Port 6Port 4Port 5
Port 2Port 1Port 3Port B
Port 8 Port 7
Figure 1.1 (c) Internal Block Diagram of H8S/2144 Group
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 10 of 1130
REJ09B0327-0400
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement
The pin arrangement of the H8S/2148 Group is shown in figure 1.2 (a), the pin arrangement of the
H8S/2147N is shown in figure 1.2 (b), and the pin arrangement of the H8S/2144 Group in figure
1.2 (c).
FP-100B
TFP-100B
(Top View)
1 2 3 4 5 6 7 8 9 10111213141516171819202122232425
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
VCC2 (VCL)
PS2CD/KIN15/CIN15/A23/PA7
PS2CC/KIN14/CIN14/A22/PA6
SCL0/SCK0/P52
RxD0/P51
TxD0/P50
VSS
SDA0/WAIT/P97
EXCL/φ/P96
CS1/ IOS/ AS/P95
IOW/ HWR/P94
PS2BD/KIN13/CIN13/A21/PA5
PS2BC/KIN12/CIN12/A20/PA4
IOR/ RD/P93
IRQ0/P92
IRQ1/P91
ADTRG/IRQ2/ECS2/LWR/P90
P14/A4/PW4
P15/A5/PW5
P16/A6/PW6
P17/A7/PW7
VSS
VSS
PB4/D4
PB5/D5
P20/A8/PW8
P21/A9/PW9
P22/A10/PW10
P23/A11/PW11
P24/A12/PW12
P25/A13/PW13
P26/A14/PW14
P27/A15/PW15/CBLANK
VCC1
PB6/D6
PB7/D7
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12/CSYNCI
P44/TMO1/HIRQ1/HSYNCO
P43/TMCI1/HIRQ11/HSYNCI
P42/TMRI0/SCK2/SDA1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PW3/A3/P13
PW2/A2/P12
PW1/A1/P11
PW0/A0/P10
CS4/D3/PB3
CS3/D2/PB2
HDB0/D8/P30
HDB1/D9/P31
HDB2/D10/P32
HDB3/D11/P33
HDB4/D12/P34
HDB5/D13/P35
HDB6/D14/P36
HDB7/D15/P37
HIRQ4/D1/PB1
HIRQ3/D0/PB0
VSS
HA0/P80
GA20/CS2/P81
HIFSD/P82
P83
TxD1/IRQ3/P84
RxD1/IRQ4/P85
SCL1/SCK1/IRQ5/P86
RESO
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
PA0/A16/CIN8/KIN8
PA1/A17/CIN9/KIN9
AVSS
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
AVCC
AVref
P67/TMOX/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4/CLAMPO
PA2/A18/CIN10/KIN10/PS2AC
PA3/A19/CIN11/KIN11/PS2AD
P63/FTIB/CIN3/KIN3/VFBACKI
P62/FTIA/CIN2/KIN2/VSYNCI/TMIY
P61/FTOA/CIN1/KIN1/VSYNCO
P60/FTCI/CIN0/KIN0/HFBACKI/TMIX
Figure 1.2 (a) Pin Arrangement of H8S/2148 Group (FP-100B, TFP-100B: Top View)
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 11 of 1130
REJ09B0327-0400
FP-100B
TFP-100B
(Top View)
1 2 3 4 5 6 7 8 9 10111213141516171819202122232425
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
VCC2
PS2CD/KIN15/CIN15/A23/PA7
PS2CC/KIN14/CIN14/A22/PA6
SCL0/SCK0/P52
RxD0/P51
TxD0/P50
VSS
SDA0/WAIT/P97
EXCL/φ/P96
CS1/ IOS/ AS/P95
IOW/ HWR/P94
PS2BD/KIN13/CIN13/A21/PA5
PS2BC/KIN12/CIN12/A20/PA4
IOR/ RD/P93
IRQ0/P92
IRQ1/P91
ADTRG/IRQ2/ECS2/LWR/P90
P14/A4/PW4
P15/A5/PW5
P16/A6/PW6
P17/A7/PW7
VSS
VSS
PB4/D4
PB5/D5
P20/A8/PW8
P21/A9/PW9
P22/A10/PW10
P23/A11/PW11
P24/A12/PW12
P25/A13/PW13
P26/A14/PW14
P27/A15/PW15
VCC1
PB6/D6
PB7/D7
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12
P44/TMO1/HIRQ1
P43/TMCI1/HIRQ11
P42/TMRI0/SCK2/SDA1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PW3/A3/P13
PW2/A2/P12
PW1/A1/P11
PW0/A0/P10
CS4/D3/PB3
CS3/D2/PB2
HDB0/D8/P30
HDB1/D9/P31
HDB2/D10/P32
HDB3/D11/P33
HDB4/D12/P34
HDB5/D13/P35
HDB6/D14/P36
HDB7/D15/P37
HIRQ4/D1/PB1
HIRQ3/D0/PB0
VSS
HA0/P80
GA20/CS2/P81
HIFSD/P82
P83
TxD1/IRQ3/P84
RxD1/IRQ4/P85
SCL1/SCK1/IRQ5/P86
RESO
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
PA0/A16/CIN8/KIN8
PA1/A17/CIN9/KIN9
AVSS
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
AVCC
AVref
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4
PA2/A18/CIN10/KIN10/PS2AC
PA3/A19/CIN11/KIN11/PS2AD
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
Figure 1.2 (b) Pin Arrangement of H8S/2147N (FP-100B, TFP-100B: Top View)
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 12 of 1130
REJ09B0327-0400
FP-100B
TFP-100B
(Top View)
RES
XTAL
EXTAL
VCC1
MD1
MD0
NMI
STBY
VCC2 (VCL)
KIN15/CIN15/A23/PA7
KIN14/CIN14/A22/PA6
SCK0/P52
RxD0/P51
TxD0/P50
VSS
WAIT/P97
EXCL/φ/P96
IOS/ AS/P95
HWR/P94
KIN13/CIN13/A21/PA5
KIN12/CIN12/A20/PA4
RD/P93
IRQ0/P92
IRQ1/P91
ADTRG/IRQ2/LWR/P90
P14/A4
P15/A5
P16/A6
P17/A7
VSS
VSS
PB4/D4
PB5/D5
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
VCC1
PB6/D6
PB7/D7
P47/PWX1
P46/PWX0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SCK2
12345678910111213141516171819202122232425
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
PA0/A16/CIN8/KIN8
PA1/A17/CIN9/KIN9
AVSS
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
AVCC
AVref
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ
6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4
PA2/A18/CIN10/KIN10
PA3/A19/CIN11/KIN11
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
A3/P13
A2/P12
A1/P11
A0/P10
D3/PB3
D2/PB2
D8/P30
D9/P31
D10/P32
D11/P33
D12/P34
D13/P35
D14/P36
D15/P37
D1/PB1
D0/PB0
VSS
P80
P81
P82
P83
TxD1/IRQ3/P84
RxD1/IRQ4/P85
SCK1/IRQ5/P86
RESO
Figure 1.2 (c) Pin Arrangement of H8S/2144 Group (FP-100B, TFP-100B: Top View)
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 13 of 1130
REJ09B0327-0400
1.3.2 Pin Functions in Each Operating Mode
Tables 1.2 (a), (b) and (c) show the pin functions of the H8S/2148 Group, H8S/2147N, and
H8S/2144 Group in each of the operating modes.
Table 1.2 (a) H8S/2148 Group Pin Functions in Each Operating Mode
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
1RES RES RES RES
2 XTAL XTAL XTAL XTAL
3 EXTAL EXTAL EXTAL EXTAL
4 VCCB VCCB VCCB VCC
5 MD1 MD1 MD1 VSS
6 MD0 MD0 MD0 VSS
7 NMI NMI NMI FA9
8STBY STBY STBY VCC
9 VCC2 (VCL) VCC2 (VCL) VCC2 (VCL) VCC
10 PA7/CIN15/
KIN15/PS2CD A23/PA7/CIN15/
KIN15/PS2CD PA7/CIN15/
KIN15/PS2CD NC
11 PA6/CIN14/
KIN14/PS2CC A22/PA6/CIN14/
KIN14/PS2CC PA6/CIN14/
KIN14/PS2CC NC
12 P52/SCK0/SCL0 P52/SCK0/SCL0 P52/SCK0/SCL0 NC
13 P51/RxD0 P51/RxD0 P51/RxD0 FA17
14 P50/TxD0 P50/TxD0 P50/TxD0 NC
15 VSS VSS VSS VSS
16 P97/WAIT/SDA0 P97/WAIT/SDA0 P97/SDA0 VCC
17 P96/φ/EXCL P96/φ/EXCL P96/φ/EXCL NC
18 AS/IOS AS/IOS P95/CS1 FA16
19 HWR HWR P94/IOW FA15
20 PA5/CIN13/
KIN13/PS2BD A21/PA5/CIN13/
KIN13/PS2BD PA5/CIN13/
KIN13/PS2BD NC
21 PA4/CIN12/
KIN12/PS2BC A20/PA4/CIN12/
KIN12/PS2BC PA4/CIN12/
KIN12/PS2BC NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 14 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
22 RD RD P93/IOR WE
23 P92/IRQ0 P92/IRQ0 P92/IRQ0 VSS
24 P91/IRQ1 P91/IRQ1 P91/IRQ1 VCC
25 LWR/P90/IRQ2/
ADTRG
LWR/P90/IRQ2/
ADTRG P90/IRQ2/ADTRG/
ECS2 VCC
26 P60/FTCI/CIN0/
KIN0/TMIX/
HFBACKI
P60/FTCI/CIN0/
KIN0/TMIX/
HFBACKI
P60/FTCI/CIN0/
KIN0/TMIX/
HFBACKI
NC
27 P61/FTOA/CIN1/
KIN1/VSYNCO P61/FTOA/CIN1/
KIN1/VSYNCO P61/FTOA/CIN1/
KIN1/VSYNCO NC
28 P62/FTIA/CIN2/
KIN2/TMIY/
VSYNCI
P62/FTIA/CIN2/
KIN2/TMIY/
VSYNCI
P62/FTIA/CIN2/
KIN2/TMIY/
VSYNCI
NC
29 P63/FTIB/CIN3/
KIN3/VFBACKI P63/FTIB/CIN3/
KIN3/VFBACKI P63/FTIB/CIN3/
KIN3/VFBACKI NC
30 PA3/CIN11/
KIN11/PS2AD A19/PA3/CIN11/
KIN11/PS2AD PA3/CIN11/
KIN11/PS2AD NC
31 PA2/CIN10/
KIN10/PS2AC A18/PA2/CIN10/
KIN10/PS2AC PA2/CIN10/
KIN10/PS2AC NC
32 P64/FTIC/CIN4/
KIN4/CLAMPO P64/FTIC/CIN4/
KIN4/CLAMPO P64/FTIC/CIN4/
KIN4/CLAMPO NC
33 P65/FTID/CIN5/
KIN5 P65/FTID/CIN5/
KIN5 P65/FTID/CIN5/
KIN5 NC
34 P66/FTOB/CIN6/
KIN6/IRQ6 P66/FTOB/CIN6/
KIN6/IRQ6 P66/FTOB/CIN6/
KIN6/IRQ6 NC
35 P67/TMOX/CIN7/
KIN7/IRQ7 P67/TMOX/CIN7/
KIN7/IRQ7 P67/TMOX/CIN7/
KIN7/IRQ7 VSS
36 AVref AVref AVref VCC
37 AVCC AVCC AVCC VCC
38 P70/AN0 P70/AN0 P70/AN0 NC
39 P71/AN1 P71/AN1 P71/AN1 NC
40 P72/AN2 P72/AN2 P72/AN2 NC
41 P73/AN3 P73/AN3 P73/AN3 NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 15 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
42 P74/AN4 P74/AN4 P74/AN4 NC
43 P75/AN5 P75/AN5 P75/AN5 NC
44 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC
45 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC
46 AVSS AVSS AVSS VSS
47 PA1/CIN9/KIN9 A17/PA1/CIN9/
KIN9 PA1/CIN9/KIN9 NC
48 PA0/CIN8/KIN8 A16/PA0/CIN8/KIN8 PA0/CIN8/KIN8 NC
49 P40/TMCI0/
TxD2/IrTxD P40/TMCI0/
TxD2/IrTxD P40/TMCI0/
TxD2/IrTxD NC
50 P41/TMO0/
RxD2/IrRxD P41/TMO0/
RxD2/IrRxD P41/TMO0/
RxD2/IrRxD NC
51 P42/TMRI0/
SCK2/SDA1 P42/TMRI0/
SCK2/SDA1 P42/TMRI0/
SCK2/SDA1 NC
52 P43/TMCI1/
HSYNCI P43/TMCI1/
HSYNCI P43/TMCI1/HIRQ11/
HSYNCI NC
53 P44/TMO1/
HSYNCO P44/TMO1/
HSYNCO P44/TMO1/HIRQ1/
HSYNCO NC
54 P45/TMRI1/
CSYNCI P45/TMRI1/
CSYNCI P45/TMRI1/HIRQ12/
CSYNCI NC
55 P46/PWX0 P46/PWX0 P46/PWX0 NC
56 P47/PWX1 P47/PWX1 P47/PWX1 NC
57 PB7/D7 PB7/D7 PB7 NC
58 PB6/D6 PB6/D6 PB6 NC
59 VCC1 VCC1 VCC1 VCC
60 A15 A15/P27/PW15/
CBLANK P27/PW15/
CBLANK CE
61 A14 A14/P26/PW14 P26/PW14 FA14
62 A13 A13/P25/PW13 P25/PW13 FA13
63 A12 A12/P24/PW12 P24/PW12 FA12
64 A11 A11/P23/PW11 P23/PW11 FA11
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 16 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
65 A10 A10/P22/PW10 P22/PW10 FA10
66 A9 A9/P21/PW9 P21/PW9 OE
67 A8 A8/P20/PW8 P20/PW8 FA8
68 PB5/D5 PB5/D5 PB5 NC
69 PB4/D4 PB4/D4 PB4 NC
70 VSS VSS VSS VSS
71 VSS VSS VSS VSS
72 A7 A7/P17/PW7 P17/PW7 FA7
73 A6 A6/P16/PW6 P16/PW6 FA6
74 A5 A5/P15/PW5 P15/PW5 FA5
75 A4 A4/P14/PW4 P14/PW4 FA4
76 A3 A3/P13/PW3 P13/PW3 FA3
77 A2 A2/P12/PW2 P12/PW2 FA2
78 A1 A1/P11/PW1 P11/PW1 FA1
79 A0 A0/P10/PW0 P10/PW0 FA0
80 PB3/D3 PB3/D3 PB3/CS4 NC
81 PB2/D2 PB2/D2 PB2/CS3 NC
82 D8 D8 P30/HDB0 FO0
83 D9 D9 P31/HDB1 FO1
84 D10 D10 P32/HDB2 FO2
85 D11 D11 P33/HDB3 FO3
86 D12 D12 P34/HDB4 FO4
87 D13 D13 P35/HDB5 FO5
88 D14 D14 P36/HDB6 FO6
89 D15 D15 P37/HDB7 FO7
90 PB1/D1 PB1/D1 PB1/HIRQ4 NC
91 PB0/D0 PB0/D0 PB0/HIRQ3 NC
92 VSS VSS VSS VSS
93 P80 P80 P80/HA0 NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 17 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
94 P81 P81 P81/CS2/GA20 NC
95 P82 P82 P82/HIFSD NC
96 P83 P83 P83 NC
97 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC
98 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC
99 P86/IRQ5/SCK1/
SCL1 P86/IRQ5/SCK1/
SCL1 P86/IRQ5/SCK1/
SCL1 NC
100 RESO RESO RESO NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 18 of 1130
REJ09B0327-0400
Table 1.2 (b) H8S/2147N Pin Functions in Each Operating Mode
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
1RES RES RES RES
2 XTAL XTAL XTAL XTAL
3 EXTAL EXTAL EXTAL EXTAL
4 VCCB VCCB VCCB VCC
5 MD1 MD1 MD1 VSS
6 MD0 MD0 MD0 VSS
7 NMI NMI NMI FA9
8STBY STBY STBY VCC
9 VCC2 VCC2 VCC2 VCC
10 PA7/CIN15/
KIN15/PS2CD A23/PA7/CIN15/
KIN15/PS2CD PA7/CIN15/
KIN15/PS2CD NC
11 PA6/CIN14/
KIN14/PS2CC A22/PA6/CIN14/
KIN14/PS2CC PA6/CIN14/
KIN14/PS2CC NC
12 P52/SCK0/SCL0 P52/SCK0/SCL0 P52/SCK0/SCL0 NC
13 P51/RxD0 P51/RxD0 P51/RxD0 FA17
14 P50/TxD0 P50/TxD0 P50/TxD0 NC
15 VSS VSS VSS VSS
16 P97/WAIT/SDA0 P97/WAIT/SDA0 P97/SDA0 VCC
17 φ/P96/EXCL φ/P96/EXCL P96/φ/EXCL NC
18 AS/IOS AS/IOS P95/CS1 FA16
19 HWR HWR P94/IOW FA15
20 PA5/CIN13/
KIN13/PS2BD A21/PA5/CIN13/
KIN13/PS2BD PA5/CIN13/
KIN13/PS2BD NC
21 PA4/CIN12/
KIN12/PS2BC A20/PA4/CIN12/
KIN12/PS2BC PA4/CIN12/
KIN12/PS2BC NC
22 RD RD P93/IOR WE
23 P92/IRQ0 P92/IRQ0 P92/IRQ0 VSS
24 P91/IRQ1 P91/IRQ1 P91/IRQ1 VCC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 19 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
25 LWR/P90/IRQ2/
ADTRG
LWR/P90/IRQ2/
ADTRG P90/IRQ2/ADTRG/
ECS2 VCC
26 P60/FTCI/CIN0/
KIN0 P60/FTCI/CIN0/
KIN0 P60/FTCI/CIN0/
KIN0 NC
27 P61/FTOA/CIN1/
KIN1 P61/FTOA/CIN1/
KIN1 P61/FTOA/CIN1/
KIN1 NC
28 P62/FTIA/CIN2/
KIN2/TMIY P62/FTIA/CIN2/
KIN2/TMIY P62/FTIA/CIN2/
KIN2/TMIY NC
29 P63/FTIB/CIN3/
KIN3 P63/FTIB/CIN3/
KIN3 P63/FTIB/CIN3/
KIN3 NC
30 PA3/CIN11/
KIN11/PS2AD A19/PA3/CIN11/
KIN11/PS2AD PA3/CIN11/
KIN11/PS2AD NC
31 PA2/CIN10/
KIN10/PS2AC A18/PA2/CIN10/
KIN10/PS2AC PA2/CIN10/
KIN10/PS2AC NC
32 P64/FTIC/CIN4/
KIN4 P64/FTIC/CIN4/
KIN4 P64/FTIC/CIN4/
KIN4 NC
33 P65/FTID/CIN5/
KIN5 P65/FTID/CIN5/
KIN5 P65/FTID/CIN5/
KIN5 NC
34 P66/FTOB/CIN6/
KIN6/IRQ6 P66/FTOB/CIN6/
KIN6/IRQ6 P66/FTOB/CIN6/
KIN6/IRQ6 NC
35 P67/CIN7/KIN7/
IRQ7 P67/CIN7/KIN7/
IRQ7 P67/CIN7/KIN7/
IRQ7 VSS
36 AVref AVref AVref VCC
37 AVCC AVCC AVCC VCC
38 P70/AN0 P70/AN0 P70/AN0 NC
39 P71/AN1 P71/AN1 P71/AN1 NC
40 P72/AN2 P72/AN2 P72/AN2 NC
41 P73/AN3 P73/AN3 P73/AN3 NC
42 P74/AN4 P74/AN4 P74/AN4 NC
43 P75/AN5 P75/AN5 P75/AN5 NC
44 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC
45 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 20 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
46 AVSS AVSS AVSS VSS
47 PA1/CIN9/KIN9 A17/PA1/CIN9/
KIN9 PA1/CIN9/KIN9 NC
48 PA0/CIN8/KIN8 A16/PA0/CIN8/KIN8 PA0/CIN8/KIN8 NC
49 P40/TMCI0/
TxD2/IrTxD P40/TMCI0/
TxD2/IrTxD P40/TMCI0/
TxD2/IrTxD NC
50 P41/TMO0/
RxD2/IrRxD P41/TMO0/
RxD2/IrRxD P41/TMO0/
RxD2/IrRxD NC
51 P42/TMRI0/
SCK2/SDA1 P42/TMRI0/
SCK2/SDA1 P42/TMRI0/
SCK2/SDA1 NC
52 P43/TMCI1 P43/TMCI1 P43/TMCI1/HIRQ11 NC
53 P44/TMO1 P44/TMO1 P44/TMO1/HIRQ1 NC
54 P45/TMRI1 P45/TMRI1 P45/TMRI1/HIRQ12 NC
55 P46/PWX0 P46/PWX0 P46/PWX0 NC
56 P47/PWX1 P47/PWX1 P47/PWX1 NC
57 PB7/D7 PB7/D7 PB7 NC
58 PB6/D6 PB6/D6 PB6 NC
59 VCC1 VCC1 VCC1 VCC
60 A15 A15/P27/PW15 P27/PW15 CE
61 A14 A14/P26/PW14 P26/PW14 FA14
62 A13 A13/P25/PW13 P25/PW13 FA13
63 A12 A12/P24/PW12 P24/PW12 FA12
64 A11 A11/P23/PW11 P23/PW11 FA11
65 A10 A10/P22/PW10 P22/PW10 FA10
66 A9 A9/P21/PW9 P21/PW9 OE
67 A8 A8/P20/PW8 P20/PW8 FA8
68 PB5/D5 PB5/D5 PB5 NC
69 PB4/D4 PB4/D4 PB4 NC
70 VSS VSS VSS VSS
71 VSS VSS VSS VSS
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 21 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
72 A7 A7/P17/PW7 P17/PW7 FA7
73 A6 A6/P16/PW6 P16/PW6 FA6
74 A5 A5/P15/PW5 P15/PW5 FA5
75 A4 A4/P14/PW4 P14/PW4 FA4
76 A3 A3/P13/PW3 P13/PW3 FA3
77 A2 A2/P12/PW2 P12/PW2 FA2
78 A1 A1/P11/PW1 P11/PW1 FA1
79 A0 A0/P10/PW0 P10/PW0 FA0
80 PB3/D3 PB3/D3 PB3/CS4 NC
81 PB2/D2 PB2/D2 PB2/CS3 NC
82 D8 D8 P30/HDB0 FO0
83 D9 D9 P31/HDB1 FO1
84 D10 D10 P32/HDB2 FO2
85 D11 D11 P33/HDB3 FO3
86 D12 D12 P34/HDB4 FO4
87 D13 D13 P35/HDB5 FO5
88 D14 D14 P36/HDB6 FO6
89 D15 D15 P37/HDB7 FO7
90 PB1/D1 PB1/D1 PB1/HIRQ4 NC
91 PB0/D0 PB0/D0 PB0/HIRQ3 NC
92 VSS VSS VSS VSS
93 P80 P80 P80/HA0 NC
94 P81 P81 P81/CS2/GA20 NC
95 P82 P82 P82/HIFSD NC
96 P83 P83 P83 NC
97 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC
98 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC
99 P86/IRQ5/SCK1/
SCL1 P86/IRQ5/SCK1/
SCL1 P86/IRQ5/SCK1/
SCL1 NC
100 RESO RESO RESO NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 22 of 1130
REJ09B0327-0400
Table 1.2 (c) H8S/2144 Group Pin Functions in Ea ch Operating Mode
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
1RES RES RES RES
2 XTAL XTAL XTAL XTAL
3 EXTAL EXTAL EXTAL EXTAL
4 VCC1 VCC1 VCC1 VCC
5 MD1 MD1 MD1 VSS
6 MD0 MD0 MD0 VSS
7 NMI NMI NMI FA9
8STBY STBY STBY VCC
9 VCC2 (VCL) VCC2 (VCL) VCC2 (VCL) VCC
10 PA7/CIN15/
KIN15 A23/PA7/CIN15/
KIN15 PA7/CIN15/
KIN15 NC
11 PA6/CIN14/
KIN14 A22/PA6/CIN14/
KIN14 PA6/CIN14/
KIN14 NC
12 P52/SCK0 P52/SCK0 P52/SCK0 NC
13 P51/RxD0 P51/RxD0 P51/RxD0 FA17
14 P50/TxD0 P50/TxD0 P50/TxD0 NC
15 VSS VSS VSS VSS
16 P97/WAIT P97/WAIT P97 VCC
17 φ/P96/EXCL φ/P96/EXCL P96/φ/EXCL NC
18 AS/IOS AS/IOS P95 FA16
19 HWR HWR P94 FA15
20 PA5/CIN13/
KIN13 A21/PA5/CIN13/
KIN13 PA5/CIN13/
KIN13 NC
21 PA4/CIN12/
KIN12 A20/PA4/CIN12/
KIN12 PA4/CIN12/KIN12 NC
22 RD RD P93 WE
23 P92/IRQ0 P92/IRQ0 P92/IRQ0 VSS
24 P91/IRQ1 P91/IRQ1 P91/IRQ1 VCC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 23 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
25 LWR/P90/IRQ2/
ADTRG
LWR/P90/IRQ2/
ADTRG P90/IRQ2/ADTRG VCC
26 P60/FTCI/CIN0/
KIN0 P60/FTCI/CIN0/
KIN0 P60/FTCI/CIN0/
KIN0 NC
27 P61/FTOA/
CIN1/KIN1 P61/FTOA/CIN1/
KIN1 P61/FTOA/CIN1/
KIN1 NC
28 P62/FTIA/CIN2/
KIN2/TMIY P62/FTIA/CIN2/
KIN2/TMIY P62/FTIA/CIN2/
KIN2/TMIY NC
29 P63/FTIB/CIN3/
KIN3 P63/FTIB/CIN3/
KIN3 P63/FTIB/CIN3/
KIN3 NC
30 PA3/CIN11/
KIN11 A19/PA3/CIN11/
KIN11 PA3/CIN11/
KIN11 NC
31 PA2/CIN10/
KIN10 A18/PA2/CIN10/
KIN10 PA2/CIN10/
KIN10 NC
32 P64/FTIC/CIN4/
KIN4 P64/FTIC/CIN4/
KIN4 P64/FTIC/CIN4/
KIN4 NC
33 P65/FTID/CIN5/
KIN5 P65/FTID/CIN5/
KIN5 P65/FTID/CIN5/
KIN5 NC
34 P66/FTOB/CIN6/
KIN6/IRQ6 P66/FTOB/CIN6/
KIN6/IRQ6 P66/FTOB/CIN6/
KIN6/IRQ6 NC
35 P67/CIN7/KIN7/
IRQ7 P67/CIN7/KIN7/
IRQ7 P67/CIN7/KIN7/
IRQ7 VSS
36 AVref AVref AVref VCC
37 AVCC AVCC AVCC VCC
38 P70/AN0 P70/AN0 P70/AN0 NC
39 P71/AN1 P71/AN1 P71/AN1 NC
40 P72/AN2 P72/AN2 P72/AN2 NC
41 P73/AN3 P73/AN3 P73/AN3 NC
42 P74/AN4 P74/AN4 P74/AN4 NC
43 P75/AN5 P75/AN5 P75/AN5 NC
44 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC
45 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 24 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
46 AVSS AVSS AVSS VSS
47 PA1/CIN9/KIN9 A17/PA1/CIN9/KIN9 PA1/CIN9/KIN9 NC
48 PA0/CIN8/KIN8 A16/PA0/CIN8/KIN8 PA0/CIN8/KIN8 NC
49 P40/TMCI0/
TxD2/IrTxD P40/TMCI0/
TxD2/IrTxD P40/TMCI0/
TxD2/IrTxD NC
50 P41/TMO0/
RxD2/IrRxD P41/TMO0/
RxD2/IrRxD P41/TMO0/
RxD2/IrRxD NC
51 P42/TMRI0/
SCK2 P42/TMRI0/
SCK2 P42/TMRI0/
SCK2 NC
52 P43/TMCI1 P43/TMCI1 P43/TMCI1 NC
53 P44/TMO1 P44/TMO1 P44/TMO1 NC
54 P45/TMRI1 P45/TMRI1 P45/TMRI1 NC
55 P46/PWX0 P46/PWX0 P46/PWX0 NC
56 P47/PWX1 P47/PWX1 P47/PWX1 NC
57 PB7/D7 PB7/D7 PB7 NC
58 PB6/D6 PB6/D6 PB6 NC
59 VCC1 VCC1 VCC1 VCC
60 A15 A15/P27 P27 CE
61 A14 A14/P26 P26 FA14
62 A13 A13/P25 P25 FA13
63 A12 A12/P24 P24 FA12
64 A11 A11/P23 P23 FA11
65 A10 A10/P22 P22 FA10
66 A9 A9/P21 P21 OE
67 A8 A8/P20 P20 FA8
68 PB5/D5 PB5/D5 PB5 NC
69 PB4/D4 PB4/D4 PB4 NC
70 VSS VSS VSS VSS
71 VSS VSS VSS VSS
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 25 of 1130
REJ09B0327-0400
Pin Name
Pin No. Expanded Modes Single-Chip Modes
FP-100B
TFP-100B Mode 1 Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1) Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0) Flash Memory
Writer Mode
72 A7 A7/P17 P17 FA7
73 A6 A6/P16 P16 FA6
74 A5 A5/P15 P15 FA5
75 A4 A4/P14 P14 FA4
76 A3 A3/P13 P13 FA3
77 A2 A2/P12 P12 FA2
78 A1 A1/P11 P11 FA1
79 A0 A0/P10 P10 FA0
80 PB3/D3 PB3/D3 PB3 NC
81 PB2/D2 PB2/D2 PB2 NC
82 D8 D8 P30 FO0
83 D9 D9 P31 FO1
84 D10 D10 P32 FO2
85 D11 D11 P33 FO3
86 D12 D12 P34 FO4
87 D13 D13 P35 FO5
88 D14 D14 P36 FO6
89 D15 D15 P37 FO7
90 PB1/D1 PB1/D1 PB1 NC
91 PB0/D0 PB0/D0 PB0 NC
92 VSS VSS VSS VSS
93 P80 P80 P80 NC
94 P81 P81 P81 NC
95 P82 P82 P82 NC
96 P83 P83 P83 NC
97 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC
98 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC
99 P86/IRQ5/SCK1 P86/IRQ5/SCK1 P86/IRQ5/SCK1 NC
100 RESO RESO RESO NC
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 26 of 1130
REJ09B0327-0400
1.3.3 Pin Functions
Table 1.3 summarizes the pin functions of this LSI.
Table 1.3 Pin Functions
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
Power
supply VCC1
VCC2
4 [H8S/2144
Group only],
59
9*
Input Power supply: For connection to the power supply.
All VCC1 and VCC2* pins shou ld be conn ect ed t o
the system power supply.
VCL 9*Input Internal step-down voltage pin: A power supply
pin for the product, applicable to product lines that
have an internal step-down voltage. In the 5-V and
4-V versions, connect external capacitors to
stabilize the internal step-down voltage between
this pin and the VSS pin. Do not connect it to Vcc.
In the 3-V version, connect this pin and the VCC1
pin to the power supply for the system. For details,
See section 26, Electrical Characteristics.
VCCB 4 [H8S/2148
Group and
H8S/2147N
only]
Input Input/output buffer power supply: Power supply
pin for the port A input/output buffer.
VSS 15, 70
71, 92 Input Ground: All VSS pins should be connected to the
system power supply (0 V).
Clock XTAL 2 Input Connected to a crystal oscillator. See section 24,
Clock Pulse Generator, for typical connection
diagrams for a crystal oscillator and external clock
input.
EXTAL 3 Input Connected to a crystal oscillator. The EXTAL pin
can also input an external clock. See section 24,
Clock Pulse Generator, for typical connection
diagrams for a crystal oscillator and external clock
input.
φ 17 Output System clock: Supplies the system clock to
external dev ic es.
EXCL 17 Input External subclock input: Input a 32.768 kHz
external sub cl oc k.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 27 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
Operating
mode
control
MD1
MD0 5
6Input Mode pins: These pins set the operating mode.
The relation between the settings of pins MD1 and
MD0 and the operating mode is shown below.
These pins should not be cha nged whil e the MCU
is operating.
MD1 MD0 Operating
Mode Description
0 1 Mode 1 Normal
Expanded mode with
on-chip ROM disabled
1 0 Mode 2 Advanced
Expanded mode with
on-chip ROM enabled or
single-c hi p mode
1 1 Mode 3 Normal
Expanded mode with
on-chip ROM enabled or
single-c hi p mode
System
control RES 1 Input Reset input: When this pin is driven low, the chip is
reset.
RESO 100 Output Reset output: Outputs reset signal to external
device.
STBY 8 Input Standby: When this pin is driven low, a transition is
made to hardware standby mode.
Address
bus A23 to
A16 10, 11, 20,
21, 30, 31,
47, 48
Output Address bus (advanced): Outputs address when
16-Mbyte space is used.
A15 to
A0 60 to 67,
72 to 79 Output Address bus: These pins output an address.
Data bus D15 to
D8 89 to 82 Input/
output Data bus (upper): Bi directional data bus.
Used for 8-bit data and upper byte of 16-bit data.
D7 to
D0 57, 58, 68,
69, 80, 81,
90, 91
Input/
output Data bus (lower): Bidirectional data bus.
Used for lower byte of 16-bit data.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 28 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
Bus control WAIT 16 Input Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address
space.
RD 22 Output Read: When this pin is low, it indicates that the
external address space is being read.
HWR 19 Output High write: When this pin is low, it indicate s that
the external address space is being written to. The
upper half of the data bus is valid.
LWR 25 Output Low write: When this pin is low, it indica tes that the
external address space is being written to. The
lower half of the data bus is valid.
AS/IOS 18 Output Address strobe: When this pin is low, it indicates
that address output on the address bus is valid.
Interrupt
signals NMI 7 Input Nonmaskable interrupt: Requests a nonmaskable
interrupt.
IRQ0 to
IRQ7 23 to 25,
97 to 99,
34, 35
Input Interrupt request 0 to 7: These pins request a
maskable interr upt.
FTCI 26 Input FRT counter clock input: Input pin for an external
clock signal for the free-running counter (FRC).
16-bit free-
running
timer (FRT) FTOA 27 Output FRT output compare A output: The output
compare A output pin.
FTOB 34 Output FRT output compare B output: The output
compare B output pin.
FTIA 28 Input FRT input capture A input: The input capture A
input pin.
FTIB 29 Input FRT input capture B input: The input capture B
input pin.
FTIC 32 Input FRT input capture C input: The input capture C
input pin.
FTID 33 Input FRT input capture D input: The input capture D
input pin.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 29 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
TMO0
TMO1
TMOX
50
53
35
Output Compare-match output: TMR0, TMR1, and TMRX
compare-match output pins.
8-bit timer
(TMR0,
TMR1,
TMRX,
TMRY) TMCI0
TMCI1 49
52 Input Counter external clock input: Input pins for the
external clock input to the TMR0 and TMR1
counters.
TMRI0
TMRI1 51
54 Input Counter external reset input: TMR0 and TMR1
counter reset input pins.
TMIX
TMIY 26
28 Input Counter external clock input and reset input:
Dual function as TMRX and TMRY counter clock
input pin and reset input pin.
PWM timer
(PWM) PW15 to
PW0 60 to 67,
72 to 79 Output PWM timer output: PWM timer pulse output pins.
14-bit PWM
timer
(PWMX)
PWX0
PWX1 55
56 Output PWMX timer output: PWM D/A pulse output pins.
TxD0
TxD1
TxD2
14
97
49
Output Transmit data: Data output pins.Serial com-
munication
interface
(SCI0, SCI1,
SCI2) RxD0
RxD1
RxD2
13
98
50
Input Receive data: Data input pins.
SCK0
SCK1
SCK2
12
99
51
Input/
output Serial clock: Clock input/output pins.
The SCK0 output type is NMOS push-pull in the
H8S/2148 Group and H8S/2147N, and is CMOS
output in the H8S/2144 Group.
SCI with
IrDA (SCI2) IrTxD
IrRxD 49
50 Output
Input IrDA transmit data/receive data: Input and output
pins for data encoded for IrDA use.
PS2AC
PS2BC
PS2CC
31
21
11
Input/
output PS2 clock: Keyboard buffer controller
synchronization clock input/o utput pins.
Keyboard
Buffer
controller
(PS2) PS2AD
PS2BD
PS2CD
30
20
10
Input/
output PS2 data: Keyboard buffer controller data
input/output pins.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 30 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
HDB7 to
HDB0 89 to 82 Input/
output Host interface data bus: Bidirectional 8-bit bus for
accessing the host interface.
Host
interface
(HIF) CS1,
CS2,
ECS2
CS3,
CS4
18, 94, 25
81, 80 Input Chip select 1, 2, 3, and 4: Input pins for selecting
host interface chan nel 1 to 4.
IOR 22 Input I/O read: Input pin that enables reading from the
host interface.
IOW 19 Input I/O write: Input pin that enables writing to the host
interface.
HA0 93 Input Command/data: Input pin that indicates whether
an access is a data access or command access.
GA20 94 Output GATE A20: A20 gate control signal output pin.
HIRQ11
HIRQ1
HIRQ12
HIRQ3
HIRQ4
52
53
54
91
90
Output Host interrupt 11, 1, 12, 3, and 4: Output pins for
interrupt requests to the host.
HIFSD 95 Input Host interface shutdown: Contro l input pi n used
to place host interface input/output pins in the high-
impedance/cutoff state.
Keyboard
control KIN0 to
KIN15 26 to 29,
32 to 35, 48,
47, 31, 30,
21, 20, 11,
10
Input Keyboard input: Matrix keyboard input pins.
Normally, P10 to P17 and P20 to P27 are used as
key-scan outputs. This enables a maximum 16-
output × 16-input, 256-key matrix to be configured.
AN7 to
AN0 45 to 38 Input Analog input: A/D converter analog input pins.A/D
converter
(ADC) CIN0 to
CIN15 26 to 29,
32 to 35,
48, 47, 31,
30, 21, 20,
11, 10
Input Expansion A/D inputs: Expansion A/D input pins
can be connected to the A/D converter, but since
they are also used as digital inp ut/o utput pins,
precision will fall.
ADTRG 25 Input A/D conversion external trigger input: Pin for
input of an ex ternal trigger to start A/D conversion.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 31 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
D/A
converter
(DAC)
DA0
DA1 44
45 Output Analog output: D/A converter analog output pins.
A/D
converter
D/A
converter
AVCC 37 Input Analog reference voltage: The analog power
supply pin for the A/D converter and D/A converter.
When the A/D and D/A converters are not used, this
pin should be connected to the syst em power
supply (+5 V or +3 V).
AVref 36 Input Analog reference voltage: The reference power
supply pin for the A/D converter and D/A converter.
When the A/D and D/A converters are not used, this
pin should be connected to the syst em power
supply (+5 V or +3 V).
AVSS 46 Input Analog ground: The ground pin for the A/D
converter and D/A converter. This pin should be
connected to the system power supply (0 V).
Timer
connection VSYNCI,
HSYNCI,
CSYNCI,
VFBACKI,
HFBACKI
28
52
54
29
26
Input Timer connection input: Timer connection
synchronous signal input pins.
VSYNCO,
HSYNCO,
CLAMPO,
CBLANK
27
53
32
60
Output Timer connection output: Timer co nne ctio n
synchronous signal output pins.
I2C bus
interface
(IIC)
(option)
SCL0
SCL1 12
99 Input/
output I2C clock input/output (channels 0 and 1): I2C
clock I/O pins. These pins have a bus drive
function.
The SCL0 output form is NMOS open-drain
SDA0
SDA1 16
51 Input/
output I2C data input/output (channels 0 and 1): I2C data
I/O pins. These pins ha ve a bus drive function.
The SDA0 output form is NMOS open-drain.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 32 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
I/O ports P17 to
P10 72 to 79 Input/
output Port 1: Eight input/output pins. The data direction of
each pin can be selected in the port 1 data direction
register (P1DDR). These pins have built-in MOS
input pull-up s, and also have LED drive cap abi lit y.
P27 to
P20 60 to 67 Input/
output Port 2: Eight input/output pins. The data direction of
each pin can be selected in the port 2 data direction
register (P2DDR). These pins have built-in MOS
input pull-up s, and also have LED drive cap abi lit y.
P37 to
P30 89 to 82 Input/
output Port 3: Eight input/output pins. The data direction of
each pin can be selected in the port 3 data direction
register (P3DDR). These pins have built-in MOS
input pull-up s, and also have LED drive cap abi lit y.
P47 to
P40 56 to 49 Input/
output Port 4: Eight input/output pins. The data direction of
each pin can be selected in the port 4 data direction
register (P4DDR).
P52 to
P50 12 to 14 Input/
output Port 5: Three input/output pins. The data direction
of each pin can be selected in the port 5 data
direction register (P5DDR). P5 2 is an NMOS push-
pull output in the H8S/2148 Group and H8S/2147N,
and is a CMOS output in the H8S/2144 Group.
P67 to
P60 35 to 32
29 to 26 Input/
output Port 6: Eight input/output pins. The data direction of
each pin can be selected in the port 6 data direction
register (P6DDR). These pins have built-in MOS
input pull-ups.
P77 to
P70 45 to 38 Input Port 7: Eight input pins.
P86 to
P80 99 to 93 Input/
output Port 8: Seven input/output pins. The data direction
of each pin can be selected in the port 8 data
direction register (P8DDR).
P97 to
P90 16 to 19
22 to 25 Input/
output Port 9: Eight input/output pins. The data direction of
each pin (exc ept P96) can be selected in the port 9
data direction register (P9DDR). P97 is an NMOS
push-pull output in the H8S/2148 Group and
H8S/2147N, and is a CMOS output in the H8S/2144
Group.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 33 of 1130
REJ09B0327-0400
Pin No.
Type Symbol FP-100B
TFP-100B I/O Name and Function
I/O ports PA7 to
PA0 10, 11, 20,
21, 30, 31,
47, 48
Input/
output Port A: Eight input/output pins. The data direction
of each pin can be selected in the port A data
direction register (PADDR). These pins have built-in
MOS input pull-ups. Thes e are the VCCB drive
pins. [H8S/2148 Group and H8S/2147N only]
PB7 to
PB0 57, 58, 68,
69, 80, 81,
90, 91
Input/
output Port B: Eight input/output pins. The data direction
of each pin can be selected in the port B data
direction register (PBDDR). These pins have built-in
MOS input pull-ups.
Note: *In F-ZTAT and mask ROM versions of HD64F2148A, HD64F2147A, HD64F2144A,
HD6432148S, HD6432148SW, HD6432147S, HD6432147SW, HD6432144S,
HD6432143S pi n NO.9 is VCL pin and is not VCC pin.
Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 34 of 1130
REJ09B0327-0400
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 35 of 1130
REJ09B0327-0400
Section 2 CPU
2.1 Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtim e contr ol.
2.1.1 Features
The H8S/2000 CPU has the following features.
• Upward-compatible with H8 /300 and H8/300H CPUs
Can execute H8/300 and H8/300 H object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
• Sixty-five basic instructions
8/16/32-b it ar ithmetic and logic in str uctions
Multiply and divide instructio ns
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @( d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx: 16, or #xx: 3 2]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes (4 Gbytes architecturally)
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 36 of 1130
REJ09B0327-0400
• High-speed operation
All frequently-u sed instructions execute in one or two states
Maximum clock rate: 20 MHz
8/16/32-bit register-register add/subtract: 50 ns
8 × 8-bit register-reg ister multiply: 600 ns
16 ÷ 8-bit register-register divide: 600 ns
16 × 16-bit register-register multiply: 1000 ns
32 ÷ 16-bit register-register divide: 1000 ns
• Two CPU operating modes
Normal mode
Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as fo llows.
Number of Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs , Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on the product.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 37 of 1130
REJ09B0327-0400
2.1.3 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers, and one 8-bit control register, have been added.
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide in structions have be en added.
Two-bit shift instructions have been added.
Instructio ns for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.1.4 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
One 8-bit control register has been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift instructions have been added.
Instructio ns for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 38 of 1130
REJ09B0327-0400
2.2 CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16
Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected
by the mode pins of the microcontroller.
CPU operating modes
Normal mode
Advanced mode
Maximum 64 kbytes for program
and data areas combined
Maximum 16 Mbytes for
program and data areas
combined
Figure 2.1 CPU Operating Modes
(1) Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
Address Space: A maximum address space of 64 kbytes can be accessed.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain
any value, even when the corresponding general register (Rn) is used as an address register. If the
general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)
or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (E n) will be affected.
Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of
effective addresses (EA) are valid.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 39 of 1130
REJ09B0327-0400
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For
details of the exception vector table, see section 4, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
Exception vector 1
Exception vector 2
Exception
vector table
(Reserved for system use)
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in th e instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-
bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 40 of 1130
REJ09B0327-0400
Stack Structure: When the program counter (PC) is pushed onto the stack in a subrou tine call,
and the PC an d condition- code register ( CCR) are pushed onto the stack in exception ha ndling,
they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the
stack. For details, see sectio n 4, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(16 bits) CCR
CCR*
PC
(16 bits)
SP
Note: * Ignored when returning.
SP
Figure 2.3 Stack Structure in Normal Mode
(2) Advanced Mode
Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally
a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4
Gbytes for program and data areas combined).
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers or address registers.
Instruction Set: All instructions and addressing modes can be used.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 41 of 1130
REJ09B0327-0400
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top
area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32
bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
For details of the exception vector table, see section 4, Exception Handling.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
Exception vector table
Reserved
Reset exception vector
(Reserved for system use)
Reserved
Exception vector 1
Reserved
H'00000010
H'00000008
H'00000007
Figure 2.4 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in th e instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area th at is regarded as
H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of this range is also the exception vector table.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 42 of 1130
REJ09B0327-0400
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is
not pushed onto the stack. For details, see section 4, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(24 bits)
CCR
PC
(24 bits)
SP SP
Reserved
Figure 2.5 Stack Structure in Advanced Mode
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 43 of 1130
REJ09B0327-0400
2.3 Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
(b) Advanced Mode
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
(a) Normal Mode
Data area
Program area
Cannot be
used by
this LSI
Figure 2.6 Memory Map
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 44 of 1130
REJ09B0327-0400
2.4 Register Configuration
2.4.1 Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general
registers and control registers.
T
————
I2 I1 I0EXR*76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
General Registers (Rn) and Extended Registers (En)
Control Registers (CR)
Legend: Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Note: * Does not affect operation in this LSI.
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
I
UI
HUNZVCCCR 76543210
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
H:
U:
N:
Z:
V:
C:
Figure 2.7 CPU Registers
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 45 of 1130
REJ09B0327-0400
2.4.2 General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum of sixteen 8-
bit reg iste rs.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 46 of 1130
REJ09B0327-0400
Free area
Stack area
SP (ER7)
Figure 2.9 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
and 8-bit cond ition-c od e registe r (CCR).
(1) Program Counter (PC)
This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is re garded as 0. )
(2) Extended Control Register (EXR)
An 8-bit register. In this LSI, this register does not affect operation.
Bit 7—Trace Bit (T): This bit is reserved. In this LSI, this bit does not affect operation.
Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits are reserved. In this LSI, these bits do not
affect operation.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 47 of 1130
REJ09B0327-0400
(3) Condition-Code Register (CCR)
This 8-bit r egister contains internal CPU statu s in formation , including an interrupt ma sk bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start o f an exception-
handling sequence. For details, refer to section 5, Interrupt Controller.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by sof twar e u sin g the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details, r e f e r to section 5, Interrupt Con tr oller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is ex ecuted, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is ex ecuted, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instru ctions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0
otherwise.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the carry
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to appendix A.1, Instruction.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 48 of 1130
REJ09B0327-0400
2.4.4 Initial Register Values
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the genera l r egisters ar e not initialized. In par ticular, the stack pointer (ER7 ) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 49 of 1130
REJ09B0327-0400
2.5 Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions op erate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.5.1 General Register Data Formats
Figure 2.10 shows the data formats in general registers.
76543210 Don’t care
70
Don’t care 76543210
43
70
70
Don’t care
Upper digit Lower digit
LSB
MSB LSB
Data Type General Register Data Format
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
RnH
RnL
RnH
RnL
RnH
RnL
MSB
Don’t care
Upper digit Lower digit
43
70
Don’t care
70
Don’t care 70
Figure 2.10 General Register Data Formats
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 50 of 1130
REJ09B0327-0400
0
MSB LSB
15
Word data
Word data
Rn
En
0
LSB
15
16
MSB
31
En Rn
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Legend:
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
0
MSB LSB
15
Longword data ERn
Data Type General Register Data Format
Figure 2.10 General Register Data Formats (cont)
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 51 of 1130
REJ09B0327-0400
2.5.2 Memory Data Formats
Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs bu t the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instructio n fetches.
76543210
70
MSB LSB
MSB
LSB
MSB
LSB
Data Type Data Format
1-bit data
Byte data
Word data
Longword data
Address
Address L
Address L
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
Figure 2.11 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 52 of 1130
REJ09B0327-0400
2.6 Instruction Set
2.6.1 Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
Data transfer MOV BWL 5
POP*1, PUSH*1WL
LDM*5, STM*5L
MOVFPE*3, MOVTPE*3B
ADD, SUB, CMP, NEG BWL 19Arithmetic
operations ADDX, SUBX, DAA, DAS B
INC, DEC BWL
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS BW
EXTU, EXTS WL
TAS*4B
Logic operations AND, OR, XOR, NOT BWL 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit-manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR B14
Branch Bcc*2, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block data transfer EEPMOV — 1
Total: 65 types
Legend: B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be us ed in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 53 of 1130
REJ09B0327-0400
2.6.2 Instr uctions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU
can use.
Table 2.2 Combinat ions of Instructions and Addressing Mo des
Addr ess in g Mo des
Function Instruction
#xx
Rn
@ERn
@(d:16,ERn)
@(d:32, ERn)
@–ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8, PC)
@(d:16, PC)
@@aa:8
—
MOV BWL BWL BWL BWL BWL BWL B BWL —BWL ————
POP, PUSH —————————————WL
LDM*3, STM*3————————————— L
Data
transfer
MOVFPE*1,
MOVTPE*1———————B——————
ADD, CMP BWL BWL ————————————
SUB WL BWL ————————————
ADDX, SUBX B B ————————————
ADDS, SUBS — L ————————————
INC, DEC —BWL ————————————
DAA, DAS — B ————————————
MULXU,
DIVXU —BW ————————————
MULXS,
DIVXS —BW ————————————
NEG —BWL ————————————
EXTU, EXTS —WL ————————————
Arithmetic
operations
TAS*2——B———————————
AND, OR,
XOR BWL BWL ————————————Logic
operations
NOT — BWL ————————————
Shift —BWL ————————————
Bit-manipulation —BB———BB— B ————
Bcc, BSR —————————— ——
JMP, JSR ———————— ——— —
Branch
RTS —————————————
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 54 of 1130
REJ09B0327-0400
Addr ess in g Mo des
Function Instruction
#xx
Rn
@ERn
@(d:16,ERn)
@(d:32, ERn)
@–ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8, PC)
@(d:16, PC)
@@aa:8
—
TRAPA —————————————
RTE —————————————
SLEEP —————————————
LDC B BWWWW— W — W ————
STC —BWWWW— W — W ————
ANDC, ORC,
XORC B—————————————
System
control
NOP —————————————
Block data transfer —————————————BW
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in this LSI.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 55 of 1130
REJ09B0327-0400
2.6.3 Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The no tation used in table 2.3
is defined below.
Operation Notation
Rd General register (des tination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
–Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Logical exclusive OR
→Move
¬NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 56 of 1130
REJ09B0327-0400
Table 2.3 Instructions Classified by Function
Type Instruction Size*1Function
Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a
general register and memory, or moves immediate data
to a general register.
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack.
POP.W Rn is identical to MOV.W @SP+, Rn.
POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM*3L @SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM*3L Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 57 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Arithmetic
operations ADD
SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted
from byte data in a general register. Use the SUBX or
ADD instruction.)
ADDX
SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data
in two general registers, or on immediate data and data
in a general register.
INC
DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
ADDS
SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a
32-bit register.
DAA
DAS B Rd decimal adjust → Rd
Decimal-a dju st s an additi on or subtrac t io n result in a
general register by referring to the CCR to produce 4-bit
BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 58 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Arithmetic
operations DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the resul t.
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of
data in a general register .
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
TAS B @ERd – 0, 1 → (<bit 7> of @ERd)*2
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 59 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Logic
operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one’s complement (lo gical complement) of
general register contents.
Shift
operations SHAL
SHAR B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
A 1-bit or 2-bit shift is possible.
SHLL
SHLR B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
A 1-bit or 2-bit shift is possible.
ROTL
ROTR B/W/L Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 60 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Bit-
manipulation
instructions
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIOR B C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 61 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Bit-
manipulation
instructions
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-O Rs the carry flag with a specif ied bit in a
general register or memory operand and stores the
result in the carry flag.
BIXOR B C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a
general register or memory operand.
BIST B ¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a
specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 62 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Branch
instructions Bcc —Branches to a specified address if a specified condition
is true. The branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Carry clear
(high or same) C = 0
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP —Branches unconditionally to a specified address.
BSR —Branches to a subroutine at a specified address.
JSR —Branches to a subroutine at a specified address.
RTS —Returns from a subroutine
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 63 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
TRAPA —Starts trap-instruction exception handling.
RTE —Returns from an exception-handling routine.
System
control
instructions SLEEP —Causes a transition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves contents of a general register or memory or
immediate data to CCR or EXR. Although CCR and EXR
are 8-bit registers, word-size transfers are performed
between them and memory. The upper 8 bits are valid.
STC B/W CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general regis ter or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with
immediate data.
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate
data.
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
NOP —PC + 2 → PC
Only increments the program counter.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 64 of 1130
REJ09B0327-0400
Type Instruction Size*1Function
Block data
transfer
instructions
EEPMOV.B
EEPMOV.W
—
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Block transfer instruction. Transfers the number of da ta
bytes specified by R4L or R4 from locations starting at
the address indicated by ER5 to locations starting at the
address indica ted by ER6 . After the transfer, the next
instruct ion is exe cuted.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
2.6.4 Basic Instruction Formats
The CPU instructio ns consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a con dition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
Condition Field: Specifies the branch ing condition of Bcc in structions.
Figure 2.12 shows examples of instruction formats.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 65 of 1130
REJ09B0327-0400
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
rn rm
op
EA (disp)
(4) Operation field, effective address extension, and condition field
op cc EA (disp) BRA d:16, etc
Figure 2.12 Instruction Formats (Examples)
2.6.5 Notes on Use of Bit-Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit-
manipulation, then write back the byte of data. Caution is therefore required when using these
instructions on a register containing write-only bits, or a port.
The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant
flag need not be read beforehand if it is clear that it has been set to 1 in an inter r upt handling
routine, etc.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of
these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-coun ter
relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 66 of 1130
REJ09B0327-0400
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.4 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement @ERn+
@–ERn
5 Absolute addr es s @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand in memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 67 of 1130
REJ09B0327-0400
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the register
value should be even.
• Register indirect with pre-decrem ent—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instru ction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word access,
or 4 for longword access. For word or longword access, the register value should be even.
Absolute Address—@aa:8, @aa:16, @aa:24 , or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit abso lute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a prog ram instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.5 indicates the accessible absolute address ranges.
Table 2.5 Absolute Address Access Ranges
Absolute Address Normal Mode Advanced Mode
Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32) H'000000 to H'FFFFFF
Program instruction
address 24 bits (@aa:24)
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 68 of 1130
REJ09B0327-0400
Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions con tain immediate data implicitly. Some bit-
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address ar e valid; the upper 8 bits are all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 69 of 1130
REJ09B0327-0400
(a) Normal Mode (b) Advanced Mode
Branch address
Specified
by @aa:8 Specified
by @aa:8 Reserved
Branch address
Figure 2.13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or an instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
2.7.2 Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 70 of 1130
REJ09B0327-0400
Table 2.6 Effective Address Calculation
No. Addressing Mode and
Instruction Format Effective Address
Calculation Effective Address (EA)
1 Register direct (Rn)
op rm rn
Operand is general regi ster
contents.
2 Register indirect (@ERn)
General register contents
31 0 31 0
rop
24 23
Don’t
care
3 Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
General register contents
Sign extension disp
31 0
31 0
31 0
op r disp Don’t
care
24 23
4 Register indirect with post-increment or pre-decrement
• Register indirect with post-increment @ERn+
General register contents
1, 2, or
4
31 0 31 0
r
op
Don’t
care
24 23
• Register indirect with pre-decrement @–ERn
General register contents
1, 2, or
4
Byte
Word
Longword
1
2
4
Operand
Size Value
Added
31 0
31 0
op rDon’t
care
24 23
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 71 of 1130
REJ09B0327-0400
No. Addressing Mode and
Instruction Format Effective Address
Calculation Effective Address (EA)
5 Absolute addr es s
@aa:8
@aa:16
@aa:32
31 08 7
@aa:24
31 016 15
31 0
31 0
op abs
op abs
abs
op
op
abs
H'FFFF
24 23
Don’t
care
Don’t
care
Don’t
care
Don’t
care
24 23
24 23
24 23
Sign
exten-
sion
6 Immediate #xx:8/#xx:16/#xx:32
op IMM
Operand is imm ediate data.
7 Program-counter relative
@(d:8, PC)/@(d:16, PC)
0
0
23
23
disp 31 0
24 23
op disp
PC contents
Don’t
care
Sign
exten-
sion
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 72 of 1130
REJ09B0327-0400
No. Addressing Mode and
Instruction Format Effective Address
Calculation Effective Address (EA)
8 Memory indirect @@aa:8
• Normal mode
0
0
31 8 7
0
15
H'000000 31 0
16 15
op abs
abs
Memory
contents
H'00
24 23
Don’t
care
• Advanced mode
31
0
31 8 7
0
abs
H'000000
31 0
24 23
op abs
Memory contents Don’t
care
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 73 of 1130
REJ09B0327-0400
2.8 Processing States
2.8.1 Overview
The CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Power-down state
CPU operation is stopped
to conserve power.*
Sleep mode
Software standby
mode
Hardware standby
mode
Processing
states
Note:
*The power-down state also includes a medium-speed mode, module stop mode,
sub-active mode, sub-sleep mode, and watch mode.
Figure 2.14 Processing States
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 74 of 1130
REJ09B0327-0400
End of bus request
Bus request
Program execution
state
Bus-released state
Sleep mode
Exception-handling state
External interrupt Software standby mode
RES = high
Reset state*1STBY = high, RES = low Hardware standby mode*2
Power-down state*3
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 25, Power-Down State.
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Interrupt
request
End of bus
request Bus
request
Request for
exception
handling
End of
exception
handling
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Figure 2.15 State Transitions
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are disabled in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14,
Watchdog Timer (WDT).
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 75 of 1130
REJ09B0327-0400
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing f low due to a reset, interrupt, or trap instr uction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
Types of Exception Handling and Their Priority
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates
the types of exception handlin g and their prio r ity. Trap instruction exception handling is always
accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7 Exception Handling Types and Priority
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with clock Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
Interrupt End of instruction
execution or end of
exception-handling
sequence*1
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence.
Low
Trap instruction When TRAPA instruction
is exec uted Exception handling starts when
a trap (TRAPA) instruction is
executed.*2
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
2. Trap instruction exception handling is always accepted in the program execution state.
Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, wh en RES goes high again,
reset exception handling starts. When reset exception handling starts the CPU fetches a start
address (vector) from the exception vector table and starts program execution from that address.
All interrupts, in cluding NMI, are disabled during reset ex ception handling and after it ends.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 76 of 1130
REJ09B0327-0400
Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the contro l register s. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.16 shows the stack after exception handling ends.
Note: * Ignored when returning.
CCR
PC
(24 bits)
SP
CCR
CCR*
PC
(16 bits)
SP
Normal mode Advanced mode
Figure 2.16 Stack Structure after Exception Handling (Examples)
2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5 Bus-Released Stat e
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. Wh ile the bus is released, all CPU internal operations are halted.
There is one other bus m a ster in addition to the CPU: the data transfer controller ( DTC).
For further details, refer to section 6, Bus Controller.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 77 of 1130
REJ09B0327-0400
2.8.6 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also
three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In
medium-speed mode, the CPU and other bus masters operate on a medium-speed clock. Module
stop mode permits halting of the operation of individual modules, other than the CPU. Subactive
mode, subsleep mode, and watch mode are power-down modes that use subclock input. For
details, refer to section 25, Power-Down State.
Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power
control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop
immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.
Softwa re Standby Mode
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SBYCR is set to 1 and the LSON b it in LPWRCR and the PSS bit in the WDT1 timer
control/status register (TCSR) are both cleared to 0. In software standby mode, the CPU and clock
halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU
registers and on-chip RAM are retained. The I/O ports also remain in their existing states.
Hardware Standby Mode
A transition to hardware standby mode is made when the STBY pin goes low. In hardware
standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 78 of 1130
REJ09B0327-0400
2.9 Basic Timing
2.9.1 Overview
The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge
of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or
three states. Different methods are used to access on-chip memory, on-chip supporting modules,
and the external address space.
2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. Th e data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows
the pin states.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
φ
Bus cycle
T1
Address
Read data
Write data
Read
access
Write
access
Figure 2.17 On-Chip Memory Access Cycle
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 79 of 1130
REJ09B0327-0400
Bus cycle
T1
UnchangedAddress bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High impedance
Figure 2.18 Pin States during On-Chip Memory Access
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 80 of 1130
REJ09B0327-0400
2.9.3 O n-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Bus cycle
T1 T2
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Internal address bus
φ
Figure 2.19 On-Chip Supporting Module Access Cycle
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 81 of 1130
REJ09B0327-0400
Bus cycle
T1 T2
Unchanged
Address bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High impedance
Figure 2.20 Pin States during On-Chip Supporting Module Access
2.9.4 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6, Bus Controller.
Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 82 of 1130
REJ09B0327-0400
2.10 Usage Note
2.10.1 TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or
ER5 is used.
2.10.2 STM/LDM Instruction
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by
one STM/LDM instru ction. The following ranges can be specified in the register list.
Two registers: ER0—ER1, ER2—ER3, or ER4—ER5
Three registers: ER0—ER2, or ER4—ER6
Four registers: ER0—ER3
The STM/LDM instruction including ER7 is not generated by the Renesas H8S and H8/300 series
C/C++compilers.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 83 of 1130
REJ09B0327-0400
Section 3 MCU Operati ng Mo des
3.1 Overview
3.1.1 Operat ing Mode Selection
This LSI has three operating modes (modes 1 to 3). These modes enable selection of the CPU
operating mode and enabling/disabling of on-chip ROM, by setting the mode pins (MD1 and
MD0).
Table 3.1 lists the MCU operating modes.
Table 3.1 MCU Operating Mode Select ion
MCU
Operating
Mode MD1 MD0
CPU
Operating
Mode Description On-Chip
ROM
000—— —
1 1 Normal Expanded mode with on-chip ROM disabled Disabled
2 1 0 Advanced Expanded mode with on-chip ROM enabled
Single-chip mo de Enabled
3 1 Normal Expanded mode with on-chip ROM enabled
Single-chip mo de
The CPU’s architecture allows for 4 Gbytes of address space, but this LSI actually access a
maximum of 16 Mbytes.
Mode 1 is an externally expanded mode that allows access to external memory and peripheral
devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a
transition can be made to ex ternal expansion mode by setting the EXPE bit in MDCR.
This LSI can only be used in modes 1 to 3. These means that the mode pins must select one of
these modes. Do not changes the inputs at the mode pins during operation.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 84 of 1130
REJ09B0327-0400
3.1.2 Register Configuration
This LSI have a mode control register (MDCR) that indicates the inputs at the mode pins (MD1
and MD0), a system control register (SYSCR) and bus control register (BCR) that control the
operation of the MCU, and a serial/timer con trol re gister (STCR) that contr ols the operation of the
supporting modules. Table 3.2 summarizes these registers.
Table 3.2 MCU Registers
Name Abbreviation R/W Initial Value Address*
Mode control register MDCR R/W Undetermined H'FFC5
System control register SYSCR R /W H'09 H'FFC4
Bus control register BCR R/W H'D7 H'FFC6
Serial/timer control register STCR R/W H'00 H'FFC3
Note: *Lower 16 bits of the address.
3.2 Register Descriptions
3.2.1 Mode Control Register (MDCR)
7
EXPE
—*
R/W*
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
—
0
—
1
MDS1
—*
R
Note: * Determined by pins MD1 and MD0.
Bit
Initial value
Read/Write
MDCR is an 8-bit read-only register that indicates the operating mode setting and the current
operating mode of the MCU.
The EXPE bit is initialized in coordination with th e mode pin states by a reset and in hardwar e
standby mode.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 85 of 1130
REJ09B0327-0400
Bit 7—Expanded Mo de Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1
and cannot be modif ied. In mod es 2 and 3, th is bit has an initial value of 0, and can be read and
written.
Bit 7
EXPE Description
0 Single chip mode is selected
1 Expanded mode is selected
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at pins
MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and
MD0. MDS1 and MDS0 are read-only bits—they cannot be written to. The mode pin (MD1 and
MD0) input levels are latched into these bits when MDCR is read.
3.2.2 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
SYSCR is an 8-bit readable/writable register that performs selection of system pin functions, reset
source monitoring, interrupt contro l mode selection, NMI detected edge selection, supporting
module pin location selection, supporting module register access control, and RAM address space
control.
Only bits 7, 6, 3, 1, and 0 are described here. For a detailed description of these bits, refer also to
the description of the relevant modules (host interface, bus controller, watchdog timer, RAM,
etc.). For information on bits 5, 4, and 2, see section 5.2.1, System Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Chip Select 2 Enable (CS2E): Specifies the location of the host interface control pin
(CS2). For details, see section 18, Host Interface. The H8S/2144 Group does not incorporate a
host interface, so do not set this bit to 1 in the H8S/2144 Group.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 86 of 1130
REJ09B0327-0400
Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode.
Bit 6
IOSE Description
0 The AS/IOS pin functions as the address strobe pin (AS)
(Low output when accessing an external area) (Initial value)
1 The AS/IOS pin functions as the I/O strobe pin (IOS)
(Low output when accessing a spec ified address from H'(FF)F000 to H'(FF)FE4F)*
Note: *In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version, the
address range is from H'(FF)F000 to H'(FF)F7FF.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a
read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 A reset is generated by watchdog timer overflow
1 A reset is generated by an external reset (Initial value)
Bit 1—Host Interface Enable (HIE): This bit controls CPU access to the host interface data
registers and control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the
keyboard controller and MOS input pull-up control registers (KMIMR, KMPCR, and KMIMRA),
the 8-bit timer (channel X and Y) data registers and control registers (TCRX/TCRY,
TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR,
TCORAX, and TCORBX), and the timer connection control registers (TCONRI, TCONRO,
TCONRS, and SEDGR).
Bit 1
HIE Description
0 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF,
CPU access to 8-bit timer (channel X and Y) data registers and control
registers, and timer con nec tion co ntro l regist ers, is perm itt ed
(Initial value)
1 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF,
CPU access to host interface data registers and control registers, and
keyboard controller and MOS input pull-up control registers, is permitted
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 87 of 1130
REJ09B0327-0400
Bit 0—RA M Enable ( R AME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in sof twar e stan dby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
3.2.3 Bus Control Register (BCR)
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
IOS0
1
R/W
2
—
1
R/W
1
IOS1
1
R/W
Bit
Initial value
Read/Write
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the I/O area range when the AS pin is designated for use as the I/O strobe. For details on bits 7
to 2, see section 6.2.1, Bus Control Register (BCR).
BCR is initia lized to H'D7 by a reset and in hardware stan dby mode.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the
AS/IOS pin output goes low when IOSE = 1.
BCR
Bit 1 Bit 0
IOS1 IOS0 Description
0 0 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F03F
1 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F0FF
1 0 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F3FF
1 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)FE4F*(Initi al val ue)
Note: *In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version, the
address range is from H'(FF)F000 to H'(FF)F7FF.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 88 of 1130
REJ09B0327-0400
3.2.4 Serial Timer Control Register (STCR)
7
IICS
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
Bit
Initial value
Read/Write
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions),
and also selects the TCNT input clock. For details of functions other than register access control,
see the descriptions of the relevant modules. If a module controlled by STCR is not used, do not
write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mod e .
Bits 7 to 5—I2C Control (IICS, IICX1, IICX0): These bits control the bus buffer function of the
port A and the op eration of the I2C bus interface when the on-chip IIC op tion is included. For
details, see section 16.2.7, Serial/Timer Control Register (STCR).
Bit 4—I2C Master Enable (IICE): Controls CPU access to the I2C bus interface data registers
and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and
control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),
and the SCI contro l registers (SMR, BRR, and SCMR).
Bit 4
IICE Description
0 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used
for SCI1 control register access (Initial value)
Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used
for SCI2 control register access
Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used
for SCI0 control register access
1 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used
for IIC1 data register and control register access
Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used
for PWMX data register and control register access
Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used
for IIC0 data register and control register access
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 89 of 1130
REJ09B0327-0400
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1 , FLMCR2, EBR1, and EBR2), the power-down mode control
registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control
register (PCSR and SYSCR2).
Bit 3
FLSHE Description
0 Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register
and supporting modu le control register ac ces s (Initial value)
1 Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register
access (F-ZTAT version only)
Bit 2—Reserved: Do not write 1 to this b it.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits
CKS2 to CKS0 in TCR, select the clock to b e input to TCNT. For details, see section 1 2.2.4,
Timer Control Register (TCR).
3.3 Operating Mode Descriptions
3.3.1 Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.
Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries
bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus.
3.3.2 Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled.
After a reset, single- chip mode is set, and the EXPE bit in MDCR m ust be set to 1 in ord e r to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset.
They can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing
the ABW bit to 0 in the WSCR register makes po r t B a data bus.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 90 of 1130
REJ09B0327-0400
3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled.
After a reset, single- chip mode is set, and the EXPE bit in MDCR m ust be set to 1 in ord e r to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing
the ABW bit to 0 in the WSCR register makes port B a data bus.
In this operating mode, the available amount of on-chip ROM in products with 64 kbytes or more
of ROM is limited to 56 kbytes.
3.4 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 3, 9, A, and B vary depending on the operating mode. Table 3.3
shows their functions in each operating mode.
Table 3.3 Pin Functions in Each Mo de
Port Mode 1 Mode 2 Mode 3
Port 1 A P*/A P*/A
Port 2 A P*/A P*/A
Port A P P*/A P
Port 3 D P*/D P*/D
Port B P*/D P*/D P*/D
Port 9 P97 P*/C P*/C P*/C
P96 C*/P P*/C P*/C
P95 to P93 C P*/C P*/C
P92 to P91 P P P
P90 P*/C P*/C P*/C
Legend:
P: I/O port
A: Address bus output
D: Data bus I/O
C: Control signals, clo ck I/O
*: After reset
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 91 of 1130
REJ09B0327-0400
3.5 Memory Map in Each Operating Mode
Figures 3.1 to 3.5 show memory maps for each of the operating modes.
The address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 Mbytes in mode 2
(advanced mode).
The on-chip ROM capacity is 64 kbytes (H8S/2142, H8S/2147, and H8S/2147N), 96 kbytes
(H8S/2143), or 128 kbytes (H8S/2144 and H8S/2148), but only 56 kbytes are available in mode 3
(normal mode).
Do not access the reserved area and addresses of modules not supported by the product. Note that
normal operation is not guaranteed when these regions are accessed.
For details, see section 6, Bus Controller.
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 92 of 1130
REJ09B0327-0400
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
H'DFFF
H'0000
H'DFFF
H'0000
External address
space On-chip ROM
External address
space
On-chip ROM
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'EFFF
H'E080
H'EFFF
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Internal I/O registers 2
On-chip RAM*
Internal I/O registers 1
H'EFFF
On-chip RAM*On-chip RAM
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 H8S/2148 (Except for F-ZTAT A-Mask Version) and H8S/2144 Memory Map in
Each Operating Mode
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 93 of 1130
REJ09B0327-0400
H'01FFFF
H'020000
H'000000
H'01FFFF
H'000000
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFFFFF
Mode 2/EXPE = 0
(advanced single-chip mode)
On-chip ROM
External address
space
On-chip ROM
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
Internal I/O registers 2
On-chip RAM*
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
On-chip RAM
Internal I/O registers 1
On-chip RAM
(128 bytes)
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 H8S/2148 (Except for F-ZTAT A-Mask Version) and H8S/2144 Memory Map in
Each Operating Mode (cont)
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 94 of 1130
REJ09B0327-0400
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
H'DFFF
H'0000
H'DFFF
H'0000
External address
space On-chip ROM
External address
space
On-chip ROM
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'EFFF
H'E080
H'EFFF
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Internal I/O registers 2
On-chip RAM*
Internal I/O registers 1
H'EFFF
H'F800H'F800
On-chip RAM*On-chip RAM
H'E080
H'FEFF
H'FFFF
H'FE50 H'FE4FH'FE4F
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
Reserved area Reserved area
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.2 H8S/2148 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 95 of 1130
REJ09B0327-0400
H'01FFFF
H'020000
H'000000
H'01FFFF
H'000000
H'FFFE4F
H'FFE080
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFFFFF
Mode 2/EXPE = 0
(advanced single-chip mode)
On-chip ROM
External address
space
On-chip ROM
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
Internal I/O registers 2
On-chip RAM*
Internal I/O registers 1
On-chip RAM
(128 bytes)*
Reserved area
External address
space
H'FFEFFF
H'FFF800
Internal I/O registers 2
On-chip RAM
Internal I/O registers 1
On-chip RAM
(128 bytes)
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.2 H8S/2148 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
(cont)
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 96 of 1130
REJ09B0327-0400
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
H'DFFF
H'0000
H'DFFF
H'0000
External address
space On-chip ROM
External address
space
On-chip ROM
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'EFFF
H'E080
H'EFFF
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Internal I/O registers 2
On-chip RAM*
Internal I/O registers 1
H'EFFF
On-chip RAM*On-chip RAM
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.3 H8S/2143 Memory Map in Each Operating Mode
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 97 of 1130
REJ09B0327-0400
H'01FFFF
H'020000
H'000000
H'017FFF
H'01FFFF
H'000000
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFFFFF
Mode 2/EXPE = 0
(advanced single-chip mode)
On-chip ROM
Reserved area
External address
space
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
Internal I/O registers 2
On-chip RAM*
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
On-chip RAM
H'017FFF
On-chip ROM
Reserved area
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.3 H8S/2143 Memory Map in Each Operating Mode (cont)
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 98 of 1130
REJ09B0327-0400
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
H'DFFF
H'0000
H'DFFF
H'0000
External address
space On-chip ROM
External address
space
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'EFFF
H'E080
H'EFFF
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Internal I/O registers 2
On-chip RAM*
Reserved area*
Internal I/O registers 1
H'EFFF
H'E880 On-chip RAM*
Reserved area*
H'E880 On-chip RAM
Reserved area
H'E880
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)*
External address
space
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
On-chip ROM
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.4 H8S/2147 (Except for F-ZTAT A-Ma sk Version), H8S/2147N, and H8S/2142
Memory Map in Each Operating Mode
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 99 of 1130
REJ09B0327-0400
H'01FFFF
H'020000
H'000000
H'00FFFF
H'01FFFF
H'000000
H'FFEFFF
H'FFE080
H'FFE880
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFFFFF
Mode 2/EXPE = 0
(advanced single-chip mode)
On-chip ROM
Reserved area
External address
space
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
Internal I/O registers 2
On-chip RAM*
Reserved area*
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
H'FFE880 On-chip RAM
Reserved area
H'00FFFF
On-chip ROM
Reserved area
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.4 H8S/2147 (Except for F-ZTAT A-Ma sk Version), H8S/2147N, and H8S/2142
Memory Map in Each Operating Mode (cont)
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 100 of 1130
REJ09B0327-0400
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
H'DFFF
H'0000
H'DFFF
H'0000
External address
space On-chip ROM
External address
space
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'EFFF
H'E080
H'EFFF
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Internal I/O registers 2
On-chip RAM*
Reserved area*
Internal I/O registers 1
H'EFFF
H'F800H'F800 H'FE4FH'FE4F
H'E880 On-chip RAM*
Reserved area*
H'E880 On-chip RAM
Reserved area
H'E880
H'E080
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)*
External address
space
Reserved area Reserved area
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
On-chip ROM
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.5 H8S/2147 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 101 of 1130
REJ09B0327-0400
H'01FFFF
H'020000
H'000000
H'00FFFF
H'01FFFF
H'000000
H'FFEFFF
H'FFE080
H'FFE880
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFE4F
H'FFF800
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFEFFF
H'FFE080
H'FFFEFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFFFFF
Mode 2/EXPE = 0
(advanced single-chip mode)
On-chip ROM
Reserved area
External address
space
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
Internal I/O registers 2
On-chip RAM*
Reserved area*
Internal I/O registers 1
On-chip RAM
(128 bytes)*
External address
space
Reserved area
H'FFE880 On-chip RAM
Reserved area
H'00FFFF
On-chip ROM
Reserved area
Internal I/O registers 2
Internal I/O registers 1
On-chip RAM
(128 bytes)
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.5 H8S/2147 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
(cont)
Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 102 of 1130
REJ09B0327-0400
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 103 of 1130
REJ09B0327-0400
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the
RES pin, or when the watchdog timer overflows.
Trace*1Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1.
Interrupt Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued.*2
Direct transition Started by a direct transition resulting from execution of a
SLEEP instruction.
Low Trap instruction (TRAPA)*3Started by execution of a trap instruc tio n (TRAPA).
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in
this LSI.) Trace exception handling is not executed after execution of an RTE
instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in the program
execution stat e.
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 104 of 1130
REJ09B0327-0400
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack .
2. The interr upt ma sk bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3 Exception Sources and Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Exception
sources
Reset
Trace
Interrupts
Direct transition
Trap instruction
(Cannot be used in this LSI)
External interrupts: NMI, IRQ7 to IRQ0
Internal interrupts: interrupt sources in
on-chip supporting modules
Figure 4.1 Exception Sources
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 105 of 1130
REJ09B0327-0400
Table 4.2 Exception Vector Table
Vector Address*1
Exception Source Vector Number Normal Mode Advanced Mode
Reset 0 H'0000 to H'0001 H'0000 to H'0003
Reserved for system use 1 H'0002 to H'0003 H'0004 to H'0007
2 H'0004 to H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
4 H'0008 to H'0009 H'0010 to H'0013
5 H'000A to H'000B H'0014 to H'0017
Direct transition 6 H'000C to H'000D H'0018 to H'001B
External interrupt NMI 7 H'000E to H'000F H'001C to H'001F
Trap instruction (4 sources) 8 H'0010 to H'0011 H'0020 to H'0023
9 H'0012 to H'0013 H'0024 to H'0027
10 H'0014 to H'0015 H'0028 to H'002B
11 H'0016 to H'0017 H'002C to H'002F
Reserved for system use 12 H'0018 to H'0019 H'0030 to H'0033
13 H'001A to H'001B H'0034 to H'0037
14 H'001C to H'001D H'0038 to H'003B
15 H'001E to H'001F H'003C to H'003F
External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043
IRQ1 17 H'0022 to H'0023 H'0044 to H'0047
IRQ2 18 H'0024 to H'0025 H'0048 to H'004B
IRQ3 19 H'0026 to H'0027 H'004C to H'004F
IRQ4 20 H'0028 to H'0029 H'0050 to H'0053
IRQ5 21 H'002A to H'002B H'0054 to H'0057
IRQ6 22 H'002C to H'002D H'0058 to H'005B
IRQ7 23 H'002E to H'002F H'005C to H'005F
Internal interrupt*224
103
H'0030 to H'0031
H'00CE to H'00CF
H'0060 to H'0063
H'019C to H'019F
Notes: 1. Lower 16 bits of the address.
2. For details on internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector
Table.
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 106 of 1130
REJ09B0327-0400
4.2 Reset
4.2.1 Overview
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset
initializes the internal state of the CPU and the registers o f on-chip supportin g modules.
Immediately af ter a reset, interrupt control mode 0 is set.
Reset exception handling begins when the RES pin changes from low to high.
The MCUs can also be reset by overflow of the watchdog timer. For details, see section 14,
Watchdog Timer (WDT).
4.2.2 Reset Sequence
The MCU enters the reset state when the RES pin goes low.
To ensure th at the chip is r eset, hold the RES pin low for at least 20 ms when powering on. To
reset the chip during operation, hold th e RES pin low for at least 20 states. For pin states in a reset,
see appendix D.1, Port States in Each Processing State.
When the RES pin goes high after being held lo w for the necessary time, the chip starts re set
exception handling as follows:
[1] The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
[2] The reset exception vector address is read and transferred to the PC, and program execution
starts from the address indicated by the PC.
Figures 4.2 and 4.3 show examples of the reset sequence.
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 107 of 1130
REJ09B0327-0400
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1) (3)
Vector
fetch Internal
processing
Fetch of
first program
instruction
High
(1) Reset exception vector address ((1) = H'0000)
(2) Start address (contents of reset exception vector address)
(3) Start address ((3) = (2))
(4) First program instruction
(2) (4)
φ
RES
Figure 4.2 Reset Sequence (Mode 3)
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 108 of 1130
REJ09B0327-0400
Address bus
Vector fetch Internal
processing
Fetch of
first program
instruction
(1) (3) Reset exception vector address ((1) = H'0000, (3) = H'0001)
(2) (4) Start address (contents of reset exception vector address)
(5) Start address ((5) = (2) (4))
(6) First program instruction
φ
RES
(1) (5)
High
(2) (4)
(3)
(6)
RD
HWR, LWR
D15 to D8
*
Note: * 3 program wait states are inserted.
**
Figure 4.3 Reset Sequence (Mode 1)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC an d
CCR will not be saved correctly , leadin g to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state en ds, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 109 of 1130
REJ09B0327-0400
4.3 Interrupts
Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0)
from 23 input pins (NMI, IRQ7 to IRQ0, and KIN15 to KIN0), and internal sources in the on-chip
supporting modules. Figure 4.4 shows the interrupt sources and th e number of interrupts of each
type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), data
transfer controller (DTC), A/D converter (ADC), host interface (HIF), keyboard buffer controller
(PS2), and I2C bus interface (option). Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts ar e controlled by the interrupt contro ller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI and
address br eak to either three priority/mask levels to enable multiplexed interrupt control.
For details on interrupts, see section 5, Interrupt Controller.
Interrupts
External
interrupts
Internal
interrupts
NMI (1)
IRQ7 to IRQ0 (8)
WDT* (2)
FRT (7)
TMR (10)
SCI (12)
DTC (1)
ADC (1)
HIF (4)
PS2 (3)
IIC (3) (option)
Other (1)
Numbers in parentheses are the numbers of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at each counter overflow.
Notes:
Figure 4.4 Interrupt Sources and Number of Interrupts
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 110 of 1130
REJ09B0327-0400
4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instructio n is executed. Trap instru ction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.3 Status of CCR and EXR after Trap Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
01———
111——
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 111 of 1130
REJ09B0327-0400
4.5 Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP CCR
CCR*
PC
(16 bits)
Interrupt control modes 0 and 1
Note: * Ignored on return.
Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode)
SP CCR
PC
(24 bits)
Interrupt control modes 0 and 1
Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode)
Section 4 Exception Handling
Rev. 4.00 Sep 27, 2006 page 112 of 1130
REJ09B0327-0400
4.6 Notes on Use of the Stack
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP: ER7) should always be kept even. Use the following
instruc tions to save registe rs:
PUSH.W Rn (or MOV.W Rn, @-SP)
PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what
happens when the SP value is odd.
SP
Legend:
CCR: Condition-code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced
mode.
SP
SP
CCR
PC
R1L
PC
H'FFEFFA
H'FFEFFB
H'FFEFFC
H'FFEFFD
H'FFEFFF
MOV.B R1L, @–ER7
SP set to H'FFEFFF
TRAP instruction executed
Data saved above SP Contents of CCR lost
Figure 4.6 Operation when SP Value Is Odd
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 113 of 1130
REJ09B0327-0400
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
This LSI control interrupts by means of an interrupt controller. The interrupt controller has the
following features:
• Two interrupt control modes
Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
• Priorities settable with ICR
An interru pt control register (ICR) is p r ovided for setting in terrupt priorities. Three prio r ity
levels can be set for each module for all interrupts except NMI and address break.
• Independent vect or address es
All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be id entified in the interrupt handling routine.
• Twenty-three external interrupt pins (nine external sources)
NMI is the highest-priority in terrup t, and is accepted at all times. A rising or falling edge at
the NMI pin can be selected for the NMI interrupt.
Falling edge, rising edge, or both edge detection, or level sensing, at pins IRQ7 to IRQ0
can be selected for interrupts IRQ7 to IRQ0.
The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt
inputs (KIN7 to KIN0), and the IRQ7 interrupt is sh ar ed b y the in terrupt from the IRQ7 pin
and eight external interrupt inputs (KIN15 to KIN8). KIN15 to KIN0 can be masked
individuall y by the user program .
• DTC control
DTC activation is controlled by means of interrupts.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 114 of 1130
REJ09B0327-0400
5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
SYSCR
NMI input
IRQ input
Internal interrupt
requests
SWDTEND to PS2IC
INTM1 INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
ICR
Interrupt controller
Priority
determination
Interrupt
request
Vector
number
I, UI CCR
CPU
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt control register
System control register
Legend:
ISCR:
IER:
ISR:
ICR:
SYSCR:
Figure 5.1 Block Diagram of Interrupt Controller
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 115 of 1130
REJ09B0327-0400
5.1.3 Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Interrupt Controller Pins
Name Symbol I/O Function
Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 7 to 0 IRQ7 to IRQ0 Input Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected.
Key input interrupt
requests 15 to 0 KIN15 to KIN0 Input Maskable external interrupts: falling edge or
level sensing can be selected.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 116 of 1130
REJ09B0327-0400
5.1.4 Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2 Interrupt Controller Registers
Name Abbreviation R/W Initial Value Address*1
System control register SYSCR R/W H'09 H'FFC4
IRQ sense control register H ISCRH R/W H'00 H'FEEC
IRQ sense control register L ISCRL R/W H'00 H'FEED
IRQ enable register IER R/W H'00 H'FFC2
IRQ status register ISR R/(W)*2H'00 H'FEEB
Keyboard matrix interrupt mask
register KMIMR R/W H'BF H'FFF1*3
Keyboard matrix interrupt mask
register A KMIMRA R/W H'FF H'FFF3*3
Interrupt control register A ICRA R/W H'00 H'FEE8
Interrupt control register B ICRB R/W H'00 H'FEE9
Interrupt control register C ICRC R/W H'00 H'FEEA
Address break control register ABRKCR R/W H'00 H'FEF4
Break address register A BARA R/W H'00 H'FEF5
Break address register B BARB R/W H'00 H'FEF6
Break address register C BARC R/W H'00 H'FEF7
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
3. When setting KMIMR and KMIMRA, the HIE bit in SYSCR must be set to 1, and also
MSTP2 bit in MSTPCRL must be set to 0.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 117 of 1130
REJ09B0327-0400
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
SYSCR is an 8-bit readable/writab le r egister that selects the inter r upt control mode, and the
detected edge for NMI, among other functions.
Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four
interrupt control modes for the interrup t contr o ller. The INTM1 bit must not be set to 1.
Bit 5 Bit 4 Interrupt
INTM1 INTM0 Control Mode Description
0 0 0 Interrupts are controlled by I bit ( Initi al val ue)
1 1 Interrupts are controlled by I and UI bits and ICR
1 0 2 Cannot be used in this LSI
1 3 Cannot be used in this LSI
Bit 2—NMI Edge Sele ct (NMIEG) : Selects the input edge for the NMI pin.
Bit 2
NMIEG Description
0 Interrupt request generated at falling edge of NMI input (Initial value)
1 Interrupt request generated at rising edge of NMI input
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 118 of 1130
REJ09B0327-0400
5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)
7
ICR7
0
R/W
6
ICR6
0
R/W
5
ICR5
0
R/W
4
ICR4
0
R/W
3
ICR3
0
R/W
0
ICR0
0
R/W
2
ICR2
0
R/W
1
ICR1
0
R/W
Bit
Initial value
Read/Write
The ICR register s ar e three 8-bit readable/writable registers that set the interrupt control level for
interrupts other than NMI and address break.
The correspondence between ICR settings and interrupt sources is shown in table 5.3.
The ICR registers ar e initialized to H'00 by a r e set and in hardware standby mode.
Bit n—Interrupt Co ntrol Level (ICRn): Sets the contro l level for the corresponding inter rupt
source.
Bit n
ICRn Description
0 Corresponding interrupt sour ce is control level 0 (non-priority) (Initial value)
1 Corresponding interrupt source is control level 1 (priority)
Note: n = 7 to 0
Table 5.3 Correspondence between Interrupt Sources and ICR Settings
Bits
Register76543210
ICRA IRQ0 IRQ1 IRQ2
IRQ3 IRQ4
IRQ5 IRQ6
IRQ7 DTC Watchdog
timer 0 Watchdog
timer 1
ICRB A/D
converter Free-
running
timer
— — 8-bit
timer
channel 0
8-bit
timer
channel 1
8-bit
timer
channels
X, Y
HIF,
Keyboard
buffer
controller
ICRC SCI
channel 0 SCI
channel 1 SCI
channel 2 IIC
channel 0
(option)
IIC
channel 1
(option)
———
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 119 of 1130
REJ09B0327-0400
5.2.3 IRQ Enable Register (IER)
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
Bit
Initial value
Read/Write
IER is an 8-bit readable/writable reg ister th at controls enabling and disabling of interrupt requests
IRQ7 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to
IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQn interrupt disabled (Initial value)
1 IRQn interrupt enabled
Note: n = 7 to 0
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
• ISCRH
15
IRQ7SCB
0
R/W
14
IRQ7SCA
0
R/W
13
IRQ6SCB
0
R/W
12
IRQ6SCA
0
R/W
11
IRQ5SCB
0
R/W
8
IRQ4SCA
0
R/W
10
IRQ5SCA
0
R/W
9
IRQ4SCB
0
R/W
Bit
Initial value
Read/Write
• ISCRL
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
3
IRQ1SCB
0
R/W
0
IRQ0SCA
0
R/W
2
IRQ1SCA
0
R/W
1
IRQ0SCB
0
R/W
Bit
Initial value
Read/Write
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 120 of 1130
REJ09B0327-0400
ISCRH and ISCRL are 8 -bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
Each of the ISCR reg ister s is initialized to H'0 0 by a reset and in hardware standby mode.
ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to
IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB)
ISCRH Bits 7 to 0
ISCRL Bits 7 to 0
IRQ7SCB to
IRQ0SCB IRQ7SCA to
IRQ0SCA Description
0 0 Interrupt request generated at IRQ7 to IRQ0 input low level
(Initial value)
1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input
1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1 Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
5.2.5 IRQ Status Register (ISR)
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
0
IRQ0F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit r eadable/writable register that in dicates the status of IRQ7 to I RQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in h a rdware standby mode.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 121 of 1130
REJ09B0327-0400
Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Bit n
IRQnF Description
0 [Clearing conditions ] (Initial val ue)
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt ex cept ion handling is executed while low-le vel det ection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high*
• When IRQn interrupt exception handling is executed while falling, rising, or both-edge
detection is set (IRQnSCB = 1 or IRQnSCA = 1)*
1 [Setting conditions]
• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in IRQn input while falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input whil e rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
Notes: n = 7 to 0
*When a product, in which a DTC is incorporated, is used in the following settings, the
corresponding flag bit is not automatically cleared even when exception handling, which
is a clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source), IRQ4F flag is not
automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source), IRQ5F flag is not
automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source), IRQ6F flag is not
automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt source), IRQ7F flag is not
automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts are used with the above
combinations, clear the interrupt flag by software in the interrupt handling routine of the
corresponding IRQ.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 122 of 1130
REJ09B0327-0400
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR)
7
KMIMR7
1
R/W
6
KMIMR6
0
R/W
5
KMIMR5
1
R/W
4
KMIMR4
1
R/W
3
KMIMR3
1
R/W
0
KMIMR0
1
R/W
2
KMIMR2
1
R/W
1
KMIMR1
1
R/W
Bit
Initial value
Read/Write
KMIMR is an 8-b it r eadable/writable register that p e r forms mask control for the keyboard matrix
interru pt inputs (pins KIN7 to KIN0). To enable key-sense input interrupts from multiple pin
inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0.
KMIMR is initialized to H'BF by a reset and in hardware standby mode and only IRQ6 (KIN6)
input is enabled.
Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control
key-sense input interrupt requests (KIN7 to KIN0).
Bits 7 to 0
KMIMR7 to
KMIMR0 Description
0 Key-sense input interrupt requests enabled
1 Key-sense input interrupt requests disabled (Initial value)*
Note: *However, the initial value of KMIMR6 is 0 because the KMIMR6 bi t controls both IRQ6
interrupt request masking and key-sense input enabling.
5.2.7 Keyboard Matrix Interrupt Mask Register (KMIMRA)
7
KMIMR15
1
R/W
6
KMIMR14
1
R/W
5
KMIMR13
1
R/W
4
KMIMR12
1
R/W
3
KMIMR11
1
R/W
0
KMIMR8
1
R/W
2
KMIMR10
1
R/W
1
KMIMR9
1
R/W
Bit
Initial value
Read/Write
KMIMRA is an 8-bit readable/writable register that performs mask control for the keyboard
matrix in ter rupt inputs (pin s KIN15 to KIN8). To enable key-sense input interrupts from multiple
pin inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0.
KMIMRA is initialized to H'FF by a reset and in hardware standby mode.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 123 of 1130
REJ09B0327-0400
Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control
key-sense input interrupt requests (KIN15 to KIN8).
Bits 7 to 0
KMIMR15
to KMIMR8 Description
0 Key-sense input interrupt requests enabled
1 Key-sense input interrupt requests disabled (Initial value)
Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0,
and registers KMIMR and KMIMRA.
IRQ6 internal signal
IRQ6E
Edge/level
selection
enable/disable
circuit
Edge/level
selection
enable/disable
circuit
IRQ6SC
IRQ6
interrupt
KMIMR0 (initial value 1)
P60/KIN0
KMIMR5 (initial value 1)
P65/KIN5
KMIMR6 (initial value 0)
P66/KIN6/IRQ6
KMIMR7 (initial value 1)
P67/KIN7/IRQ7
IRQ7 internal signal
IRQ7E
IRQ7SC
IRQ7
interrupt
KMIMR8 (initial value 1)
PA0/KIN8
KMIMR9 (initial value 1)
PA1/KIN9
KMIMR15 (initial value 1)
PA7/KIN15
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
and Registers KMIMR an d KMI MRA
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 124 of 1130
REJ09B0327-0400
If any of bits KMIMR15 to KMIMR8 is cleared to 0, interrupt input from the IRQ7 pin will be
ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins,
either low-lev el sensing or falling - edg e sensing must be designated as the interrupt sen se co ndition
for the corresponding interrupt source (IRQ6 or IRQ7).
5.2.8 Addres s Break Control Register (ABRKCR)
7
CMF
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
BIE
0
R/W
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
ABRKCR is an 8-bit readable/writable register that performs address break control.
ABRKCR is initial ized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Condition Ma tch Flag (CMF): This is the address break source flag, used to indicate that
the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an
address break is requested.
Bit 7
CMF Description
0 [Clearing cond iti on]
When address break interrupt exception handling is executed (Initial value)
1 [Setting condition]
When address set by BARA to BARC is prefetched while BIE = 1
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Break Interrupt Enable (BIE): Selects address break enabling or disabling.
Bit 0
BIE Description
0 Address break disabled (Initial value)
1 Address break enabled
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 125 of 1130
REJ09B0327-0400
5.2.9 Break Address Reg isters A, B, C (BARA, BARB, BARC)
7
A23
0
R/W
6
A22
0
R/W
5
A21
0
R/W
4
A20
0
R/W
3
A19
0
R/W
0
A16
0
R/W
2
A18
0
R/W
1
A17
0
R/W
Bit
BARA
Initial value
Read/Write
7
A15
0
R/W
6
A14
0
R/W
5
A13
0
R/W
4
A12
0
R/W
3
A11
0
R/W
0
A8
0
R/W
2
A10
0
R/W
1
A9
0
R/W
Bit
BARB
Initial value
Read/Write
7
A7
0
R/W
6
A6
0
R/W
5
A5
0
R/W
4
A4
0
R/W
3
A3
0
R/W
0
—
0
—
2
A2
0
R/W
1
A1
0
R/W
Bit
BARC
Initial value
Read/Write
BAR consists of three 8-bit readable/writable registers (BARA, BARB, and BARC), and is used to
specify the address at which an address break is to be executed.
Each of the BAR registers is initialized to H'00 by a reset and in hardwar e standby mode. They are
not initialized in software standby m ode.
BARA Bits 7 to 0—Address 23 to 16 (A23 to A16)
BARB Bits 7 to 0—Address 15 to 8 (A15 to A8)
BARC Bits 7 to 1—Address 7 to 1 (A7 to A1)
These bits specify the address at which an address break is to be executed. BAR bits A23 to A1
are compared with internal address bus lines A23 to A1, respectively.
The address at which the first instruction byte is located should be specified as the break address.
Occurrence of the address break condition may not be recognized for other addresses.
In normal mode, no comparison is made with address lines A23 to A16.
BARC Bit 0—Reserved: This bit cannot be modified and is always read as 0.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 126 of 1130
REJ09B0327-0400
5.3 Interrupt Sources
Interrupt sou r ces comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts.
5.3.1 External Interrupts
There are nine external interrupt sources from 25 input pins (23 actual pins): NMI, IRQ7 to IRQ0,
and KIN15 to KIN0. KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the
IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore the
H8S/2148 Group or H8S/2144 Group chip from software standby mode.
NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt
control mode and the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be
used to select whether an interrupt is requested at a risin g edge or a falling ed ge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Inter rupts
Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to
IRQ0 have the following features:
• Using ISCR, it is p ossible to select whether an interrupt is generated by a low level, fallin g
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt control level can be set with ICR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 127 of 1130
REJ09B0327-0400
IRQn interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge/level
detection circuit
IRQnSCA, IRQnSCB
IRQn
input
Note: n: 7 to 0
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0
Figure 5.4 shows the timing of IRQnF setting.
φ
IRQn
input pin
IRQnF
Figure 5.4 Timing of IRQnF Setting
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. Therefore, when a pin is used as an external interrupt input pin, clear the
corresponding DDR bit to 0 and do not use the pin as an I/O pin for another function. Wh en the
IRQ6 pin is assigned as the IRQ6 interrupt input pin, then set the KMIMR6 bit to 0.
When the IRQ7 pin is used as the IRQ7 interrupt input pin, bits KMIMR15 to KMIMR8 must all
be set to 1. If any of these bits is cleared to 0, interrup t inpu t from the IRQ7 pin will be ignored.
As interrup t r e quest f lags IRQ7F to IRQ0F are set when the setting condition is met, regar dless of
the IER setting, only the necessary flags should be referenced.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 128 of 1130
REJ09B0327-0400
Interrupts K IN15 t o KIN0
Interrupts KIN15 to KIN0 are requested by input signals at pins KIN15 to KIN 0. When any of
pins KIN15 to KIN0 are used as key-sense inputs, the corresponding KMIMR bits should be
cleared to 0 to enable those key-sense input interrupts. The remaining unused key-sense input
KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN15 to KIN8 correspond
to the IRQ7 interr upt, and interrupts KIN7 to KIN0 correspon d to the IRQ6 interrupt. Interrupt
request g eneration pin conditions, in ter rupt request enabling, interrupt control level settin g, and
interrupt request status indications, are all in accordance with the IRQ7 and IRQ6 interrupt
settings.
When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins, either
low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for
the corresponding interrupt source (IRQ6 or IRQ7).
5.3.2 Internal Interrupts
There are 43 sources for internal interrupts from on-chip supporting modules, plus one software
interrupt source (address break).
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select en abling or disablin g of these interrupts. If any one of these is set to
1, an interrup t requ e st is issued to the inter rup t contr o ller.
• The interrupt co ntrol level can be set by me ans o f ICR.
• The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. Wh en the DTC is
activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect.
5.3.3 Interrupt Exception Vector Table
Table 5.4 shows in terrupt exception ha ndling sources, vector add r esses, and interrupt prio rities.
For default priorities, the lower the vector number, the high e r the prio r ity.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 129 of 1130
REJ09B0327-0400
Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address
Interrupt Source
Origin of
Interrupt
Source Vector
Number Normal
Mode Advanced
Mode ICR Priority
NMI 7 H'000E H'00001C High
IRQ0 External
pin 16 H'0020 H'000040 ICRA7
IRQ1 17 H'0022 H'000044 ICRA6
IRQ2 18 H'0024 H'000048 ICRA5
IRQ3 19 H'0026 H'00004C
IRQ4 20 H'0028 H'000050 ICRA4
IRQ5 21 H'002A H'000054
IRQ6, KIN7 to KIN0 22 H'002C H'000058 ICRA3
IRQ7, KIN15 to KIN8 23 H'002E H'00005C
SWDTEND (software
activation interrupt end) DTC 24 H'0030 H'000060 ICRA2
WOVI0 (interval timer) Watchdog
timer 0 25 H'0032 H'000064 ICRA1
WOVI1 (interval timer) Watchdog
timer 1 26 H'0034 H'000068 ICRA0
Address break (PC break) —27 H'0036 H'00006C
ADI (A/D conversion end) A/D 28 H'0038 H'000070 ICRB7
Reserved —29
to
47
H'003A
to
H'005E
H'000074
to
H'0000BC
ICIA (input capture A) 48 H'0060 H'0000C0 ICRB6
ICIB (input capture B) Free-running
timer 49 H'0062 H'0000C4
ICIC (input capture C) 50 H'0064 H'0000C8
ICID (input capture D) 51 H'0066 H'0000CC
OCIA (output compare A) 52 H'0068 H'0000D0
OCIB (output compare B) 53 H'006A H'0000D4
FOVI (overflow) 54 H'006C H'0000D8
Reserved 55 H'006E H'0000DC
Reserved —56
to
63
H'0070
to
H'007E
H'0000E0
to
H'0000FC Low
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 130 of 1130
REJ09B0327-0400
Vector Address
Interrupt Source
Origin of
Interrupt
Source Vector
Number Normal
Mode Advanced
Mode ICR Priority
CMIA0 (compare-match A) 64 H'0080 H'000100 ICRB3 High
CMIB0 (compare-match B) 8-bit timer
channel 0 65 H'0082 H'000104
OVI0 (overflow) 66 H'0084 H'000108
Reserved 67 H'0086 H'00010C
CMIA1 (compare-match A) 68 H'0088 H'000110 ICRB2
CMIB1 (compare-match B) 69 H'008A H'000114
OVI1 (overflow) 70 H'008C H'000118
Reserved
8-bit timer
channel 1
71 H'008E H'00011C
CMIAY (compare-match A) 72 H'0090 H'000120 ICRB1
CMIBY (compare-match B) 73 H'0092 H'000124
OVIY (overflow) 74 H'0094 H'000128
ICIX (input capture X)
8-bit timer
channels
Y, X
75 H'0096 H'00012C
IBF1 (IDR1 reception completed) 76 H'0098 H'000130 ICRB0
IBF2 (IDR2 reception completed) 77 H'009A H'000134
IBF3 (IDR3 reception completed) 78 H'009C H'000138
IBF4 (IDR4 reception completed)
Host
interface
79 H'009E H'00013C
ERI0 (receive error 0) 80 H'00A0 H'000140
RXI0 (reception com ple ted 0) 81 H'00A2 H'000144
TXI0 (transmit data empty 0) 82 H'00A4 H'000148
TEI0 (transmission end 0)
SCI
channel 0
83 H'00A6 H'00014C
ICRC7
ERI1 (receive error 1) 84 H'00A8 H'000150 ICRC6
RXI1 (reception com ple ted 1) 85 H'00AA H'000154
TXI1 (transmit data empty 1) 86 H'00AC H'000158
TEI1 (transmission end 1)
SCI
channel 1
87 H'00AE H'00015C
ERI2 (receive error 2) 88 H'00B0 H'000160 ICRC5
RXI2 (reception com ple ted 2) SCI
channel 2 89 H'00B2 H'000164
TXI2 (transmit data empty 2) 90 H'00B4 H'000168
TEI2 (transmission end 2) 91 H'00B6 H'00016C
IICI0 (1-byte transmission/
reception completed) IIC channel 0
(option) 92 H'00B8 H'000170 ICRC4
DDCSWI (format switch) 93 H'00BA H'000174 Low
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 131 of 1130
REJ09B0327-0400
Vector Address
Interrupt Source
Origin of
Interrupt
Source Vector
Number Normal
Mode Advanced
Mode ICR Priority
IICI1 (1-byte transmission/
reception completed) IIC channel 1
(option) 94 H'00BC H'000178 ICRC3 High
Reserved 95 H'00BE H'00017C
PS2IA (reception completed A) 96 H'00C0 H'000180 ICRB0
PS2IB (reception completed B) 97 H'00C2 H'000184
PS2IC (reception completed C) 98 H'00C4 H'000188
Reserved
Keyboard
buffer
controller
(PS2) 99 H'00C6 H'00018C
Reserved —100
to
103
H'00C8
to
H'00CE
H'000190
to
H'00019C Low
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 132 of 1130
REJ09B0327-0400
5.4 Address Breaks
5.4.1 Features
With this LSI, it is p ossible to identif y the prefetch of a specific address by the CPU an d generate
an address break interrupt, using the ABRKCR and BAR registers. When an address break
interrupt is generated, address break interrupt exception handling is executed.
This function can be used to detect the beginning of execution of a bug location in the program,
and branch to a correction routine.
5.4.2 Block Diagram
A block diagram of the address break function is shown in figure 5.5.
BAR ABRKCR
Comparator
Match
signal Control logic Address break
interrupt request
Internal address
Prefetch signal
(internal signal)
Figure 5.5 Block Diagram of Address Break Function
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 133 of 1130
REJ09B0327-0400
5.4.3 Operation
ABRKCR and BAR settings can be made so that an address break interrupt is generated when the
CPU prefetches the address set in BAR. This address break function issues an interrupt request to
the interrupt controller when the address is prefetch ed, and the interrupt controller deter m ines the
interrupt priority. When the interrupt is accepted, interrupt exception handling is started on
completion of the currently executing instruction. With an address break interrupt, interru p t mask
control by the I and UI bits in the CPU’s CCR is ineffective.
The register settings when the address break function is used are as follows.
1. Set the br eak address in bits A23 to A1 in BAR.
2. Set the BIE b it in ABRKCR to 1 to enable address br eaks. An address break will not be
requested if the BIE bit is cleared to 0.
When the setting condition o ccurs, th e CMF f lag in ABRKCR is set to 1 and an in ter rupt is
requested. If necessary, the source should be identified in the interrupt handling routine.
5.4.4 Usage Notes
• With the addr ess break function, the address at which the fir st in str uction byte is located
should be specified as the break address. Occurrence of the address break condition may not be
recognized for other addresses.
• In normal mode, no comparison is made with address lines A23 to A16.
• If a branch in str uction (Bcc, BSR), jump instruction (JMP, JSR), RTS instruction , or RTE
instruction is located immediately before the address set in BAR, execution o f this instruction
will output a prefetch signal for that address, an d an address break may be requested. This can
be prevented by not making a break address setting for an address immediately following one
of these instructions, or by determining within the interrupt handlin g routine whether interrupt
handling was initiated by a genuine condition occurrence.
• As an address break interrupt is generated by a combination of the internal prefetch sign al and
address, the timing of the start of interrupt exception handling depends on the content and
execution cycle of the instruction at the set address and the preceding instruction. Figure 5.6
shows some address timing examples.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 134 of 1130
REJ09B0327-0400
Address bus
Break request
signal
Breakpoint NOP instruction is executed at breakpoint address H'0312 and
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
φ
Instruction
fetch Internal
operation Internal
operation
Vector
fetch
Stack save Instruction
fetch
H'0310
NOP
execution
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
NOP
execution NOP
execution Interrupt exception handling
H'0312 H'0314 H'0316 H'0318 H'0036SP-2 SP-4
• Program area in on-chip memory, 1-state execution instruction at specified break address
Instruction
fetch
Address bus
Break request
signal
Breakpoint MOV instruction is executed at breakpoint address H'0312,
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
φ
Internal
operation Internal
operation
Vector
fetch
Stack save Instruction
fetch
H'0310
NOP
execution
H'0310 NOP
H'0312 MOV.W #xx:16,Rd
H'0316 NOP
H'0318 NOP
MOV.W
execution Interrupt exception handling
H'0312 H'0314 H'0316 H'0318 H'0036SP-2 SP-4
• Program area in on-chip memory, 2-state execution instruction at specified break address
Address bus
Break request
signal
Breakpoint NOP instruction at breakpoint address H'0312 is not executed;
fetch from address H'0312 starts after end of exception handling.
φ
Instruction
fetch Internal
operation Internal
operation
Vector
fetch
Stack save
H'0310
NOP
execution
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Interrupt exception handling
H'0312 H'0314 H'0036SP-2 SP-4
• Program area in external memory (2-state access, 16-bit-bus access),
1-state execution instruction at specified break address
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch Instruction
fetch Instruction
fetch Instruction
fetch
Instruction
fetch
Instruction
fetch
Figure 5.6 Examples of Address Break Timing
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 135 of 1130
REJ09B0327-0400
5.5 Interrupt Operation
5.5.1 Interrupt Control Modes and Interrupt Operation
Interrupt operations in this LSI differ depending on the interrupt control mode.
NMI and address break interrupts are accepted at all times except in the reset state and the
hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an
enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding
interrupt r equest. Interrupt sources for which th e enab le b its are set to 1 are controlled by the
interrupt controller.
Table 5.5 shows the interrup t control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated
by the I and UI bits in the CPU’s CCR.
Table 5.5 Interrupt Control Modes
SYSCR
Interrupt
Control Mode INTM1 INTM0 Priority Setting
Register Interrupt
Mask Bits Description
0 0 0 ICR I Interrupt mask control is
performed by the I bit
Priority can be set with ICR
1 1 ICR I, UI 3-level interrupt mask control
is performed by the I and UI
bits
Priority can be set with ICR
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 136 of 1130
REJ09B0327-0400
Figure 5.7 shows a block diagram of th e priority decision circuit.
ICR
UII
Default priority
determination Vector
number
Interrupt
acceptance control
and 3-level mask
control
Interrupt
source
Interrupt control modes
0 and 1
Figure 5.7 Block Diagram of Interrupt Control Operation
Interrupt Acceptance Control and 3-Level Control
In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is
performed by means of the I and UI bits in CCR, and ICR (control level).
Table 5.6 shows the interrupts selected in each interrupt control mode.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 137 of 1130
REJ09B0327-0400
Table 5.6 Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode I UI Selected Interrupts
00*All interrupts (c ontrol level 1 has priority)
1*NMI and address break interrupts
10*All interrupts (c ontrol level 1 has priority)
1 0 NMI, address break and control level 1
interrupts
1 NMI, and address break interrupts
Legend:
*: Don’t care
Default Priority Determination
The priority is deter m ined for the selected interrupt, and a vector number is generated.
If the same value is set for ICR, acceptance of multiple in terrupts is en abled, and so only the
interrupt source with the highest priority according to the p reset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.7 shows operations and control signal functions in each interrupt control mode.
Table 5.7 Operations and Control Signal Functions in Each Interrupt Control Mode
Setting I n terrupt Acceptance Control
3-Level Control
Interrupt
Control Mode INTM1 INTM0 I UI ICR
Default Priori ty
Determination T
(Trace)
000
OIM —PR O—
101
OIM IM PR O—
Legend:
O: Interrupt operation con trol perform e d
IM: Used as interrupt mask bit
PR: Sets priority
—: Not used
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 138 of 1130
REJ09B0327-0400
5.5.2 Interrupt Co nt rol Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to
0, and disabled when set to 1. Control level 1 interrupt sources have higher priority.
Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt r equ est is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requ ests
are held pending . If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
3. The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
bit is set to 1, only NMI and address break interrupt are accepted, and other interrupt requests
are held pending .
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
5. The PC and CCR a re saved to the sta c k area by interrupt exception hand ling. The PC saved on
the stack shows the address of the first in struction to be executed after returning from th e
interrup t handling routine.
6. Next, the I bit in CCR is set to 1. This disables all interru pts except NMI and a dd ress break.
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 139 of 1130
REJ09B0327-0400
Program execution state
Interrupt generated?
NMI?
Control level 1
interrupt?
IRQ0?
IRQ1?
PS2IC?
IRQ0?
IRQ1?
PS2IC?
I = 0?
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Hold pending
Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Contro l Mode 0
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 140 of 1130
REJ09B0327-0400
5.5.3 Interrupt Co nt rol Mode 1
Three-level m a sking is implemented for IRQ interrupts and on-chip su pporting module inter rup ts
by means of the I and UI bits in the CPU’s CCR, and ICR.
• Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when
set to 1.
• Control level 1 interrupt requests are en abled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
For example, if the inter rup t en able bit for an interrupt request is set to 1 , and H'20, H'0 0 , and H'00
are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control
level 1 and othe r interr upts to control level 0 ) , the situ ation is as follo ws:
• When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...)
• When I = 1 and UI = 0, only NMI, IRQ2, IRQ3 and address break interrupts are enabled
• When I = 1 and UI = 1, only NMI and address break interrupts are enabled
Figure 5.9 shows the state transitions in these cases.
Only NMI interrupts and
address break enabled
All interrupts enabled
Exception handling execution
or I ← 1, UI ← 1
I ← 0
I ← 1, UI ← 0
I ← 0 UI ← 0
Exception handling execution
or UI ← 1
Only NMI, IRQ2, IRQ3,
and address break
interrupts enabled
Figure 5.9 Example of State Transitions in Interrupt Control Mode 1
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 141 of 1130
REJ09B0327-0400
Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt r equ est is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requ ests
are held pending . If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest prio r ity according to the
priority system shown in table 5.4 is selected.
3. The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If
the I bit is set to 1, only an NMI and address break interrupts are accepted, and other interrupt
requests are held pending.
An interru pt request set to interrupt control level 1 has pr iority over an interrupt request set to
interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and
the UI bit is cleared to 0.
When both the I bit and the UI bit are set to 1, only an NMI and address break interrupts are
accepted, and other interrupt requests are held pending.
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first in struction to be executed after returning from th e
interrup t handling routine.
6. Next, the I and UI bits in CCR are set to 1. This disables all interrupts exc e pt NMI and address
break.
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 142 of 1130
REJ09B0327-0400
Program execution state
Interrupt generated?
NMI?
Control level 1
interrupt?
IRQ0?
IRQ1?
PS2IC?
IRQ0?
IRQ1?
PS2IC?
UI = 0?
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Hold pending
I = 0? I = 0
Yes Yes
No
No
Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Contro l Mode 1
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 143 of 1130
REJ09B0327-0400
5.5.4 Interrupt Exception Handling Seque nce
Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip m emor y.
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 144 of 1130
REJ09B0327-0400
(14)(12)(10)(8)(6)(4)(2)
(1) (5) (7) (9) (11) (13)
Interrupt handling
routine instruction
prefetch
Internal
operation
Vector fetchStack
Instruction
prefetch Internal
operation
Interrupt
acceptance
Interrupt level determination
Wait for end of instruction
Interrupt
request signal
Internal
address bus
Internal
read signal
Internal
write signal
Internal
data bus
φ
(3)
(1)
(2) (4)
(3)
(5)
(7)
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (vector
address contents)
Interrupt handling routine start address ((13) = (10) (12))
First instruction of interrupt handling routine
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
Figure 5.11 Interrupt Exception Handling
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 145 of 1130
REJ09B0327-0400
5.5.5 Interrupt Response Times
This LSI are capable of fast word access to on-chip memory, and high-speed processing can be
achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM.
Table 5.8 shows interrupt response times—the interval between generation of an interrupt request
and execution of th e f ir st in str uction in the interrup t handling routine. The symbols used in table
5.8 are explained in table 5.9.
Table 5.8 Interrupt Respo nse Times
Number of States
No. Item Normal Mode Advanced Mode
1 Interrupt priority de termination*133
2 Number of wait states until executing
instruct ion end s*21 to 19+2·SI1 to 19+2·SI
3 PC, CCR stack save 2·SK2·SK
4 Vector fetch SI2·SI
5 Instruction fetch*32·SI2·SI
6 Internal processing*422
Total (using on-chip memory) 11 to 31 12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.9 Number of States in Interrupt Handling Routine Execution
Object of Access
External Device
8-Bit Bus 16-Bit Bus
Symbol Internal
Memory 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI1 4 6+2m 2 3+m
Branch address read SJ
Stack manipulation SK
Legend:
m: Number of wait states in an external device ac cess
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 146 of 1130
REJ09B0327-0400
5.6 Usage Notes
5.6.1 Conte ntion between Interrupt G e neration and Di sabling
When an inter r upt enable bit is cleared to 0 to disab le in ter rupts, the disabling becomes eff ective
after execution of the instruction.
In other word s, when an interrupt enable bit is cleared to 0 by an instr uction such as BCLR or
MOV, if an interrupt is generated during execution of the in struction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will b e ex ecuted on co mpletio n of the instruction. However, if there is an interrupt
request of high e r prio r ity than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower - prio r ity inter rupt will be ignored.
The same also applies when an interrup t source flag is cleared to 0.
Figure 5.12 shows an example in which the CMIEA bit in 8-bit timer register TCR is cleared to 0.
Internal
address bus
Internal
write signal
φ
CMIEA
CMFA
CMIA
interrupt signal
TCR write cycle by CPU CMIA exception handling
TCR address
Figure 5.12 Contention between Interrupt Generation and Disabling
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 147 of 1130
REJ09B0327-0400
The above contention will n ot occur if an enable bit or interrupt source flag is cleared to 0 while
the interru pt is masked.
5.6.2 Instructions That Disable Interrupts
Instructions that disable in terrupts are LDC, ANDC, ORC, and XORC. After any o f these
instruction s is ex ecuted, all interrupts ex cep t NMI are disabled and the next instru ction is always
executed. Wh en the I bit or UI bit is set by on e of these instruction s, th e new v a lue becomes valid
two states after execution of the instruction ends.
5.6.3 Interrupts during Ex ecution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an in ter rupt request (including NMI) issued d urin g the transfer
is not accepted until the mo v e is completed.
With the EEPMOV.W ins tr uction, if an interr upt r e quest is issued d u ring the transfer, interrup t
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 148 of 1130
REJ09B0327-0400
5.7 DTC Activation by Interrupt
5.7.1 Overview
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation req uest to DTC
• Both of the above
For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer
Controller (DTC).
5.7.2 Block Diagram
Figure 5.13 shows a block diagram of the DTC and interrupt controller.
Selection
circuit
DTCER
DTVECR
Control logic
Determination of
priority CPU
DTC
DTC activation
request vector
number
Clear signal
CPU interrupt
request vector
number
Select
signal
Interrupt
request
Interrupt source
clear signal
IRQ
interrupt
On-chip
supporting
module
Clear signal
Interrupt controller I, UI
SWDTE
clear signal
Figure 5.13 Interrupt Control for DTC
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 149 of 1130
REJ09B0327-0400
5.7.3 Operation
The interrupt controller has three main functions in DTC con trol.
Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt
request with the DTCE bit of DTCERA to DTCERE in the DTC.
After a DTC data transf er , the DTCE bit can be cleared to 0 and an interrupt request sen t to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC performs the specified number of data transfers and the transfer counter reaches 0,
following the DTC data transfer the DTCE b it is clear ed to 0 and an interrupt request is sent to the
CPU.
Determination o f Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table,
for the respective priorities.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrup t so urce, the DTC data transfer is per formed first, followed by CPU interrupt exceptio n
handling.
Table 5.10 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERE in the DTC an d the DISEL bit of MRB
in the DTC.
Table 5.10 Interrupt Source Selection and Clearing Control
Settings
DTC Interrupt Source Selection/Clearing Control
DTCE DISEL DTC CPU
0*×∆
10 ∆×
1∆
Legend:
∆: The relevant interr upt is use d. Interru pt sourc e clearing is perfo rm ed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
×: The relevant bit cannot be used.
*: Don’t care
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 150 of 1130
REJ09B0327-0400
Usage Note
SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the
prescribed register, and are not dependent upon th e DISEL bit.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 151 of 1130
REJ09B0327-0400
Section 6 Bus Controller
6.1 Overview
This LSI have a built-in bus co ntroller (BSC) that allows external addr ess space bus specifications,
such as bus width and number of access states, to be set.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU and data transfer controller (DTC).
6.1.1 Features
The features of the bus contro ller are listed below.
• Basic bus interface
2-state access or 3-state access can be selected
Program wait states can be inserted
• Burst ROM interface
External space can be designated as ROM interface space
1-state or 2-state burst access can be selected
• Idle cycle insertio n
An idle cycle can be inserted when an external write cycle immediately follows an external
read cycle
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 152 of 1130
REJ09B0327-0400
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
Bus controller
BCR
WSCR
Wait controller
Bus arbiter
Internal
control signals
Bus mode signal
Internal
data bus
CPU bus request signal
DTC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
External bus control signals
WAIT
Figure 6.1 Block Diagram of Bus Controller
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 153 of 1130
REJ09B0327-0400
6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the bus contro ller.
Table 6.1 Bus Controller Pins
Name Symbol I/O Function
Address strobe AS Output Strobe signal indicating that address output on
address bus is enabled (when IOSE bit is 0)
I/O select IOS Output I/O select signal (when IOSE bit is 1)
Read RD Output Strobe signal ind ic atin g that extern al spa ce is
being read
High write HWR Output Strobe signal ind ic atin g that external spa ce is
being written to, and that the upper data bus
(D15 to D8) is enabled
Low write LWR Output Strobe signal indicatin g that external space is
being written to, and that the lower data bus
(D7 to D0) is enabled
Wait WAIT Input Wait request signal when external 3-state
access space is accessed
6.1.4 Register Configuration
Table 6.2 summarizes the registers of the bus controller.
Table 6.2 Bus Controller Registers
Name Abbreviation R/W Initial Value Address*
Bus control register BCR R/W H'D7 H'FFC6
Wait state control regi ster WSCR R/W H'33 H'FFC7
Note: *Lower 16 bits of the address.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 154 of 1130
REJ09B0327-0400
6.2 Register Descriptions
6.2.1 Bus Control Register (BCR)
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
IOS0
1
R/W
2
—
1
R/W
1
IOS1
1
R/W
Bit
Initial value
Read/Write
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the extent of the I/O area when the I/O strobe function has been selected for the AS pin.
BCR is initia lized to H'D7 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Reserved. Do not write 0 to this bit.
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not a one-state idle cycle is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 6
ICIS0 Description
0 Idle cycle not inserted in case of successive external read and external write cycles
1 Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether external space is designated as a burst
ROM interface space. The selection applies to the en tire external space.
Bit 5
BRSTRM Description
0 Basic bus interface (Initial value)
1 Burst ROM interface
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 155 of 1130
REJ09B0327-0400
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1 Description
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 stat es (Initi al val ue)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access (Initial value)
1 Max. 8 words in burst access
Bit 2—Reserved: Do not write 0 to this b it.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4.
6.2.2 Wait State Control Register (WSCR)
7
RAMS
0
R/W
6
RAM0
0
R/W
5
ABW
1
R/W
4
AST
1
R/W
3
WMS1
0
R/W
0
WC0
1
R/W
2
WMS0
0
R/W
1
WC1
1
R/W
Bit
Initial value
Read/Write
WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access
states, wait mode, and number of wait states for external memory space. The on-chip memory and
internal I/O register bus width and number of access states are fixed, irrespective of the WSCR
settings.
WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 156 of 1130
REJ09B0327-0400
Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved b its. Alway s write
0 when writin g to these bits in the A-mask version.
Bit 5—Bu s Width Control ( A BW): Specifies whether the external memory space is 8-bit access
space or 16-bit access space.
Bit 5
ABW Description
0 External memory space is designated as 16-bit access space
1 External memory space is designated as 8-bit access space (Initial value)
Bit 4—Access State Control (AST): Specifies whether the external memory space is 2-state
access space or 3-state access space, and simultaneously enables or disables wait state insertion.
Bit 4
AST Description
0 External memory space is design ated as 2-state ac ces s spa ce
Wait state insertion in external memory space accesses is disabled
1 External memory space is design ated as 3-state ac ces s spa ce (Initial value)
Wait state insertion in external memory space accesses is enabled
Bits 3 and 2—Wa it Mode Select 1 and 0 (WMS1, WM S0): These bits select the wait mode
when external memory space is accessed while the AST bit is set to 1.
Bit 3 Bit 2
WMS1 WMS0 Description
0 0 Program wait mode (Initial value)
1 Wait-disabled mode
1 0 Pin wait mode
1 Pin auto-wait mode
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 157 of 1130
REJ09B0327-0400
Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0): These bits select the number of program wait
states when external memory space is accessed while the AST bit is set to 1.
Bit 1 Bit 0
WC1 WC0 Description
0 0 No program wait states are inserted
1 1 program wait state is inserted in external memory space accesses
1 0 2 program wait states are inserted in external memory space accesses
1 3 program wait states are inserted in external memory space accesses
(Initial value)
6.3 Overview of Bus Control
6.3.1 Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and wait mode and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with the ABW bit.
Number of Access States: Two or three access states can be selected with the AST bit.
When 2-state access space is designated, wait insertion is disabled. The number of access states on
the burst ROM interface is determined without regard to the AST bit setting.
Wait Mode and Number of Program Wait States: When 3-state access space is designated by
the AST bit, the wait mo de and the number of program wait states to be inserted automa tically is
selected with WMS1, WMS0, WC1, and WC0. From 0 to 3 program wait states can be selected.
Table 6.3 shows the bus specifications for each basic bus interface area.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 158 of 1130
REJ09B0327-0400
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
Bus Specifications (Basic Bus Interface)
ABW AST WMS1 WMS0 WC1 WC0 Bus Width Access
States Program
Wait States
00———— 16 2 0
101—— 16 3 0
—*—*00 3 0
11
10 2
13
10———— 820
101—— 830
—*—*00 3 0
11
10 2
13
Note: *Except when WMS1 = 0 and WMS0 = 1
6.3.2 Advanced Mode
The initial state of the external space is basic bus interface, three-state access space. In ROM-
enabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O
registers is external space. The on-chip RAM is enabled when the RAME bit in the system control
register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and
the corresponding space becomes external space.
6.3.3 Normal Mode
The initial state of the external memory space is basic bus interface, three-state access space. In
ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is
external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, on-chip
RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME
bit in the system control register ( SYSCR) is set to 1; wh en the RAME bit is cleared to 0, th e on-
chip RAM is disabled and the corresponding space becomes external space.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 159 of 1130
REJ09B0327-0400
6.3.4 I/O Select Signal
In this LSI, an I/O select sign a l (IOS) can be output, with the signal output going low when the
designated external space is accessed.
Figure 6.2 shows an example of IOS signal output timing.
φ
Address bus
IOS
T
1
T
2
T
3
Bus cycle
External address in IOS set range
Figure 6.2 IOS
IOSIOS
IOS Signal O ut put Timing
Enabling or disabling of IOS signal output is controlled by the setting of the IOSE bit in SYSCR.
In expanded mode, this pin operates as the AS output pin after a reset, and therefore the IOSE bit
in SYSCR mu st be set to 1 in o rder to use this pin as the IOS signal output. See section 8, I/O
Ports, for details.
The range of addresses for which the IOS signal is ou tput can be set with bits IOS1 an d IOS0 in
BCR. T he IOS signal address ranges are shown in table 6.4.
Table 6. 4 IOS
IOSIOS
IOS Signal Output Range Settings
IOS1 IOS0 IOS
IOSIOS
IOS Signal Output Range
0 0 H'(FF)F000 to H'(FF)F03F
1 H'(FF)F000 to H'(FF)F0FF
1 0 H'(FF)F000 to H'(FF)F3FF
1 H'(FF)F000 to H'(FF)FE4F*(Initial value)
Note: *In the H8S/2148 and H8S/2147 F-ZTAT A-mask version, the address range is from
H'(FF)F000 to H'(FF)F7FF.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 160 of 1130
REJ09B0327-0400
6.4 Basic Bus Interface
6.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with the ABW bit, the AST bit, and the WMS1, WMS0,
WC1, and WC0 bits (see table 6.3).
6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8 - bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word access is performed as two byte accesses, and a longword
access, as four byte accesses.
D15 D8 D7 D0
Upper data bus
Lower data bus
Byte size
Word size 1st bus cycle
2nd bus cycle
Longword size 1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 161 of 1130
REJ09B0327-0400
16-Bit Access Space
Figure 6.4 illustrates d a ta alig nment control for the 16-bit access space. With the 16-bit access
space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The
amount of data that can be accessed at one time is one byte or one word, and a longword access is
executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D15 D8 D7 D0
Upper data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Lower data bus
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 162 of 1130
REJ09B0327-0400
6.4.3 Valid Strobes
Table 6.5 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.5 Data Buses Used and Valid St robes
Area Access
Size Read/
Write Address Valid
Strobe Upper Data Bus
(D15 to D8) Lower Data Bus
(D7 to D0)
Byte Read —RD Valid Port, etc.
8-bit access
space Write —HWR Port, etc.
Byte Read Even RD Valid Invalid16-bit access
space Odd Invalid Valid
Write Even HWR Valid Undefined
Odd LWR Undefined Valid
Word Read —RD Valid Valid
Write —HWR, LWR Valid Valid
Legend:
Undefined: Undefi ned data is out put.
Invalid: Input state; input value is ign ored.
Port, etc.: Pins are used as port or on-chip supporting module input/output pins, and not as data
bus pins.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 163 of 1130
REJ09B0327-0400
6.4.4 Basic Timing
8-Bit 2-State Access Space
Figure 6.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
Bus cycle
T1T2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
D15 to D8 Valid
Write
Figure 6.5 Bus Timing for 8-Bit 2-State Access Space
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 164 of 1130
REJ09B0327-0400
8-Bit 3-State Access Space
Figure 6.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used.
Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
D15 to D8 Valid
Write
T
3
Figure 6.6 Bus Timing for 8-Bit 3-State Access Space
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 165 of 1130
REJ09B0327-0400
16-Bit, 2-State Access Space
Figures 6.7 to 6.9 show the bus timing for 16-bit, 2-state access space. When 16-bit access space is
accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to
D0) f or odd a ddresses.
Wait states cannot be inserted.
Bus cycle
T1T2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 Undefined
Write
High
Figure 6.7 16-Bit, 2-State Access Space Bus Timing (1)
(Even Address Byte Access)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 166 of 1130
REJ09B0327-0400
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Invalid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 Undefined
D7 to D0 Valid
Write
HIgh
Figure 6.8 16-Bit, 2-State Access Space Bus Timing (2)
(Odd Address Byte Access)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 167 of 1130
REJ09B0327-0400
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Valid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 Valid
Write
Figure 6.9 16-Bit, 2-State Access Space Bus Timing (3)
(Word Access)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 168 of 1130
REJ09B0327-0400
16-Bit, 3-State Access Space
Figures 6.10 to 6.12 show the bus timing for 16-bit, 3-state access space. When 16-bit access
space is accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data
bus (D7 to D0) for odd addresses.
Wait states can be inserted.
Bus cycle
T1T2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 Undefined
Write
High
T3
Figure 6.10 16-Bit, 3-State Access Space Bus Timing (1)
(Even Address Byte Access)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 169 of 1130
REJ09B0327-0400
Bus cycle
T1T2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Invalid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 Undefined
D7 to D0 Valid
Write
High
T3
Figure 6.11 16-Bit, 3-State Access Space Bus Timing (2)
(Odd Address Byte Access)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 170 of 1130
REJ09B0327-0400
Bus cycle
T1T2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 Valid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 Valid
Write
T3
Figure 6.12 16-Bit, 3-State Access Space Bus Timing (3)
(Word Access)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 171 of 1130
REJ09B0327-0400
6.4.5 Wait Control
When accessing external space, the MCU can extend the bus cycle by inserting one or more wait
states (TW). There are three ways of inserting wait states: program wait insertion, pin wait insertion
using the WAIT pin, and a combination of the two.
Program Wait Mode: In program wait mode, the number of TW states specified by bits WC1 and
WC0 are always inserted between the T2 and T3 states when external space is accessed.
Pin Wait Mode: In pin wait mode, the number of TW states specified by bits WC1 and WC0 are
always inserted between the T2 and T3 states when external space is accessed. If the WAIT pin is
low at the fall of φ in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held
low, TW states are inserted until it goes high .
Pin wait mode is useful for inserting four or more wait states, or for changing the number of TW
states for different external devices.
Pin Auto-Wait Mode: In pin auto-wait mode, if the WAIT pin is low at the fall of φ in the T2
state, the number of TW states specified by bits WC1 and WC0 are inserted when external space is
accessed. No additional TW states are inserted even if the WAIT pin remains low. Pin auto-wait
mode can be used for an easy interface to low-speed memory, simply by routing the chip select
signal to th e WAIT pin.
Figure 6.13 shows an example of wait state insertion timing.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 172 of 1130
REJ09B0327-0400
By program wait
T
1
Address bus
φ
AS/IOS (IOSE = 0)
RD
Data bus Read data
Read
HWR, LWR
Write data
Write
Note: indicates the timing of WAIT pin sampling using the φ clock.
WAIT
Data bus
T
2
T
w
T
w
T
w
T
3
By WAIT pin
Figure 6.13 Example of Wait State Insertion Timing
The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input
disabled.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 173 of 1130
REJ09B0327-0400
6.5 Burst ROM Interface
6.5.1 Overview
With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM
interfacing can be performed.
External space can be designated as burst ROM space by means of the BRSTRM bit in BCR.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
6.5.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordan ce
with the setting of the AST bit. Also, when the AST bit is set to 1, wait state in sertion is possible.
One or two states can be selected fo r the burst cycle, according to the setting of the BRSTS1 bit in
BCR. Wait states cannot be inserted.
When the BRSTS0 bit in BCR is cleared to 0, burst access of up to 4 wo rds is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6.14 (a) and (b). The timing
shown in figure 6.14 (a) is for the case where the AST and BRSTS1 bits are both set to 1, and that
in figure 6.14 (b) is for the case where both these bits are cleared to 0.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 174 of 1130
REJ09B0327-0400
T1
Address bus
φ
A
S/IOS (IOSE = 0)
Data bus
T2T3T1T2T1
Full access
T2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.14 (a) Example of Burst ROM Access Timing (when AST = BRSTS1 = 1)
T1
Address bus
φ
A
S/IOS (IOSE = 0)
Data bus
T2T1T1
Full access
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.14 (b) Example of Burst ROM Access Timing (when AST = BRSTS1 = 0)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 175 of 1130
REJ09B0327-0400
6.5.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4 . 5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
6.6 Idle Cycle
6.6.1 Operation
When this LSI chip accesses external space, it can insert a 1-state idle cycle (TI) between bus
cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, with a long output floating time, an d
high-speed memory, I/O interfaces, and so on.
If an e xternal write occurs after a n external r e ad w hile the ICIS0 bit in BCR is set to 1, an id le
cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal
mode.
Figure 6.15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In ( b), an idle cycle is inserted, and a data collisio n is prevented.
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 176 of 1130
REJ09B0327-0400
T1
Address bus
φ
RD
Bus cycle A
Data bus
T2T3T1T2
Bus cycle B
Long output
floating time
Data collision
(a) Idle cycle not inserted
T1
φ
RD
T2T3TIT1
(b) Idle cycle inserted
T2
HWR, LWR
HWR, LWR
Address bus
Data bus
Bus cycle A Bus cycle B
Figure 6.15 Example of Idle Cycle Operation
6.6.2 Pin States in Idle Cycle
Table 6.6 shows pin states in an idle cycle.
Table 6.6 Pin States in Idle Cy cle
Pins Pin State
A23 to A0, IOS Contents of next bus cycle
D15 to D0 High impedance
AS High
RD High
HWR, LWR High
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 177 of 1130
REJ09B0327-0400
6.7 Bus Arbitration
6.7.1 Overview
This LSI have a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and the DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter d e termin es priorities at the prescrib ed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes po ssession of the bus and
begins its operation.
6.7.2 Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledg e signal to the bus master making the request. If there are bus requests from
both bus masters, the bus requ est acknowledge signal is sent to the one with the higher priority.
When a bus master receives the bus request acknowledge signal, it takes possession of the bus
until that signal is canceled.
The order of pr iority of the bus masters is as follows:
(High) DTC > CPU (Low)
Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 178 of 1130
REJ09B0327-0400
6.7.3 Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU
The CPU is the lowest-priority bus master, and if a bu s request is received from the DTC, the bus
arbiter transf ers the bus to the DTC. The timing for transfer of the bus is as follo ws:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the opera tions.
See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not
transferred.
• If the CPU is in sleep mode, it transfers the bus immediately.
DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC does n ot release the bus until it has completed a series of processing operatio ns.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 179 of 1130
REJ09B0327-0400
Section 7 Data Transfer Controller (DTC)
Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N.
7.1 Overview
The H8S/2148 Group includes a data transfer controller (DTC). The DTC can be activated by an
interrupt or so ftware, to transfer data.
7.1.1 Features
• Transfer possible over any number of channels
Transfer information is stored in me mor y
One activation source can trigger a number of data transfers (chain transfer)
• Wide range of tr ansfer modes
Normal, repeat, and block tran sfer modes available
Incrementing, decrementing, and fixing of transfer source and destination addresses can be
selected
• Direct specification of 16-Mbyte address space possible
24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
An interrupt request can be issued to the CPU after one data transfer ends
An interrupt request can be issued to the CPU after all specified data transfers have ended
• Activation by software is possible
• Module stop mode can be set
The initial setting enables DTC registers to be accessed. DTC operation is halted by setting
module stop mode
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 180 of 1130
REJ09B0327-0400
7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on- chip RAM*. A 32-b it bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state read ing and writing of the DTC register
information.
Note: * Wh e n the DTC is used, the RAME b it in SYSCR must be set to 1.
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA
CRB
DAR
SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB: DTC mode registers A and B
CRA, CRB: DTC transfer count registers A and B
SAR: DTC source address register
DAR: DTC destination address register
DTCERA to DTCERE: DTC enable registers A to E
DTVECR: DTC vector register
DTCERA
to
DTCERE
DTVECR
Figure 7.1 Block Diagram of DTC
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 181 of 1130
REJ09B0327-0400
7.1.3 Register Configuration
Table 7.1 summarizes the DTC registers.
Table 7.1 DTC Registers
Name Abbreviation R/W Initial Value Address*1
DTC mode register A MRA —*2Undefined —*3
DTC mode register B MRB —*2Undefined —*3
DTC source address register SAR —*2Undefined —*3
DTC destination address register DAR —*2Undefined —*3
DTC transfer count register A CRA —*2Undefined —*3
DTC transfer count register B CRB —*2Undefined —*3
DTC enable registers DTCER*4R/W H'00 H'FEEE to H'FEF2
DTC vector register DTVECR*4R/W H'00 H'FEF3
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information.
They cannot be located in ext ernal memory space.
When the DTC is used, do not clear the RAME bit in SYSCR to 0.
4. The H8S/2144 Group and H8S/2147N do not include an on-chip DTC, and therefore the
DTCER and DTVECR register addresses should not be accessed by the CPU.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 182 of 1130
REJ09B0327-0400
7.2 Register Descriptions
7.2.1 DTC Mode Register A (MRA)
7
SM1 6
SM0 5
DM1 4
DM0 3
MD1 0
Sz
2
MD0 1
DTS
Bit
Initial value
—
Unde-
fined
Read/Write —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7 Bit 6
SM1 SM0 Description
0 — SAR is fixed
1 0 SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1 SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a da ta tr ansfer.
Bit 5 Bit 4
DM1 DM0 Description
0 — DAR is fixed
1 0 DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1 DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 183 of 1130
REJ09B0327-0400
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3 Bit 2
MD1 MD0 Description
0 0 Normal mode
1 Repeat mode
1 0 Block transfer mode
1 —
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1
DTS Description
0 Destination side is repeat area or block area
1 Source side is repeat area or block area
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0
Sz Description
0 Byte-size transfer
1 Word-size transfer
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 184 of 1130
REJ09B0327-0400
7.2.2 DTC Mode Register B (MRB)
7
CHNE 6
DISEL 5
—4
—3
—0
—
2
—1
—
Bit
Initial value
Read/Write —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined
MRB is an 8-bit register that contr ols the DTC oper ating m ode.
Bit 7—DTC C hain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer,
multiple data transfers can be perfo r med consecutively in respon se to a single transfer request.
With data transf er for which CHNE is set to 1, there is no determination of the end of the specified
number of transfers, clearing of the interrupt source flag, or clearing of DTCER.
Bit 7
CHNE Description
0 End of DTC data transfer (activation waiting state is entered)
1 DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL Description
0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: In the H8S/2148 Group these bits have no effect on DTC operation, and
should always be written with 0.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 185 of 1130
REJ09B0327-0400
7.2.3 DTC Source Address Register (SAR)
23 22 21 20 19 43210
Bit
Initial value
—
Unde-
fined
Read/write —
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4 DTC Destination Address Register (DAR)
23 22 21 20 19 43210
Bit
Initial value
—
Unde-
fined
Read/write —
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 186 of 1130
REJ09B0327-0400
7.2.5 DTC Transfer Count Register A (CRA)
15 14 13 12 11109876543210
CRAH CRAL
Bit
Initial value
—
Unde-
fined
Read/Write —
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)
and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an
8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are transferred when the count reaches H'00. This operation is repeated.
7.2.6 DTC Transfer Count Register B (CRB)
15 14 13 12 11109876543210
Bit
Initial value
————————————————
Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined
Read/Write
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 187 of 1130
REJ09B0327-0400
7.2.7 DTC Enable Registers (DTCER)
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
Bit
Initial value
Read/Write
The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable reg ister s ar e initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn Description
0 DTC activat ion by interr upt is dis abl ed (Initial value)
[Clearing cond iti ons ]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
1 DTC activat ion by interr upt is ena bled
[Holding cond iti on]
When the DISEL bit is 0 and the specified number of transfers have not ended
Note: n = 7 to 0
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number
generated by the interrupt controller in each case.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial sett ing only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 188 of 1130
REJ09B0327-0400
7.2.8 DTC Vector Register (DTVECR)
7
SWDTE
0
R/(W)*
6
DTVEC6
0
R/W
5
DTVEC5
0
R/W
4
DTVEC4
0
R/W
3
DTVEC3
0
R/W
0
DTVEC0
0
R/W
2
DTVEC2
0
R/W
1
DTVEC1
0
R/W
A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1
is read.
Bit
Initial value
Read/Write
Note: *
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Specifies enabling or disabling of DTC
software activation . To clear the SWDTE bit by software , read SWDTE wh en set to 1, then write 0
in the bit.
Bit 7
SWDTE Description
0 DTC software activation is di sabled (Initial value)
[Clearing cond iti on]
When the DISEL bit is 0 and the specified number of transfers have not ended
1 DTC software activation is enabled
[Holding cond iti ons ]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
• During software-activated data transfer
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number fo r DTC software activation.
The vector address is H'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). For
example, if DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 189 of 1130
REJ09B0327-0400
7.2.9 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle
and a transitio n is made to module stop mode . Note that 1 canno t be written to the MSTP14 bit
when the DTC is being activated. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 6—Module Stop (M STP14): Specifies the DTC module stop mode.
MSTPCRH
Bit 6
MSTP14 Description
0 DTC module stop mode is cleared (Initial value
)
1 DTC module stop mode is set
7.3 Operation
7.3.1 Overview
When activated, the DTC reads register information that is already stored in memory and transfers
data on the basis of that register information. After the data transfer, it writes updated register
inform ation back to memory. Pre-storage of register information in memory makes it possible to
transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to
perform a number of transfers with a single activation.
Figure 7.2 shows a flowchart of DTC operation.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 190 of 1130
REJ09B0327-0400
Start
Read DTC vector Next transfer
Read register information
Data transfer
Write register information
Clear activation flag
CHNE = 1?
End
No
No
Yes
Yes
Transfer counter = 0
or DISEL = 1?
Clear DTCER
Interrupt exception
handling
Figure 7.2 Flowchart of DTC Operation
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 7.2 outlines the functions of the DTC.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 191 of 1130
REJ09B0327-0400
Table 7.2 DTC Functions
Address Registers
Transfer Mode Activation Source Transfer
Source Transfer
Destination
• Normal mode
One transfer request transfers one
byte or one word
Memory addres ses are incremented
or decremented by 1 or 2
Up to 65,536 transfers possible
• Repeat mode
One transfer request transfers one
byte or one word
Memory addres ses are incremented
or decremented by 1 or 2
After the specified number of transfers
(1 to 256), the initial state resumes and
operation co ntin ues
• Block transfer mode
One transfer request transfers a block
of the specified size
Block size is from 1 to 256 bytes or
words
Up to 65,536 transfers possible
A block area can be designated at either
the source or destination
• IRQ
• FRT ICI, OCI
• 8-bit timer CMI
• Host interface IBF
• SCI TXI or RXI
• A/D converter ADI
• IIC IICI
• Software
24 bits 24 bits
7.3.2 Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software (software
activation). An interrupt request can be directed to the CPU or DTC, as designated by the
corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding
bit is set to 1, an d to the CPU when the bit is cleared to 0.
At the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer)
the interrupt source or the corresponding DTCER bit is cleared. Table 7.3 shows activation
sources and DTCER clearing.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 192 of 1130
REJ09B0327-0400
The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0.
Table 7.3 Activation Sources and DTCER Clearing
Activation
Source
When DISEL Bit Is 0 and
Specified Number of Transfers
Have Not Ended
When DISEL Bit Is 1 or
Specified Number of Transfers
Have Ended
Software
activation SWDTE bit cleared to 0 • SWDTE bit held at 1
• Interrupt request sent to CPU
Interrupt
activation • Corresponding DTCER bit held
at 1
• Activati on sour ce flag cle ared
to 0
• Corresponding DTCER bit cleared to 0
• Activati on sour ce flag hel d at 1
• Activation source interrupt request
sent to CPU
Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
On-chip
supporting
module
IRQ interrupt
DTVECR
Selection circuit
Interrupt controller CPU
DTC
DTCER
Clear
control
Select
Interrupt
request
Source flag cleared
Clear
Clear request
Interrupt mask
Figure 7.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC is activated in acco rdance with the default priorities.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 193 of 1130
REJ09B0327-0400
7.3.3 DTC Vector Table
Figure 7.4 shows the correspondence between DTC vector addresses and register information.
Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER
bits. When the DTC is activated by software, the vector address is obtained from: H'0400 +
DTVECR[6:0] << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the
vector address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register in f orm ation should be an integral multiple of four.
The configuration of the vector address is the same in both normal and advanced modes, a 2-byte
unit being used in both cases. These two bytes sp ecify the lower bits of the address in the on-chip
RAM.
Register information
start address Register information
Chain transfer
DTC vector
address
Figure 7.4 Correspondence between DTC Vector Address and Register Information
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 194 of 1130
REJ09B0327-0400
Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Interrupt Source Origin of
Interrupt Source Vector
Number Vector
Address DTCE*Priority
Write to DTVECR Software DTVECR
(Decimal
indication)
H'0400 +
DTVECR
[6:0] << 1
—High
IRQ0 External pin 1 6 H'0420 DTCEA7
IRQ1 17 H'0422 DTCEA6
IRQ2 18 H'0424 DTCEA5
IRQ3 19 H'0426 DTCEA4
ADI (A/D conversion end) A/D 28 H'0438 DTCEA3
ICIA (FRT input capture A) FRT 48 H'0460 DTCEA2
ICIB (FRT input capture B) 49 H'0462 DTCEA1
OCIA (FRT output co mpare A) 52 H'0468 DTCEA0
OCIB (FRT output co mpare B) 54 H'046A DTCEB7
CMIA0 (TMR0 compare-match A) TMR0 64 H'0480 DTCEB2
CMIB0 (TMR0 compare-match B) 65 H'0482 DTCEB1
CMIA1 (TMR1 compare-match A) TMR1 68 H'0488 DTCEB0
CMIB1 (TMR1 compare-match B) 69 H'048A DTCEC7
CMIAY (TMRY compare-match A) TMRY 72 H'0490 DTCEC6
CMIBY (TMRY compare-match B) 73 H'0492 DTCEC5
IBF1 (IDR1 reception comp leted) HIF 76 H'0498 DTCEC4
IBF2 (IDR2 reception comp leted) 77 H'049A DTCEC3
RXI0 (reception completed 0) SCI channel 0 81 H'04A2 DTCEC2
TXI0 (transmit data empty 0) 82 H'04A4 DTCEC1
RXI1 (reception completed 1) SCI channel 1 85 H'04AA DTCEC0
TXI1 (transmit data empty 1) 86 H'04AC DTCED7
RXI2 (reception completed 2) SCI channel 2 89 H'04B2 DTCED6
TXI2 (transmit data empty 2) 90 H'04B4 DTCED5
IICI0 (IIC0 1-byte transmission/
reception completed) IIC0 (option) 92 H'04B8 DTCED4
IICI1 (IIC1 1-byte transmission/
reception completed) IIC1 (option) 94 H'04BC DTCED3 Low
Note: *DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 195 of 1130
REJ09B0327-0400
7.3.4 Location of Register Information in Address Space
Figure 7.5 shows how the register information should be located in the address space.
Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address
of the register information (vector address contents). In chain tr ansfer, locate the register
information in consecutive areas.
Locate the register information in the on-chip RAM ( a ddresses: H'FFEC00 to H'FFEFFF).
Register information
start address
Chain transfer
Register information
for 2nd transfer
in chain transfer
MRA SAR
MRB DAR
CRA CRB
4 bytes
Lower address
CRA CRB
Register information
MRA
0123
SAR
MRB DAR
Figure 7.5 Location of DTC Register Information in Address Space
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 196 of 1130
REJ09B0327-0400
7.3.5 Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in
normal mode.
Table 7.5 Register Information in Normal Mode
Name Abbreviation Function
DTC source address register SAR Transfer source address
DTC destination address register DAR Transfer destination address
DTC transfer count register A CRA Transfer count
DTC transfer count register B CRB Not used
Transfer
SAR DAR
Figure 7.6 Memory Mapping in Normal Mode
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 197 of 1130
REJ09B0327-0400
7.3.6 Repeat Mode
In repeat mode, one operation transfers on e byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial address r egister state specified b y the transfer counter and r epeat area resumes and transf er
is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts
cannot be requested when DISEL = 0.
Table 7.6 lists the register information in repeat mode and figu re 7.7 shows memory mapping in
repeat mode.
Table 7.6 Register Information in Repeat Mode
Name Abbreviation Function
DTC source address register SAR Transfer source address
DTC destination address register DAR Transfer destination address
DTC transfer count register AH CRAH Holds number of transfers
DTC transfer count register AL CRAL Transfer count
DTC transfer count register B CRB Not used
Transfer
Repeat area
SAR or
DAR DAR or
SAR
Figure 7.7 Memory Mapping in Repeat Mode
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 198 of 1130
REJ09B0327-0400
7.3.7 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is specified as a block area.
The block size is 1 to 2 56. When the transfer of on e block ends, the initial state of the block size
counter and the address register specified in the block area is restored. The other address register is
successively incremented or decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrup t is requested.
Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory
mapping in block transfer mode.
Table 7.7 Register Information in Block Transfer Mode
Name Abbreviation Function
DTC source address register SAR Transfer source address
DTC destination address register DAR Transfer destination address
DTC transfer count regi ster AH CRAH Holds block size
DTC transfer count register AL CRAL Block size count
DTC transfer count register B CRB Transfer counter
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 199 of 1130
REJ09B0327-0400
Transfer
SAR or
DAR DAR or
SAR
Block area
First block
Nth block
·
·
·
Figure 7.8 Memory Mapping in Block Transfer Mode
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 200 of 1130
REJ09B0327-0400
7.3.8 Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.9 shows memory mapping for chain transfer.
Source
Source
Destination
Destination
DTC vector
address Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Figure 7.9 Memory Mapping in Chain Transfer
In the case of transf er with CHNE set to 1, an interrupt request to the CPU is not gen e r a ted at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 201 of 1130
REJ09B0327-0400
7.3.9 Operation Timing
Figures 7.10 to 7.12 show examples of DTC operation timing.
DTC activation
request
DTC
request
Address
Vector read
Transfer
information read Transfer
information write
Data transfer
Read Write
φ
Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode)
Read Write Read Write
Data transfer
Transfer
information write
Transfer
information read
Vector read
φ
DTC activation
request
DTC request
Address
Figure 7.11 DTC Operation Timing (Block Transfer Mode, with Block Size of 2)
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 202 of 1130
REJ09B0327-0400
Read Write Read Write
Address
φ
DTC activation
request
DTC
request Data transfer Data transfer
Transfer
information
write
Transfer
information
write
Transfer
information
read
Transfer
information
read
Vector read
Figure 7.12 DTC Operation Timing (Chain Transfer)
7.3.10 Number of DTC Execution States
Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of
states required for each execution phase.
Table 7.8 DTC Execution Phases
Mode Vector Read
I
Register Information
Read/Write
JData Read
KData Write
L
Internal
Operation
M
Normal1 6 113
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
Legend:
N: Block size (initial setting of CRAH and CRAL)
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 203 of 1130
REJ09B0327-0400
Table 7.9 Number of States Required for Each Execution Phase
Object of Access
On-
Chip
RAM
On-
Chip
ROM Internal I/O
Registers External Devices
Bus width 32 16 8 16 8 8 16 16
Access stat es 1 1 2 2 2 3 2 3
Vector read SI— 1 ——46+2m23+mExecution
phase Register
information
read/write
SJ1————— ——
Byte data read SK112223+m23+m
Word data read SK114246+2m23+m
Byte data write SL112223+m23+m
Word data write SL114246+2m23+m
Internal operation SM111111 11
The number of execution states is calculated from the formula below. No te that Σ means the sum
of all transfer s activated by one activation even t ( th e number for which the CHNE bit is set to one,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is tran sferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 204 of 1130
REJ09B0327-0400
7.3.11 Procedures for Using the DTC
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enab le b its for the interrupt sources to be used as the activation sour ces to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is r equested. If the DTC is to contin u e
transferrin g data, set the DTCE bit to 1.
Activatio n by Software
The procedu r e for using the DTC with softwar e activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Check th at the SWDTE bit is 0.
4. Write 1 in the SWDTE bit and the vector number to DTVECR.
5. Check th e vector number written to DTVECR.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not re quested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE b it
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interru pt is requested.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 205 of 1130
REJ09B0327-0400
7.3.12 Examples of Use of the DTC
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start addr ess of the RAM area where the d a ta will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. Th e RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0 , and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 206 of 1130
REJ09B0327-0400
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to th e SWDTE bit and the vector number (H'60 ) to DTVECR. Th e wr ite data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the tr ansfer, an SWDTEND interrup t o c curs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 207 of 1130
REJ09B0327-0400
7.4 Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL b it was set to 1. In the case of interrupt activation,
the interru pt set as the activation sour ce is generated. These interrupts to the CPU are subject to
CPU mask level an d interrupt controller priority lev e l contr ol.
In the case of activation by software, a software-activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers
have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or dur in g data transfer even if the SWDTE bit is set to 1.
7.5 Usage Notes
Module Stop
When the MSTP14 bit in MSTPCR is se t to 1, the DTC clock stops, and the DTC enters th e
module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating.
When the DTC is placed in the module stop state, the DTCER registers must all be in the cleared
state when the MSTP14 bit is set to 1.
On-Chip RA M
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
DTCE Bit Setting
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial sett ing only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 208 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 209 of 1130
REJ09B0327-0400
Section 8 I/O Ports
8.1 Overview
This LSI have ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7).
Tables 8.1 to 8.3 summarize the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for th e
input-only port) and data registers (DR, ODR) that store output data.
Ports 1 to 3, 6, A, and B have a built-in MOS input pull-up function. For ports A an d B, the on/off
status of the MOS input pull-up is controlled by DDR and ODR. Ports 1 to 3 and 6 have a MOS
input pull-up control register (PCR), in addition to DDR and DR, to contro l the on/off status of the
MOS input pull-ups.
Ports 1 to 6, 8, 9, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O
ports can drive a Darlington transistor when in output mode. Ports 1, 2, and 3 can drive an LED
(10 mA sink current).
PA4 to PA7 in port A have bus buffer drive capability. In the H8S/2148 Group and H8S/2147N,
P52 in port 5 and P97 in port 9 are NMOS push-pull outputs.
Note that the H8S/2144 Group and H8S/2147N have subset specifications that do not include
some supporting modules. For differences in pin functions, see table 8.1, H8S/2148 Group Port
Functions, table 8.2, H8S/2147N Port Functions, and table 8.3, H8S/2144 Group Port Functions.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 210 of 1130
REJ09B0327-0400
Table 8.1 H8S/2148 Group Port Functions
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 1 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P17 to P10/
A7 to A0/
PW7 to PW0
Lower address
output
(A7 to A0)
When DDR = 0
(after res et): input
port
When DDR = 1:
lower address
output (A7 to A0) or
PWM timer output
(PW7 to PW0)
I/O port also functioni ng as
PWM timer output (PW7 to
PW0)
Port 2 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P27/A15/PW15/
CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
Upper address
output
(A15 to A8)
When DDR = 0
(after res et): input
port or timer
connection output
(CBLANK)
When DDR = 1:
upper address
output (A15 to A8),
PWM timer output
(PW15 to PW8),
timer connection
output (CBLANK),
or output ports (P27
to P24)
I/O port also functioni ng as
PWM timer output (PW15
to PW8) and timer
connection output
(CBLANK)
Port 3 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P37 to P30/
HDB7 to HDB0/
D15 to D8
Data bus input/output (D15 t o D8) I/O port also functioning as
host interface data bus
input/out put (HDB 7 to
HDB0)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 211 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 4 • 8-bit I/O port P47/PWX1
P46/PWX0
P45/TMRI1/
HIRQ12/CSYNCI
P44/TMO1/
HIRQ1/HSYNCO
P43/TMCI1/
HIRQ11/HSYNCI
P42/TMRI0/
SCK2/SDA1
P41/TMO0/
RxD2/IrRxD
P40/TMCI0/
TxD2/IrTxD
I/O port also functioni ng as 14-bit
PWM timer output (PWX1, PWX0),
8-bit timer 0 and 1 input/output
(TMCI0, TMRI0, TMO0, TMCI1,
TMRI1, TMO1), timer connection
input/out put (HSYNCO, CS Y NCI,
HSYNCI), S CI2 input/ output (TxD2,
RxD2, SCK2), IrDA interface
input/out put (I rTxD, I rRxD), and I2C
bus interfac e 1 (option) input/out put
(SDA1)
I/O port also functioni ng as
14-bit PWM timer output
(PWX1, PWX0), 8-bit timer
0 and 1 input/output
(TMCI0, TMRI 0, TMO0,
TMCI1, TMRI 1, TMO1),
timer connection
input/out put (HSYNCO,
CSYNCI, HSYNCI), host
interface host CPU
interrupt request output
(HIRQ12, HIRQ1,
HIRQ11), SCI2 input/
output (TxD2, RxD2,
SCK2), IrDA interface
input/out put (I rTx D, IrRxD),
and I2C bus interf ace 1
(option) input/output
(SDA1)
Port 5 • 3-bit I/ O port P52/SCK0/SCL0
P51/RxD0
P50/TxD0
I/O port also functioni ng as SCI0 input/output (TxD0, RxD0,
SCK0) and I2C bus interf ace 0 (option) i nput/ output (SCL0)
Port 6 • 8-bit I/O port P67/IRQ7/TMOX/
KIN7/CIN7
P66/IRQ6/FTOB/
KIN6/CIN6
P65/FTID/KIN5/
CIN5
P64/FTIC/KIN4/
CIN4/CLAMPO
P63/FTIB/KIN3/
CIN3/VFBACKI
P62/FTIA/TMIY/
KIN2/CIN2/
VSYNCI
P61/FTOA/KIN1/
CIN1/VSYNCO
P60/FTCI/TMIX/
KIN0/CIN0/
HFBACKI
I/O port also functioni ng as ext ernal int errupt i nput (IRQ7, IRQ6),
FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB),
8-bit timer X and Y input/output (TMOX, TMIX, TMIY), timer
connection i nput/ out put (CLAMP O, VFBACKI, VSYNCI,
VSYNCO, HFBACKI ), key-sense interrupt input (KIN7 to KIN0),
and expansion A/D converter i nput (CIN7 to CIN0)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 212 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 7 • 8-bit I/ O port P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Input port also functioning as A/ D convert er anal og input (AN7 t o
AN0) and D/A converter analog output (DA 1, DA0)
Port 8 • 7-bit I/O port P86/IRQ5/SCK1/
SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82/HIFSD
P81/CS2/GA20
P80/HA0
I/O port also functioni ng as ext ernal
interrupt i nput (IRQ5, IRQ4, IRQ3),
SCI1 input/output (TxD1, RxD1,
SCK1), and I2C bus interface 1
(option) input/output (SCL1)
I/O port also functioni ng as
external interrupt input
(IRQ5, IRQ4, IRQ3), SCI1
input/out put (TxD1, RxD1,
SCK1), host interface
control input/output (CS2,
GA20, HA0, HIFSD), and
I2C bus interface 1 (option)
input/out put (S CL1)
Port 9 • 8-bit I/O port P97/WAIT/SDA0 I/O port also functi oni ng as
expanded data bus control input
(WAIT) and I2C bus interfac e 0
(option) input / output (SDA 0)
I/O port also functioni ng as
I2C bus interface 0 (option)
input/out put (S DA0)
P96/φ/EXCL When DDR =
0: input port or
EXCL input
When DDR =
1 (after reset):
φ output
When DDR = 0 (after reset): input port or EX CL
input
When DDR = 1: φ output
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
Expanded data bus control output
(AS/IOS, HWR, RD)I/O port also functioning as
host interface control input
(CS1, IOW, IOR)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 213 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 9 • 8-bit I/O port P92/IRQ0
P91/IRQ1
I/O port also functioni ng as ext ernal int errupt i nput (IRQ0, IRQ1)
P90/LWR/IRQ2/
ADTRG/ECS2I/O port also functioning as
expanded data bus control output
(LWR), external int errupt input
(IRQ2), and A/D converter external
trigger input (ADTRG)
I/O port also functioni ng as
external interrupt input
(IRQ2), A/D converter
external trigger input
(ADTRG), and host
interface c ontrol input
(ECS2)
Port A • 8-bit I/O port PA 7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
I/O port also
functioning as
key-sense
interrupt i nput
(KIN15 to
KIN8),
expansion A/D
convert er input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt i nput
(KIN15 to KIN8),
expansion A/D
convert er input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC , PS2AD,
PS2AC)
I/O port also functioni ng as
key-sense interrupt i nput
(KIN15 to KIN8),
expansion A/D convert e r
input (CIN15 to CIN8), and
keyboard buffer cont rol l er
input/out put (PS2CD,
PS2 CC, PS2BD, PS2BC,
PS2AD , PS2AC)
Port B • 8-bit I/O port PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
In 8-bit bus mode (ABW = 1): I/O
port
In 16-bit bus mode (ABW = 0): data
bus input/out put (D7 to D0)
I/O port also functioni ng as
HIF control input/output
pins (CS3, CS4, HIRQ3,
HIRQ4)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 214 of 1130
REJ09B0327-0400
Table 8.2 H8S/2147N Port Functions
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 1 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P17 to P10/
A7 to A0/
PW7 to PW0
Lower address
output
(A7 to A0)
When DDR = 0
(after res et): input
port
When DDR = 1:
lower address
output (A7 to A0) or
PWM timer output
(PW7 to PW0)
I/O port also functioni ng as
PWM timer output (PW7 to
PW0)
Port 2 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P27/A15/PW15
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
Upper address
output
(A15 to A8)
When DDR = 0
(after res et): input
port
When DDR = 1:
upper address
output (A15 to A8),
PWM timer output
(PW15 to PW8), or
output ports (P27 to
P24)
I/O port also functioni ng as
PWM timer output (PW15
to PW8)
Port 3 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P37 to P30/
HDB7 to HDB0/
D15 to D8
Data bus input/output (D15 t o D8) I/O port also functioning as
host interface data bus
input/out put (HDB 7 to
HDB0)
Port 4 • 8-bit I/O port P47/PWX1
P46/PWX0
P45/TMRI1/
HIRQ12
P44/TMO1/
HIRQ1
P43/TMCI1/
HIRQ11
P42/TMRI0/
SCK2/SDA1
P41/TMO0/
RxD2/IrRxD
P40/TMCI0/
TxD2/IrTxD
I/O port also functioni ng as 14-bit
PWM timer output (PWX1, PWX0),
8-bit timer 0 and 1 input/output
(TMCI0, TMRI0, TMO0, TMCI1,
TMRI1, TMO1), SCI2 input/output
(TxD2, RxD2, S CK2), IrDA interface
input/out put (I rTxD, I rRxD), and I2C
bus interfac e 1 (option) input/out put
(SDA1)
I/O port also functioni ng as
14-bit PWM timer output
(PWX1, PWX0), 8-bit timer
0 and 1 input/output
(TMCI0, TMRI 0, TMO0,
TMCI1, TMRI 1, TMO1),
host interf ace host CPU
interrupt request output
(HIRQ12, HIRQ1,
HIRQ11), SCI2 input/
output (TxD2, RxD2,
SCK2), IrDA interface
input/out put (I rTx D, IrRxD),
and I2C bus interf ace 1
(option) input/output
(SDA1)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 215 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 5 • 3-bit I/ O port P52/SCK0/SCL0
P51/RxD0
P50/TxD0
I/O port also functioni ng as SCI0 input/output (TxD0, RxD0,
SCK0) and I2C bus interf ace 0 (option) i nput/ output (SCL0)
Port 6 • 8-bit I/O port P67/IRQ7/KIN7/
CIN7
P66/IRQ6/FTOB/
KIN6/CIN6
P65/FTID/KIN5/
CIN5
P64/FTIC/KIN4/
CIN4
P63/FTIB/KIN3/
CIN3
P62/FTIA/TMIY/
KIN2/CIN2
P61/FTOA/KIN1/
CIN1
P60/FTCI/KIN0/
CIN0
I/O port also functioni ng as ext ernal int errupt i nput (IRQ7, IRQ6),
FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB),
8-bit timer Y input (TMIY), key-sense interrupt input (KIN7 to
KIN0), and expansion A/D converter input (CIN7 to CIN0)
Port 7 • 8-bit I/ O port P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Input port also functioning as A/ D convert er anal og input (AN7 t o
AN0) and D/A converter analog output (DA 1, DA0)
Port 8 • 7-bit I/O port P86/IRQ5/SCK1/
SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82/HIFSD
P81/CS2/GA20
P80/HA0
I/O port also functioni ng as ext ernal
interrupt i nput (IRQ5, IRQ4, IRQ3),
SCI1 input/output (TxD1, RxD1,
SCK1), and I2C bus interface 1
(option) input/output (SCL1)
I/O port also functioni ng as
external interrupt input
(IRQ5, IRQ4, IRQ3), SCI1
input/out put (TxD1, RxD1,
SCK1), host interface
control input/output (CS2,
GA20, HA0, HIFSD), and
I2C bus interface 1 (option)
input/out put (S CL1)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 216 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 9 • 8-bit I/O port P97/WAIT/SDA0 I/O port also functi oni ng as
expanded data bus control input
(WAIT) and I2C bus interfac e 0
(option) input / output (SDA 0)
I/O port also functioni ng as
I2C bus interface 0 (option)
input/out put (S DA0)
P96/φ/EXCL When DDR =
0: input port or
EXCL input
When DDR =
1 (after reset):
φ output
When DDR = 0 (after reset): input port or EX CL
input
When DDR = 1: φ output
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
Expanded data bus control output
(AS/IOS, HWR, RD)I/O port also functioning as
host interface control input
(CS1, IOW, IOR)
P92/IRQ0
P91/IRQ1
I/O port also functioni ng as ext ernal int errupt i nput (IRQ0, IRQ1)
P90/LWR/IRQ2/
ADTRG/ECS2I/O port also functioning as
expanded data bus control output
(LWR), external int errupt input
(IRQ2), and A/D converter external
trigger input (ADTRG)
I/O port also functioni ng as
external interrupt input
(IRQ2), A/D converter
external trigger input
(ADTRG), and host
interface c ontrol input
(ECS2)
Port A • 8-bit I/O port PA 7/A 23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
I/O port also
functioning as
key-sense
interrupt i nput
(KIN15 to
KIN8),
expansion A/D
convert er input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt i nput
(KIN15 to KIN8),
expansion A/D
convert er input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC , PS2AD,
PS2AC)
I/O port also functioni ng as
key-sense interrupt i nput
(
K
IN1
5
to KIN8), expansion
A/D converter i nput (CIN15
to CIN8), and keyboard
buffer controller
input/out put (PS2CD,
PS2 CC, PS2BD, PS2BC,
PS2AD , PS2AC)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 217 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port B • 8-bit I/O port PB 7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
In 8-bit bus mode (ABW = 1): I/O
port
In 16-bit bus mode (ABW = 0): data
bus input/out put (D7 to D0)
I/O port also functioni ng as
HIF control input/output
pins (CS3, CS4, HIRQ3,
HIRQ4)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 218 of 1130
REJ09B0327-0400
Table 8.3 H8S/2144 Group Port Functions
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 1 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P17 to P10/
A7 to A0 Lower address
output (A7 to
A0)
When DDR = 0
(after res et): input
port
When DDR = 1:
lower address
output (A7 to A0)
I/O port
Port 2 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P27 to P20/
A15 to A8 Upper address
output (A15 to
A8)
When DDR = 0
(after res et): input
port
When DDR = 1:
upper address
output (A15 to A8)
or output port (P27
to P24)
I/O port
Port 3 • 8-bit I/O port
• Built-in MOS
input pull-
ups
•LED drive
capability
P37 to P30/
D15 to D8 Data bus i nput/ output (D15 to D8) I/ O port
Port 4 • 8-bit I/O port P47/PWX1
P46/PWX0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SCK2
P41/TMO0/RxD2/
IrRxD
P40/TMCI0/
TxD2/IrTxD
I/O port also functioni ng as 14-bit PWM timer out put (PWX1,
PWX0), 8-bit timer 0 and 1 input/output (TMCI0, TMRI0, TMO0,
TMCI1, TMRI1, TMO1), SCI2 input/output (TxD2, RxD2, SCK2),
and IrDA interface i nput/ output (IrTxD, IrRxD)
Port 5 • 3-bit I/O port P52/SCK0
P51/RxD0
P50/TxD0
I/O port also functioni ng as SCI0 input/output (TxD0, RxD0,
SCK0)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 219 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 6 • 8-bit I/O port P67/IRQ7/KIN7/
CIN7
P66/IRQ6/FTOB/
KIN6/CIN6
P65/FTID/KIN5/
CIN5
P64/FTIC/KIN4/
CIN4
P63/FTIB/KIN3/
CIN3
P62/FTIA/TMIY/
KIN2/CIN2
P61/FTOA/KIN1/
CIN1
P60/FTCI/KIN0/
CIN0
I/O port also functioni ng as ext ernal int errupt i nput (IRQ7, IRQ6),
FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB),
8-bit timer Y input (TMIY), key-sense interrupt input (KIN7 to
KIN0), and expansion A/D converter input (CIN7 to CIN0)
Port 7 • 8-bit i nput
port P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Input port also functioning as A/ D convert er anal og input (AN7 t o
AN0) and D/A converter analog output (DA 1, DA0)
Port 8 • 7-bit I/O port P86/IRQ5/SCK1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82
P81
P80
I/O port also functioni ng as ext ernal int errupt i nput (IRQ5, IRQ4,
IRQ3) and SCI1 input/output (TxD1, Rx D1, SCK1)
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 220 of 1130
REJ09B0327-0400
Expanded Modes Single-Chip Mode
Port Description Pins Mode 1 Mode 2, Mode 3
(EXPE = 1) Mode 2, Mode 3
(EXPE = 0)
Port 9 • 8-bit I/O port P97/WAIT I/O port also functi oni ng as
expanded data bus control input
(WAIT)
I/O port
P96/φ/EXCL When DDR =
0: input port or
EXCL input
When DDR =
1 (after reset):
φ output
When DDR = 0 (after reset): input port or EX CL
input
When DDR = 1: φ output
P95/AS/IOS
P94/HWR
P93/RD
Expanded data bus control
output(AS/IOS, HWR, RD)I/O port
P92/IRQ0
P91/IRQ1
I/O port also functioni ng as ext ernal int errupt i nput (IRQ0, IRQ1)
P90/LWR/
IRQ2/ADTRG I/O port also funct i oni ng as
expanded data bus control output
(LWR), external int errupt input
(IRQ2), and A/D converter external
trigger input (ADTRG)
I/O port also functioni ng as
external interrupt input
(IRQ2) and A/D converter
external trigger input
(ADTRG)
Port A • 8-bit I/O por t PA7 to PA0 /
A23 to A16/
KIN15 to KIN8/
CIN15 to CIN8
I/O port also
functioning as
key-sense
interrupt i nput
(KIN15 to
KIN8), and
expansion A/D
convert er input
(CIN15 to
CIN8)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt i nput
(KIN15 to KIN8),
and expansion A/D
convert er input
(CIN15 to CIN8)
I/O port also functioni ng as
key-sense interrupt i nput
(KIN15 to KIN8) and
expansion A/D convert e r
input (CIN15 to CIN8)
Port B • 8-bit I/O port PB7 to PB0/
D7 to D0 In 8-bit bus mode (ABW = 1): I/O
port
In 16-bit bus mode (ABW = 0): data
bus input/out put (D7 to D0)
I/O port
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 221 of 1130
REJ09B0327-0400
8.2 Port 1
8.2.1 Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as address bus output pins (A7 to A0), and as
8-bit PWM output pins (PW7 to PW0) (H8S/2148 Group and H8S/2147N only). Port 1 functions
change according to the operating mode. Port 1 has a built-in MOS input pull-up function that can
be controlled by software.
Figure 8.1 shows the port 1 pin configuration.
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
Port 1
Port 1 pins
A7 (Output)
A6 (Output)
A5 (Output)
A4 (Output)
A3 (Output)
A2 (Output)
A1 (Output)
A0 (Output)
Pin functions in mode 1
A7 (Output)/P17 (Input)/PW7 (Output)
A6 (Output)/P16 (Input)/PW6 (Output)
A5 (Output)/P15 (Input)/PW5 (Output)
A4 (Output)/P14 (Input)/PW4 (Output)
A3 (Output)/P13 (Input)/PW3 (Output)
A2 (Output)/P12 (Input)/PW2 (Output)
A1 (Output)/P11 (Input)/PW1 (Output)
A0 (Output)/P10 (Input)/PW0 (Output)
Pin functions in modes 2 and 3 (EXPE = 1)
P17 (I/O)/PW7 (Output)
P16 (I/O)/PW6 (Output)
P15 (I/O)/PW5 (Output)
P14 (I/O)/PW4 (Output)
P13 (I/O)/PW3 (Output)
P12 (I/O)/PW2 (Output)
P11 (I/O)/PW1 (Output)
P10 (I/O)/PW0 (Output)
Pin functions in modes 2 and 3 (EXPE = 0)
Figure 8.1 Port 1 Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 222 of 1130
REJ09B0327-0400
8.2.2 Register Configuration
Table 8.4 shows the port 1 register configuration.
Table 8.4 Port 1 Registers
Name Abbreviation R/W Initial Value Address*
Port 1 data direction register P1DDR W H'00 H'FFB0
Port 1 data register P1DR R/W H'00 H'FFB2
Port 1 MOS pull-up control
register P1PCR R/W H'00 H'FFAC
Note: *Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
0
P10DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
Bit
Initial value
Read/Write
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be returned.
P1DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. Th e address output pins maintain their output state in a transition to
software standby mode.
• Mode 1
The corresponding port 1 pins are address outputs, regardless of the P1DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
• Modes 2 and 3 (EXPE = 1)
The corresponding port 1 pins are address outputs or PWM outputs when P1DDR bits are set
to 1, and input ports when cleared to 0.
• Modes 2 and 3 (EXPE = 0)
The corresponding port 1 pins are output ports or PWM outputs when P1DDR bits are set to 1,
and input ports when cleared to 0.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 223 of 1130
REJ09B0327-0400
Port 1 Data Register (P1DR)
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
0
P10DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
Bit
Initial value
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read directly,
regardless of the actual pin states. If a port 1 read is performed while P1DDR bits are cleared to 0,
the pin states are read.
P1DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 1 MOS Pull-Up Control Register (P1P CR)
7
P17PCR
0
R/W
6
P16PCR
0
R/W
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
0
P10PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
Bit
Initial value
R/W
P1PCR is an 8-bit readable/writable register that controls the port 1 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3, the MOS input pull-up is turned on when a P1PCR bit is set to 1 while the
corresponding P1DDR bit is cleared to 0 (input port setting).
P1PCR is initialized to H'00 by a r e set and in hardware stand by mode. It retains its prior state in
software standby mode.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 224 of 1130
REJ09B0327-0400
8.2.3 Pin Functions in Each Mode
Mode 1
In mode 1, port 1 pins automatically function as address outputs. The port 1 pin functions are
shown in figure 8.2.
A7 (Output)
A6 (Output)
A5 (Output)
A4 (Output)
A3 (Output)
A2 (Output)
A1 (Output)
A0 (Output)
Port 1
Figure 8.2 Port 1 Pin Functions (Mode 1)
Modes 2 and 3 (EXPE = 1)
In modes 2 and 3 (when EXPE = 1), port 1 pins function as address outputs, PWM outputs, or
input ports, and input or output can be specified on a bit-by-bit basis. Wh en a bit in P1DDR is set
to 1, the corresponding pin functions as an address output or PWM output, and when cleared to 0,
as an input port.
The port 1 pin functions are shown in figure 8.3.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 225 of 1130
REJ09B0327-0400
A7 (Output)
A6 (Output)
A5 (Output)
A4 (Output)
A3 (Output)
A2 (Output)
A1 (Output)
A0 (Output)
Port 1
When P1DDR = 1
and PWOERA = 0
P17 (Input)
P16 (Input)
P15 (Input)
P14 (Input)
P13 (Input)
P12 (Input)
P11 (Input)
P10 (Input)
When P1DDR = 0
PW7 (Output)
PW6 (Output)
PW5 (Output)
PW4 (Output)
PW3 (Output)
PW2 (Output)
PW1 (Output)
PW0 (Output)
When P1DDR = 1
and PWOERA = 1
Figure 8.3 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 1))
Modes 2 and 3 (EXPE = 0)
In modes 2 and 3 (when EXPE = 0), port 1 pins function as PWM outputs or I/O ports, and input
or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the
corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input
port.
The port 1 pin functions are shown in figure 8.4.
P17 (I/O)
P16 (I/O)
P15 (I/O)
P14 (I/O)
P13 (I/O)
P12 (I/O)
P11 (I/O)
P10 (I/O)
Port 1
P1n: Input pin when P1DDR = 0,
output pin when P1DDR = 1
and PWOERA = 0
PW7 (Output)
PW6 (Output)
PW5 (Output)
PW4 (Output)
PW3 (Output)
PW2 (Output)
PW1 (Output)
PW0 (Output)
When P1DDR = 1
and PWOERA = 1
Figure 8.4 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 0))
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 226 of 1130
REJ09B0327-0400
8.2.4 MOS In put Pull-Up Function
Port 1 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-by-
bit basis.
When a P1DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P1PCR bit to 1 turns
on the MOS input pull-up for that p in.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.5 summarizes the MOS input pull-up states.
Table 8.5 MOS Input P ull-Up Sta tes (Port 1)
Mode Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
1 Off Off Off Off
2, 3 Off Off On/Off On/Off
Legend:
Off: MOS input pull-up is always off.
On/Off:On when P1DDR = 0 and P1PCR = 1; otherwise off.
8.3 Port 2
8.3.1 Overview
Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output pins (A15 to A8), 8-bit
PWM output pins (PW15 to PW8) (H8S/2148 Group and H8S/2147N only), and the timer
connection output pin (CBLANK) (H8S/2148 Group only). Port 2 functions change according to
the operating mode. Port 2 has a built-in MOS input pull-up function that can be controlled by
software.
Figure 8.5 shows the port 2 pin configuration.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 227 of 1130
REJ09B0327-0400
P27/A15/PW15/CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
Port 2
Port 2 pins
A15 (Output)
A14 (Output)
A13 (Output)
A12 (Output)
A11 (Output)
A10 (Output)
A9 (Output)
A8 (Output)
Pin functions in mode 1
A15 (Output)/P27 (I/O)/PW15 (Output)/CBLANK (Output)
A14 (Output)/P26 (I/O)/PW14 (Output)
A13 (Output)/P25 (I/O)/PW13 (Output)
A12 (Output)/P24 (I/O)/PW12 (Output)
A11 (Output)/P23 (Input)/PW11 (Output)
A10 (Output)/P22 (Input)/PW10 (Output)
A9 (Output)/P21 (Input)/PW9 (Output)
A8 (Output)/P20 (Input)/PW8 (Output)
Pin functions in modes 2 and 3 (EXPE = 1)
P27 (I/O)/PW15 (Output)/CBLANK (Output)
P26 (I/O)/PW14 (Output)
P25 (I/O)/PW13 (Output)
P24 (I/O)/PW12 (Output)
P23 (I/O)/PW11 (Output)
P22 (I/O)/PW10 (Output)
P21 (I/O)/PW9 (Output)
P20 (I/O)/PW8 (Output)
Pin functions in modes 2 and 3 (EXPE = 0)
Figure 8.5 Port 2 Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 228 of 1130
REJ09B0327-0400
8.3.2 Register Configuration
Table 8.6 shows the port 2 register configuration.
Table 8.6 Port 2 Registers
Name Abbreviation R/W Initial Value Address*
Port 2 data direction register P2DDR W H'00 H'FFB1
Port 2 data register P2DR R/W H'00 H'FFB3
Port 2 MOS pull-up control
register P2PCR R/W H'00 H'FFAD
Note: *Lower 16 bits of the address.
Port 2 Data Direction Register (P2DDR)
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
4
P24DDR
0
W
3
P23DDR
0
W
0
P20DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
Bit
Initial value
Read/Write
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined valu e will be returned.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. Th e address output pins maintain their output state in a transition to
software standby mode.
• Mode 1
The corresponding port 2 pins are address outputs, regardless of the P2DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
• Modes 2 and 3 (EXPE = 1)
The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set
to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output
ports by setting the IOSE bit to 1.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 229 of 1130
REJ09B0327-0400
• Modes 2 and 3 (EXPE = 0)
The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1,
and input ports when cleared to 0.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting.
Port 2 Data Register (P2DR)
7
P27DR
0
R/W
6
P26DR
0
R/W
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
0
P20DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
Bit
Initial value
R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20).
If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly,
regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0,
the pin states are read.
P2DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 2 MOS Pull-Up Control Register (P2P CR)
7
P27PCR
0
R/W
6
P26PCR
0
R/W
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
0
P20PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
Bit
Initial value
R/W
P2PCR is an 8-bit readable/writable register that controls the port 2 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3, the MOS input pull-up is turned on when a P2PCR bit is set to 1 while the
corresponding P2DDR bit is cleared to 0 (input port setting).
P2PCR is initialized to H'00 by a r e set and in hardware stand by mode. It retains its prior state in
software standby mode.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 230 of 1130
REJ09B0327-0400
8.3.3 Pin Functions in Each Mode
Mode 1
In mode 1, port 2 pins automatically function as address outputs. The port 2 pin functions are
shown in figure 8.6.
A15 (Output)
A14 (Output)
A13 (Output)
A12 (Output)
A11 (Output)
A10 (Output)
A9 (Output)
A8 (Output)
Port 2
Figure 8.6 Port 2 Pin Functions (Mode 1)
Modes 2 and 3 (EXPE = 1)
In modes 2 and 3 (when EXPE = 1), port 2 pins function as address outputs, PWM outputs, or I/O
ports, and input or output can be specified on a bit-by-bit basis. When a bit in P2DDR is set to 1,
the corresponding pin functions as an address output or PWM output, and when cleared to 0, as an
input port. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to
1. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
The port 2 pin functions are shown in figure 8.7.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 231 of 1130
REJ09B0327-0400
A15 (Output)/P27 (Output)
A14 (Output)/P26 (Output)
A13 (Output)/P25 (Output)
A12 (Output)/P24 (Output)
A11 (Output)
A10 (Output)
A9 (Output)
A8 (Output)
Port 2
When P2DDR = 1
and PWOERB = 0
P27 (Input)/CBLANK (Output)
P26 (Input)
P25 (Input)
P24 (Input)
P23 (Input)
P22 (Input)
P21 (Input)
P20 (Input)
When P2DDR = 0
PW15 (Output)/CBLANK (Output)
PW14 (Output)
PW13 (Output)
PW12 (Output)
PW11 (Output)
PW10 (Output)
PW9 (Output)
PW8 (Output)
When P2DDR = 1
and PWOERB = 1
Figure 8.7 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 1))
Modes 2 and 3 (EXPE = 0)
In modes 2 and 3 (when EXPE = 0), port 2 pins function as PWM outputs (P27 can also function
as the timer connection output (CBLANK)) or I/O ports, and input or output can be specified on a
bit-by- bit basis. When a bit in P2DDR is set to 1, the co rresponding p in fu nctions as a PWM
output or output port, and when cleared to 0, as an input port. P27 can be used as an on-chip
supporting module output pin regardless of the P27DDR setting.
The port 2 pin functions are shown in figure 8.8.
P27 (I/O)/CBLANK (Output)
P26 (I/O)
P25 (I/O)
P24 (I/O)
P23 (I/O)
P22 (I/O)
P21 (I/O)
P20 (I/O)
Port 2
P2n: Input pin when P2DDR = 0,
output pin when P2DDR = 1
and PWOERB = 0
PW15 (Output)/CBLANK (Output)
PW14 (Output)
PW13 (Output)
PW12 (Output)
PW11 (Output)
PW10 (Output)
PW9 (Output)
PW8 (Output)
When P2DDR = 1
and PWOERB = 1
Figure 8.8 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 0))
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 232 of 1130
REJ09B0327-0400
8.3.4 MOS In put Pull-Up Function
Port 2 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-by-
bit basis.
When a P2DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P2PCR bit to 1 turns
on the MOS input pull-up for that p in.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.7 summarizes the MOS input pull-up states.
Table 8.7 MOS Input P ull-Up Sta tes (Port 2)
Mode Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
1 Off Off Off Off
2, 3 Off Off On/Off On/Off
Legend:
Off: MOS input pull-up is always off.
On/Off:On when P2DDR = 0 and P2PCR = 1; otherwise off.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 233 of 1130
REJ09B0327-0400
8.4 Port 3
8.4.1 Overview
Port 3 is an 8-bit I/O port. Port 3 pins also function as host data bus I/O pins (HDB7 to HDB0)
(H8S/2148 Group and H8S/2147N only), and as data bus I/O pins. Port 3 functions change
according to the operating mod e. Port 3 has a built-in MOS input pull-up function that can be
controlled by softw are.
Figure 8.9 shows the port 3 pin configuration.
P37/D15/HDB7
P36/D14/HDB6
P35/D13/HDB5
P34/D12/HDB4
P33/D11/HDB3
P32/D10/HDB2
P31/D9/HDB1
P30/D8/HDB0
Port 3
Port 3 pins
D15 (I/O)
D14 (I/O)
D13 (I/O)
D12 (I/O)
D11 (I/O)
D10 (I/O)
D9 (I/O)
D8 (I/O)
Pin functions in modes 1, 2 and 3 (EXPE = 1)
P37 (I/O)/HDB7 (I/O)
P36 (I/O)/HDB6 (I/O)
P35 (I/O)/HDB5 (I/O)
P34 (I/O)/HDB4 (I/O)
P33 (I/O)/HDB3 (I/O)
P32 (I/O)/HDB2 (I/O)
P31 (I/O)/HDB1 (I/O)
P30 (I/O)/HDB0 (I/O)
Pin functions in modes 2 and 3 (EXPE = 0)
Figure 8.9 Port 3 Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 234 of 1130
REJ09B0327-0400
8.4.2 Register Configuration
Table 8.8 shows the port 3 register configuration.
Table 8.8 Port 3 Registers
Name Abbreviation R/W Initial Value Address*
Port 3 data direction register P3DDR W H'00 H'FFB4
Port 3 data register P3DR R/W H'00 H'FFB6
Port 3 MOS pull-up control
register P3PCR R/W H'00 H'FFAE
Note: *Lower 16 bits of the address.
Port 3 Data Direction Register (P3DDR)
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
0
P30DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
Bit
Initial value
Read/Write
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. P3DDR cannot be read; if it is, an undefined valu e will be returned.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 1, 2, and 3 (EXPE = 1)
The input/output direction specified by P3DDR is ignored, and pins automatically function as
data I/O pins.
After a reset, and in hardware standby mode or software standby mode, the data I/O pins go to
the high-impedance state.
• Modes 2 and 3 (EXPE = 0)
The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports
when cleared to 0.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 235 of 1130
REJ09B0327-0400
Port 3 Data Register (P3DR)
7
P37DR
0
R/W
6
P36DR
0
R/W
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
0
P30DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
Bit
Initial value
Read/Write
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30).
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly,
regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0,
the pin states are read.
P3DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 3 MOS Pull-Up Control Register (P3P CR)
7
P37PCR
0
R/W
6
P36PCR
0
R/W
5
P35PCR
0
R/W
4
P34PCR
0
R/W
3
P33PCR
0
R/W
0
P30PCR
0
R/W
2
P32PCR
0
R/W
1
P31PCR
0
R/W
Bit
Initial value
Read/Write
P3PCR is an 8-bit readable/writable register that controls the port 3 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3 (when EXPE = 0), the MOS input pu ll-up is turned on when a P3 PCR bit is set
to 1 while the corresponding P3DDR bit is cleared to 0 (input po rt setting).
P3PCR is initialized to H'00 by a r e set and in hardware stand by mode. It retains its prior state in
software standby mode.
The MOS input pull-up function cannot be used in slave mode (when the host interface is
enabled).
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 236 of 1130
REJ09B0327-0400
8.4.3 Pin Functions in Each Mode
Modes 1, 2, and 3 (EXPE = 1)
In modes 1, 2, and 3 (when EXPE = 1), port 3 pins automatically function as data I/O pins. The
port 3 pin functions are shown in figure 8.10.
D15 (I/O)
D14 (I/O)
D13 (I/O)
D12 (I/O)
D11(I/O)
D10 (I/O)
D9 (I/O)
D8 (I/O)
Port 3
Figure 8.10 Port 3 Pin Functions (Modes 1, 2, and 3 (EXPE = 1))
Modes 2 and 3 (EXPE = 0)
In modes 2 and 3 (when EXPE = 0), port 3 functions as host interface data bus I/O pins (HDB7 to
HDB0) or as I /O ports. When the HI12E bit is set to 1 in SYSCR2 and a transition is made to
slave mode, port 3 functions as the host interface data bus. In slave mode, P3DR and P3DDR
should be cleared to H'00. When the HI12E bit is cleared to 0, port 3 functions as an I/O port, and
input or output can be specified on a bit-by-bit basis. When a bit in P3DDR is set to 1, the
corresponding pin functions as an output port, and when cleared to 0, as an input port.
The port 3 pin functions are shown in figure 8.11.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 237 of 1130
REJ09B0327-0400
P37 (I/O)/HDB7 (I/O)
P36 (I/O)/HDB6 (I/O)
P35 (I/O)/HDB5 (I/O)
P34 (I/O)/HDB4 (I/O)
P33 (I/O)/HDB3 (I/O)
P32 (I/O)/HDB2 (I/O)
P31 (I/O)/HDB1 (I/O)
P30 (I/O)/HDB0 (I/O)
Port 3
Figure 8.11 Port 3 Pin Functions (Modes 2 and 3 (EXPE = 0))
8.4.4 MOS In put Pull-Up Function
Port 3 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 2 and 3 (when EXPE = 0), and can be specified as on
or off on a bit-by-bit basis.
When a P3DDR bit is cleared to 0 in mode 2 or 3 (when EXPE = 0), setting the corresponding
P3PCR bit to 1 turns on the MOS input pull- up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.9 summarizes the MOS input pull-up states.
Table 8.9 MOS Input P ull-Up Sta tes (Port 3)
Mode Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
1, 2, 3 (EXPE = 1) Off Off Off Off
2, 3 (EXPE = 0) Off Off On/Off On/Off
Legend:
Off: MOS input pull-up is always off.
On/Off:On when P3DDR = 0 and P3PCR = 1; otherwise off.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 238 of 1130
REJ09B0327-0400
8.5 Port 4
8.5.1 Overview
Port 4 is an 8-bit I/O port. Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0),
8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1),
timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO) (H8S/2148 Group only), SCI2 I/O pins
(TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface output pins
(HIRQ12, HIRQ1, HIRQ11) (H8S/2148 Group and H8S/2147N only), and the IIC1 I/O pin
(SDA1) (option in H8S/2148 Group and H8S/2147N only). Port 4 pin functions are the same in all
operating modes.
Figure 8.12 shows the port 4 pin configuration.
P47 (I/O)/PWX1 (Output)
P46 (I/O)/PWX0 (Output)
P45 (I/O)/TMRI1 (Input)/HIRQ12 (Output)/CSYNCI (Input)
P44 (I/O)/TMO1 (Output)/HIRQ1 (Output)/HSYNCO (Output)
P43 (I/O)/TMCI1 (Input)/HIRQ11 (Output)/HCYNCI (Input)
P42 (I/O)/TMRI0 (Input)/SCK2 (I/O)/SDA1 (I/O)
P41 (I/O)/TMO0 (Output)/RxD2 (Input)/IrRxD (Input)
P40 (I/O)/TMCI0 (Input)/TxD2 (Output)/IrTxD (Output)
Port 4
Port 4 pins
Figure 8.12 Port 4 Pin Functions
8.5.2 Register Configuration
Table 8.10 shows the port 4 register configuration.
Table 8.10 Port 4 Registers
Name Abbreviation R/W Initial Value Address*
Port 4 data direction register P4DDR W H'00 H'FFB5
Port 4 data register P4DR R/W H'00 H'FFB7
Note: *Lower 16 bits of the address.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 239 of 1130
REJ09B0327-0400
Port 4 Data Direction Register (P4DDR)
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
3
P43DDR
0
W
0
P40DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
Bit
Initial value
Read/Write
P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 4. P4DDR cannot be read; if it is, an undefined valu e will be returned.
When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when
cleared to 0, as an input port.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. As 14-bit PWM and SCI2 are initialized in software standby mode, the
pin states are determined by the TMR0, TMR1, HIF, IIC1, P4DDR, and P4DR specifications.
Port 4 Data Register (P4DR)
7
P47DR
0
R/W
6
P46DR
0
R/W
5
P45DR
0
R/W
4
P44DR
0
R/W
3
P43DR
0
R/W
0
P40DR
0
R/W
2
P42DR
0
R/W
1
P41DR
0
R/W
Bit
Initial value
Read/Write
P4DR is an 8-bit readable/writable register that stores output data for the port 4 pins (P47 to P40).
If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly,
regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0,
the pin states are read.
P4DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.5.3 Pin Functions
Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0,
TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1 ), timer connection I/O pins
(CSYNCI, HSYNCI, HSYNCO), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 240 of 1130
REJ09B0327-0400
(IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin
(SDA1). The port 4 pin functions are shown in table 8.11.
Table 8.11 Port 4 Pin Functions
Pin Selection Method and Pin Functions
P47/PWX1 The pin function is switched as shown below according to the combination of
bit OEB in DACR of 14-bit PWM, and bit P47DDR.
OEB 0 1
P47DDR 0 1 —
Pin function P47 input pin P47 output pin PWX1 output pin
P46/PWX0 The pin function is switched as shown below according to the combination of
bit OEA in DACR of 14-bit PWM, and bit P46DDR.
OEA 0 1
P46DDR 0 1 —
Pin function P46 input pin P46 output pin PWX0 output pin
P45/TMRI1/
HIRQ12/CSYNCI The pin function is switched as shown below according to the combination of
the operating mode and bit P45DDR.
P45DDR 0 1
Operating
mode —Not slave mode Slave mode
Pin function P45 input pin P45 output pin HIRQ12 output pin
TMRI1 input pin, CSYNCI input pin
When bits CCLR1 and CCLR0 in TCR1 of TMR1 are set to 1, this pin is used
as the TMRI1 input pin. It can also be used as the CSYNCI input pin.
P44/TMO1/
HIRQ1/HSYNCO The pin function is switched as shown below according to the combination of
the operating mode, bits OS3 to OS0 in TCSR of TMR1, bit HOE in TCONRO
of the timer connection function, and bit P44DDR.
HOE 0 1
OS3 to OS0 All 0 Not all 0 —
P44DDR 0 1 ——
Operating
mode —Not slave
mode Slave
mode ——
Pin function P44
input pin P44
output pin HIRQ1
output pin TMO1
output pin HSYNCO
output pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 241 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P43/TMCI1/
HIRQ11/HSYNCI The pin function is switched as shown below according to the combination of
the operating mode and bit P43DDR.
P43DDR 0 1
Operating
mode —Not slave mode Slave mode
Pin function P43 input pin P43 output pin HIRQ11 output pin
TMCI1 input pin, HSYNCI input pin
When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1,
this pin is used as the TMCI1 input pin. It can also be used as the HSYNCI
input pin.
P42/TMRI0/
SCK2/SDA1 The pin function is switched as shown below according to the combination of
bit ICE in ICCR of IIC1, bits CKE1 and CKE0 in SCR of SCI2, bit C/A in SMR
of SCI2, and bit P42DDR.
ICE 0 1
CKE1 0 1 0
C/A01— 0
CKE0 0 1 —— 0
P42DDR 0 1 ————
Pin function P42
input pin P42
output pin SCK2
output pin SCK2
output pin SCK2
input pin SDA1
I/O pin
TMRI0 input pin
When this pin is used as the SDA1 I/O pin, bits CKE1 and CKE0 in SCR of
SCI2 and bit C/A in SMR of SCI2 must all be cleared to 0. SDA1 is an NMOS-
only output, and has dir ect bu s drive cap abi lity.
When bits CCLR1 and CCLR0 in TCR0 of TMR0 are set to 1, this pin is used
as the TMRI0 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 242 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P41/TMO0/RxD2/
IrRxD The pin function is switched as shown below according to the combination of
bits OS3 to OS0 in TCSR of TMR0, bit RE in SCR of SCI2 and bit P41DDR.
OS3 to OS0 All 0 Not all 0
RE 0 1 0
P41DDR 0 1 ——
Pin function P41
input pin P41
output pin RxD2/IrRxD
input pin TMO0
output pin
When this pin is used as the TMO0 output pin, bit RE in SCR of SCI2 must be
cleared to 0.
P40/TMCI0/TxD2/
IrTxD The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI2 and bit P40DDR.
TE 0 1
P40DDR 0 1 —
Pin function P40
input pin P40
output pin TxD2/IrTxD
output pin
TMCI0 input pin
When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR0,
this pin is used as the TMCI0 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 243 of 1130
REJ09B0327-0400
8.6 Port 5
8.6.1 Overview
Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0), and the
IIC0 I/O pin (SCL0) (option in H8S/2148 Group and H8S/2147N only). In the H8S/2148 Group
and H8S/2147N, P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain
output. Port 5 pin functions are the same in all operating modes.
Figure 8.13 shows the port 5 pin configuration.
P52 (I/O)/SCK0 (I/O)/SCL0 (I/O)
P51 (I/O)/RxD0 (Input)
P50 (I/O)/TxD0 (Output)
Port 5
Port 5 pins
Figure 8.13 Port 5 Pin Functions
8.6.2 Register Configuration
Table 8.12 shows the port 5 register configuration.
Table 8.12 Port 5 Registers
Name Abbreviation R/W Initial Value Address*
Port 5 data direction register P5DDR W H'F8 H'FFB8
Port 5 data register P5DR R/W H'F8 H'FFBA
Note: *Lower 16 bits of the address.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 244 of 1130
REJ09B0327-0400
Port 5 Data Direction Register (P5DDR)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P50DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
Bit
Initial value
Read/Write
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. P5DDR cannot be read; if it is, an undefined valu e will be returned. Bits 7 to 3 are
reserved.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P5DDR is initialized to H'F8 by a reset and in hardware stan dby mode. It retains its prio r state in
software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR,
P5DDR, and P5DR specifications.
Port 5 Data Register (P5DR)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P50DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
Bit
Initial value
Read/Write
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50).
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly,
regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0,
the pin states are read.
Bits 7 to 3 are reserved; they cannot be modified and are always read as 1.
P5DR is initia lized to H'F8 by a r e set and in hardware standby mode. It retains its prior state in
software standby mode.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 245 of 1130
REJ09B0327-0400
8.6.3 Pin Functions
Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0) and the IIC0 I/O pin (SCL0). The
port 5 pin functions are shown in table 8.13.
Table 8.13 Port 5 Pin Functions
Pin Selection Method and Pin Functions
P52/SCK0/SCL0 The pin function is switched as shown below according to the combination of
bits CKE1 and CKE0 in SCR of SCI0, bit C/A in SMR of SCI0, bit ICE in ICCR
of IIC0, and bit P52DDR.
ICE 0 1
CKE1 0 1 0
C/A01— 0
CKE0 0 1 —— 0
P52DDR 0 1 ————
Pin function P52
input pin P52
output pin SCK0
output pin SCK0
output pin SCK0
input pin SCL0
I/O pin
When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of
SCI0 and bit C/A in SMR of SCI0 must all be cleared to 0.
SCL0 is an NMOS open-drain output, and has direct bus drive capability.
In the H8S/2148 Group and H8S/2147N, when set as the P52 output pin or
SCK0 output pin, this pin is an NMOS push-pull output.
P51/RxD0 The pin function is switched as shown below according to the combination of
bit RE in SCR of SCI0 and bit P51DDR.
RE 0 1
P51DDR 0 1 —
Pin function P51 input pin P51 output pin RxD0 input pi n
P50/TxD0 The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI0 and bit P50DDR.
TE 0 1
P50DDR 0 1 —
Pin function P50 input pin P50 output pin TxD0 output pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 246 of 1130
REJ09B0327-0400
8.7 Port 6
8.7.1 Overview
Port 6 is an 8-bit I/O port. Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins
(FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX) (H8S/2148
Group only), the timer Y (TMRY) input pin (TMIY), timer conn ection I/O pins (HFBACKI,
VSYNCI, VSYNCO, VFBACKI, CLAMPO) (H8S/2148 Group only), key-sense interrupt input
pins (KIN7 to KIN0), expansion A/D converter input pins (CIN7 to CIN0), and external interrupt
input pins (IRQ7, IRQ6). In the H8S/2148 Group and H8S/2147N, the port 6 input level can be
switched in four stages. Port 6 pin functions are the same in all operating modes.
Figure 8.14 shows the port 6 pin configuration.
P67 (I/O)/TMOX (Output)/KIN7 (Input)/CIN7 (Input)/IRQ7 (Input)
P66 (I/O)/FTOB (Output)/KIN6 (Input)/CIN6 (Input)/IRQ6 (Input)
P65 (I/O)/FTID (Input)/KIN5 (Input)/CIN5 (Input)
P64 (I/O)/FTIC (Input)/KIN4 (Input)/CIN4 (Input)/CLAMPO (Output)
P63 (I/O)/FTIB (Input)/KIN3 (Input)/CIN3 (Input)/VFBACKI (Input)
P62 (I/O)/FTIA (Input)/KIN2 (Input)/CIN2 (Input)/VSYNCI (Input)/TMIY (Input)
P61 (I/O)/FTOA (Output)/KIN1 (Input)/CIN1 (Input)/VSYNCO (Output)
P60 (I/O)/FTCI (Input)/KIN0 (Input)/CIN0 (Input)/HFBACKI (Input)/TMIX (Input)
Port 6
Port 6 pins
Figure 8.14 Port 6 Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 247 of 1130
REJ09B0327-0400
8.7.2 Register Configuration
Table 8.14 shows the port 6 register configuration.
Table 8.14 Port 6 Registers
Name Abbreviation R/W Initial Value Address*1
Port 6 data direction register P6DDR W H'00 H'FFB9
Port 6 data register P6DR R/W H'00 H'FFBB
Port 6 MOS pull-up control register KMPCR R/W H'00 H'FFF2*2
System control regi ster 2 SYSCR2 R/W H'00 H'FF83
Notes: 1. Lower 16 bits of the address.
2. KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY. To select
KMPCR, set the HIE bit to 1 in SYSCR and set the MSTP2 bit to 0 in MSTPCRL.
Port 6 Data Direction Register (P6DDR)
7
P67DDR
0
W
6
P66DDR
0
W
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
0
P60DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
Bit
Initial value
Read/Write
P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 6. P6DDR cannot be read; if it is, an undefined valu e will be returned.
Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P6DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 248 of 1130
REJ09B0327-0400
Port 6 Data Register (P6DR)
7
P67DR
0
R/W
6
P66DR
0
R/W
5
P65DR
0
R/W
4
P64DR
0
R/W
3
P63DR
0
R/W
0
P60DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
Bit
Initial value
Read/Write
P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60).
If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly,
regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0,
the pin states are read.
P6DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 6 MOS Pull-Up Control Register (KMPCR)
Bit 76543210
KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
KMPCR is an 8-bit readable/writab le register that contro ls the port 6 built-in MOS in put pull-ups
on a bit-by-bit basis.
The MOS input pull-up is turned on when a KMPCR bit is set to 1 while the corresponding
P6DDR bit is cleared to 0 (input port setting).
KMPCR is initia lized to H'00 b y a reset and in hardware standby m ode . I t retains its prior state in
software standby mode.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 249 of 1130
REJ09B0327-0400
System Control Register 2 (SYSCR2) (H8S/2148 Group and H8S/2147N Only)
Bit 76543210
KWUL1 KWUL0 P6PUE —SDE CS4E CS3E HI12E
Initial value00000000
Read/Write R/W R/W R/W —R/W R/W R/W R/W
SYSCR2 is an 8-bit readable/writable register that controls port 6 input level selection and the
operation of host interface functions.
Only bits 7, 6, and 5 are described here. See section 18.2.2, System Control Register 2 (SYSCR2),
for infor m ation on bits 4 to 0.
SYSCR2 is initialized to H'00 by a r e set and in hardware standby mode .
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level setting
can be changed by software, using these bits. The setting of these bits also changes the input level
of the pin functions multiplexed with port 6 .
Bit 7 Bit 6
KWUL1 KWUL0 Description
0 0 Standard input level is selected as port 6 input level (Initial value)
1 Input level 1 is selected as port 6 input level
1 0 Input level 2 is selected as port 6 input level
1 Input level 3 is selected as port 6 input level
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings.
Bit 5
P6PUE Description
0 Standard current specification is selected for port 6 MOS input pull-up function
(Initial value)
1 Current-limit specification is selected for port 6 MOS input pull-up function
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 250 of 1130
REJ09B0327-0400
8.7.3 Pin Functions
Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to
FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY),
timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLA MPO), key-sense
interrupt input pins (KIN7 to KIN0), comparator input pins (CIN7 to CIN0), and external interrupt
input pins (IRQ7, IRQ6). In the H8S/2148 Group and H8S/2147N, the port 6 input level can be
switched in four stages. The port 6 pin functions are shown in table 8.15.
Table 8.15 Port 6 Pin Functions
Pin Selection Method and Pin Functions
P67/TMOX/IRQ7/
KIN7/CIN7 The pin function is switched as shown below according to the combination of
bits OS3 to OS0 in TCSR of TMRX and bit P67DDR.
OS3 to OS0 All 0 Not all 0
P67DDR 0 1 —
Pin function P67 input pin P67 output pin TMOX output pin
IRQ7 input pin, KIN7 input pin, CIN7 input pin
This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER.
It can always be used as the KIN7 or CIN7 input pin.
P66/FTOB/IRQ6/
KIN6/CIN6 The pin function is switched as shown below according to the combination of
bit OEB in TOCR of the FRT and bit P66DDR.
OEB 0 1
P66DDR 0 1 —
Pin function P66 input pin P66 output pin FTOB output pin
IRQ6 input pin, KIN6 input pin, CIN6 input pin
This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER.
It can always be used as the KIN6 or CIN6 input pin.
P65DDR 0 1
P65/FTID/KIN5/
CIN5 Pin function P65 input pin P65 output pin
FTID input pin, KIN5 input pin, CIN5 input pin
This pin can always be used as the FTID, KIN5, or CIN5 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 251 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P64/FTIC/KIN4/
CIN4/CLAMPO The pin function is switched as shown below according to the comb ination of
bit CLOE in TCONRO of the timer connection function and bit P64DDR.
CLOE 0 1
P64DDR 0 1 —
Pin function P64
input pin P64
output pin CLAMPO
output pin
FTIC input pin, KIN4 input pin, CIN4 input pin
This pin can always be used as the FTIC, KIN4, or CIN4 input pin.
P63DDR 0 1
P63/FTIB/KIN3/
CIN3/VFBACKI Pin function P63 input pin P63 output pin
FTIB input pin, VFBACKI input pin, KIN3 input pin,
CIN3 input pin
This pin can always be used as the FTIB, KIN3, CIN3, or VFBACKI input pin.
P62DDR 0 1
Pin function P62 input pin P62 output pin
P62/FTIA/TMIY/
KIN2/CIN2/
VSYNCI
FTIA input pin, VSYNCI input pin, TMIY input pin,
KIN2 input pin, CIN2 input pin
This pin can always be used as the FTIA, TMIY, KIN2, CIN2, or VSYNCI input
pin.
P61/FTOA/KIN1/
CIN1/VSYNCO The pin functi on is switched as shown below according to the combination of
bit OEA in TOCR of the FRT, bit VOE in TCONRO of the timer connection
function, and bit P61DDR.
VOE 0 1
OEA 0 1 0
P61DDR 0 1 ——
Pin function P61
input pin P61
output pin FTOA
output pin VSYNCO
output pin
KIN1 input pin, CIN1 input pin
When this pin is used as the VSYNCO pin, bit OEA in TOCR of the FRT must
be cleared to 0.
This pin can always be used as the KIN1 or CIN1 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 252 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P60DDR 0 1
Pin function P60 input pin P60 output pin
P60/FTCI/TMIX/
KIN0/CIN0/
HFBACKI
FTCI input pin, HFBACKI input pin, TMIX input pin,
KIN0 input pin, CIN0 input pin
This pin is used as the FTCI input pin when an external clock is selected with
bits CKS1 and CKS0 in TCR of the FRT.
It can always be used as the TMIX, KIN0, CIN0, or HFBACKI input pin.
8.7.4 MOS In put Pull-Up Function
Port 6 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in any operating mode, and can be specified as on or off on a
bit-by-bit basi s .
When a P6DDR bit is cleared to 0, settin g the correspondin g KMPCR bit to 1 tu rns o n the MOS
input pull-up for that pin. The MOS input pull-up curren t specification can be changed by means
of the P6PUE bit. When a pin is designated as an on-chip supporting module output pin, the MOS
input pull-up is always off.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.16 summarizes the MOS input pull-up states.
Table 8.1 6 MOS Input Pull-Up Stat es (Port 6)
Mode Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
1, 2, 3 Off Off On/Off On/Off
Legend:
Off: MOS input pull-up is always off.
On/Off:On when P6DDR = 0 and KMPCR = 1; otherwise off.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 253 of 1130
REJ09B0327-0400
8.8 Port 7
8.8.1 Overview
Port 7 is an 8-bit input port. Port 7 pins also function as the A/D converter analog input pins (AN0
to AN7) and D/A converter analog output pins (DA0, DA1). Port 7 functions are the same in all
operating modes.
Figure 8.15 shows the port 7 pin configuration.
P77 (Input)/AN7 (Input)/DA1 (Output)
P76 (Input)/AN6 (Input)/DA0 (Output)
P75 (Input)/AN5 (Input)
P74 (Input)/AN4 (Input)
P73 (Input)/AN3 (Input)
P72 (Input)/AN2 (Input)
P71 (Input)/AN1 (Input)
P70 (Input)/AN0 (Input)
Port 7
Port 7 pins
Figure 8.15 Port 7 Pin Functions
8.8.2 Register Configuration
Table 8.17 shows the port 7 register configuration. Port 7 is an input-only port, and does not have
a data direction register or data register.
Table 8.17 Port 7 Registers
Name Abbreviation R/W Initial Value Address*1
Port 7 input data register P7PIN R Undefined H'FFBE*2
Notes: 1. Lower 16 bits of the address.
2. P7PIN has the same address as PBDDR.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 254 of 1130
REJ09B0327-0400
Port 7 Input Data Register (P7PIN)
7
P77PIN
—*
R
6
P76PIN
—*
R
5
P75PIN
—*
R
4
P74PIN
—*
R
3
P73PIN
—*
R
0
P70PIN
—*
R
2
P72PIN
—*
R
1
P71PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by the state of pins P77 to P70.
When a P7PIN read is performed, the pin states are always read.
P7PIN has the same address as PBDDR; if a write is perf ormed, data will be written into PBDDR
and the port B settin g will be changed.
8.8.3 Pin Functions
Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter
analog output pins (DA0, DA1).
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 255 of 1130
REJ09B0327-0400
8.9 Port 8
8.9.1 Overview
Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the
IIC1 I/O pin (SCL1) (option in H8S/2148 Group and H8S/2147N only), HIF I/O pins (CS2,
GA20, HA0, HIFSD) (H8S/2148 Group and H8S/2147N only), and external interrupt input pins
(IRQ5 to IRQ3). Port 8 pin functions are the same in all op erating modes. Figure 8.16 shows the
port 8 pin configuration.
P86 (I/O)/IRQ5 (Input)/SCK1 (I/O)/SCL1 (I/O)
P85 (I/O)/IRQ4 (Input)/RxD1 (Input)
P84 (I/O)/IRQ3 (Input)/TxD1 (Output)
P83 (I/O)
P82 (I/O)/HIFSD (Input)
P81 (I/O)/CS2 (Input)/GA20 (Output)
P80 (I/O)/HA0 (Input)
Port 8
Port 8 pins
Figure 8.16 Port 8 Pin Functions
8.9.2 Register Configuration
Table 8.18 summarizes the port 8 registers.
Table 8.18 Port 8 Registers
Name Abbreviation R/W Initial Value Address*1
Port 8 data direction register P8DDR W H'80 H'FFBD*2
Port 8 data register P8DR R/W H'80 H'FFBF
Notes: 1. Lower 16 bits of the address.
2. P8DDR has the same address as PBPIN.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 256 of 1130
REJ09B0327-0400
Port 8 Data Direction Register (P8DDR)
Bit 76543210
—P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Initial value10000000
Read/Write —WWWWWWW
P8DDR is a 7-bit write-only register, the individual bits of which specify input or output for the
pins of port 8. P8DDR has the same address as PBPIN, and if r ead, the port B state will be
returned.
Setting a P8DDR bit to 1 makes the corresponding port 8 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P8DDR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 8 Data Register (P8DR)
Bit 76543210
—P86DR P85DR P84DR P83DR P82DR P81DR P80DR
Initial value10000000
Read/Write —R/W R/W R/W R/W R/W R/W R/W
P8DR is a 7-bit readable/writable reg ister that stores output data for the port 8 pins (P86 to P80). If
a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly,
regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0,
the pin states are read.
P8DR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.9.3 Pin Functions
Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1), HIF
I/O pins (CS2, GA20, HA0, HIFSD), and external interrupt input pins (IRQ5 to IRQ3). The port 8
pin functions are shown in table 8.19.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 257 of 1130
REJ09B0327-0400
Table 8.19 Port 8 Pin Functions
Pin Selection Method and Pin Functions
P86/IRQ5/SCK1/
SCL1 The pin function is switched as shown below according to the combination of
bits CKE1 and CKE0 in SCR of SCI1, bit C/A in SMR of SCI1, bit ICE in ICCR
of IIC1, and bit P86DDR.
ICE 0 1
CKE1 0 1 0
C/A01— 0
CKE0 0 1 —— 0
P86DDR 0 1 ————
Pin function P86
input pin P86
output pin SCK1
output pin SCK1
output pin SCK1
input pin SCL1
I/O pin
IRQ5 input pin
When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 inpu t pin.
When this pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of
SCI1 and bit C/A in SMR of SCI1 must all be cleared to 0. SCL1 is an NMOS-
only output, and has dir ect bu s drive cap abi lity.
P85/IRQ4/RxD1 The pin function is switched as shown below according to the combination of
bit RE in SCR of SCI1 and bit P85DDR.
RE 0 1
P85DDR 0 1 —
Pin function P85 input pin P85 output pin RxD1 input pin
IRQ4 input pin
When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 inpu t pin.
P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI1 and bit P84DDR.
TE 0 1
P84DDR 0 1 —
Pin function P84 input pin P84 output pin TxD1 output pin
IRQ3 input pin
When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 inpu t pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 258 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P83 The pin function is switched as shown below according to bit P83DDR.
P83DDR 0 1
Pin function P83 input pin P83 output pin
P82/HIFSD The pin function is switched as shown below according to the combination of
operating mode, bit SDE in SYSCR2, and bit P82DDR.
Operating
mode Not slave mode Slave mode
SDE —01
P82DDR0101—
Pin function P82
input pin P82
output pin P82
input pin P82
output pin HIFSD
input pin
P81/GA20/CS2 The pin function is switched as shown below according to the combination of
operating mode, bit CS2E in SYSCR, bit FGA20E in HICR of the HIF, and bit
P81DDR.
Operating
mode Not slave mode Slave mode
FGA20E —01
CS2E —01—
P81DDR0101—01
Pin function P81
input
pin
P81
output
pin
P81
input
pin
P81
output
pin
CS2
input
pin
P81
input
pin
GA20
output
pin
This pin should be used as the GA20 output pin or CS2 input pin only in mode
2 or 3 (EXPE = 0).
P80/HA0 The pin function is switched as shown below according to the combination of
operating mode and bit P80DDR.
Operating
mode Not slave mode Slave mode
P80DDR 0 1 —
Pin function P80 input pin P80 output pin HA0 input pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 259 of 1130
REJ09B0327-0400
8.10 Port 9
8.10.1 Overview
Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins (IRQ0 to
IRQ2), the A/D converter external trigger input pin (ADTRG), host interface input pins (ECS2,
CS1, IOW, IOR) (H8S/2148 Group and H8S/2147N only), the IIC0 I/O pin (SDA0) (option in
H8S/2148 Group and H8S/2147N on ly), the subclock input pin (EXCL), bus control signal I/O
pins (AS/IOS, RD, HWR, LWR, WAIT), and the system clock (φ) output pin. In H8S/2148 Group
and H8S/2147N, P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and
has direct bu s dr ive capability.
Figure 8.17 shows the port 9 pin configuration.
P97/WAIT/SDA0
P96/φ/EXCL
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG/ECS2
Port 9
Port 9 pins
WAIT (Input)/P97 (I/O)/SDA0 (I/O)
φ (Output)/P96 (Input)/EXCL (Input)
AS (Output)/IOS (Output)
HWR (Output)
RD (Output)
P92 (I/O)/IRQ0 (Input)
P91 (I/O)/IRQ1 (Input)
P90 (I/O)/LWR (Output)/IRQ2 (Input)/ADTRG (Input)
Pin functions in modes 1, 2 and 3 (EXPE = 1)
P97 (I/O)/SDA0 (I/O)
P96 (Input)/φ (Output)/EXCL (Input)
P95 (I/O)/CS1 (Input)
P94 (I/O)/IOW (Input)
P93 (I/O)/IOR (Input)
P92 (I/O)/IRQ0 (Input)
P91 (I/O)/IRQ1 (Input)
P90 (I/O)/IRQ2 (Input)/ADTRG (Input)/ECS2 (Input)
Pin functions in modes 2 and 3 (EXPE = 0)
Figure 8.17 Port 9 Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 260 of 1130
REJ09B0327-0400
8.10.2 Register Configuration
Table 8.20 summarizes the port 9 registers.
Table 8.20 Port 9 Registers
Name Abbreviation R/W Initial Value Address*1
Port 9 data direction register P9DDR W H'40/H'00*2H'FFC0
Port 9 data register P9DR R/W H'00 H'FFC1
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port 9 Data Direction Register (P9DDR)
Bit 76543210
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Mode 1
Initial value01000000
Read/Write W W W W W W W W
Modes 2 and 3
Initial value00000000
Read/Write W W W W W W W W
P9DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 9. P9DDR cannot be read; if it is, an undefined valu e will be returned.
P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3) by a reset and in hardware standby
mode. It retains its prior state in software standby mode.
• Modes 1, 2 and 3 (EXPE = 1)
Pin P97 functions as a bus control input (WAIT), the IIC0 I/O pin (SDA0), or an I/O port,
according to the wait mode setting . When P97 functions as an I/O port, it becomes an output
port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0.
Pin P96 functions as the φ output pin when P96DDR is set to 1, and as the subclock input
(EXCL) or an input port when P96DDR is cleared to 0.
Pins P95 to P93 automatically become bus control outputs (AS/IOS, HWR, RD), regardless of
the input/output direction indicated by P95DDR to P93DDR.
Pins P92 and P91 become output ports when P92DDR and P91DDR are set to 1, and input
ports when P92DDR and P91DDR are cleared to 0.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 261 of 1130
REJ09B0327-0400
When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (LWR),
regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90
becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0.
• Modes 2 and 3 (EXPE = 0)
When the corresponding P9DDR bits are set to 1, pin P96 functions as the φ output pin and
pins P97 and P95 to P90 become output ports. Wh en P9DDR bits are cleared to 0, the
corresponding pins become input ports.
Port 9 Data Register (P9DR)
Bit 76543210
P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR
Initial value 0 —*000000
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Note: *Determined by the state of pin P96.
P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90).
With the exceptio n of P96, if a port 9 read is performed while P9DDR bits are set to 1 , the P9DR
values are read directly, regardless of the actual pin states. If a port 9 read is performed while
P9DDR bits are cleared to 0, the pin states are read.
P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.10.3 Pin Functions
Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter trigger
input pin (ADTRG), HIF input pins ( ECS2, CS1, IOW, IOR), the IIC0 I/O pin (SDA0), the
subclock input pin (EXCL), bus control signal I/O pins ( AS/IOS, RD, HWR, LWR, WAIT), and
the system clock (φ) output pin. The pin functions differ between the mode 1, 2, and 3 (EXPE = 1)
expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin functions
are shown in table 8.21.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 262 of 1130
REJ09B0327-0400
Table 8.21 Port 9 Pin Functions
Pin Selection Method and Pin Functions
P97/WAIT/SDA0 The pin function is switched as shown below according to the combination of
operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR.
Operating
mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0)
WMS1 0 1 —
ICE 0 1 — 01
P97DDR 0 1 —— 01—
Pin function P97
input
pin
P97
output
pin
SDA0
I/O pin WAIT
input
pin
P97
input
pin
P97
output
pin
SDA0
I/O pin
When this pin is set as the P97 output pin in the H8S/2148 Group and
H8S/2147N, it is an NMOS push-pull output. SDA0 is an NMOS open-drain
output, and has direct bus drive capability.
P96/φ/EXCL The pin function is switched as shown below according to the combination of
bit EXCLE in LPWRCR and bit P96DDR.
P96DDR 0 1
EXCLE 0 1 0
Pin function P96 input pin EXCL input pin φ output pin
When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.
P95/AS/IOS/CS1 The pin function is switched as shown below according to the combination of
operating mode, bit IOSE in SYSCR, bit HI12E in SYSCR2, and bit P95DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3 (EXPE = 0)
HI12E —01
P95DDR —01—
IOSE 0 1 ———
Pin function AS
output pin IOS
output pin P95
input pin P95
output pin CS1
input pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 263 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P94/HWR/IOW The pin function is switched as shown below according to the combination of
operating mode, bit HI12E in SYSCR2, and bit P94DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3 (EXPE = 0)
HI12E —01
P94DDR —01—
Pin function HWR
output pin P94
input pin P94
output pin IOW
input pin
P93/RD/IOR The pin function is switched as shown below according to the combination of
operating mode, bit HI12E in SYSCR2, and bit P93DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3 (EXPE = 0)
HI12E —01
P93DDR —01—
Pin function RD output pin P93 input pin P93 output pin IOR input pin
P92/IRQ0 P92DDR 0 1
Pin function P92 input pin P92 output pin
IRQ0 input pin
When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin.
P91/IRQ1 P91DDR 0 1
Pin function P91 input pin P91 output pin
IRQ1 input pin
When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 264 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
P90/LWR/IRQ2/
ADTRG/ECS2 The pin function is switched as shown below according to the combination of
operating mode, bit ABW in WSCR, bits HI12E and CS2E in SYSCR2, bit
FGA20E in HICR, and bit P90DDR.
Operating
mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0)
ABW 0 1 —
HI12E —Any one 0 1
FGA20E — 1
CS2E — 1
P90DDR —0101—
Pin function LWR
output pin P90
input pin P90
output pin P90
input pin P90
output pin ECS2
input pin
IRQ2 input pin, ADTRG in put pin
When the IRQ2E bit in IER is set to 1 in mode 1, 2, or 3 (EXPE = 1) with the
ABW bit in WSCR set to 1, or in mode 2 and 3 (EXPE = 0), this pin is used as
the IRQ2 input pin.
When TRGS1 and TRGS0 in ADCR of the A/D converter are both set to 1, this
pin is used as the ADTRG input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 265 of 1130
REJ09B0327-0400
8.11 Port A
8.11.1 Overview
Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins
(PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD) (H8S/2148 Group and H8S/2147N only),
key-sense in terrupt input pins (KIN15 to KIN8), expansion A/D converter input pins (CIN15 to
CIN8), and address output pins (A23 to A16). Port A pin functions are the same in all operating
modes. Figure 8.18 shows the port A pin configuration.
PA7/A23/KIN15/CIN15/PS2CD
PA6/A22/KIN14/CIN14/PS2CC
PA5/A21/KIN13/CIN13/PS2BD
PA4/A20/KIN12/CIN12/PS2BC
PA3/A19/KIN11/CIN11/PS2AD
PA2/A18/KIN10/CIN10/PS2AC
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
Port A
Port A pins
PA7 (I/O)/KIN15 (Input)/CIN15 (Input)/PS2CD (I/O)
PA6 (I/O)/KIN14 (Input)/CIN14 (Input)/PS2CC (I/O)
PA5 (I/O)/KIN13 (Input)/CIN13 (Input)/PS2BD (I/O)
PA4 (I/O)/KIN12 (Input)/CIN12 (Input)/PS2BC (I/O)
PA3 (I/O)/KIN11 (Input)/CIN11 (Input)/PS2AD (I/O)
PA2 (I/O)/KIN10 (Input)/CIN10 (Input)/PS2AC (I/O)
PA1 (I/O)/KIN9 (Input)/CIN9 (Input)
PA0 (I/O)/KIN8 (Input)/CIN8 (Input)
Pin functions in modes 1 and 2 (EXPE = 0) and mode 3
PA7 (I/O)/A23 (Output)/KIN15 (Input)/CIN15 (Input)/PS2CD (I/O)
PA6 (I/O)/A22 (Output)/KIN14 (Input)/CIN14 (Input)/PS2CC (I/O)
PA5 (I/O)/A21 (Output)/KIN13 (Input)/CIN13 (Input)/PS2BD (I/O)
PA4 (I/O)/A20 (Output)/KIN12 (Input)/CIN12 (Input)/PS2BC (I/O)
PA3 (I/O)/A19 (Output)/KIN11 (Input)/CIN11 (Input)/PS2AD (I/O)
PA2 (I/O)/A18 (Output)/KIN10 (Input)/CIN10 (Input)/PS2AC (I/O)
PA1 (I/O)/A17 (Output)/KIN9 (Input)/CIN9 (Input)
PA0 (I/O)/A16 (Output)/KIN8 (Input)/CIN8 (Input)
Pin functions in mode 2 (EXPE = 1)
Figure 8.18 Port A Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 266 of 1130
REJ09B0327-0400
8.11.2 Register Configuration
Table 8.22 summarizes the port A registers.
Table 8.22 Port A Registers
Name Abbreviation R/W Initial Value Address*1
Port A data direction register PADDR W H'00 H'FFAB*2
Port A output data register PAODR R/W H'00 H'FFAA
Port A input data register PAPIN R Undefined H'FFAB*2
Notes: 1. Lower 16 bits of the address.
2. PADDR and PAPIN have the same address.
Port A Data Direction Register (PADDR)
Bit 76543210
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value00000000
Read/Write W W W W W W W W
PADDR is an 8-bit write-o nly register, the individual bits of which specify input or output for the
pins of port A.
Setting a PADDR bit to 1 mak es the corresponding port A pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PADDR is initialized to H'0 0 by a reset and in hardware standby mod e. It retains its pr ior state in
software standby mode.
Port A Output Data Register (PAODR)
Bit 76543210
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
PAODR is an 8-bit readab le/writable register that stores output data for the port A pins (PA7 to
PA0). PAODR can always be read or written to, regardless of the contents of PADDR.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 267 of 1130
REJ09B0327-0400
PAODR is initialized to H'0 0 by a reset and in hardware standby mod e. It retains its pr ior state in
software standby mode.
Port A Input Dat a Register (PAPIN)
Bit 76543210
PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN
Initial value —*—*—*—*—*—*—*—*
Read/Write R R R R R R R R
Note: *Determined by the state of pins PA7 to PA0.
Reading PAPIN always returns the pin states.
8.11.3 Pin Functions
Port A pins also function as keyboard buffer controller I/O pins (PS2AC, PS2AD, PS2BC,
PS2BD, PS2CC, PS2CD), key-sense interrupt input pins (KIN15 to KIN8), expansion A/D
converter input pins (CIN15 to CIN8), and address output pins (A23 to A16). The port A pin
functions are shown in table 8.23.
Table 8.23 Port A P in F unctions
Pin Selection Method and Pin Functions
PA7/A23/PS2CD/
KIN15/CIN15 The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA7DDR.
Operating
mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
KBIOE 0 1 0 1
PA7DDR 0 1 —01—
IOSE ———— 01—
Pin function PA7
input
pin
PA7
output
pin
PS2CD
output
pin
PA7
input
pin
A23
output
pin
PA7
output
pin
PS2CD
output
pin
KIN15 input pin, CIN15 input pin, PS2CD input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2CD, KIN15, or CIN15 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 268 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
PA6/A22/PS2CC/
KIN14/CIN14 The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA6DDR.
Operating
mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
KBIOE 0 1 0 1
PA6DDR 0 1 —01—
IOSE ———— 01—
Pin function PA6
input
pin
PA6
output
pin
PS2CC
output
pin
PA6
input
pin
A22
output
pin
PA6
output
pin
PS2CC
output
pin
KIN14 input pin, CIN14 input pin, PS2CC input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2CC, KIN14, or CIN14 input pin.
PA5/A21/PS2BD/
KIN13/CIN13 The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA5DDR.
Operating
mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
KBIOE 0 1 0 1
PA5DDR 0 1 —01—
IOSE ———— 01—
Pin function PA5
input
pin
PA5
output
pin
PS2BD
output
pin
PA5
input
pin
A21
output
pin
PA5
output
pin
PS2BD
output
pin
KIN13 input pin, CIN13 input pin, PS2BD input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2BD, KIN13, or CIN13 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 269 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
PA4/A20/PS2BC/
KIN12/CIN12 The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA4DDR.
Operating
mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
KBIOE 0 1 0 1
PA4DDR 0 1 —01—
IOSE ———— 01—
Pin function PA4
input
pin
PA4
output
pin
PS2BC
output
pin
PA4
input
pin
A20
output
pin
PA4
output
pin
PS2BC
output
pin
KIN12 input pin, CIN12 input pin, PS2BC input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2BC, KIN12, or CIN12 input pin.
PA3/A19/PS2AD/
KIN11/CIN11 The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA3DDR.
Operating
mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
KBIOE 0 1 0 1
PA3DDR 0 1 —01—
IOSE ———— 01—
Pin function PA3
input
pin
PA3
output
pin
PS2AD
output
pin
PA3
input
pin
A19
output
pin
PA3
output
pin
PS2AD
output
pin
KIN11 input pin, CIN11 input pin, PS2AD input pin
This pin can always be used as the PS2AD, KIN11, or CIN11 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 270 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
PA2/A18/PS2AC/
KIN10/CIN10 The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA2DDR.
Operating
mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
KBIOE 0 1 0 1
PA2DDR 0 1 —01—
IOSE ———— 01—
Pin function PA2
input
pin
PA2
output
pin
PS2AC
output
pin
PA2
input
pin
A18
output
pin
PA2
output
pin
PS2AC
output
pin
KIN10 input pin, CIN10 input pin, PS2AC input pin
This pin can always be used as the PS2AC, KIN10, or CIN10 input pin.
PA1/A17/KIN9/
CIN9 The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA1DDR.
Operating
mode Modes 1,
2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
PA1DDR 0 1 0 1
IOSE ——— 01
Pin function PA1
input pin PA1
output pin PA1
input pin A17
output pin PA1
output pin
KIN9 input pin, CIN9 input pin
This pin can always be used as the KIN9 or CIN9 input pin.
PA0/A16/KIN8/
CIN8 The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA0DDR.
Operating
mode Modes 1,
2 (EXPE = 0), 3 Mode 2 (EXPE = 1)
PA0DDR 0 1 0 1
IOSE ——— 01
Pin function PA0
input pin PA0
output pin PA0
input pin A16
output pin PA0
output pin
KIN8 input pin, CIN8 input pin
This pin can always be used as the KIN8 or CIN8 input pin.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 271 of 1130
REJ09B0327-0400
8.11.4 MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in any operating mode, and can be specified as on or off on a
bit-by-bit basi s .
When a PADDR bit is cleared to 0, setting the corresponding PAODR bit to 1 turns on the MOS
input pull-up for that pin. The MOS input pull-up for pins PA7 to PA4 is always off when IICS is
set to 1. When the keyboard buffer control pin function is selected for pins PA7 to PA2, the MOS
input pull-up is always off.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.24 summarizes the MOS input pull-up states.
Table 8.2 4 MOS Input Pull-Up States (P ort A)
Mode Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
1, 2, 3 Off Off On/Off On/Off
Legend:
Off: MOS input pull-up is always off.
On/Off:On when PADDR = 0 and PAODR = 1; otherwise off.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 272 of 1130
REJ09B0327-0400
8.12 Port B
8.12.1 Overview
Port B is an 8-bit I/O port. Port B pins also have HIF input/output pins (CS3, CS4, HIRQ3,
HIRQ4) (H8S/2148 Group and H8S/2147N only), and a data bus input/output function (as D7 to
D0). The pin functions depend on the operating mode.
Figure 8.19 shows the port B pin configuration.
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
Port B
Port B pins
D7 (I/O)
D6 (I/O)
D5 (I/O)
D4 (I/O)
D3 (I/O)
D2 (I/O)
D1 (I/O)
D0 (I/O)
Mode 1, modes 2 and 3 (EXPE = 1) when ABW = 0
PB7 (I/O)
PB6 (I/O)
PB5 (I/O)
PB4 (I/O)
PB3 (I/O)/CS4 (Input)
PB2 (I/O)/CS3 (Input)
PB1 (I/O)/HIRQ4 (Output)
PB0 (I/O)/HIRQ3 (Output)
Mode 1, modes 2 and 3 (EXPE = 1) when ABW = 1,
and mode 1, modes 2 and 3 (EXPE = 0)
Figure 8.19 Port B Pin Functions
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 273 of 1130
REJ09B0327-0400
8.12.2 Register Configuration
Table 8.25 summarizes the port B registers.
Table 8.25 Port B Registers
Name Abbreviation R/W Initial Value Address*1
Port B data direction register PBDDR W H'00 H'FFBE*2
Port B output data register PBODR R/W H'00 H'FFBC
Port B input data register PBPIN R Undefined H'FFBD*3
Notes: 1. Lower 16 bits of the address.
2. PBDDR has the same address as P7PIN.
3. PBPIN has the same address as P8DDR.
Port B Data Direction Register (PBDDR)
Bit 76543210
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value00000000
Read/Write W W W W W W W W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR h as the same address as P7PIN, and if r ead, the port 7 pin states will be
returned.
Setting a PBDDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. It re tains its prior state in
software standby mode.
• Modes 1, 2 and 3 (EXPE = 1)
When the ABW bit in WSCR is cleared to 0, port B p ins automatically b e come data I/O pins
(D7 to D0), regard less of the input/output direction indicated by PBDDR. When the ABW bit
is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if the bit is cleared to 0.
Data I/O pins go to the high-impedance state after a reset, and in hardware standby mode or
software standby mode.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 274 of 1130
REJ09B0327-0400
• Modes 2 and 3 (EXPE = 0)
A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input
port if the bit is cleared to 0.
Port B Output Data Register (PBODR)
Bit 76543210
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
PBODR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBODR can always be read or written to, regardless of th e contents of PBDDR.
PBODR is initialized to H'00 by a reset and in hardware standby mode. It re tains its prior state in
software standby mode.
Port B Input Da ta Register (P BP IN)
Bit 76543210
PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN
Initial value —*—*—*—*—*—*—*—*
Read/Write R R R R R R R R
Note: *Determined by the state of pins PB7 to PB0.
Reading PBPIN always returns the pin states.
PBPIN has the same address as P8DDR. If a write is per f ormed, data will be written to P8DDR
and the port 8 settings will change.
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 275 of 1130
REJ09B0327-0400
8.12.3 Pin Functions
Port B pins also function as HIF input pins (CS3, CS4, HIRQ3, HIRQ4) [H8S/2148 Group and
H8S/2147N only] and data bus I/O pins (D7 to D0). The port B pin functions are shown in table
8.26.
Table 8.26 Po rt B Pin Functions
Pin Selection Method and Pin Functions
PB7/D7 The pin function is switched as shown below according to the combination of
the operating mode, bit PB7DDR, and bit ABW in WSCR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
ABW 0 1 —
PB7DDR —0101
Pin function D7
I/O pin PB7
input pin PB7
output pin PB7
input pin PB7
output pin
PB6/D6 The pin function is switched as shown below according to the combination of
the operating mode, bit PB6DDR, and bit ABW in WSCR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
ABW 0 1 —
PB6DDR —0101
Pin function D6
I/O pin PB6
input pin PB6
output pin PB6
input pin PB6
output pin
PB5/D5 The pin function is switched as shown below according to the combination of
the operating mode, bit PB5DDR, and bit ABW in WSCR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
ABW 0 1 —
PB5DDR —0101
Pin function D5
I/O pin PB5
input pin PB5
output pin PB5
input pin PB5
output pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 276 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
PB4/D4 The pin function is switched as shown below according to the combination of
the operating mode, bit PB4DDR, and bit ABW in WSCR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
ABW 0 1 —
PB4DDR —0101
Pin function D4
I/O pin PB4
input pin PB4
output pin PB4
input pin PB4
output pin
PB3/D3/CS4 The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and
bit PB3DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
HI12E —Either cleared to 0 1
CS4E — 1
ABW 0 1 ——
PB3DDR —0101—
Pin function D3
I/O pin PB3
input pin PB3
output pin PB3
input pin PB3
output pin CS4
input pin
PB2/D2/CS3 The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and
bit PB2DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
HI12E —Either cleared to 0 1
CS3E — 1
ABW 0 1 ——
PB2DDR —0101—
Pin function D2
I/O pin PB2
input pin PB2
output pin PB2
input pin PB2
output pin CS3
input pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 277 of 1130
REJ09B0327-0400
Pin Selection Method and Pin Functions
PB1/D1/HIRQ4 The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and
bit PB1DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
HI12E —Either cleared to 0 1
CS4E — 1
ABW 0 1 ——
PB1DDR —0101—
Pin function D1
I/O pin PB1
input pin PB1
output pin PB1
input pin PB1
output pin HIRQ4
output pin
PB0/D0/HIRQ3 The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and
bit PB0DDR.
Operating
mode Modes 1, 2, 3
(EXPE = 1) Modes 2, 3
(EXPE = 0)
HI12E —Either cleared to 0 1
CS3E — 1
ABW 0 1 ——
PB0DDR —0101—
Pin function D0
I/O pin PB0
input pin PB0
output pin PB0
input pin PB0
output pin HIRQ3
output pin
Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 278 of 1130
REJ09B0327-0400
8.12.4 MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 1, 2 and 3 (EXPE = 1) with the ABW bit in WSCR
set to 1, and in modes 2 and 3 (EXPE = 0), and can be specified as on or off on a bit-by-bit basis.
When a PBDD R bit is cleared to 0, setting the corresponding PBODR bit to 1 turns on the MOS
input pull-up for that pin. When a pin is designated as an on-chip supporting module output pin,
the MOS input pull-up is always off.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.27 summarizes the MOS input pull-up states.
Table 8.2 7 MOS Input Pull-Up States (Port B)
Mode Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
1, 2, 3 (EXPE = 1) with
ABW in WSCR = 0 Off Off Off Off
1, 2, 3 (EXPE = 1) with
ABW in WSCR = 1, and
2, 3 (EXPE = 0)
On/Off On/Off
Legend:
Off: MOS input pull-up is always off.
On/Off:On when PBDDR = 0 and PBODR = 1; otherwise off.
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 279 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Ti mers
Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N.
9.1 Overview
The H8/2148 Group has an on-chip pulse width modulation (PWM) timer module with sixteen
outputs. Sixteen output waveforms are generated from a common time base, enabling PWM
output with a high carrier frequency to be produced using pulse division. The PWM timer module
has sixteen 8-bit PWM data registers (PWDRs), and an output pulse with a duty cycle of 0 to
100% can be obtained as specified by PWDR and the port data register (P1DR or P2DR).
9.1.1 Features
The PWM timer module has the following features.
• Operable at a maximu m carrier frequency of 1.25 MHz using pulse division (at 20-MHz
operation)
• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
• Direct or inverted PWM output, and PWM output enab le/disable control
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 280 of 1130
REJ09B0327-0400
9.1.2 Block Diagram
Figure 9.1 shows a block diagram of th e PWM timer module.
PWDR0
PWDR1
PWDR2
PWDR3
PWDR4
PWDR5
PWDR6
PWDR7
PWDR8
PWDR9
PWDR10
PWDR11
PWDR12
PWDR13
PWDR14
PWDR15
P10/PW0
P11/PW1
P12/PW2
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
P20/PW8
P21/PW9
P22/PW10
P23/PW11
P24/PW12
P25/PW13
P26/PW14
P27/PW15
Port/PWM output control
Comparator 0
Comparator 1
Comparator 2
Comparator 3
Comparator 4
Comparator 5
Comparator 6
Comparator 7
Comparator 8
Comparator 9
Comparator 10
Comparator 11
Comparator 12
Comparator 13
Comparator 14
Comparator 15
PWDPRB
PWOERB
P2DDR
P2DR
PWDPRA
PWOERA
P1DDR
P1DR
Module
data bus
Bus interface
Internal
data bus
PWSL
Clock
selection
φ
Internal clock
φ/2
Legend:
PWSL:
PWDR:
PWDPRA:
PWDPRB:
PWOERA:
PWOERB:
PCSR:
P1DDR:
P2DDR:
P1DR:
P2DR:
PWM register select
PWM data register
PWM data polarity register A
PWM data polarity register B
PWM output enable register A
PWM output enable register B
Peripheral clock select register
Port 1 data direction register
Port 2 data direction register
Port 1 data register
Port 2 data register
TCNT
PCSR
φ/4 φ/8
φ/16
Figure 9.1 Block Diagram of PWM Timer Module
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 281 of 1130
REJ09B0327-0400
9.1.3 Pin Configuration
Table 9.1 shows the PWM output pin.
Table 9.1 Pin Config uration
Name Abbreviation I/O Function
PWM output pin 0 to 15 PW0 to PW15 Output PWM timer pulse output 0 to 15
9.1.4 Register Configuration
Table 9.2 lists the registers of the PWM timer module.
Table 9.2 PWM Timer Module Registers
Name Abbreviation R/W Initial Value Address*1
PWM register select PWSL R/W H'20 H'FFD6
PWM data registers 0 to 15 PWDR0 to
PWDR15 R/W H'00 H'FFD7
PWM data polari ty register A PWDPRA R/W H'00 H'FFD5
PWM data polari ty register B PWDPRB R/W H'00 H'FFD4
PWM output enable register A PWOERA R/W H'00 H'FFD3
PWM output enable register B PWOERB R/W H'00 H'FFD2
Port 1 data direction register P1DDR W H'00 H'FFB0
Port 2 data direction register P2DDR W H'00 H'FFB1
Port 1 data register P1DR R/W H'00 H'FFB2
Port 2 data register P2DR R/W H'00 H'FFB3
Peripheral clock select register PCSR R/W H'00 H'FF82*2
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Note: 1.Lower 16 bits of the address.
2. Some registers in the 8-bit timer are assigned in the addresses as other registers. In
this case, register selection is performed by the FLSHE bit in the serial timer control
register (STCR).
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 282 of 1130
REJ09B0327-0400
9.2 Register Descriptions
9.2.1 PWM Register Select (PWSL)
Bit
Initial value
Read/Write
7
PWCKE
0
R/W
6
PWCKS
0
R/W
5
—
1
4
—
0
3
RS3
0
R/W
0
RS0
0
R/W
2
RS2
0
R/W
1
RS1
0
R/W
—
—
PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the
PWM data register.
PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits,
together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the
PWM timer.
PWSL PCSR
Bit 7 Bit 6 Bit 2 Bit 1
PWCKE PWCKS PWCKB PWCKA Description
0 — — — Clock input is disabled (Initial value)
10 ——φ (system clock) is selected
100φ/2 is selected
1φ/4 is selected
10φ/8 is selected
1φ/16 is selected
The PWM resolution, PWM conversion period, and carrier frequency depend on the selected
internal clock, and can be found from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
Thus, with a 20-MHz system clock (φ), the resolution, PWM conversion period, and carrier
frequency are as shown below.
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 283 of 1130
REJ09B0327-0400
Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ
φφ
φ = 20 MHz
Internal Clock
Frequency Resolution PWM Conversion
Period Carrier Frequency
φ50 ns 12.8 µs 1250 kHz
φ/2 100 ns 25.6 µs 625 kHz
φ/4 200 ns 51.2 µs 312.5 kHz
φ/8 400 ns 102.4 µs 156.3 kHz
φ/16 800 ns 204.8 µs 78.1 kHz
Bit 5—Reserved: This bit is always read as 1 and canno t be modified.
Bit 4—Reserved: This bit is always read as 0 and cannot be modified.
Bits 3 to 0—Register Select (RS3 to RS0): These bits select the PWM data register.
Bit 3 Bit 2 Bit 1 Bit 0
RS3 RS2 RS1 RS0 Register Selection
0000 PWDR0 selected
1 PWDR1 selected
1 0 PWDR2 selected
1 PWDR3 selected
1 0 0 PWDR4 selected
1 PWDR5 selected
1 0 PWDR6 selected
1 PWDR7 selected
1000 PWDR8 selected
1 PWDR9 selected
1 0 PWDR10 selected
1 PWDR11 selected
1 0 0 PWDR12 selected
1 PWDR13 selected
1 0 PWDR14 selected
1 PWDR15 selected
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 284 of 1130
REJ09B0327-0400
9.2.2 PWM Data Registers (PWDR0 to PWDR15)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to
be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1
ratio in the conversion period. The upper 4 bits specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16. The lower 4 bits specify how many extra pulses are to be added
within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256
is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output
should be used.
PWDR is initia lized to H'00 by a reset, an d in th e standby modes, watch mode, su bactive mode,
subsleep mode, and module stop mode.
9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
PWDPRA
Bit
Initial value
Read/Write
7
OS7
0
R/W
6
OS6
0
R/W
5
OS5
0
R/W
4
OS4
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
PWDPRB
Bit
Initial value
Read/Write
7
OS15
0
R/W
6
OS14
0
R/W
5
OS13
0
R/W
4
OS12
0
R/W
3
OS11
0
R/W
0
OS8
0
R/W
2
OS10
0
R/W
1
OS9
0
R/W
Each PWDPR is an 8 - bit readable/writab le r egister th at co ntrols the polarity of th e PWM output.
Bits OS0 to OS15 correspond to outputs PW0 to PW15.
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 285 of 1130
REJ09B0327-0400
PWDPR is initialized to H'00 by a reset and in hardware standby mode.
OS Description
0 PWM direct output (PWDR value corresponds to high width of output) (Initial value)
1 PWM inverted output (PWDR value corresponds to low width of output)
9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB)
PWOERA
Bit
Initial value
Read/Write
7
OE7
0
R/W
6
OE6
0
R/W
5
OE5
0
R/W
4
OE4
0
R/W
3
OE3
0
R/W
0
OE0
0
R/W
2
OE2
0
R/W
1
OE1
0
R/W
PWOERB
Bit
Initial value
Read/Write
7
OE15
0
R/W
6
OE14
0
R/W
5
OE13
0
R/W
4
OE12
0
R/W
3
OE11
0
R/W
0
OE8
0
R/W
2
OE10
0
R/W
1
OE9
0
R/W
Each PWOER is an 8-bit readable/writable register that switches between PWM output and port
output. Bits OE15 to OE0 correspond to outputs PW15 to PW0. To set a pin in the output state, a
setting in the port direction register is also necessary. Bits P17DDR to P10DDR correspond to
outputs PW7 to PW0, and bits P27DDR to P20DDR correspond to outputs PW15 to PW8.
PWOER is initialized to H'00 by a r e set and in hardware standby m ode.
DDR OE Description
0 0 Port input (Initial value)
1 Port input
1 0 Port output or PWM 256/256 output
1 PWM output (0 to 255/256 output)
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 286 of 1130
REJ09B0327-0400
9.2.5 Peripheral Clock Select Register (PCSR)
Bit
Initial value
Read/Write
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
—
0
—
2
PWCKB
0
R/W
1
PWCKA
0
R/W
PCSR is an 8-bit readable/writable register that selects the PWM timer input clock.
PCSR is initialized to H'00 by a reset, and in hardware standby m ode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 and 1—PWM Clock Select (PWCKB, PWCKA): Together with bits PWCKE and
PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM timer. For
details, see section 9.2.1, PWM Register Select (PWSL).
Bit 0—Reserved: Do not set this bit to 1.
9.2.6 Port 1 Data Direction Register (P1DDR)
Bit
Initial value
Read/Write
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
0
P10DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for
each pin of port 1 on a bit-by-bit basis.
Port 1 pins are multip lexed with pins PW0 to PW7. The bit corresponding to a pin to be used for
PWM output should be set to 1.
For details on P1DDR, see section 8.2, Port 1.
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 287 of 1130
REJ09B0327-0400
9.2.7 Port 2 Data Direction Register (P2DDR)
Bit
Initial value
Read/Write
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
4
P24DDR
0
W
3
P23DDR
0
W
0
P20DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for
each pin of port J on a bit-by-bit basis.
Port 2 pins are multip lexed with pins PW8 to PW15. The bit correspond ing to a pin to be used for
PWM output should be set to 1.
For details on P2DDR, see section 8.3, Port 2.
9.2.8 Port 1 Data Register (P1DR)
Bit
Initial value
Read/Write
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
0
P10DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
P1DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when
OS = 1).
For details on P1DR, see section 8.2, Port 1.
9.2.9 Port 2 Data Register (P2DR)
Bit
Initial value
Read/Write
7
P27DR
0
R/W
6
P26DR
0
R/W
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
0
P20DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
P2DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when
OS = 1).
For details on P2DR, see section 8.3, Port 2.
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 288 of 1130
REJ09B0327-0400
9.2.10 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 8-b it PWM timer operation is halted and a transition is made to
module stop mode. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (M STP11): Specifies PWM module stop mode.
MSTPCRH
Bit 3
MSTP11 Description
0 PWM module stop mode is cleared
1 PWM module stop mode is set (Initial value)
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 289 of 1130
REJ09B0327-0400
9.3 Operation
9.3.1 Correspondence betwee n PWM Data Register Contents and Output Waveform
The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a
resolution of 1/16, as shown in table 9.4.
Table 9.4 Duty Cycle of Basic Pulse
0123456789ABC D EF0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Upper 4 Bits Basic Pulse Waveform (Internal)
.
.
.
Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 290 of 1130
REJ09B0327-0400
The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in
table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the
resolution, added before th e rising edge of a basic pulse. When the upper 4 bits of PWDR are
0000, there is no rising edge of the basic pulse, bu t the timing for adding pulses is the same.
Table 9.5 Position of Pulses Added to Basic Pulses
Basic Pulse No.
Lower 4 Bits0123456789101112131415
0000
0001 Yes
0010 Yes Yes
0011 Yes Yes Yes
0100 Yes Yes Yes Yes
0101 Yes Yes Yes Yes Yes
0110 Yes Yes Yes Yes Yes Yes
0111 Yes Yes Yes Yes Yes Yes Yes
1000 Yes Yes Yes Yes Yes Yes Yes Yes
1001 Yes Yes Yes Yes Yes Yes Yes Yes Yes
1010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
1011 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
1100 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
1101 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
1110 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Additional pulse provided
No additional pulse
Resolution width
Additional pulse
Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000)
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 291 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
10.1 Overview
This LSI have an on-chip 14-bit pulse-width modulator (PWM) with two output channels.
Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
Both channels share the same counter (DACNT) and control register (DACR).
10.1.1 Features
The features of the 14-bit PWM (D/A) are listed below.
• The pulse is subdivided into multiple base cycles to reduce ripple.
• Two resolution settings and two base cycle settings are available
The resolution can be set equal to one or two system clock cycles. The base cycle can be set
equal to T × 64 or T × 256, where T is the resolution.
• Four operating rates
The two resolution settings and two base cycle settings combine to give a selection of four
operating rates .
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 292 of 1130
REJ09B0327-0400
10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the PWM (D/A) module.
Internal clock
φ
φ/2
PWX0
PWX1
DADRA
DADRB
DACNT
DACR
Legend:
DACR: PWM D/A control register ( 6 bits)
DADRA: PWM D/A data register A (15 bits)
DADRB: PWM D/A data register B (15 bits)
DACNT: PWM D/A counter (14 bits)
Control logic
Clock selection Clock
Internal data bus
Basic cycle
compare-match A
Fine-adjustment
pulse addition A
Basic cycle
compare-match B
Fine-adjustment
pulse addition B
Basic cycle overflow
Comparator
A
Comparator
B
Bus interface
Module data bus
Figure 10.1 PWM D/A Block Diagram
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 293 of 1130
REJ09B0327-0400
10.1.3 Pin Configuration
Table 10.1 lists the pins used by the PWM (D/A) module.
Table 10.1 PWM T imer Input and Output Pins
Name Abbr. I/O Function
PWM output pin 0 PWX0 Output PWM output, channel A
PWM output pin 1 PWX1 Output PWM output, channel B
10.1.4 Register Configuration
Table 10.2 lists the registers of the PWM (D/A) module.
Table 10.2 Register Configuration
Name Abbreviation R/W Initial value Address*1
PWM D/A control registe r DACR R/W H'30 H'FFA0*2
PWM D/A data register A high DADRAH R/W H'FF H'FFA0*2
PWM D/A data register A low DADRAL R/W H'FF H'FFA1*2
PWM D/A data register B high DADRBH R/W H'FF H'FFA6*2
PWM D/A data register B low DADRBL R/W H'FF H'FFA7*2
PWM D/A counter high DACNTH R/W H'00 H'FFA6*2
PWM D/A counter low DACNTL R/W H'03 H'FFA7*2
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Registers in the 14-bit PWM timer are assigned to the same addresses as the other
registers. In this case, register selection is performed by the IICE bit in the serial timer
control register (STCR), and also the same addresses are shared by DADRAH and
DACR, and by DADRB and DACNT. Switch ing is performed by the REGS bit in DACNT
or DADRB.
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 294 of 1130
REJ09B0327-0400
10.2 Register Descriptions
10.2.1 PWM (D/A) Counter (DACNT)
15
7
0
R/W
14
6
0
R/W
13
5
0
R/W
12
4
0
R/W
11
3
0
R/W
8
0
0
R/W
10
2
0
R/W
9
1
0
R/W
Bit (CPU)
BIT (Counter)
Initial value
Read/Write
7
8
0
R/W
6
9
0
R/W
5
10
0
R/W
4
11
0
R/W
3
12
0
R/W
0
—
REGS
1
R/W
2
13
0
R/W
1
—
—
1
—
DACNTH DACNTL
DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The
input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the
DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are
performed using a tempor ary register (TEMP). See section 10.3, Bus Master Interface, fo r details.
DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with
14-bit precisio n, it uses all DACNT bits. When a channel op e r a tes with 12-bit precision, it uses the
lower 12 (counter) bits and ignores the upper two (counter) bits.
DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode, and by the PWME bit.
Bit 1 of DACNTL (CPU) is not used, and is always read as 1.
DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS Description
0 DADRA and DADRB can be access ed
1 DACR and DACNT can be accessed (Initial value)
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 295 of 1130
REJ09B0327-0400
10.2.2 D/A Data Registers A and B (DADRA and DADRB)
15
13
DA13
1
R/W
14
12
DA12
1
R/W
13
11
DA11
1
R/W
12
10
DA10
1
R/W
11
9
DA9
1
R/W
8
6
DA6
1
R/W
10
8
DA8
1
R/W
9
7
DA7
1
R/W
Bit (CPU)
Bit (Data)
DADRA
Initial value
Read/Write
7
5
DA5
1
R/W
6
4
DA4
1
R/W
5
3
DA3
1
R/W
4
2
DA2
1
R/W
3
1
DA1
1
R/W
0
—
—
1
—
2
0
DA0
1
R/W
1
—
CFS
1
R/W
DADRH DADRL
DA13
1
R/W
DA12
1
R/W
DA11
1
R/W
DA10
1
R/W
DA9
1
R/W
DA6
1
R/W
DA8
1
R/W
DA7
1
R/W
DADRB
Initial value
Read/Write
DA5
1
R/W
DA4
1
R/W
DA3
1
R/W
DA2
1
R/W
DA1
1
R/W
REGS
1
R/W
DA0
1
R/W
CFS
1
R/W
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DAD RA
corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The CPU can read
and write the PWM (D/A) data register valu es, but since DADRA and DADRB are 16-bit
registers, data transfers between them and the CPU are performed using a temporary register
(TEMP). See section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is no t u sed an d is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the stan dby modes, watch mode, sub active mode,
subsleep mode, and module stop mode.
Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an
analog value is set in the upper 14 bits of the PWM (D/A) data register.
In each base cycle, the DACNT value is continually compared with these upper 14 bits to
determine the duty cycle of the output waveform, and to decide whether to output a fine-
adjustment pulse equal in width to the resolution. To enable this operation, the data reg ister must
be set within a rang e that depends o n the carrier frequency select bit (CFS). If the DADR value is
outside this range, the PWM output is held constant.
A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and
DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data
bits correspond to the two highest counter (DACNT) bits.
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 296 of 1130
REJ09B0327-0400
Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS Description
0 Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1 Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF (Initial value)
DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS Description
0 DADRA and DADRB can be access ed
1 DACR and DACNT can be accessed (Initial value)
10.2.3 PWM D/A Control Register (DACR)
7
TEST
0
R/W
6
PWME
0
R/W
5
—
1
—
4
—
1
—
3
OEB
0
R/W
0
CKS
0
R/W
2
OEA
0
R/W
1
OS
0
R/W
Bit
Initial value
Read/Write
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Test Mode (TEST): Selects test mode, wh ich is used in testing the chip. Normally this bit
should be cleared to 0.
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 297 of 1130
REJ09B0327-0400
Bit 7
TEST Description
0 PWM (D/A) in user state: normal operation (Initial value)
1 PWM (D/A) in test state: correct conversion results unobtainable
Bit 6—PWM Enable (PWME): Starts or stops the PWM (D/A) counter (DACNT).
Bit 6
PWME Description
0 DACNT operates as a 14-bit up-counter (Initial value)
1 DACNT halts at H'0003
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Output Enable B (OEB): Enables or disables output on PWM (D/A) channel B.
Bit 3
OEB Description
0 PWM (D/A) channel B output (at the PWX1 pin) is disabled (Initial value)
1 PWM (D/A) channel B output (at the PWX1 pin) is enabled
Bit 2—Output Enable A (OEA): Enables or disables output on PWM (D/A) channel A.
Bit 2
OEA Description
0 PWM (D/A) channel A output (at the PWX0 pin) is disabled (Initial value)
1 PWM (D/A) channel A output (at the PWX0 pin) is enabled
Bit 1—Output Select (OS): Selects the phase of the PWM (D/A) output.
Bit 1
OS Description
0 Direct PWM output (Initial value)
1 Inverted PWM output
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 298 of 1130
REJ09B0327-0400
Bit 0—Clock Select (CKS): Selects the PWM (D/A) r esolution. I f the system clock (φ) frequency
is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
Bit 0
CKS Description
0 Operates at resolution (T) = system clock cycle time (tcyc) (Initial value)
1 Operates at resolution (T) = system clock cycle time (tcyc) × 2
10.2.4 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 14- bit PWM timer oper a tion is halted and a transition is made to
module stop mode. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (M STP11): Specifies PWMX module stop mode.
MSTPCRH
Bit 3
MSTP11 Description
0 PWMX module stop mode is cleared
1 PWMX module stop mode is set (Initial value)
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 299 of 1130
REJ09B0327-0400
10.3 Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written and read as follo ws (tak ing th e example of the CPU in terface).
• Write
When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written , the lower-byte write data and TEMP value ar e comb ined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte
value is transfer r e d to TEMP. Next, wh en the lo wer by te is read, the lo wer-b y te value in
TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time using an MOV instruction (by word
access or two consecutive byte accesses), and the upper byte should always be accessed before the
lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is
accessed. Also note that a bit-manipulation instruction cannot be used to access these registers.
Figure 10.2 shows the data flow for access to DACNT. The other registers are accessed similarly.
Example 1: Write to DACNT
MOV.W R0, @DACNT ; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0 ; Transfer contents of DADRA to R0
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 300 of 1130
REJ09B0327-0400
Table 10.3 Read and Write Access Methods for 16-Bit Registers
Read Write
Register Name Word Byte Word Byte
DADRA and DADRB Yes Yes Yes ×
DACNT Yes ×Yes ×
Legend:
Yes: Permitted type of ac cess. Word access includes successive byte accesses to the upper byte
(first) and lower byte (second).
×: This type of access may give incorrect results.
CPU
(H'AA)
Upper byte
Bus
interface
Module data bus
Upper-Byte Write
TEMP
(H'AA)
DACNTL
( )
DACNTH
( )
CPU
(H'57)
Lower byte
Bus
interface
Module data bus
Lower-Byte Write
TEMP
(H'AA)
DACNTL
(H'57)
DACNTH
(H'AA)
Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 301 of 1130
REJ09B0327-0400
CPU
(H'AA)
Upper byte
Bus
interface
Module data bus
Upper-Byte Read
TEMP
(H'57)
DACNTL
(H'57)
DACNTH
(H'AA)
CPU
(H'57)
Lower byte
Bus
interface
Module data bus
Lower-Byte Read
TEMP
(H'57)
DACNTL
( )
DACNTH
( )
Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT)
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 302 of 1130
REJ09B0327-0400
10.4 Operation
A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS =
0, the value in DADR correspo nds to the total width (TL) of the low (0) pulses output in one
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value co rrespo nds to th e total width (TH) of th e high (1)
output pulses. Figure 10.4 shows the types of waveform output available.
t
f
t
L
T
L
= ∑ t
Ln
(when OS = 0)
m
n = 1
1 conversion cycle
(T × 2
14
(= 16384))
Basic cycle
(T × 64 or T × 256)
T: Resolution
Legend:
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 10.3 PWM D/A Operation
Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 10.4 ind icates th e range of DADR settings that give an output
waveform like the one in figure 10.3, and lists the conversion cy cle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 303 of 1130
REJ09B0327-0400
Table 10.4 Settings and Operation (Examples when φ
φφ
φ = 10 MHz)
Fixed DADR Bits
Bit Data
CKS
Resolution
T
(µs) CFS
Base
Cycle
(µs)
Conversion
Cycle
(µs)
TL (if OS = 0)
TH (if OS = 1) Precision
(Bits) 3210
Conversion
Cycle*
(µs)
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 1638.4
12 0 0 409.6
0 6.4 1638.4
2. (Data value) × T
(DADR = H'0401 to
H'FFFD) 10 0 0 0 0 102.4
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 1638.4
12 0 0 409.6
00.1
1 25.6 1638.4
2. (Data value) × T
(DADR = H'0103 to
H'FFFF) 10 0 0 0 0 102.4
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 3276.8
12 0 0 819.2
0 12.8 3276.8
2. (Data value) × T
(DADR = H'0401 to
H'FFFD) 10 0 0 0 0 204.8
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 3276.8
12 0 0 819.2
10.2
1 51.2 3276.8
2. (Data value) × T
(DADR = H'0103 to
H'FFFF) 10 0 0 0 0 204.8
Note: *This column indicates the conversion cycle when specific DADR bits are fixed.
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 304 of 1130
REJ09B0327-0400
1. OS = 0 (DADR corresponds to TL)
a. CFS = 0 [base cycle = resolution (T) ×
××
× 64]
tL1 tL2 tL3 tL255 tL256
tf1 tf2 tf255 tf256
1 conversion cycle
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL
Figure 10.4 (1) Output Waveform
b. CFS = 1 [base cycle = resolution (T) ×
××
× 256]
tL1 tL2 tL3 tL63 tL64
tf1 tf2 tf63 tf64
1 conversion cycle
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tL1 + tL2 + tL3 + · · · + tL63 + tL64 = TL
Figure 10.4 (2) Output Waveform
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 305 of 1130
REJ09B0327-0400
2. OS = 1 (DADR corresponds to TH)
a. CFS = 0 [base cycle = resolution (T) ×
××
× 64]
t
H1
t
H2
t
H3
t
H255
t
H256
t
f1
t
f2
t
f255
t
f256
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f255
= t
f256
= T × 64
t
H1
+ t
H2
+ t
H3
+ · · · + t
H255
+ t
H256
= T
H
Figure 10.4 (3) Output Waveform
b. CFS = 1 [base cycle = resolution (T) ×
××
× 256]
t
H1
t
H2
t
H3
t
H63
t
H64
t
f1
t
f2
t
f63
t
f64
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f63
= t
f64
= T × 256
t
H1
+ t
H2
+ t
H3
+ · · · + t
H63
+ t
H64
= T
H
Figure 10.4 (4) Output Waveform
Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 306 of 1130
REJ09B0327-0400
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 307 of 1130
REJ09B0327-0400
Section 11 16-Bit Free-Running Timer
11.1 Overview
This LSI have a single-channel on-chip 16-bit free-running timer (FRT) module that uses a 16-bit
free-running counter as a time base. Applications of the FRT module include rectangular-wave
output (up to two independent waveforms), input pulse width measurement, and measurement of
external clock periods.
11.1.1 Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
The free-running counter can be driven by an internal clock source (φ/2, φ/8, or φ/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
Each comparator can generate an independent waveform.
• Four input capture channels
The current count can be captured on the risin g or falling edge (selectable) of an input
signal.
The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
Two compare-match interrupts, four input capture interrupts, and one overflow interrupt
can be requested independently.
• Special functions provided by automatic addition function
The contents of OCRAR and OCRAF can be added to the contents of OCRA
automatically, en abling a periodic waveform to be generated without software intervention.
The contents of ICRD can be added automatically to the contents of OCRDM × 2, enabling
input capture operations in this interval to be restricted.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 308 of 1130
REJ09B0327-0400
11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the free-running timer.
External
clock source Internal
clock sources
Clock select
Comparator A
OCRA (H/L)
Comparator B
OCRB (H/L)
Bus interface
Internal
data bus
φ/2
φ/8
φ/32
FTCI
Compare-
match A
Clear
Clock
FTOA
FTOB
Overflow
ICRA (H/L)
Compare-
match B
Input capture
FRC (H/L)
TCSR
FTIA
FTIB
FTIC
FTID
Control
logic
Module data bus
TIER
TCR
TOCR
Interrupt signals
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Legend:
OCRA, B:
FRC:
ICRA, B, C, D:
TCSR:
Output compare register A, B (16 bits)
Free-running counter (16 bits)
Input capture register A, B, C, D (16 bits)
Timer control/status register (8 bits)
TIER:
TCR:
TOCR:
Timer interrupt enable register (8 bits)
Timer control register (8 bits)
Timer output compare control
register (8 bits)
ICRB (H/L)
ICRC (H/L)
ICRD (H/L)
OCRA R/F (H/L)
+
+
OCRDM L
×1
×2
Comparator M
Compare-match M
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 309 of 1130
REJ09B0327-0400
11.1 .3 Input and Output Pins
Table 11.1 lists the input and output pins of the free-running timer module.
Table 11.1 Free-Running T imer Input and Output Pins
Name Abbreviation I/O Function
Counter clock input FTCI Input FRC counter clock inp ut
Output compare A FTOA Output Output compare A output
Output compare B FTOB Output Output compare B output
Input capture A FTIA Input Input cap ture A input
Input capture B FTIB Input Input cap ture B input
Input capture C FTIC Input Input capture C input
Input capture D FTID Input Input capture D input
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 310 of 1130
REJ09B0327-0400
11.1.4 Register Configuration
Table 11.2 lists the registers of the free-running timer modu le.
Table 11.2 Register Configuration
Name Abbreviation R/W Initial Value Address*1
Timer interrupt enable register TIER R/W H'01 H'FF90
Timer control/status register TCSR R/(W)*2H'00 H'FF91
Free-running counter FRC R/W H'0000 H'FF92
Output compare register A OCRA R/W H'FFFF H'FF94*3
Output compare register B OCRB R/W H'FFFF H'FF94*3
Timer control register TCR R/W H'00 H'FF96
Timer output compare control
register TOCR R/W H'00 H'FF97
Input capture register A ICRA R H'0000 H'FF98*4
Input capture register B ICRB R H'0000 H'FF9A*4
Input capture register C ICRC R H'0000 H'FF9C*4
Input capture register D ICRD R H'0000 H'FF9E
Output compare register AR OCRAR R/W H'FFFF H'FF98*4
Output compare register AF OCRAF R/W H'FFFF H'FF9A*4
Output compare register DM OCRDM R/W H'0000 H'FF9C*4
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Bits 7 to 1 are read-only; only 0 can be written to clear the flags.
Bit 0 is readable/writable.
3. OCRA and OCRB share the same address. Access is controlled by the OCRS
bit in TOCR.
4. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and
OCRDM. Access is controlled by the ICRS bit in TOCR.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 311 of 1130
REJ09B0327-0400
11.2 Register Descriptions
11.2.1 Free-Running Counter (FRC)
Bit
Initial
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
value
WriteRead/
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a
clock source. The clock source is selected by bits CKS1 and CKS0 in TCR.
FRC can also be cleared by compare-match A.
When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in TCSR is set to 1.
FRC is initialized to H'0000 by a reset and in hardware standby mode.
11.2.2 Output Compare Registers A and B (OCRA, OCRB)
Bit
Initial
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
value
WriteRead/
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the co rresponding output compare
flags (OCFA or OCFB) is set in TCSR.
In addition, if the output enable bit (OEA or OEB) in TOCR is set to 1, wh en OCR and FRC
values match, the logic level selected by the output lev el bit (OLVLA or OLVLB) in TOCR is
output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB
output leve ls ar e 0 until the first compare-match.
OCR is initialized to H'FFFF by a reset and in hardware standby mode.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 312 of 1130
REJ09B0327-0400
11.2.3 Input Capture Registers A to D (ICRA to ICRD)
Bit
Initial
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
value
WriteRead/
There are four input capture registers, A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is
detected, the current FRC value is copied to the corresponding input capture register (ICRA to
ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to
1. The input capture edge is selected by the input edge select b its (IEDGA to IEDGD) in TCR.
ICRC and ICRD c a n be u sed as ICRA a nd ICRB buffer registers, r espectively, and made to
perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR.
Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA =
1). When ICRC is used as th e ICRA buffer, both rising and falling edges can be specified as
transitions of th e external input signal by setting IEDGA ≠ IEDGC. When IEDGA = IEDGC,
either the rising or falling edge is designated. See table 11.3.
Note: T he FRC contents are tr ansferred to the in put capture register reg ardless of the value of
the input capture flag (ICF).
BUFEAIEDGA IEDGC
FTIA Edge detect and
capture signal
generating circuit
FRCICRC ICRA
Figure 11.2 Input Capt ure Buf fering (Example)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 313 of 1130
REJ09B0327-0400
Table 11.3 Buffered Input Capture Edge Selection (Example)
IEDGA IEDGC Description
0 0 Captured on falling edge of input capture A (FTIA) (Initial value)
1 Captured on both rising and falling edges of inpu t capture A (FTIA)
10
1 Captured on rising edge of input capture A (FTIA)
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
periods (1.5φ). When triggering is enabled on both edges, the input capture pulse width should be
at least 2.5 system clock periods (2.5φ).
ICR is initialized to H'0000 by a reset and in hardware standby mode.
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF)
Bit
Initial
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
value
WriteRead/
OCRAR and OCRAF are 16-bit readable/writable registers.
When the OCRAMS bit in TOCR is set to 1 , the operation of OCRA is changed to in clude the use
of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added
alternately to OCRA, an d the result is written to OCRA. The write op eration is perfor med on the
occurren ce of comp ar e-match A. In the first compare-match A after the OCRAMS bit is set to 1,
OCRAF is added.
The operation due to compare-match A varies according to whether the compare-match follows
addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output
on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A
following addition of OCRAR.
When the OCRA automatically addition func tion is u sed , do not set internal clock φ/2 as the FRC
counter input clock together with an OCRAR (or OCRAF) value of H'0001 or less.
OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 314 of 1130
REJ09B0327-0400
11.2.5 Output Compare Register DM (OCRDM)
Bit
Initial
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
value
WriteRead/
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
When the ICRDMS bit in TOCR is set to 1 and th e contents of OCRDM are other th an H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is add ed to
the contents o f ICRD, and the result is com pared with the FRC value. The point at which the
values match is taken as the end of the mask in terval. New in put capture D events are disabled
during the mask interval.
A mask interv al is not generated wh en the ICRDMS bit is set to 1 and the contents of OCRDM are
H'0000.
OCRDM is initialized to H'0000 by a reset and in hardware standby mode.
11.2.6 Timer Interrupt Enable Register (TIER)
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
R/W
TIER is an 8-bit readable/writable register th at enables and disables interr upts.
TIER is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture
interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 315 of 1130
REJ09B0327-0400
Bit 7
ICIAE Description
0 Input capture interrupt request A (ICIA) is disabled (Initial value)
1 Input capture interrupt request A (ICIA) is enabled
Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to r e quest input captu r e
interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE Description
0 Input capture interrupt request B (ICIB) is disabled (Initial value)
1 Input capture interrupt request B (ICIB) is enabled
Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture
interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE Description
0 Input capture interrupt request C (ICIC) is disabled (Initial value)
1 Input capture interrupt request C (ICIC) is enabled
Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture
interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE Description
0 Input capture interrupt request D (ICID) is disabled (Initial value)
1 Input capture interrupt request D (ICID) is enabled
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled (Initial value)
1 Output compare interrupt request A (OCIA) is enabled
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 316 of 1130
REJ09B0327-0400
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE Description
0 Output compare interrupt request B (OCIB) is disabled (Initial value)
1 Output compare interrupt request B (OCIB) is enabled
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running
timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled (Initial value)
1 Timer overflow interrupt request (FOVI) is enabled
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
11.2.7 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
4
ICFD
0
3
OCFA
0
0
CCLRA
0
R/W
2
OCFB
0
R/(W)*
1
OVF
0
R/(W)*
R/(W)*
R/(W)*R/(W)*
Note: * Only 0 can be written in bits 7 to 1 to clear these flags.
TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals.
TCSR is initialized to H'00 by a reset and in hardware standby mode.
Timing is described in section 11.3, Operation.
Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that
the old ICRA value has been moved into ICRC and the new FRC value has been transferred to
ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 317 of 1130
REJ09B0327-0400
Bit 7
ICFA Description
0 [Clearing condition]
Read ICFA when ICFA = 1, then write 0 in ICFA (Initial value)
1 [Setting condition]
When an input capture signal causes the FRC value to be transferred to
ICRA
Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been
transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that
the old ICRB value has been mo ved into ICRD and the new FRC va lue has been transfer red to
ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB Description
0 [Clearing condition]
Read ICFB when ICFB = 1, then write 0 in ICFB (Initial value)
1 [Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRB
Bit 5—Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been
transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the
signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is
not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an extern al interrupt
signal (by setting the ICICE bit to 1).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC Description
0 [Clearing condition]
Read ICFC when ICFC = 1, then write 0 in ICFC (Initial value)
1 [Setting condition]
When an input capture signal is receiv ed
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 318 of 1130
REJ09B0327-0400
Bit 4—Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been
transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of the
signal transition in FTID (input capture signal) specified by th e IEDGD bit, ICFD is set but da ta is
not transferred to ICRD. Therefore, in buffer operation, ICFD can be used as an external interrupt
by setting the ICIDE bit to 1.
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4
ICFD Description
0 [Clearing condition]
Read ICFD when ICFD = 1, then write 0 in ICFD (Initial value)
1 [Setting condition]
When an input capture signal is receiv ed
Bit 3—Output Compare Flag A (OCFA): This status flag indicates that the FRC value matches
the OCRA value. This flag must be cleared by software. It is set by hardware, however, and
cannot be set by software.
Bit 3
OCFA Description
0 [Clearing condition]
Read OCFA when OCFA = 1, then write 0 in OCFA (Initial value)
1 [Setting condition]
When FRC = OCRA
Bit 2—Output Compare Flag B (OCFB): This status flag indicates that the FRC value matches
the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot
be set by software.
Bit 2
OCFB Description
0 [Clearing condition]
Read OCFB when OCFB = 1, then write 0 in OCFB (Initial value)
1 [Setting condition]
When FRC = OCRB
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 319 of 1130
REJ09B0327-0400
Bit 1—Timer Overflow Flag (OVF): Th is status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF Description
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF (Initi al val ue)
1 [Setting condition]
When FRC changes from H'FFFF to H'0000
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-
match A (when the FRC and OCRA values match).
Bit 0
CCLRA Description
0 FRC clearing is disabled (Initial value)
1 FRC is cleared at compare-match A
11.2.8 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
TCR is an 8-bit readable/writable reg ister that selects the rising o r falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 320 of 1130
REJ09B0327-0400
Bit 7
IEDGA Description
0 Capture on the falling edge of FTIA (Initial value)
1 Capture on the rising edge of FTIA
Bit 6—Input Edge Select B (IEDGB): Selects the r isin g or falling edge of the input capture B
signal (FTIB).
Bit 6
IEDGB Description
0 Capture on the falling edge of FTIB (Initial value)
1 Capture on the rising edge of FTIB
Bit 5—Input Edge Se lect C (IEDGC) : Selects the rising or falling edge of the input capture C
signal (FTIC).
Bit 5
IEDGC Description
0 Capture on the falling edge of FTIC (Initial value)
1 Capture on the rising edge of FTIC
Bit 4—Input Edge Se lect D (IEDGD) : Selects the rising or falling edge of the input capture D
signal (FTID).
Bit 4
IEDGD Description
0 Capture on the falling edge of FTID (Initial value)
1 Capture on the rising edge of FTID
Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for
ICRA.
Bit 3
BUFEA Description
0 ICRC is not used as a buffer register for input capture A (Initial value)
1 ICRC is used as a buffer register for input capture A
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 321 of 1130
REJ09B0327-0400
Bit 2—Buf fer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for
ICRB.
Bit 2
BUFEB Description
0 ICRD is not used as a buffer register for input capture B (Initial value)
1 ICRD is used as a buffer register for input capture B
Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal
clock sources for the FRC. External clock pulses are coun ted on the rising edge of signals input to
the external clock input pin (FTCI).
Bit 1 Bit 0
CKS1 CKS0 Description
00 φ/2 internal clock source (Initial value)
1φ/8 internal clock source
10 φ/32 internal clo ck sour ce
1 External clock source (rising edg e)
11.2.9 Timer Output Compare Control Register (TOCR)
Bit
Initial value
Read/Write
7
ICRDMS
0
R/W
6
OCRAMS
0
R/W
5
ICRS
0
R/W
4
OCRS
0
3
OEA
0
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
R/W R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, switches access between output compare registers A and B, controls the
ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C.
TOCR is initialized to H'0 0 by a reset and in hard ware standby mode.
Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal
operating mode or in the operating mode using OCRDM.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 322 of 1130
REJ09B0327-0400
Bit 7
ICRDMS Description
0 The normal operating mode is specified for ICRD (Initial value)
1 The operating mode using OCRDM is specified for ICRD
Bit 6—Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the
normal operating mode or in the operating mode using OCRAR and OCRAF.
Bit 6
OCRAMS Description
0 The normal operating mode is specified for OCRA (Initial value)
1 The operating mode us ing OCRAR and OCRAF is specified for OCRA
Bit 5—Input Capture Register Select (ICRS): The same addresses are shared by ICRA and
OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which
registers are selected wh en the shared addresses ar e r ead or wr itten to. The operation of ICRA,
ICRB, and ICRC is not affected.
Bit 5
ICRS Description
0 The ICRA, ICRB, and ICRC registers are selected (Initial value)
1 The OCRAR, OCRAF, and OCRDM registers are selected
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4
OCRS Description
0 The OCRA register is se lec ted (Initial value)
1 The OCRB register is selected
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 323 of 1130
REJ09B0327-0400
Bit 3—Output Enable A (OEA): Enables or disables output of the output compare A signal
(FTOA).
Bit 3
OEA Description
0 Output compare A output is disabled (Initial value)
1 Output compare A output is enabled
Bit 2—Output Enable B (OEB): Enables or disables output of the output compare B signal
(FTOB).
Bit 2
OEB Description
0 Output compare B output is disabled (Initial value)
1 Output compare B output is enabled
Bit 1—O u tput Leve l A (OLV LA ): Selects the logic level to be o u tput at the FTOA pin in
response to compare-match A (signal indicating a match between the FRC and OCRA values).
When the OCRAMS bit is 1, this bit is ignored.
Bit 1
OLVLA Description
0 0 output at compare-match A (Initial value)
1 1 output at compare-match A
Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in
response to compare-match B (signal indicating a match between the FRC and OCRB values).
Bit 0
OLVLB Description
0 0 output at compare-match B (Initial value)
1 1 output at compare-match B
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 324 of 1130
REJ09B0327-0400
11.2.10 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and
module stop mode is entered. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (M STP13): Specifies the FRT module stop mode.
Bit 5
MSTPCRH Description
0 FRT module stop mode is cleared
1 FRT module stop mode is set (Initial value)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 325 of 1130
REJ09B0327-0400
11.3 Operation
11.3.1 FRC Increment Timing
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
Internal Clock
Any of three internal clocks (φ/2, φ/8, or φ/32) created by division of the system clock (φ) can be
selected by making the appropriate setting in bits CKS1 and CKS0 in TCR. Figure 11.3 shows the
increment timing.
N – 1
FRC input
clock
φ
FRC
Internal
clock
N N + 1
Figure 11.3 Increment Timing with Internal Clock Source
External Clock
If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC increments on the rising
edge of the external clock signal.
The pulse width of the external clock signal must be at least 1.5 system clock (φ) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 11.4 shows the increment timing.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 326 of 1130
REJ09B0327-0400
N + 1N
FRC input
clock
φ
FRC
External
clock input pin
Figure 11.4 Increment Timing with External Clock Source
11.3.2 Output Compare Output Tim ing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or
OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the
timing of this operation for compar e-match A.
N + 1NN + 1N
N
OCRA
φ
Compare-match A
signal
FRC
OLVLA
Output compare A
output pin FTOA
Clear*
Note: * Vertical arrows ( ) indicate instructions executed by software.
N
Figure 11.5 Timing of Output Compare A Output
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 327 of 1130
REJ09B0327-0400
11.3.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
N H'0000
FRC
φ
Compare-match A
signal
Figure 11.6 Clearing of FRC by Compare-Match A
11.3.4 Input Capture Input Timing
Input Capture Input Timing
An internal in put capture signal is gen e r a ted from the rising or fallin g edge of the signal at the
input capture pin, as selected by the co rresponding IEDGx (x = A to D) bit in TCR. Figure 11.7
shows the usual input capture timing when the rising edge is selected (IEDGx = 1).
Input capture
signal
φ
Input capture
input pin
Figure 11.7 Input Capture Signal Timing (Usual Case)
If the upper byte of ICRA/B/C/D is being read when the co rresponding input capture signal
arrives, the internal input capture signal is delayed by one system clock (φ) period. Figure 11.8
shows the tim ing for this case.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 328 of 1130
REJ09B0327-0400
Input capture
signal
φ
Input capture
input pin
T1T2
ICRA/B/C/D read cycle
Figure 11.8 Input Capture Signal Timing (In put Capture Input when ICRA/B/C/D Is Read)
Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB.
Figure 11.9 shows how input capture operates when ICRA and ICRC are use d in bu ffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
n n + 1 N N + 1
MnnN
mM Mn
φ
FTIA
Input capture
signal
FRC
ICRA
ICRC
Figure 11.9 Buffered Input Capture Timing (Usual Case)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 329 of 1130
REJ09B0327-0400
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICIEC bit is set, an interrupt will be requested. The FRC va lue will not be transferred to
ICRC, however.
In buffered input capture, if the upper byte of either of the two registers to which data will be
transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,
input capture is delayed by one system clock (φ) period. Figure 11.10 shows the timing when
BUFEA = 1.
Input capture
signal
φ
FTIA
T
1
T
2
Read cycle:
CPU reads ICRA or ICRC
Figure 11.10 Buffered Input Capture Timing
(Input Capture Input whe n ICRA or ICRC Is Read)
11.3.5 Timing of Input Capture Flag ( ICF) Setting
The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure
11.11 shows the timing of this operation.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 330 of 1130
REJ09B0327-0400
ICFA/B/C/D
φ
FRC
Input capture
signal
N
NICRA/B/C/D
Figure 11.11 Setting of Input Capt ure Flag (ICFA/B/C/D)
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the
FRC value m a tches the OCRA or OCR B v alue. This compare-match signal is g e nerated at the last
state in which the two values match , just be f ore FRC increments to a n e w value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the n ext period of the clock source. Figure 11.12 show s the timing of the setting of OCFA
and OCFB.
OCRA or OCRB
φ
Compare-match
signal
FRC N N + 1
N
OCFA or OCFB
Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 331 of 1130
REJ09B0327-0400
11.3.7 Setting of FRC Overflow Flag (OVF)
The FRC ove rflow flag (OVF) is set to 1 wh en FRC o verflows ( c hanges fro m H'FFFF to H'0000) .
Figure 11.13 shows the timing of this operation.
H'FFFF H'0000
Overflow signal
φ
FRC
OVF
Figure 11.13 Setting of Overflow Flag (OVF)
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF
When the OCRAMS bit in TOCR is set to 1, the conten ts of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. The OCRA write timing is shown in figure 11.14.
OCRAR, F
OCRA
FRC
φ
A
N N+A
Compare-match
signal
N N+1
Figure 11.14 OCRA Automatic Additio n Timing
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 332 of 1130
REJ09B0327-0400
11.3.9 ICRD and OCRDM Mask Signal Genera tion
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture function is generated.
The mask sig nal is set by the inpu t capture signal. The mask signal setting tim ing is shown in
figure 11.15.
The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and
an FRC compare-match. The mask signal clearing timing is shown in figure 11.16.
Input capture
mask signal
φ
Input capture
signal
Figure 11. 15 Input Capture Mask Signal Setting Timing
Compare-match
signal
ICRD +
OCRDM × 2
FRC
φ
N
Input capture
mask signal
N N+1
Figure 11.16 Input Capture Mask Signal Clearing Timing
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 333 of 1130
REJ09B0327-0400
11.4 Interrupts
The free-running tim er can request seven interrup ts ( th ree types): input capture A to D (I CIA,
ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 11.4 lists information about these interrupts.
Table 11.4 Free-Running Timer Interrupts
Interrupt Description DTC Activation Priority
ICIA Requested by ICFA Possible High
ICIB Requested by ICFB Possible
ICIC Requested by ICFC Not possible
ICID Requested by ICFD Not possible
OCIA Requested by OCFA Possible
OCIB Requested by OCFB Possible
FOVI Requested by OVF Not possible Low
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 334 of 1130
REJ09B0327-0400
11.5 Sample Application
In the example below, the free-running timer is used to generate pulse outputs with a 50% duty
cycle and arbitrary phase relationship. The programming is as follows:
• The CCLRA bit in TCS R is set to 1.
• Each time a compare-match interrupt occurs, software inverts the co rresponding output level
bit in TOCR (OLVLA or OLVLB).
FRC
Counter clear
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 11.17 Pulse Output (Example)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 335 of 1130
REJ09B0327-0400
11.6 Usage Notes
Application programmers should note that the following types of contention can occur in the free-
running timer.
Contention between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed.
Figure 11.18 shows this type of contention.
T1T2
FRC write cycle
Address FRC address
Internal write
signal
φ
Counter clear
signal
FRC N H'0000
Figure 11.18 FRC Write-Clear Contention
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 336 of 1130
REJ09B0327-0400
Contention between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented.
Figure 11.19 shows this type of contention.
T1T2
FRC write cycle
Address
Internal write signal
φ
FRC input clock
FRC N M
Write data
FRC address
Figure 11.19 FRC Write-Increment Contention
Contention between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is inhibited.
Figure 11.20 shows this type of contention.
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 337 of 1130
REJ09B0327-0400
If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in
the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority an d the compare-match signal is inh ibited. Consequently, th e r e sult of
the automatic addition is not written to OCRA.
Figure 11.21 shows this type of contention.
T
1
T
2
OCRA or OCRB write cycle
Address
Internal write signal
φ
FRC
OCR N M
Write data
OCR address
N N + 1
Compare-match
signal Inhibited
Figure 11.20 Contention between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 338 of 1130
REJ09B0327-0400
Address
Internal write signal
φ
OCRAR (OCRAF)
FRC
OCRA N
The compare-match signal is inhibited and
automatic addition does not occur.
OCRAR(OCRAF) address
Old data New data
N N + 1
Compare-match
signal Inhibited
Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Not Used)
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 339 of 1130
REJ09B0327-0400
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may cause FRC to increment. This depends on
the time at which th e clock select bits (CKS1 and CKS0) are rewritten, as sh own in table 11.5.
When an inter nal clock is used, the FRC clock is generated on detection of the falling edge of th e
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 11.5, the changeover is regar ded as a falling
edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock can also cause FRC to increment.
Table 11.5 Switching of Internal Clock and FRC Operation
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits FRC Operation
1 Switching from
low to low
N + 1
Clock before
switchover
Clock after
switchover
FRC clock
FRC
CKS bit rewrite
N
2 Switching from
low to high
N + 1 N + 2
Clock before
switchover
Clock after
switchover
FRC clock
FRC
CKS bit rewrite
N
Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 340 of 1130
REJ09B0327-0400
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits FRC Operation
3 Switching from
high to low
N + 1NN + 2
*
Clock before
switchover
Clock after
switchover
FRC clock
FRC
CKS bit rewrite
4 Switching from
high to high
N + 1 N + 2N
Clock before
switchover
Clock after
switchover
FRC clock
CKS bit rewrite
FRC
Note: *Generated on the assumption that the switchover is a falling edge; FRC is incremented.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 341 of 1130
REJ09B0327-0400
Section 12 8-Bit Timers
12.1 Overview
This LSI include an 8-bit timer module with two channels (T MR0 and TMR1). Each channel h a s
an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are
constantly compared with the TCNT value to detect compare-matches. The 8-bit timer module can
be used as a multifunction timer in a variety of applications, such as generation of a rectangular-
wave output with an arbitrary duty cycle.
The H8S/2148 Group also has two similar 8-bit timer channels (TMRX and TMRY), and the
H8S/2144 Group and H8S/2147N has one (TMRY). These channels can be used in a connected
configuration using the timer connection function. TMRX and TMRY have greater input/output
and interrupt function related restrictions than TMR0 and TMR1.
12.1.1 Features
• Selection of clock sources
TMR0, TMR1: The counter input clock can be selected from six internal clocks and an
external clock (enabling use as an external event counter).
TMRX, TMRY: The counter input clock can be selected from three internal clocks and an
external clock (enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two compare-match signals
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of
pulse output or PWM output with an arbitrary duty cycle.
(Note: TMRY does not have a timer output pin.)
• Cascading of the two channels (TMR0, TMR1)
Operation as a 16-bit timer can be performed using channel 0 as the upper half and channel
1 as the lower half (16-bit count mode).
Channel 1 can be used to count channel 0 compare-match occurrences (compare-match
count mode).
• Multiple interru pt sources for each channel
TMR0, TMR1, TMRY: Two compare-match interrupts and one overflow interrupt can be
requested independently.
TMRX: One input capture source is available.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 342 of 1130
REJ09B0327-0400
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1).
TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input
capture function. For details, see section 13, Timer Connection.
External clock
sources Internal clock
sources TMR0
φ/8, φ/2
φ/64, φ/32
φ/1024, φ/256
Clock 1
Clock 0
Compare-match A1
Compare-match A0
Clear 1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
TMO0
TMRI0
Internal bus
TCORA0
Comparator A0
Comparator B0
TCORB0
TCSR0
TCR0
TCORA1
Comparator A1
TCNT1
Comparator B1
TCORB1
TCSR1
TCR1
TMCI0
TMCI1
TCNT0
Overflow 1
Overflow 0
Compare-match B1
Compare-match B0
TMO1
TMRI1
Clock select
Control logic
Clear 0
TMR1
φ/8, φ/2
φ/64, φ/128
φ/1024, φ/2048
TMRX
φ
φ/2
φ/4
TMRY
φ/4
φ/256
φ/2048
Figure 12.1 Block Diagram of 8-Bit Timer Module
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 343 of 1130
REJ09B0327-0400
12.1.3 Pin Configuration
Table 12.1 summarizes the input and output pins of the 8-bit timer module.
Table 12.1 8- Bit Timer Input and Out put Pins
Channel Name Symbol*I/O Function
0 Timer output TMO0 Output Output controlled by compare-match
Timer clock input TMCI0 Input Extern al clock input for the counter
Timer reset input TMRI0 Input External reset input for the counter
1 Timer output TMO1 Output Output controlled by compare-match
Timer clock input TMCI1 Input Extern al clock input for the counter
Timer reset input TMRI1 Input External reset input for the counter
X Timer output TMOX Output Output controlled by compare-match
Timer clock/
reset input HFBACKI/TMIX
(TMCIX/TMRIX) Input External clock/reset input for the
counter
Y Timer clock/reset
input VSYNCI/TMIY
(TMCIY/TMRIY) Input External clock/reset input for the
counter
Note: *The abbreviations TMO, TMCI, and TMRI are used in the text, omitting the channel
number.
Channel X and Y I/O pins have the same internal configuration as channels 0 and 1,
and therefore the same abbreviations are used.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 344 of 1130
REJ09B0327-0400
12.1.4 Register Configuration
Table 12.2 summarizes the registers of the 8- bit timer module.
Table 12.2 8-Bit Timer Registers
Channel Name Abbreviation*3R/W Initial value Address*1
0 T imer control register 0 TCR0 R/W H'00 H'FFC8
Timer control/status register 0 TCSR0 R/(W)*2H'00 H'FFCA
Time constant register A0 TCORA0 R/W H'FF H'FFCC
Time constant register B0 TCORB0 R/W H'FF H'FFCE
Time counter 0 TCNT0 R/W H'00 H'FFD0
1 T imer control register 1 TCR1 R/W H'00 H'FFC9
Timer control/status register 1 TCSR1 R/(W)*2H'10 H'FFCB
Time constant register A1 TCORA1 R/W H'FF H'FFCD
Time constant register B1 TCORB1 R/W H'FF H'FFCF
Timer counter 1 TCNT1 R/W H'00 H'FFD1
Common Serial/timer control register STCR R/W H'00 H'FFC3
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Timer connection register S TCONRS R/W H'00 H'FFFE
X Timer control register X TCRX R/W H'00 H'FFF0
Timer control/status register X TCSRX R/(W)*2H'00 H'FFF1
Time constant register AX TCORAX R/W H'FF H'FFF6
Time constant register BX TCORBX R/W H'FF H'FFF7
Timer counter X TCNTX R/W H'00 H'FFF4
Time constant register C TCORC R/W H'FF H'FFF5
Input capture register R TICRR R H'00 H'FFF2
Input capture regi ster F TICRF R H'00 H'FFF3
Y Timer control register Y TCRY R/W H'00 H'FFF0
Timer control/status register Y TCSRY R/(W)*2H'00 H'FFF1
Time constant register AY TCORAY R/W H'FF H'FFF2
Time constant register BY TCORBY R/W H'FF H'FFF3
Timer counter Y TCNTY R/W H'00 H'FFF4
Timer input select register TISR R/W H'FE H'FFF5
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bits 7 to 5, to clear these flags.
3. The abbreviations TCR, TCSR, TCORA, TCORB, and TCNT are used in the text,
omitting the channel designation (0, 1, X, or Y).
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 345 of 1130
REJ09B0327-0400
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits
for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access.
(Access is not divided into two 8-bit accesses.)
In the H8S/2148 Group, certain of the channel X and channel Y registers are assigned to the same
address. The TMRX/Y bit in TCONRS determines which register is accessed.
12.2 Register Descriptions
12.2.1 Timer Counter (TCNT)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
TCNTX,TCNTY
Bit
Initial value
Read/Write
15
0
R/W
Bit
Initial value
Read/Write
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
TCNT0 TCNT1
Each TCNT is an 8-bit readable/writable up-counter.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word
access.
TCNT increments on pulses generated from an internal or external clock source. This clock source
is selected by cloc k select bits CKS2 to CKS0 in TCR.
TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits
CCLR1 and CCLR0 in TCR select the method of clearing.
When TCNT ove r flows from H'FF to H'0 0, the overflow flag (OVF) in TCSR is set to 1.
The timer counters are initialized to H'00 by a reset and in hardware standby mode.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 346 of 1130
REJ09B0327-0400
12.2.2 Time Constant Register A (TCORA)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
TCORAX, TCORAY
Bit
Initial value
Read/Write
15
1
R/W
Bit
Initial value
Read/Write
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORA0 TCORA1
TCORA is an 8-bit readable/writable register.
TCORA0 and TCORA1 comprise a single 16-bit register, so they can be accessed together by
word access.
TCORA is continu a lly compared with the value in TCNT. When a match is detected, th e
corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, th at comparison is
disabled during the T2 state of a TCORA write cycle.
The timer output can be freely controlled by these compare-match signals and the settings of
output select bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF by a reset and in hardware standby mode.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 347 of 1130
REJ09B0327-0400
12.2.3 Time Constant Register B (TCORB)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
TCORBX, TCORBY
Bit
Initial value
Read/Write
15
1
R/W
Bit
Initial value
Read/Write
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORB0 TCORB1
TCORB is an 8-bit readable/writable register. TCORB0 and TCORB1 comprise a single 16-bit
register, so they can be accessed together by word access.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is
disabled during the T2 state of a TCORB write cycle.
The timer output can be freely controlled by these compare-match signals and the settings of
output select bits OS3 and OS2 in TCSR.
TCORB is initia lized to H'FF by a re set and in hardware standby mode.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 348 of 1130
REJ09B0327-0400
12.2.4 Timer Control Register (TCR)
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
TCR is an 8-bit readable/writable register that selects the clock source and the time at which
TCNT is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in hardware standby mode.
For details of the timing, see section 1 2.3, Operation.
Bit 7—Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt
request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value.
Bit 7
CMIEB Description
0 CMFB interrupt request (CMIB) is disabled (Initial value)
1 CMFB interrupt request (CMIB) is enabled
Bit 6—Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt
request (CMIA) is enabled or disabled wh en th e CMFA f lag in TCSR is set to 1.
Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value.
Bit 6
CMIEA Description
0 CMFA interrupt request (CMIA) is disabled (Initial value)
1 CMFA interrupt request (CMIA) is enabled
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 349 of 1130
REJ09B0327-0400
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request
(OVI) is enabled or disabled when the OVF flag in TCSR is set to 1.
Note that an OVI interrupt is not requested by TMRX, reg a r dless of the OVIE value.
Bit 5
OVIE Description
0 OVF interrupt request (OVI) is disabled (Initial value)
1 OVF interrupt request (OVI) is enabled
Bits 4 and 3—Counter Clear 1 a nd 0 (CCLR1, CCLR0): These bits select the method by which
the timer counter is cleared: by compare-match A or B, or by an external reset input.
Bit 4 Bit 3
CCLR1 CCLR0 Description
0 0 Clearing is disabled (Initial value)
1 Cleared on compare-match A
1 0 Cleared on compare-match B
1 Cleared on rising edge of external reset input
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 350 of 1130
REJ09B0327-0400
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
The input clock can be selected from either six or three clocks, all divided from the system clock
(φ). The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1, because of the cascading function.
TCR STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 0 — — Clock input disabled (Initial value)
001—0 φ/8 internal clock source, counted on the falling edge
001—1 φ/2 internal clock source, counted on the falling edge
010—0 φ/64 internal clock source, counted on the falling
edge
010—1 φ/32 internal clock source, counted on the falling
edge
011—0 φ/1024 internal clock source, counted on the falling
edge
011—1 φ/256 internal clock source, counted on the falling
edge
1 0 0 — — Counted on TCNT1 ov erflow signal*
1 0 0 0 — — Clock input disabled (Initial value)
0010 —φ/8 internal clock source, counted on the falling edge
0011 —φ/2 internal clock source, counted on the falling edge
0100 —φ/64 internal clock source, counted on the falling
edge
0101 —φ/128 internal clock source, counted on the falling
edge
0110 —φ/1024 internal clock source, counted on the falling
edge
0111 —φ/2048 internal clock source, counted on the falling
edge
1 0 0 — — Counted on TCNT0 compare-match A*
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 351 of 1130
REJ09B0327-0400
TCR STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
X 0 0 0 — — Clock input disabled (Initial value)
0 0 1 — — Counted on φ internal clock source
010——φ/2 internal clock source, counted on the falling edge
011——φ/4 internal clock source, counted on the falling edge
1 0 0 — — Clock input disabled
Y 0 0 0 — — Clock input disabled (Initial value)
001——φ/4 internal clock source, counted on the falling edge
010——φ/256 internal clock source, counted on the falling
edge
011——φ/2048 internal clock source, counted on the falling
edge
1 0 0 — — Clock input disabled
Common 1 0 1 — — External clock source, counted at rising edge
1 1 0 — — External clock source, counted at falling edge
1 1 1 — — External clock source, counted at both rising and
falling edges
Note: *If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare-match signal, no incrementing clock will be generated. Do not use this
setting.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 352 of 1130
REJ09B0327-0400
12.2.5 Timer Control/Status Register (TCSR)
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ICIE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
Note: * Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags.
TCSRY
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ICF
0
R/(W)*
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSRX
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSR1
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSR0
TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture
status in TMRX only), and controls compare-match output.
TCSR0, TCSRX, and TCSRY are initialized to H'0 0, and TCSR1 is initialized to H'10, by a reset
and in hardware standby mode.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 353 of 1130
REJ09B0327-0400
Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and
TCORB match.
Bit 7
CMFB Description
0 [Clearing conditions ]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
(Initial value)
1 [Setting condition]
When TCNT = TCORB
Bit 6—Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and
TCORA match.
Bit 6
CMFA Description
0 [Clearing conditions ]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
(Initial value)
1 [Setting condition]
When TCNT = TCORA
Bit 5 —Timer Overflow Flag (OVF): Status flag indicating that TCNT has ov erflowed (changed
from H'FF to H'00).
Bit 5
OVF Description
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF (Initi al val ue)
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 354 of 1130
REJ09B0327-0400
TCSR0
Bit 4—A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests by
compare-match A.
Bit 4
ADTE Description
0 A/D converter start requests by compare-match A are disabled (Initial value)
1 A/D converter start requests by compare-match A are enabled
TCSR1
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
TCSRX
Bit 4—Input Capture Flag (ICF): Status flag that indicates detection of a rising edge followed
by a falling edge in the external reset signal af ter the ICST bit in TCONRI has been set to 1.
Bit 4
ICF Description
0 [Clearing condition]
Read ICF when ICF = 1, then write 0 in ICF (Initial val ue)
1 [Setting condition]
When a rising edge followed by a falling edge is detected in the external reset signal
after the ICST bit in TCONRI has been set to 1
TCSRY
Bit 4—Input Capture Interrupt Enable (ICIE): Selects enabling or disabling of th e interrupt
request by ICF (ICIX) when the ICF bit in TCSRX is set to 1.
Bit 4
ICIE Description
0 Interrupt request by ICF (ICIX) is disabled (Initial value)
1 Interrupt request by ICF (ICIX) is enabled
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 355 of 1130
REJ09B0327-0400
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is
to be changed by a compare-match of TCOR and TCNT.
OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the
effect of compare-match A on the output level, and both of them can be controlled independently.
Note, however, that pr iorities are set such that: trigg er output > 1 outp ut > 0 output. If compare-
matches occur simultaneously, the output changes according to the co mpare-match with the higher
priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer outp ut is 0 until the first compare-m atch occurs.
Bit 3 Bit 2
OS3 OS2 Description
0 0 No change when compare-match B occurs (Initial value)
1 0 is output when compare-match B occurs
1 0 1 is output when compare-match B occurs
1 Output is inverted when compare-match B occurs (toggle output)
Bit 1 Bit 0
OS1 OS0 Description
0 0 No change when compare-match A occurs (Initial value)
1 0 is output when compare-match A occurs
1 0 1 is output when compare-match A occurs
1 Output is inverted when compare-match A occurs (toggle output)
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 356 of 1130
REJ09B0327-0400
12.2.6 Serial/Timer Control Register (STCR)
7
IICS
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
Bit
Initial value
Read/Write
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and
also selects the TCNT input clock.
For details on functions not related to the 8-bit timers, see section 3.2.4, Serial Timer Control
Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is
not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mod e .
Bits 7 to 4—I2C Control (IICS, IICX1, IICX0 , IICE): These bits con tr ol the bus buffer f unction
of port A and the operation of the I2C bus interface when the IIC option is included on-chip. See
section 16.2.7, Serial/Timer Control Register (STCR), for details.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting modu le
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details..
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits
CKS2 to CKS0 in TCR, select the clock to b e input to TCNT. For details, see section 1 2.2.4,
Timer Control Register (TCR).
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 357 of 1130
REJ09B0327-0400
12.2.7 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
Only bit 1 is described here. For de tails on functions not related to the 8-bit timers, see section s
3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data
registers and control registers, and timer connection control registers.
Bit 1
HIE Description
0 CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is enabled (Initial value)
1 CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is disabled
12.2.8 Timer Connection Register S (TCONRS)
7
TMRX/Y
0
R/W
6
ISGENE
0
R/W
5
HOMOD1
0
R/W
4
HOMOD0
0
R/W
3
VOMOD1
0
R/W
0
CLMOD0
0
R/W
2
VOMOD0
0
R/W
1
CLMOD1
0
R/W
Bit
Initial value
Read/Write
TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY
registers and timer connection operation.
TCONRS is initia lized to H'00 by a reset an d in hardware standby mode.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 358 of 1130
REJ09B0327-0400
Bit 7—TMRX/TMRY Access Select (T MRX/Y): The TMRX and TMRY registers can only be
accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2148 Group, some of the TMRX
registers and the TMRY reg isters are assigned to th e sam e m emory space addresses (H'FFF0 to
H'FFF5), and the TMRX/Y b it determines which registers are accessed. In the H8S/2144 Group
and H8S/2147N, there is no control of TMRY register access by this bit.
Bit 7 Accessible Registers
TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7
0
(Initial value) TMRX
TCRX TMRX
TCSRX TMRX
TICRR TMRX
TICRF TMRX
TCNTX TMRX
TCORC TMRX
TCORAX TMRX
TCORBX
1TMRY
TCRY TMRY
TCSRY TMRY
TCORAY TMRY
TCORBY TMRY
TCNTY TMRY
TISR
12.2.9 Input Capture Regi ster (TICR) [TMRX Additional Functio n]
7
0
—
6
0
—
5
0
—
4
0
—
3
0
—
0
0
—
2
0
—
1
0
—
Bit
Initial value
Read/Write
TICR is an 8-b it in ternal register to wh ich th e conten ts of TCNT are transferred on the falling edge
of external reset input. The CPU cannot read or write to TICR directly.
The TICR function is used in timer connection. For details, see section 13, Timer Connection.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 359 of 1130
REJ09B0327-0400
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
TCORC is an 8-bit readable/writable register. Th e sum of the contents of TCORC and TICR is
continually compared with the valu e in TCNT. When a match is detected, a compare-match C
signal is generated. Note, however, that comparison is disabled during the T2 state of a TCORC
write cycle and a TICR input capture cycle.
TCORC is initia lized to H'FF by a re set and in hardware standby mode.
The TCORC function is used in timer connection. For details, see section 13, Timer Connection.
12.2.11 Input Capture Regi st ers R and F (TICRR, TICRF) [TMRX Additional Fu nct ions]
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Initial value
Read/Write
TICRR and TICRF are 8-bit r ead-o nly registers. When the ICST bit in TCONRI is set to 1,
TICRR and TICRF capture the contents of TCNT successively on the rise and fall of the external
reset input. When one capture operation ends, the ICST bit is cleared to 0.
TICRR and TICRF are each initialized to H'00 by a reset and in hardware stan dby mode.
The TICRR and TICRF functions are used in timer connection. For details, see section 12.3.6,
Input Capture Operation, and section 13, Timer Connection.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 360 of 1130
REJ09B0327-0400
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Functio n]
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IS
0
R/W
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the
counter.
TISR is initialized to H'FE by a reset and in h ardware stan dby mode.
Bits 7 to 1—Reserved: Do not write 0 to th ese b its.
Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer
clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source
for the counter.
Bit 0
IS Description
0 IVG signal is selected (H8S/2148 Group) (Initial value)
External clock/reset input is disabled (H8S/214 4 Group and H8 S/21 47N)
1 VSYNCI/TMIY (TMCIY/TMRIY) is selected
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 361 of 1130
REJ09B0327-0400
12.2.13 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP12 bit or MSTP8 bit is set to 1, 8-bit timer operation is halted on channels 0 and 1
or channels X and Y, respectively, and a transition is made to module stop mode. For details, see
section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 4—Module Stop (M STP12): Specifies 8-bit timer (channel 0/1) module stop
mode.
MSTPCRH
Bit 4
MSTP12 Description
0 8-bit timer (channel 0/1) module stop mode is cleared
1 8-bit timer (channel 0/1) mod ule sto p mode is set (Initial value)
MSTPCRH Bit 0—Module Stop (M STP8): Specifies 8-bit timer (channel X/Y) and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8 Description
0 8-bit timer (channel X/Y) and timer connection module stop mode is cleared
1 8-bit timer (channel X/Y) and timer connection module stop mode
is set (Initial value)
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 362 of 1130
REJ09B0327-0400
12.3 Operation
12.3.1 TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock
An internal clock created by dividing the system clock (φ) can be selected by setting bits CKS2 to
CKS0 in TCR. Figure 12.2 shows the count timing.
φ
Internal clock
TCNT input
clock
TCNT N – 1 N N + 1
Figure 12.2 Count Timing for Internal Clock Input
External Clock
Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising
edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states f or incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 12.3 shows the timing of incrementation at both edges of an external clock signal.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 363 of 1130
REJ09B0327-0400
φ
External clock
input pin
TCNT input
clock
TCNT N – 1 N N + 1
Figure 12.3 Count Timing for External Clock Input
12.3.2 Compare-Match Timing
Setting of Compare-Mat ch Flags A and B (CMF A, CMF B)
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCOR and TCNT values match. The compare-match signal is generated at the last state in which
the match is tru e , just before the timer counter is updated.
Therefore, when TCOR and TCNT m atch, the compare-match sign a l is not generated until the
next incrementation clock input. Figure 12.4 shows this timing.
φ
TCNT N N + 1
TCOR N
Compare-match
signal
CMF
Figure 12.4 Timing of CMF Setting
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 364 of 1130
REJ09B0327-0400
Timer Output Timing
When compare-match A or B occurs, the timer output changes as specified by the output select
bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0,
be set to 1, or toggle.
Figure 12.5 shows the timing when the output is set to toggle at compare-match A.
φ
Compare-match A
signal
Timer output
pin
Figure 12.5 Timing of Timer Output
Timing of Compare-Match Clear
TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation.
φ
N H'00
Compare-match
signal
TCNT
Figure 12.6 Timing of Compare-Match Clear
12.3.3 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.7 shows the timing of this operation.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 365 of 1130
REJ09B0327-0400
φ
Clear signal
External reset
input pin
TCNT N H'00N – 1
Figure 12.7 Timing of Clearing by External Reset Input
12.3.4 Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer co unt overflows (changes f rom H'FF to H'00). Figure
12.8 shows the timing of this operation.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 12.8 Timing of OVF Setting
12.3.5 Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer
mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (compare-
match count mode). In this case, the timer operates as described below.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 366 of 1130
REJ09B0327-0400
16-Bit Count Mode
When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
• Setting of compare-match flags
The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs.
The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
• Counter clear specification
If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear
by the TMRI0 pin has also been set.
The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot
be cleared independently.
• Pin output
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with
the 16-bit compare-match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with
the lower 8-bit compare-match conditio ns.
Compare-Ma tch Count Mode
When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare-match A’s for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
Usage Note
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT0 and TCNT1 are not gene r a ted and thus the counters will stop operating.
Simultaneous setting of these two modes should therefore be avoided.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 367 of 1130
REJ09B0327-0400
12.3.6 Input Capture Operation
TMRX has input capture registers of TICR, TI CRR, and TICRF. Na rrow pulse w i dth can be
measur e d with TI CRR a nd TICRF, using one capture operatio n contro lle d by the ICST bit in the
TCONRI register o f the timer connection . When TMRIX detects a risin g and falling edge
successively after the ICST bit has been set to 1, the values of TCNT at that time are transferred to
TICRR and TICRF and ICST bit is cleared to 0.
The TMRIX input signal can be selected by setting other bits in the TCONRI register.
(1) Input ca pture input timing
Figure 12.9 shows the timing of the input capture operation.
φ
Input capture
signal
TMRIX
TCNTX
TICRR
TICRF
nn
M
mm
n + 1 N N +1
n
N
Figure 12.9 Timing of Input Capture Operation
If the input cap ture signal e nters while T ICRR and T ICRF are be ing read, it is internally delay ed
one system clock (φ) period. Figure 12.10 shows the timing of th is operation.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 368 of 1130
REJ09B0327-0400
φ
Input capture
signal
TMRIX
TICRR, TICRF read cycle
T1 T2
Figure 12.10 Timing of Input Capture Signal
(When Input Capture Input Signal Enters while T ICRR and TICRF Are Being Read)
(2) Input ca pt ure signal input selection
Input capture input signal (TMRIX) in TMRX is switched by setting bits in the TCONRI register.
Figure 12.11 and Table 12.3 show the input capture signal selections.
See section 13.2.1, Timer Connection Register I (TCONRI), for details.
Signal
selector
Polarity
inversion
Polarity
inversion
Polarity
inversion
TMIX pin
TMRI1 pin
HFINV,
HIINV
TMCI1 pin
TMRIX
TMRX
SIMOD1,
SIMOD0 ICST
Figure 12.11 Switching of Input Capture Signal
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 369 of 1130
REJ09B0327-0400
Table 12.3 Input Capture Signal Selection
TCONRI
Bit 4 Bit 7 Bit 6 Bit 3 Bit 1
ICST SIMOD1 SIMOD0 HFINV HIINV Description
0————Input capture function not used
1000—TMIX pin input signal
1 — Inverted signal of TMIX pin input
1 — 0 TMRI1 pin input signal
—1 Inverted signal of TMRI1 pin input
11—0 TMCI1 pin input signal
—1 Inverted signal of TMCI1 pin input
12.4 Interrupt Sources
The TMR0, TMR1, and TMRY 8-bit timers can generate th r ee types o f interrupt: compare-match
A and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX interrupt. An
interrupt is requested when the corresponding interrupt enab le bit is set in TCR or TCSR.
Independent signals are sent to the interrupt controller for each interrupt. It is also possible to
activate the DTC by means of CMIA and CMIB interrupts from TMR0, TMR1 and TMRY.
An overview of 8-bit timer interrupt sources is given in tables 12.4 to 12.6.
Table 12.4 TMR0 and TMR1 8-Bit Timer Interrupt Sources
Interrupt source Description DTC Activation Interrupt Priority
CMIA Requested by CMFA Possible High
CMIB Requested by CMFB Possible
OVI Requested by OVF Not possible Low
Table 12.5 TMRX 8-Bit Timer Interrupt Source
Interrupt source Description DTC Activation
ICIX R eque sted by ICF Not possible
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 370 of 1130
REJ09B0327-0400
Table 12.6 TMRY 8-Bit Timer Interrupt Sources
Interrupt source Description DTC Activation Interrupt Priority
CMIA Requested by CMFA Possible High
CMIB Requested by CMFB Possible
OVI Requested by OVF Not possible Low
12.5 8-Bit Timer Application Example
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle,
as shown in figure 12.12. The control bits are set as follows:
• In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared by a
TCORA compare-match.
• In TCSR, bits OS3 to OS0 are set to B'0110, causing 1 output at a TCORA compare-match and
0 output at a TCORB compare-match.
With these settings, the 8-bit timer provides output o f pulses at a rate determined by TCORA with
a pulse width d etermined by TCORB. No software intervention is required.
TCNT
H'FF Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.12 Pulse Output (Example)
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 371 of 1130
REJ09B0327-0400
12.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer module.
12.6.1 Contention betw een TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows
this oper a tion.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12.13 Contention between TCNT Write and Clear
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 372 of 1130
REJ09B0327-0400
12.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is no t incremented. Figure 12.14 shows this operation.
φ
Address TCNT address
Internal write signal
TCNT input clock
TCNT NM
T1T2
TCNT write cycle by CPU
Counter write data
Figure 12.14 Contention between TCNT Write and Increment
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 373 of 1130
REJ09B0327-0400
12.6.3 Contention between TCOR Writ e and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.15 shows this operation.
With TMRX, an ICR input capture contends with a compare-match in the same way as with a
write to TCORC. In this case, the input capture has priority and the compare-match signal is
inhibited.
φ
Address TCOR address
Internal write signal
TCNT
TCOR NM
T1T2
TCOR write cycle by CPU
TCOR write data
NN + 1
Compare-match signal
Inhibited
Figure 12.15 Contention between TCOR Write and Compare-Match
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 374 of 1130
REJ09B0327-0400
12.6.4 Contention between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the prior ities f or the output states set for compare-match A and compare-match B, as shown in
table 12.7.
Table 12.7 Timer Output Priorities
Output Setting Priority
Toggle output High
1 output
0 output
No change Low
12.6.5 Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 12.8 shows the
relationship between the timin g at which the internal clock is switched ( by writing to the CKS1
and CKS0 bits) and the TCNT operation
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 12.8, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
Erroneous incrementation can also happen when switching between intern al and external clocks.
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 375 of 1130
REJ09B0327-0400
Table 12.8 Switching of Internal Clock and TCNT Operation
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits TCNT Clock Operation
1 Switching from low
to low*1
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit rewrite
N N + 1
2 Switching from low
to high*2
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit rewrite
N N + 1 N + 2
Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 376 of 1130
REJ09B0327-0400
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits TCNT Clock Operation
3 Switching from high
to low*3
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit rewrite
N N + 1 N + 2
*4
4 Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
CKS bit rewrite
N N + 1 N + 2
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 377 of 1130
REJ09B0327-0400
Section 13 Timer Connection
Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N.
13.1 Overview
The H8S/2148 Group allows interconnection between a combination of input signals, the
input/output of the single free-running timer (FRT) channel and the three 8-bit timer channels
(TMR1, TMRX, and TMRY) . Th is capability can be used to implement comp lex functions such as
PWM decoding and clamp waveform output. All the timers are initially set f or independent
operation.
13.1.1 Features
The features of the tim er connection facility are as follows.
• Five input pins and four output pins, all of which can be designated for phase inversion.
Positive logic is assumed for all signals used within the timer connection facility.
• An edge-detection circuit is connected to the input pins, simplifying signal input detection.
• TMRX can be used for PWM input signal decoding and clamp waveform generation.
• An external clock signal divided by TMR1 can be used as the FRT capture input signal.
• An internal synchronization signal can be generated using the FRT and TMRY.
• A signal generated/modified using an input signal and timer connection can be selected and
output.
13.1.2 Block Diagram
Figure 13 .1 sh ows a block diagram of the timer connection facility.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 378 of 1130
REJ09B0327-0400
Edge
detection
Edge
detection
VSYNCI/
FTIA/TMIY
VFBACKI/
FTIB
FTIC
FTID
Phase
inversion
Phase
inversion Phase
inversion
phase
inversion
phase
inversion
Phase
inversion
IVI
signal
selection
READ
flag
Edge
detection
Edge
detection
Edge
detection
Phase
inversion
Phase
inversion
Phase
inversion
READ
flag
IVI signal
FRT
input
selec-
tion
SET
sync
RES VSYNC modify
FTIA
FTIB
FTIC
FTID
16-bit FRT
OCRA +VR, +VF
ICRD +1M, +2M
compare match
FTOA
CMA(R)
CMA(F)
FTOB
CM2MCM1M
RESSET
2f H mask generation
2f H mask/flag
CBLANK waveform
generation
TMR1
input
selection
TMCI
8-bit TMR1
TMRI
CMB
TMO
SET IVG signal
IVO signal
RES
VSYNC
generation
IVO
signal
selection
TMIY
signal
selection
FRT
output
selection VSYNCO/
FTOA
TMRI/TMCI
TMO
8-bit TMR Y IHG signal
CBLANK
HSYNCO/
TMO1
TMOX
TMO1
output
selection
IHO
signal
selection
CL4 generation
CL4 signal
CLAMPO
/
FTIC
CL
signal
selection
PDC signal
PWM decoding
8-bit TMRX CMB
TMO
CMA
ICR
ICR +1C
compare match
CLAMP waveform generation
TMCI
TMRI
CM1C
CL1 signal
CL2 signal
CL3 signal
IHI signal
IHI
signal
selection
HSYNCI/
TMCI1
CSYNCI/
TMRI1
HFBACKI/
FTCI/TMIX
Figure 13.1 Block Diagram of Timer Connect ion Facility
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 379 of 1130
REJ09B0327-0400
13.1 .3 Input and Output Pins
Table 13.1 lists the timer connection input and output pins.
Table 13.1 Timer Con nect ion Input and Output Pins
Name Abbreviation Input/
Output Function
Vertical syn chr o ni zati on
signal input pin VSYNC I Input Vertical synchro ni zati on signal
input pin or FTIA input pin/TMIY
input pin
Horizontal synchronization
signal input pin HSYNCI Input Horizontal synchronization signal
input pin or TMCI1 input pin
Composite synchronization
signal input pin CSYNCI Input Composite synchronization signal
input pin or TMRI1 input pin
Spare vertical synchron iz atio n
signal input pin VFBACKI Input Spare vertical synchronizatio n
signal input pin or FTIB input pin
Spare horizontal
synchro ni zati on signal input
pin
HFBACKI Input Spare horizontal synchronization
signal input pin or FTCI input
pin/TMIX input pin
Vertical syn chr o ni zati on
signal output pin VSYNC O Output Vertical syn chro ni zati on signal
output pin or FTOA output pin
Horizontal synchronization
signal output pin HSYNCO Output Horizontal synchronization signal
output pin or TMO1 output pin
Clamp waveform output pin CLAMPO Output Clamp waveform output pin or
FTIC input pin
Blanking waveform output pin CBLANK Output Blanking waveform output pin
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 380 of 1130
REJ09B0327-0400
13.1.4 Register Configuration
Table 13.2 lists the timer connection registers. Timer connection registers can on ly be accessed
when the HIE bit in SYSCR is 0.
Table 13.2 Register Configuration
Name Abbreviation R/W Initial Value Address*1
Timer connection register I TCONRI R/W H'00 H'FFFC
Timer connection register O TCONRO R/W H'00 H'FFFD
Timer connection register S TCONRS R/W H'00 H'FFFE
Edge sense register SEDGR R/(W)*2H'00*3H'FFFF
Module stop control register MSTPRH R/W H'3F H'FF86
MSTPRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Bits 7 to 2: Only 0 can be written to clear the flags.
3. Bits 1 and 0: Undefined (reflect the pin states).
13.2 Register Descriptions
13.2.1 Timer Connection Register I (TCONRI)
Bit
Initial value
Read/Write
7
SIMOD1
0
R/W
6
SIMOD0
0
R/W
5
SCONE
0
R/W
4
ICST
0
R/W
3
HFINV
0
R/W
0
VIINV
0
R/W
2
VFINV
0
R/W
1
HIINV
0
R/W
TCONRI is an 8- bit readable/writable register that controls connection b e tween timers, the signal
source for synchronization signal input, phase inversion, etc.
TCONR1 is initialized to H'00 by a reset and in hardware standby mode.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 381 of 1130
REJ09B0327-0400
Bits 7 and 6—Input Synchro nization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits
select the signal source of the IHI and IVI signals.
Bit 7 Bit 6 Description
SIMOD1 SIMOD0 Mode IHI Signal IVI Signal
0 0 No signal (Initial value) HFBACKI input VFBACKI input
1 S-on-G mode CSYNCI input PDC input
1 0 Composite mode HSYNCI input PDC input
1 Separate mode HSYNCI input VSYNCI input
Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the
FRT FTI input and the TMR1 TMCI1/TMRI1 input.
Bit 5 Description
SCONE Mode FTIA FTIB FTIC FTID TMCI1 TMRI1
0 Normal connection (Initial value) FTIA
input FTIB
input FTIC
input FTID
input TMCI1
input TMRI1
input
1 Synchronization signal
connection mode IVI
signal TMO1
signal VFBACKI
input IHI
signal IHI
signal IVI
inverse
signal
Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected
to the IHI sig nal. TMRX has input capture registers (TICR, TICRR, an d TICRF). TICRR and
TICRF can measure the width of a short pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
Bit 4
ICST Description
0 The TICRR and TICRF input capture functions are stopped (Initial value)
[Clearing cond iti on]
When a rising edge followed by a falling edge is detected on TMRIX
1 The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 382 of 1130
REJ09B0327-0400
Bits 3 to 0— Input Synchronization Signal Inversion (HFINV, VFINV, H IINV, VIINV):
These bits select inversion of the input phase of the spare horizontal synchronization signal
(HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal
synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the
vertical synchron ization signal (VSYNCI).
Bit 3
HFINV Description
0 The HFBACKI pin state is used directly as the HFBACKI input (Initial value)
1 The HFBACKI pin state is inverted before use as the HFBACKI input
Bit 2
VFINV Description
0 The VFBACKI pin state is used directly as the VFBACKI input (Initial value)
1 The VFBACKI pin state is inverted before use as the VFBACKI input
Bit 1
HIINV Description
0 The HSYNCI and CSYNCI pin states are used directly as the HSYNCI
and CSYNCI inputs (Initial value)
1 The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and
CSYNCI inputs
Bit 0
VIINV Description
0 The VSYNCI pin state is used directly as the VSYNCI input (Initial value)
1 The VSYNCI pin state is inverted before use as the VSYNCI input
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 383 of 1130
REJ09B0327-0400
13.2.2 Timer Connection Register O (TCONRO)
Bit
Initial value
Read/Write
7
HOE
0
R/W
6
VOE
0
R/W
5
CLOE
0
R/W
4
CBOE
0
R/W
3
HOINV
0
R/W
0
CBOINV
0
R/W
2
VOINV
0
R/W
1
CLOINV
0
R/W
TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion,
etc.
TCONRO is initialized to H'00 by a reset and in h ardwar e standby mode.
Bits 7 and 4—Output Enable (HOE, VOE, CLOE, CBOE): These bits control
enabling/disabling of horizontal synchronization signal (HSYNCO), vertical synchronization
signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK) output.
When output is disabled, the state of the relevant pin is determined by the port DR and DDR, FRT,
TMR, and PWM settings.
Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some
FRT and TMR input signal sources are determined by the SCONE bit in TCONRI.
Bit 7
HOE Description
0 The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/
HIRQ1 pin (Initial value)
1 The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin
Bit 6
VOE Description
0 The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/
KIN1/CIN1 pin (Initial value)
1 The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 384 of 1130
REJ09B0327-0400
Bit 5
CLOE Description
0 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the
P64/FTIC/KIN4/CIN4 pin (Initial val ue)
1 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
Bit 4
CBOE Description
0 The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin (Initial value)
1 In mode 1 (expanded mode with on-chip ROM disabled):
The P27/A15/PW15/CBLANK pin functions as the A15 pin
In modes 2 and 3 (modes with on-chip ROM enabled):
The P27/A15/PW15/CBLANK pin functions as the CBLANK pin
Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV,
CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal
(HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO),
and the blank waveform (CBLANK).
Bit 3
HOINV Description
0 The IHO signal is used directly as the HSYNCO output (Initial value)
1 The IHO signal is inverted before use as the HSYNCO output
Bit 2
VOINV Description
0 The IVO signal is used directly as the VSYNCO output (Initial value)
1 The IVO signal is inverted before use as the VSYNCO output
Bit 1
CLOINV Description
0 The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the
CLAMPO output (Initial value)
1 The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as
the CLAMPO output
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 385 of 1130
REJ09B0327-0400
Bit 0
CBOINV Description
0 The CBLANK signal is used directly as the CBLANK output (Initial value)
1 The CBLANK signal is inverted before use as the CBLANK output
13.2.3 Timer Connection Register S (TCONRS)
Bit
Initial value
Read/Write
7
TMRX/Y
0
R/W
6
ISGENE
0
R/W
5
HOMOD1
0
R/W
4
HOMOD0
0
R/W
3
VOMOD1
0
R/W
0
CLMOD0
0
R/W
2
VOMOD0
0
R/W
1
CLMOD1
0
R/W
TCONRS is an 8-bit readable/writable register that selects 8-bit timer TMRX/TMRY access and
the synchronization signal output signal source and generation method.
TCONRS is initia lized to H'00 by a reset an d in hardware standby mode.
Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be
accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2148 Group, some of the TMRX
registers and the TMRY reg isters are assigned to th e sam e m emory space addresses (H'FFF0 to
H'FFF5), and the TMRX/Y b it determines which registers are accessed. In the H8S/2144 Group
and H8S/2147N, there is no control of TMRY register access by this bit.
Bit 7
TMRX/Y Description
0 The TMRX registers are ac cessed at addresses H'FFF0 to H'FFF5 (Initial value)
1 The TMRY registers are ac cessed at addresses H'FFF0 to H'FFF5
Bit 6—Internal Synchroniza tion Signal Select ( ISG ENE): Selects in ternal synch r onization
signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 386 of 1130
REJ09B0327-0400
Bits 5 and 4—H orizontal Synchronization Out put Mode Select 1 and 0 (HOMOD1 ,
HOMOD0): These bits select the signal source and generation method for the IHO signal.
Bit 6 Bit 5 Bit 4
ISGENE HOMOD1 HOMOD0 Description
0 0 0 The IHI signal (without 2fH modification) is selected
(Initial value)
1 The IHI signal (with 2fH modification) is selected
1 0 The CL1 signal is selected
1
1 0 0 The IHG signal is selected
1
10
1
Bits 3 and 2—Vert ical Synchronizatio n Output Mode Select 1 and 0 (VO MOD 1, VOMOD0):
These bits select the signal source and generation method for the IVO signal.
Bit 6 Bit 3 Bit 2
ISGENE VOMOD1 VOMOD0 Description
0 0 0 The IVI signal (without fall modification or
IHI synchroni zat ion) is selected (Initial value)
1 The IVI signal (without fall modification, with IHI
synchronization) is selected
1 0 The IVI signal (with fall modification, without IHI
synchronization) is selected
1 The IVI signal (with fall modification and IHI
synchronization) is selected
1 0 0 The IVG signal is selected
1
10
1
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 387 of 1130
REJ09B0327-0400
Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for th e CLO signal (clamp waveform).
Bit 6 Bit 1 Bit 0
ISGENE CLMOD1 CLMOD2 Description
0 0 0 The CL1 signal is selected (Initial value)
1 The CL2 signal is selected
1 0 The CL3 signal is selected
1
1 0 0 The CL4 signal is selected
1
10
1
13.2.4 Edge Sense Register (SEDGR)
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written, to clear the flags.
2. The initial value is undefined since it depends on the pin states.
7
VEDG
0
R/(W)
6
HEDG
0
R/(W)
5
CEDG
0
R/(W)
4
HFEDG
0
R/(W)
3
VFEDG
0
R/(W)
0
IVI
—*
2
R
2
PREQF
0
R/(W)
1
IHI
—*
2
R
*
1
*
1
*
1
*
1
*
1
*
1
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the ph ase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are in itialized to 0 by a reset and in hardware stan dby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 388 of 1130
REJ09B0327-0400
Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin.
Bit 7
VEDG Description
0 [Clearing condition]
When 0 is written in VEDG after reading VEDG = 1 (Initial value)
1 [Setting condition]
When a rising edge is detected on the VSYNCI pin
Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin.
Bit 6
HEDG Description
0 [Clearing condition]
When 0 is written in HEDG after reading HEDG = 1 (Initial val ue)
1 [Setting condition]
When a rising edge is detected on the HSYNCI pin
Bit 5—CSYNCI Edge (CEDG): Detects a rising edge on the CSYNCI pin.
Bit 5
CEDG Description
0 [Clearing condition]
When 0 is written in CEDG after reading CEDG = 1 (Initial val ue)
1 [Setting condition]
When a rising edge is detected on the CSYNCI pin
Bit 4—HFBACKI Edge (HFEDG): Detects a rising edge on the HFBACKI pin.
Bit 4
HFEDG Description
0 [Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1 (Initial value)
1 [Setting condition]
When a rising edge is detected on the HFBACKI pin
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 389 of 1130
REJ09B0327-0400
Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin.
Bit 3
VFEDG Description
0 [Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1 (Initial value)
1 [Setting condition]
When a rising edge is detected on the VFBACKI pin
Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH
modificatio n condition. The genera tion of a falling/rising edge in the IHI signal during a m a sk
interval is expressed as the occurrence of a 2fH modification condition. For details, see section
13.3.4, IHI Signal 2fH Modification.
Bit 2
PREQF Description
0 [Clearing condition]
When 0 is written in PREQF after reading PREQF = 1 (Initial value)
1 [Setting condition]
When an IHI signal 2fH modification condition is detected
Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and
phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signa l is positive or negative, then maintain the IHI sig nal at positive
phase by modifying TCONRI.
Bit 1
IHI Description
0 The IHI signal is low
1 The IHI signal is high
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 390 of 1130
REJ09B0327-0400
Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and
phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IVI sig nal at positive
phase by modifying TCONRI.
Bit 0
IVI Description
0 The IVI signal is low
1 The IVI signal is high
13.2.5 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit
timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt
and enter module stop mode. See section 25.5., Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (M STP13): Specifies FRT module stop mode.
MSTPCRH
Bit 5
MSTP13 Description
0 FRT module stop mode is cleared
1 FRT module stop mode is set (Initial value)
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 391 of 1130
REJ09B0327-0400
MSTPCRH Bit 4—Module Stop (M STP12): Specifies 8-bit timer channel 0 and 1 module stop
mode.
MSTPCRH
Bit 4
MSTP12 Description
0 8-bit timer channel 0 and 1 module stop mode is cleared
1 8-bit timer channel 0 and 1 module stop mode is set (Initial value)
MSTPCRH Bit 0—Module Stop (M STP8): Specifies 8-bit timer channel X and Y and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8 Description
0 8-bit timer channel X and Y and timer connection module stop mode is cleared
1 8-bit timer channel X and Y and timer connection module stop mode is
set (Initial value)
13.3 Operation
13.3.1 PWM Decoding (PDC Signal Generation)
The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding th e pulse wid th is wr itten in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is
reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using
TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold.
Examples of TCR and TCORB settings are shown in tables 13.3 and 13.4, and the timing chart is
shown in figu re 13.2.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 392 of 1130
REJ09B0327-0400
Table 13.3 Examples of TCR Settings
Bit(s) Abbreviation Contents Description
7
6
5
CMIEB
CMIEA
OVIE
0
0
0
Interrupts due to compare-match and ov erflow are
disabled
4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external
reset signal (IHI signal)
2 to 0 CKS2 to CKS0 001 Incremented on internal clock: φ
Table 13.4 Examples of TCOR B (Pulse Width Threshold) Settings
φ
φφ
φ:10 MHz φ
φφ
φ: 12 MHz φ
φφ
φ: 16 MHz φ
φφ
φ: 20 MHz
H'07 0.8 µs 0.67 µs 0.5 µs 0.4 µs
H'0F 1.6 µs 1.33 µs 1 µs 0.8 µs
H'1F 3.2 µs 2.67 µs 2 µs 1.6 µs
H'3F 6.4 µs 5.33 µs 4 µs 3.2 µs
H'7F 12.8 µs 10.67 µs 8 µs 6.4 µs
IHI signal
Counter reset
caused by
IHI signal
Counter clear
caused by
TCNT overflow
At the 2nd compare-match,
IHI signal is not tested
IHI signal is tested
at compare-match
PDC signal
TCNT
TCORB
(threshold)
Figure 13.2 Timing Chart for PWM Decoding
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 393 of 1130
REJ09B0327-0400
13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
The timer connection facility and TMRX can be used to generate sign als with different duty cycles
and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal).
Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4
signal can be generated using TMRY.
The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is
high, th e CL2 signal rises simultaneo usly with the fall o f the I HI signal. The fall of both the CL1
and the CL2 signal can be specified by TCORA.
The rise of the CL3 sign al can be specified as simultaneous with the sampling of the fall of the IHI
signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3
signal ca n also fall when the IHI signal rises.
TCNT in TMRX is set to count internal clock pulses and to be cleared on the rising edge of the
external reset signal (IHI sig nal).
The value to be used as the CL1 signal pulse width is wr itten in TCORA. Write a value of H'02 or
more in TCORA when internal clock φ is selected as the TMRX counter clock, and a value or
H'01 or more when φ/2 is selected. When internal clock φ is selected, the CL1 signal pulse width
is (TCORA set valu e +3 ±0.5). When the CL2 signal is used, the setting m ust be made so that th is
pulse width is greater than the IHI sign al pulse width.
The value to be used as the CL3 signal pulse width is wr itten in TCORC. The TICR reg ister in
TMRX captures the value of TCNT at the inverse of the external reset signal edge (in this case, the
falling edge of the IHI signal). The timing of the fall of the CL3 signal is de ter mined by the sum of
the contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes
the fall timing set by the conten ts of TCORC, since the IHI signal will cause the CL3 sig nal to fall.
Examples of TMRX TCR settings are the same as those in table 13.3. The clamp waveform timing
charts are shown in figures 13.3 and 13.4.
Since the rise of the CL1 and CL2 signals is synchron ized with the edge of the IHI signal, and
their fall is syn c hronized with the sy stem clock, the pulse width v a r iation is equivalent to the
resolution of the system clock.
Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse
width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to
the resolu tion of the system clock.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 394 of 1130
REJ09B0327-0400
IHI signal
CL1 signal
CL2 signal
TCNT
TCORA
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)
IHI signal
CL3 signal
TCNT
TICR+TCORC
TICR
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period
The timer connection facility, TMR1, and the free-running timer (FRT) can be used to m easure the
period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of inverted
IVI signal, the rise and fall of the IHI signal divided waveform can be virtually synchronized with
the IVI signal. This enables period measurement to be carried out efficiently.
To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the
external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal
(inverted IVI sig n a l) . The v alue to be used as the division factor is wr itten in TCORA, and the
TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings
are shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI signal
divided waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform
is given by (ICRD(3) – ICRD(2)) × the resolution.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 395 of 1130
REJ09B0327-0400
Table 13.5 Examples of TCR and TCSR Settings
Register Bit(s) Abbreviation Contents Description
TCR in TMR1 7 CMIEB 0
6CMIEA 0
5OVIE 0
Interrupts due to compare-matc h
and overflow are disabled
4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge
of the external reset signal (inverted
IVI signal)
2 to 0 CKS2 to CKS0 101 TCNT is incremented on the rising
edge of the external clock (IHI
signal)
TCSR in TMR1 3 to 0 OS3 to OS0 0011
1001
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): division by 512
or
when TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: division by
256
TCR in FRT 6 IEDGB 0/1 0: FRC value is transferred to ICRB
on falling edge of input capture
input B (IHI divided signal
waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture
input B (IHI divided signal
waveform)
1 and 0 CKS1, CKS0 01 FRC is incremented on internal
clock: φ/8
TCSR in FRT 0 CCLRA 0 FRC clearing is disabled
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 396 of 1130
REJ09B0327-0400
IVI signal
IHI signal
divided
waveform
FRC
ICRB
ICRB(1)
ICRB(2)
ICRB(3)
ICRB(4)
Figure 13.5 Timing Chart for Measurement of IVI Signal and
IHI Signal Divided Waveform Periods
13.3.4 IHI Signal and 2fH Modification
By using the timer connection FRT, ev en if th er e is a part of th e I H I sign al with twice the
frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of
the IHI signal must be approximately 30% or less, or approximately 70% or above.
The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data
captured in ICRD in the FRT, and compare-ma tch e s generated at these points. The in terval
between the two compare-matches is called a mask interval. A value equivalent to approximately
1/3 the IHI signal p e r iod is wr itten in OCRDM. ICRD is set so th at capture is perf ormed on the
rise of the IHI signal.
Since the IHI sig nal supplied to the IHO signal selection circuit is norma lly set on the rise of the
IHI signal and reset on the fall, its waveform is the same as th at of the original IHI signal. Wh en
2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture
is also disabled during these intervals.
Examples of FRT TCR settings are shown in table 13.6, and the 2fH modification timing chart is
shown in figu re 13.6.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 397 of 1130
REJ09B0327-0400
Table 13.6 Examples o f TCR, TCSR, TCO R, and OCRDM Settings
Register Bit(s) Abbreviation Contents Description
TCR in FRT 4 IEDGD 1 FRC value is transferred to ICRD on
the rising edge of input capture input
D (IHI signal)
1 and 0 CKS1, CKS0 01 FRC is incremented on internal clock:
φ/8
TCSR in FRT 0 CCLRA 0 FRC clearing is disabled
TCOR in FRT 7 ICRDMS 1 ICRD is set to the operating mode in
which OCRDM is used
OCRDM in FRT 7 to 0 OCRDM7 to 0 H'01 to H'FF Specifies the period during which
ICRD operation is masked
IHI signal
(without 2fH
modification)
IHI signal
(with 2fH
modification)
Mask interval
ICRD + OCRDM × 2
ICRD + OCRDM
FRC
ICRD
Figure 13.6 2fH Modification Timing Chart
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 398 of 1130
REJ09B0327-0400
13.3.5 IVI Signal Fall Modification and IHI Synchronization
By using the timer connection TMR1, the fa ll of th e I VI signal can be shifted backward by the
specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized
with the rise of th e IHI signal.
To perform 8-bit timer divided waveform period measurement, TCNT in TMR1 is set to count
external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal
(inverse of the IVI signal). The number o f IHI signal pulses until th e f a ll of the IVI signal is
written in TCORB.
Since the IVI sig nal supplied to the IVO signal selection circuit is norma lly set on the rise of the
IVI signal and reset on the fall, its waveform is the same as th at of the original IVI signal. Wh en
fall modification is selected, a reset is performed on a TMR1 TCORB compare-match.
The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal,
regardless of whether or not fall modification is selected.
Examples of TMR1 TCORB, TCR, and TCSR settings are shown in table 13.7, and the fall
modification/IHI synchronization timing chart is shown in figure 13.7.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 399 of 1130
REJ09B0327-0400
Table 13.7 Examples o f TCORB, TCR, and TCSR Settings
Register Bit(s) Abbreviation Contents Description
7CMIEB 0
6CMIEA 0
5OVIE 0
Interrupts due to compare-match and
overflow are disabled
4 and 3 CCLR1,
CCLR0 11 TCNT is cleared by the rising edge of the
external reset signal (inverse of the IVI
signal)
TCR in
TMR1
2 to 0 CKS2 to CKS0 101 TCNT is incremented on the rising edge of
the external clock (IHI signal)
TCSR in
TMR1 3 to 0 OS3 to OS0 0011
1001
Not changed by compare-match B; output
inverted by com par e-m atch A (toggle
output)
or
when TCORB ≤ TCORA, 1 output on
compare-match B, 0 output on compare-
match A
TOCRB in TMR1 H'03
(example) Compare-match on the 4th (example) rise
of the IHI signal after the rise of the
inverse of the IVI signal
012345
TCNT TCNT = TCORB (3)
IHI signal
IVI signal (PDC signal)
IVO signal
(without fall modification,
with IHI synchronization)
IVO signal
(with fall modification,
without IHI synchronization)
IVO signal
(with fall modification
and IHI synchronization)
Figure 13.7 Fall Modification/IHI Synchronization Timing Chart
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 400 of 1130
REJ09B0327-0400
13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
By using the timer connection FRT and TMRY, it is p ossible to autom atically generate in ternal
signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is
synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the
IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in
synchronization with the IHG signal.
The contents of OCRA in the FRT are updated by the automatic addition of the contents of
OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the
0 interval of th e I VG signal is written in OCRAR, and a value corresp onding to the 1 interval of
the IVG signal is wr itten in OCRAF. The IVG signal is set by a compare-match after an OCRAR
addition, and reset by a comp are-match after an OCRAF addition.
The IHG signal is the TMRY 8-bit timer output. TMRY is set to count internal clock pulses, and
to be cleared on TCORA compare-match, to fix the period and set the timer output. TCORB is set
so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and
the rise of the IVG signal can be treated in the same way as a TCORA compare-match.
The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG
signal, and has a 1 interval of 6 system clock periods.
Examples of settings of TCORA, TCORB, TCR, and TCSR in TMRY, and OCRAR, OCRAF,
and TCR in the FRT, ar e shown in table 13 .8, and the IHG signal/IVG sig nal timing chart is
shown in figu re 13.8.
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 401 of 1130
REJ09B0327-0400
Table 13.8 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR
Settings
Register Bit(s) Abbreviation Contents Description
TCR in
TMRY 7 CMIEB 0 Interru pts due to compare-m atc h and
overflow are disabled
6CMIEA 0
5OVIE 0
4 and 3 CCLR1,
CCLR0 01 TCNT is cleared by compar e-m atch A
2 to 0 CKS2 to CKS0 001 TCNT is incremented on internal clock:
φ/4
TCSR in
TMRY 3 to 0 OS3 to OS0 0110 0 output on compare-match B
1 output on compare-match A
TOCRA in
TMRY H'3F
(example) IHG signal period = φ × 256
TOCRB in
TMRY H'03
(example) IHG signal 1 interval = φ × 16
TCR in FRT 1 and 0 CKS1,
CKS0 01 FRC is incremented on internal clock: φ/8
OCRAR in FRT H'7FEF
(example) IVG signal 0
interval =
φ × 262016
IVG signal period =
φ × 262144 (1024
times IHG signal)
OCRAF in FRT H'000F
(example) IVG signal 1
interval = φ × 128
TOCR in FRT 6 OCRAMS 1 OCRA is set to the operating mode in
which OCRAR and OCRAF are used
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 402 of 1130
REJ09B0327-0400
6 system clocks6 system clocks6 system clocks
OCRA (4) =
OCRA (3) +
OCRAR
OCRA (3) =
OCRA (2) +
OCRAF
OCRA (2) =
OCRA (1) +
OCRAR
OCRA (1) =
OCRA (0) +
OCRAF
OCRA
FRC
CL4
signal
IHG
signal
TCORA
TCORB
TCNT
IVG signal
Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 403 of 1130
REJ09B0327-0400
13.3.7 HSYNCO Output
With the HSYNCO output, the mean ing of the signal source to be selected and use or non-use of
modification varies according to the IHI signal source and the waveform required by external
circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9.
Table 13.9 Meaning of HSYNCO Output in Each Mode
Mode IHI Signal IHO Signal Meaning of IHO Signal
No signal HFBACKI
input IHI signal (without
2fH modification) HFBACKI input is output directly
IHI signal (with 2fH
modification) Meaningless unless there is a double-frequency
part in the HFBACKI input
CL1 signal HFBACKI input 1 interval is changed before output
IHG signal Internal synchroni zati on sig nal is outp ut
S-on-G
mode CSYNCI
input IHI signal (without
2fH modification) CSYNCI input (composite synchronization signal)
is output directly
IHI signal (with 2fH
modification) Double-frequency part of CSYNCI input (composite
synchroni zation signal) is eliminated bef ore outp ut
CL1 signal CSYNCI input (composite synchronization signal)
horizontal syn chronization signal part is sep arate d
before output
IHG signal Internal synchroni zati on sig nal is outp ut
Composite
mode HSYNCI
input IHI signal (without
2fH modification) HSYNCI input (composite synchronization signal)
is output directly
IHI signal (with 2fH
modification) Double-frequency part of HSYNCI input (composite
synchroni zation signal) is eliminated bef ore outp ut
CL1 signal HSYNCI input (composite synchronization signal)
horizontal syn chronization signal part is sep arate d
before output
IHG signal Internal synchroni zati on sig nal is outp ut
Separate
mode HSYNCI
input IHI signal (without
2fH modification) HSYNCI input (horizontal synchronization signal) is
output directly
IHI signal (with 2fH
modification) Meaningless unless there is a double-frequency
part in the HSYNCI input (horizontal
synchro ni zati on signal)
CL1 signal HSYNCI input (horizontal synchronization signal) 1
interval is changed before output
IHG signal Internal synchroni zati on sig nal is outp ut
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 404 of 1130
REJ09B0327-0400
13.3.8 VSYNCO Output
With the VSYNCO output, the mean ing of the signal source to be selected and use or non-use of
modification varies according to the IVI signal source and the waveform required by external
circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10.
Table 13.10 Meaning of VSYNCO Output in Each Mo de
Mode IVI Signal IVO Signal Meaning of IVO Signal
No signal VFBACKI
input IVI signal (without fall
modification or IHI
synchronization)
VFBACKI input is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VFBACKI input is
synchronized with HFBACKI input
IVI signal (with fall
modification, without IHI
synchronization)
VFBACKI input fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VFBACKI input fall is modified and signal is
synchronized with HFBACKI input before
output
IVG signal Intern al syn chro ni zati on signal is output
S-on-G
mode or
composite
mode
PDC signal IVI signal (without fall
modification or IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchro ni zati on signal) vertical
synchroni zation signal part is separated
before output
IVI signal (without fall
modification, with IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchro ni zati on signal) vertical
synchroni zation signal part is separated, and
signal is synchronized with CSYNCI/HSYNCI
input before output
IVI signal (with fall
modification, without IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchro ni zati on signal) vertical
synchroni zation signal part is separated, and
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchro ni zati on signal) vertical
synchroni zation signal part is separated, fall is
modified, and signal is synchronized with
CSYNCI/HSYNCI input before output
IVG signal Intern al syn chro ni zati on signal is output
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 405 of 1130
REJ09B0327-0400
Mode IVI Signal IVO Signal Meaning of IVO Signal
Separate
mode VSYNCI
input IVI signal (without fall
modification or IHI
synchronization)
VSYNCI input (vertical synchronization signal)
is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VSYNCI input (v ertical
synchronization signal) is synchr oni ze d with
HSYNCI input (horizontal synchronization
signal)
IVI signal (with fall
modification, without IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified and sign al is synchronized with
HSYNCI input (horizontal synchronization
signal) befor e output
IVG signal Intern al syn chro ni zati on signal is output
13.3.9 CBLANK Output
Using the signals generated/selected with timer connection, it is possible to generate a waveform
based on the composite synchronization signal (blanking waveform).
One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs,
with the pha se polarity made positive b y means of bits HFINV and VFINV in TCONRI, with the
IVO signal.
The composition logic is shown in figure 13.9.
Reset
Set
CBLANK signal
(positive)
HFBACKI input (positive)
VFBACKI input (positive)
IVO signal (positive)
Q
Falling edge sensing
Rising edge sensing
Figure 13.9 CBLANK Output Waveform Generation
Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 406 of 1130
REJ09B0327-0400
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 407 of 1130
REJ09B0327-0400
Section 14 Watchdog Timer (WDT)
14.1 Overview
This LSI have an on-chip watchdog timer with two channels (WDT0, WDT1) for monitoring
system operation. The WDT outputs an overflow signal (RESO) if a system crash prevents the
CPU from writin g to the timer counter, allo wing it to overflow. At the same time, the WDT can
also gener ate an internal reset signa l or internal NMI interrup t sig nal.
When this watchdog function is not needed, the WDT can be used as an in terval timer. In interval
timer mode, an interval timer interrupt is generated each time the counter overflows.
14.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• Internal reset o r internal interrupt generated when th e tim er counter overflows
WOVI interrupt generation in interval timer mode
Choice of internal reset or NMI interrupt generation in watchdog timer mode
• RESO output in watchdog timer mode
In watchdog timer mode, a low-level signal is ou tput from the RESO pin when the counter
overflows (when internal reset is selected)
• Choice of 8 (WDT0) or 16 (WDT1) counter input clocks
Maximum WDT interval: system clock period × 13107 2 × 256
Subclock can be selected for the WDT1 input counter
Maximum in ter val when the subclock is selected: subclock period × 256 × 256
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 408 of 1130
REJ09B0327-0400
14.1.2 Block Diagram
Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1.
Overflow
WOVI0
(interrupt request
signal)
Internal reset
signal*1
RESO signal*1
TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock Clock
select
Internal clock
source
Bus
interface
Module bus
Internal bus
WDT0
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
Internal NMI
interrupt request
signal*2
Interrupt
control
Reset
control
Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT
in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over
the internal reset signal.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (a) Block Diagram of WDT0
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 409 of 1130
REJ09B0327-0400
Overflow
TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock Clock
select
Interrupt
control
Reset
control
Internal clock
source
Bus
interface
Module bus
Internal bus
WDT1
WOVI1
(interrupt request
signal)
Internal reset
signal*
1
Internal NMI
(interrupt request
signal)*
2
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
φ
SUB
/2
φ
SUB
/4
φ
SUB
/8
φ
SUB
/16
φ
SUB
/32
φ
SUB
/64
φ
SUB
/128
φ
SUB
/256
RESO signal*
1
Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT
in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over
the internal reset signal.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (b) Block Diagram of WDT1
14.1.3 Pin Configuration
Table 14.1 describes the WDT input pin.
Table 14.1 WDT Pin
Name Symbol I/O Function
Reset output pin RESO Output Watchdog tim er mode counter ov erflow si gna l
output
External subclo ck inp ut pin EXC L Input WDT1 prescaler counter inp ut clock
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 410 of 1130
REJ09B0327-0400
14.1.4 Register Configuration
The WDT has four registers, as summarized in table 14.2. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 14.2 WDT Registers
Address*1
Channel Name Abbreviation R/W Initial Value Write*2Read
0 Timer control/status
register 0 TCSR0 R/(W)*3H'00 H'FFA8 H'FFA8
Timer counter 0 TCNT0 R/W H'00 H'FFA8 H'FFA9
1 Timer control/status
register 1 TCSR1 R/(W)*3H'00 H'FFEA H'FFEA
Timer counter 1 TCNT1 R/W H'00 H'FFEA H'FFEB
Comm on System control
register SYSCR R/W H'09 H'FFC4 H'FFC4
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 14.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
14.2 Register Descriptions
14.2.1 Timer Counter (TCNT)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts cou nting pulses generated from the in ter nal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF flag in TCSR is set to 1. Watchdog timer overflow signal (RESO) output,
an internal reset, NMI interrupt, interval timer interrup t (WOVI), etc., can be generated , depending
on the mode selected by the WT/IT bit and RST/NMI bit.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 411 of 1130
REJ09B0327-0400
TCNT is initialized to H'00 by a reset, in hardware standby mod e, or wh en the TME bit is cleared
to 0. It is no t initialized in software standby mode.
Note: * T CNT is write-protected by a password to prevent accidental overwriting. For details
see section 14.2.4, Notes on Register Access.
14.2.2 Timer Control/Status Register (TCSR)
• TCSR0
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
RSTS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
• TCSR1
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
TCSR is an 8-b it r eadable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * T CSR is write-protected by a password to prevent accidental ov erwriting. For details
see section 14.2.4, Notes on Register Access.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 412 of 1130
REJ09B0327-0400
Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF
to H'00.
Bit 7
OVF Description
0 [Clearing conditions ]
• Write 0 in the TME bit (Initial value)
• Read TCSR when OVF = 1*, then write 0 in OVF
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.)
Note: *When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read
at least twice.
Bit 6—Timer Mode Select (WT/IT
ITIT
IT): Selects whether the WDT is used as a watchdog timer or
interval timer. I f used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI
interrupt when TCNT overflows. When inter nal reset is selected in watchd og timer mode, a low-
level signal is output from the RESO pin.
Bit 6
WT/IT
ITIT
IT Description
0 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when
TCNT overflows (Initial value)
1 Watchdog timer mode: Generates a reset or NMI interrupt when TCNT overflows
At the same time, a low-level signal is output from the RESO pin (when internal reset
is selected)
Bit 5—Timer Enable (TME) : Selects whether TCNT runs or is halted.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted (Initial value)
1 TCNT counts
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 413 of 1130
REJ09B0327-0400
TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1.
TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For
details, see the descr iption of the CKS2 to CKS0 bits belo w.
WDT1 TCSR
Bit 4
PSS Description
0 T CNT counts φ-based prescaler (PSM) divided clock pulses (Initial value)
1 T CNT counts φSUB-based prescaler (PSS) divided clock pulses
Bit 3—Reset or NMI (RST/NMI
NMINMI
NMI): Specifies whether an internal reset or NMI interrupt is
requested on TCNT overflow in watchdog timer mode.
Bit 3
RST/NMI
NMINMI
NMI Description
0 An NMI interrupt is requested (Initial value)
1 An internal reset is requested
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ), or subclock (φSUB) for input to TCNT.
• WDT0 input clock selection
Bit 2 Bit 1 Bit 0 Description
CKS2 CKS1 CKS0 Clock Overflow Period* (when φ
φφ
φ = 20 MHz)
000 φ/2 (Initial value) 25.6 µs
1φ/64 819.2 µs
10 φ/128 1.6 ms
1φ/512 6.6 ms
100 φ/2048 26.2 ms
1φ/8192 104.9 ms
10 φ/32768 419.4 ms
1φ/131072 1.68 s
Note: *The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 414 of 1130
REJ09B0327-0400
• WDT1 input clock selection
Bit 4 Bit 2 Bit 1 Bit 0 Description
PSS CKS2 CKS1 CKS0 Clock Overflow Period* (whe n φ
φφ
φ = 20 MHz
and φ
φφ
φSUB = 32.768 kHz)
0000 φ/2 (Initial value) 25.6 µs
1φ/64 819.2 µs
10 φ/128 1.6 ms
1φ/512 6.6 ms
100 φ/2048 26.2 ms
1φ/8192 104.9 ms
10 φ/32768 419.4 ms
1φ/131072 1.68 s
1000 φSUB/2 15.6 ms
1φSUB/4 31.3 ms
10 φSUB/8 62.5 ms
1φSUB/16 125 ms
100 φSUB/32 250 ms
1φSUB/64 500 ms
10 φSUB/128 1 s
1φSUB/256 2 s
Note: *The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.
14.2.3 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overf low in addition to external reset input. XRST is a
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 415 of 1130
REJ09B0327-0400
read-only bit. It is set to 1 by an external reset, and when the RST/NMI bit is 1, is cleared to 0 by
an internal re set due to watchdog timer overflow.
Bit 3
XRST Description
0 Reset is generated by watchdog timer overflow
1 Reset is generated by external reset inp ut (Initial value)
14.2.4 Notes on Register Access
The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult
to write to. The procedures for writing to and reading these registers are given below.
Writing to TCNT and TCSR (Example of WDT0)
These registers must be written to by a word transfer instruction. They cannot be written to with
byte transfer instructions.
Figure 14 .2 sh ows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the wr itten word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
TCSR write
Address: H'FFA8
Address: H'FFA8
H'5A Write data
15 8 7 0
H'A5 Write data
15 8 7 0
Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0)
Reading TCNT and TCSR (Example of WDT0)
These registers are read in the same way as other registers. The read addresses are H'FFA8 for
TCSR, and H'FFA9 fo r T CNT.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 416 of 1130
REJ09B0327-0400
14.3 Operation
14.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must
prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error, an
internal reset or NMI interrup t request is generated.
When the RST/NMI bit is set to 1, the chip is reset for 518 system clock periods (518 φ) by a
counter overflow, and at the same time a low-level signal is output from the RESO pin for 132
states. This is illustr a ted in figure 14.3 . The sy stem can be reset using this RESO signal.
When the RST/NMI bit cleared to 0, an NMI interrupt request is generated by a counter overflow.
In this case, the RESO output signal remains high.
An internal re set r e quest f r om the watchdog timer and reset in put f r om th e RES pin are handled
via the same vecto r. The reset source can be identified fro m the v a lue of the XRST bit in SYSCR.
If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1.
An NMI interrupt re quest f r om the watchdog timer and an in terrupt request from the NMI pin are
handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request
and an NMI pin interrupt request must therefore be avoided.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 417 of 1130
REJ09B0327-0400
TCNT value
H'00 Time
H'FF
WT/IT = 1
TME = 1 H'00 written
to TCNT WT/IT = 1
TME = 1 H'00 written
to TCNT
518 system
clock periods
Internal reset signal
Legend:
Overflow
RESO and internal
reset generated
OVF = 1*
RESO signal
WT/IT: Timer mode select bit
TME: Timer enable bit
OVF: Overflow flag
Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.
132 system
clock periods
Figure 14.3 Operation in Watchdog Timer Mode (RST/NMI
NMINMI
NMI = 1)
14.3.2 Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.
An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the
WDT is operating as an interval timer, as shown in figure 14.4. This function can be used to
generate interrupt requests at regular intervals.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 418 of 1130
REJ09B0327-0400
TCNT count
H'00 Time
H'FF
WT/IT = 0
TME = 1 WOVI
Overflow Overflow Overflow Overflow
Legend:
WOVI: Interval timer interrupt request generation
WOVI WOVI WOVI
Figure 14.4 Operation in Interval Timer Mode
14.3.3 Timing of Setting of Overflow Flag (OVF)
The OVF flag is set to 1 if TCNT overflows during in ter val timer operation. At the sam e time, an
interval timer interrupt (WOVI) is req uested. This timing is sh own in figure 14.5.
If NMI request generation is selected in watchdog timer mode, when TCNT overflows the OVF
bit in TCSR is set to 1 and at the same time an NMI interrupt is re quested.
φ
TCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 14.5 Timing of OVF Setting
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 419 of 1130
REJ09B0327-0400
14.3.4 RESO
RESORESO
RESO Signal Output Timing
When TCNT over flows in watchdog tim er mod e , the OVF bit is set to 1 in TCSR. If the RST/NMI
bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a
low-level signal is output from the RESO pin. The timing is shown in figure 14.6.
φ
TCNT H'FF H'00
132 states
518 states
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
Figure 14.6 RESO
RESORESO
RESO Signal Output Timing
14.4 Interrupts
During interval timer mode operation, an overflow gener ates an interval timer interrupt (WOVI) .
The interval timer interrupt is requested wh enever the OVF flag is set to 1 in TCSR. OVF mu st be
cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in
watchdog timer mode, an overflow generates an NMI interrupt request.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 420 of 1130
REJ09B0327-0400
14.5 Usage Notes
14.5.1 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 14.7 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT NM
T
1
T
2
TCNT write cycle
Counter write data
Figure 14.7 Contention between TCNT Write and Increment
14.5.2 Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, error s could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0 ) before
changing the value of bits CKS2 to CKS0.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 421 of 1130
REJ09B0327-0400
14.5.3 Switching between Watchdo g Timer Mode a nd Int erval Timer Mo de
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
14.5.4 System Reset by RESO
RESORESO
RESO Signal
If the RESO outp ut signal is input to the chip’s RES pin, the chip will not be initialized correctly.
Ensure that th e RESO signal is not logically input to the chip’s RES pin. Wh en resetting the entire
system with the RESO signal, use a circuit such as that shown in figure 14.8.
Reset input
Reset signal to entire system
Chip
RES
RESO
Figure 14.8 Sample Circuit for System Reset by RESO
RESORESO
RESO Signal
14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode, and
Watch Mo de
If the mode is switched between high-speed mode and subactive mode or between high-speed
mode and watch mode when WDT1 is u sed as a r ealtime clock counter, an error will occur in the
counter value when the internal clock is switched.
When the mode is switched from high-speed mode to subactive mode or watch mode, the
increment timing is delayed by approximately 2 or 3 clock cycles when th e WDT1 control clock is
switched fro m the main clock to the subclock.
Also, since the main clock oscillator is halted during subclock operation, when the mode is
switched from watch mode or subactive mode to high-speed mode, the clock is not supplied until
internal oscillation stabilizes. As a result, after oscillation is started, counter incremen ting is halted
during the oscillation stabilization time set by bits STS2 to STS0 in SBYCR, and there is a
corresponding discrepancy in the counter value.
Section 14 Wa tchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 422 of 1130
REJ09B0327-0400
Caution is therefore required when using WDT1 as the realtime clock counter.
No error occurs in the counter value while WDT1 is operating in the same mode.
14.5.6 OVF Flag Clear Condition
To clear OVF flag in WOVI handling routine, read TCSR when OVF = 1 , then write with 0 to
OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF
flag set and TCSR read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0
to OVF.
In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear
condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF.
LOOP BTST.B #7, @TCSR ; OVF flag read
BEQ LOOP ; if OVF=1, exit from loop
MOV.B @TCSR, R0L ; OVF=1 read again
MOV.W #H'A521, R0 ; OVF flag clear
MOV.W R0,@TCSR ; :
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 423 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
15.1 Overview
This LSI are equipped with a 3-channel serial communication interface (SCI). The SCI can handle
both asynchronous and clocked synchronous serial communication. A function is also provided for
serial commu nication between processor s (multiprocessor communication f unction).
One of the three SCI channels can transmit and receive IrDA communication waveforms based on
IrDA specification version 1.0.
15.1.1 Features
SCI features are listed below.
• Choice of asynchronous or synchronous serial communication mode
Asynchronous mode:
Serial data communication is executed using an asyn chronous system in which
synchronization is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Un iversal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
A multipro cessor communicatio n function is provided that enables serial data
communication with a number of processors
Choice of 12 serial data transfer formats
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Multiprocessor bit: 1 or 0
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level
directly in case of a framing error
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 424 of 1130
REJ09B0327-0400
Synchronous mode:
Serial data communication is synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
commun ication function
One serial data transfer format
Data length: 8 bits
Receive error detection: Overrun errors detected
• Full-duplex communication capab ility
The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• LSB-first or MSB-first transfer can be selected
This selection can be made regardless of the communication mode (with the exception of
7-bit data transfer in asynchronous mode)*
Note: * L SB-first transfer is used in the exam ples in this section.
• Built-in bau d rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Capability of transmit and receive clock output
The P86/SCK1 and P42/SCK2 pins are CMOS type outputs
The P52/SCK0 pin is an NMOS push-pull type output in the H8S/2148 Group and
H8S/2147N, and is a CMOS output in the H8S/2144 Group (When the P52/SCK0 pin is
used as an outpu t in the H8S/2148 Group and H8S/2147N, external pull-up resistor must be
connected in order to output high level)
• The transmit-data-empty interrupt and receive-data-full interrupt can activate the data transfer
controller ( DTC) to execute data transfer
• Four interrupt sources
Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive
error) that can issue requests independently
The transmit-data-empty interrupt and receive-data-full interrupt can activate the data
transfer controller (DTC) to execute data transfer
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 425 of 1130
REJ09B0327-0400
15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the SCI.
Bus interface
TDR
RSR
RDR
Module data bus
TSR
SSR
SCMR
SCR
SMR
Transmission/
reception control
BRR
Baud rate
generator
Internal
data bus
RxD
TxD
SCK
Parity generation
Parity check
Clock
External clock
φ
φ/4
φ/16
φ/64
TXI
TEI
RXI
ERI
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
SCMR: Serial interface mode register
BRR: Bit rate register
Figure 15.1 Block Diagram of SCI
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 426 of 1130
REJ09B0327-0400
15.1.3 Pin Configuration
Table 15.1 shows the serial pins used by the SCI.
Table 15.1 SCI Pins
Channel Pin Name Symbol*I/O Function
0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output
Receive data pin 0 RxD0 Input SCI0 receive data input
Transmit data pin 0 TxD0 Output SCI0 transmit data output
1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output
Receive data pin 1 RxD1 Input SCI1 receive data input
Transmit data pin 1 TxD1 Output SCI1 transmit data output
2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output
Receive data pin 2 RxD2/IrRxD Input SCI2 receive data input
(normal/IrDA)
Transmit data pin 2 TxD2/IrTxD Output SCI2 transmit data output
(normal/IrDA)
Note: *The abbreviations SCK, RxD, and TxD are used in the text, omitting the channel
number.
15.1.4 Register Configuration
The SCI has the internal registers shown in table 15.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the
transmitter/receiver.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 427 of 1130
REJ09B0327-0400
Table 15.2 SCI Registers
Channel Name Abbreviation R/W Initial Value Address*1
0 Serial mode register 0 SMR0 R/W H'00 H'FFD8*3
Bit rate register 0 BRR0 R/W H'FF H'FFD9*3
Serial control register 0 SCR0 R/W H'00 H'FFDA
Transmit data register 0 TDR0 R/W H'FF H'FFDB
Serial status register 0 SSR0 R/(W)*2H'84 H'FFDC
Receive dat a register 0 RDR0 R H'00 H'FFDD
Serial interface mode register 0 SCMR0 R/W H'F2 H'FFDE*3
1 Serial mode register 1 SMR1 R/W H'00 H'FF88*3
Bit rate register 1 BRR1 R/W H'FF H'FF89*3
Serial control register 1 SCR1 R/W H'00 H'FF8A
Transmit data register 1 TDR1 R/W H'FF H'FF8B
Serial status register 1 SSR1 R/(W)*2H'84 H'FF8C
Receive data regist er 1 RDR1 R H'0 0 H'FF8D
Serial interface mode register 1 SCMR1 R/W H'F2 H'FF8E*3
2 Serial mode register 2 SMR2 R/W H'00 H'FFA0*3
Bit rate register 2 BRR2 R/W H'FF H'FFA1*3
Serial control register 2 SCR2 R/W H'00 H'FFA2
Transmit data register 2 TDR2 R/W H'FF H'FFA3
Serial status register 2 SSR2 R/(W)*2H'84 H'FFA4
Receive data register 2 RDR2 R H'00 H'FFA5
Serial interface mode register 2 SCMR2 R/W H'F2 H'FFA6*3
Keyboard compara tor contr ol
register KBCOMP R/W H'00 H'FEE4
Common Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
3. Some serial communication interface registers are assigned to the same addresses as
other registers. In this case, register selection is performed by the IICE bit in the serial
timer control register (STCR).
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 428 of 1130
REJ09B0327-0400
15.2 Register Descriptions
15.2.1 Receive Shift Register (RSR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit
Read/Write
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferr ed to RDR automatically.
RSR cannot be directly read or written to by the CPU.
15.2.2 Receive Data Register (RDR)
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Initial value
Read/Write
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, continuous receive operations can be
performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mod e , subsleep
mode, and module stop mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 429 of 1130
REJ09B0327-0400
15.2.3 Transmit Shift Register (TSR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit
Read/Write
TSR is a register used to transmit serial d ata.
To perform serial data transmission , the SCI first transfers transmit data from TDR to TSR, then
sends the data to the TxD pin starting with the LSB (bit 0).
When transm ission of one byte is completed, the nex t tr ansmit data is transf erred from TDR to
TSR, and transm ission started, au tomatically. Howev er, d ata transfer from TDR to TSR is not
performed if the TDRE bit in SSR is set to 1.
TSR cannot be directly read or written to by the CPU.
15.2.4 Transmit Data Register (TDR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
TDR is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR is empty , it transfers the tr ansmit data written in TDR to TSR and
starts serial transmission. Continuous serial transmission can be carried out by writing the next
transmit data to TDR during serial transmission of the data in TSR.
TDR can be read or written to by the CPU at all times.
TDR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 430 of 1130
REJ09B0327-0400
15.2.5 Serial Mode Register (SMR)
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read o r written to by the CPU at all times.
SMR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Communication Mode (C/A
AA
A): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7
C/A
AA
ADescription
0 Asynchronous mode (Initial value
)
1 Synchronous mode
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR Description
0 8-bit data (Initial value
)
1 7-bit data*
Note: *When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSB-
first/MSB-first sel ect ion is not ava ila ble.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 431 of 1130
REJ09B0327-0400
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, or when a
multipro cessor format is used, p arity bit addition and check ing is not performed, rega rdless o f the
PE bit setting.
Bit 5
PE Description
0 Parity bit addition and checking disabled (Initial value
)
1 Parity bit addition and checking enabled*
Note: *When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
Bit 4—Parity Mode (O/E
EE
E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is on ly valid when the PE bit is set to 1 , enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity
bit addition and checking is disabled in async hronous mode, and when a multiprocessor format is
used.
Bit 4
O/E
EE
EDescription
0 Even parity*1 (Initial value
)
1 Odd parity*2
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bi ts in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bi ts in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 432 of 1130
REJ09B0327-0400
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP
bit setting is invalid since stop bits are not added.
Bit 3
STOP Description
01 stop bit
*1 (Initial value
)
1 2 stop bits*2
Notes: 1. In transmission, a single 1 bi t (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit settin g. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as th e star t bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit p a r ity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocesso r communication fun c tion, see section 15.3.3, Multipr ocessor
Communication Function.
Bit 2
MP Description
0 Multiprocessor func tion disabled (Initial value
)
1 Multiprocessor format selected
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source fo r the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.8, Bit Rate Register (BRR).
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 433 of 1130
REJ09B0327-0400
Bit 1 Bit 0
CKS1 CKS0 Description
00φ clock (Initial value)
1φ/4 clock
10φ/16 clock
1φ/64 clock
15.2.6 Serial Control Register (SCR)
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit
Initial value
Read/Write
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrup t
(TXI) request generation when serial transmit d a ta is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1 .
Bit 7
TIE Description
0 Transmit-data-empty interrupt (TXI) request disabled* (Initial value
)
1 Transmit-data-empty interrupt (TXI) request enabled
Note: *TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
then clearing it to 0, or clearing the TIE bit to 0.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 434 of 1130
REJ09B0327-0400
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE Description
0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
disabled* (Initial value
)
1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
enabled
Note: *RXI and ERI interrupt request canc ellation can be performed by reading 1 from the
RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE Description
0 Transmission disabl ed*1 (Initial value
)
1 Transmission enabled*2
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transmission format before setting the TE
bit to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE Description
0 Reception disabled *1 (Initial value
)
1 Reception enabled*2
Notes: 1. Cl earing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SMR setting must be performed to decide the reception format before setting the RE bit
to 1.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 435 of 1130
REJ09B0327-0400
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or d isables multiprocessor interrup ts.
The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR
set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multiprocessor interrupts disabled (normal reception performed) (Initial value
)
[Clearing cond iti ons ]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1 Multiprocessor interrupts enabled*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: *When receive data including MPB = 0 is received, receive data transfer from RSR to
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR,
is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is
set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request g e neration if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2
TEIE Description
0 Transmit-end interrupt (TEI) request disabled* (Initial value
)
1 Transmit-end interrupt (TEI) reques t enabled*
Note: *TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 436 of 1130
REJ09B0327-0400
external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out
before the SCI’s operating mode is determined using SMR.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1 Bit 0
CKE1 CKE0 Description
0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port*1
Synchronous mo de Internal clock/SCK pin f un ctions as seri al clo ck
output*1
1 Asynchronou s mode Internal clo ck/SCK pin fun ctio ns as clock output*2
Synchronous mo de Internal clock/SCK pin f un ctio ns as seri al clo ck
output
1 0 Asynchronous mode External clock/SCK pin function s as clo ck input*3
Synchronous mo de External clock/SCK pin functions as serial clock
input
1 Asynchronou s mode External clo ck/SCK pin fun ction s as clo ck input*3
Synchronous mo de External clock/SCK pin functions as serial clock
input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
15.2.7 Serial Status Register (SSR)
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Bit
Initial value
Read/Write
Note: *Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multipr ocessor bits.
SSR can be read o r wr itten to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 437 of 1130
REJ09B0327-0400
SSR is initialized to H'8 4 by a reset, and in stan dby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE Description
0 [Clearing conditions ]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions] (Initial value)
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF Description
0 [Clearing conditions] (Initial value)
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 438 of 1130
REJ09B0327-0400
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER Description
0 [Clearing condition] (Initial value)*1
When 0 is written in ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1*2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER Description
0 [Clearing condition] (Initial value)*1
When 0 is written in FER after reading FER = 1
1 [Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception ends,
and the stop bit is 0*2
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 439 of 1130
REJ09B0327-0400
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 3
PER Description
0 [Clearing condition] (Initial value)*1
When 0 is written in PER after reading PER = 1
1[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
match the parity setting (even or odd) specified by the O/E bit in SMR*2
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Bit 2—Transmit End (T EN D ): Indicates that there is no valid d a ta in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND Description
0 [Clearing conditions ]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1[Setting conditions] (Initial value
)
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 440 of 1130
REJ09B0327-0400
Bit 1—Multiprocessor Bit (MPB): When reception is performed using a multipro cesso r format
in asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB Description
0 [Clearing condition] (Initial value)
*
When data with a 0 multiprocessor bit is received
1 [Setting condition]
When data with a 1 multiprocessor bit is received
Note: *Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
format.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor form at is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT Description
0 Data with a 0 multiprocessor bit is transmitted (Initial value
)
1 Data with a 1 multiprocessor bit is transmitted
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 441 of 1130
REJ09B0327-0400
15.2.8 Bit Rate Register (BRR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all tim es.
BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 1 5.3 shows sam ple BRR settin gs in async hronou s mode, and table 15.4 shows sample BRR
settings in synchronous mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 442 of 1130
REJ09B0327-0400
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ
φφ
φ (MHz)
φ
φφ
φ = 2 MHz φ
φφ
φ = 2.097152 MHz φ
φφ
φ = 2.4576 MHz φ
φφ
φ = 3 MHz
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34
9600 ———06–2.48 0 7 0.00 0 9 –2.34
19200 ——————030.0004–2.34
31250 0 1 0.00 ——————020.00
38400 ——————010.00———
Operating Frequency φ
φφ
φ (MHz)
φ
φφ
φ = 3.6864 MHz φ
φφ
φ = 4 MHz φ
φφ
φ = 4.9152 MHz φ
φφ
φ = 5 MHz
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25
150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16
300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16
600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36
9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 5 0.00 ———070.00071.73
31250 ———030.0004–1.70 0 4 0.00
38400 0 2 0.00 ———030.00031.73
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 443 of 1130
REJ09B0327-0400
Operating Frequency φ
φφ
φ (MHz)
φ
φφ
φ = 6 MHz φ
φφ
φ = 6.144 MHz φ
φφ
φ = 7.3728 MHz φ
φφ
φ = 8 MHz
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40 ———070.00
38400 0 4 –2.34040.00050.00———
Operating Frequency φ
φφ
φ (MHz)
φ
φφ
φ = 9.8304 MHz φ
φφ
φ = 10 MHz φ
φφ
φ = 12 MHz φ
φφ
φ = 12.288 MHz
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08
150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00
300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00
600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00
1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00
2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00
4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00
9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00
19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00
31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40
38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 444 of 1130
REJ09B0327-0400
Operating Frequency φ
φφ
φ (MHz)
φ
φφ
φ = 14 MHz φ
φφ
φ = 14.7456 MHz φ
φφ
φ = 16 MHz φ
φφ
φ = 17.2032 MHz
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48
150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00
300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00
600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00
1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00
2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00
4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00
9600 0 45 –0.93 0 47 0.00 0 51 0.16 0 55 0.00
19200 0 22 –0.93 0 23 0.00 0 25 0.16 0 27 0.00
31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 16 1.20
38400 ———0 11 0.00 0 12 0.16 0 13 0.00
Operating Frequency φ
φφ
φ (MHz)
φ
φφ
φ = 18 MHz φ
φφ
φ = 19.6608 MHz φ
φφ
φ = 20 MHz
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%)
110 3 79 –0.12 3 86 0.31 3 88 –0.25
150 2 233 0.16 2 255 0.00 3 64 0.16
300 2 116 0.16 2 127 0.00 2 129 0.16
600 1 233 0.16 1 255 0.00 2 64 0.16
1200 1 116 0.16 1 127 0.00 1 129 0.16
2400 0 233 0.16 0 255 0.00 1 64 0.16
4800 0 116 0.16 0 127 0.00 0 129 0.16
9600 0 58 –0.69 0 63 0.00 0 64 0.16
19200 0 28 1.02 0 31 0.00 0 32 –1.36
31250 0 17 0.00 0 19 –1.70 0 19 0.00
38400 0 14 –2.34 0 15 0.00 0 15 1.73
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 445 of 1130
REJ09B0327-0400
Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode)
Operating Frequency φ
φφ
φ (MHz)
Bit Rate φ
φφ
φ = 2 MHz φ
φφ
φ = 4 MHz φ
φφ
φ = 8 MHz φ
φφ
φ = 10 MHz φ
φφ
φ = 16 MHz φ
φφ
φ = 20 MHz
(bits/s) nNnNnNnNnNnN
110 3 70 ——
250 2 124 2 249 3 124 ——3 249
500 1 249 2 124 2 249 ——3 124 ——
1 k 1 124 1 249 2 124 ——2 249 ——
2.5 k 0 199 1 99 1 199 1 249 2 99 2 124
5 k 0 99 0 199 1 99 1 124 1 199 1 249
10 k 0 49 0 99 0 199 0 249 1 99 1 124
25 k 0 19 0 39 0 79 0 99 0 159 0 199
50 k 0 9 0 19 0 39 0 49 0 79 0 99
100 k 0 4 0 9 0 19 0 24 0 39 0 49
250 k 0 1 0 3 0 7 0 9 0 15 0 19
500 k 0 0*0103040709
1 M 0 0*01 0304
2.5 M 0 0*01
5 M 00
*
Legend:
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
*: Continuous transfer is not possible.
Note: As far as possible, the setting should be made so that the error is no more than 1%.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 446 of 1130
REJ09B0327-0400
The BRR setting is found from the following equations.
Asynchronous mode:
N = × 10
6
– 1
64 × 2
2n–1
× B
φ
Synchronous mode:
N = × 10
6
– 1
8 × 2
2n–1
× B
φ
Where B: Bit rate (bits/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n Clock CKS1 CKS0
0φ00
1φ/4 0 1
2φ/16 1 0
3φ/64 1 1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) = – 1 × 100
(N + 1) × B × 64 × 22n–1
× 106
φ
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 447 of 1130
REJ09B0327-0400
Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6
and 15.7 show the maximum bit rates with external clock input.
Table 15.5 Maximum Bit Rat e for Each Frequency (Asynchronous Mode)
φ
φφ
φ (MHz) Maximum Bit Rate (bits/s) n N
2 62500 0 0
2.097152 65536 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
14.7456 460800 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
19.6608 614400 0 0
20 625000 0 0
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 448 of 1130
REJ09B0327-0400
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ
φφ
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)
2 0.5000 31250
2.097152 0.5243 32768
2.4576 0.6144 38400
3 0.7500 46875
3.6864 0.9216 57600
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
12 3.0000 187500
12.288 3.0720 192000
14 3.5000 218750
14.7456 3.6864 230400
16 4.0000 250000
17.2032 4.3008 268800
18 4.5000 281250
19.6608 4.9152 307200
20 5.0000 312500
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 449 of 1130
REJ09B0327-0400
Table 15.7 Maximum Bit Rat e with External Clo c k Input (Synchro nous Mode)
φ
φφ
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)
2 0.3333 333333.3
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
20 3.3333 3333333.3
15.2.9 Serial Interface Mode Register (SCMR)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit
Initial value
Read/Write
SCMR is an 8-bit readable/writab le r egister u sed to select SCI functio ns.
SCMR is initial ized to H'F2 by a reset, and in standby mode, watch mode, subactive mod e ,
subsleep mode, and module stop mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3
SDIR Description
0 TDR contents are transmitted LSB-first (Initial value
)
Receive data is stored in RDR LSB-first
1 TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 450 of 1130
REJ09B0327-0400
Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does no t
affect the log ic level of the parity bit(s): p a r ity bit inversion r equ ir e s inversion of the O/E bit in
SMR.
Bit 2
SINV Description
0 TDR contents are transmitted without modification (Initial value
)
Receive data is stored in RDR without modification
1 TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be
written in this bit.
Bit 0
SMIF Description
0 Normal SCI mode (Initial value
)
1 Reserved mode
15.2.10 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bit MSTP7, MSTP6, or MSTP5 is set to 1, SCI0, SCI1, or SCI2 operation, respectively,
stops at the end of th e bus cycle and a transition is m ade to module stop mode. For details, see
section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 451 of 1130
REJ09B0327-0400
Bit 7—Module Stop (MSTP7): Specifies the SCI0 module stop mode.
MSTPCRL
Bit 7
MSTP7 Description
0 SCI0 module stop mode is cleared
1 SCI0 module stop mode is set (Initial value
)
Bit 6—Module Stop (MSTP6): Specifies the SCI1 module stop mode.
MSTPCRL
Bit 6
MSTP6 Description
0 SCI1 module stop mode is cleared
1 SCI1 module stop mode is set (Initial value
)
Bit 5—Module Stop (MSTP5): Specifies the SCI2 module stop mode.
MSTPCRL
Bit 5
MSTP5 Description
0 SCI2 module stop mode is cleared
1 SCI2 module stop mode is set (Initial value
)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 452 of 1130
REJ09B0327-0400
15.2.11 Keyboard Comparator Control Register (KBCOMP)
7
IrE
0
R/W
6
IrCKS2
0
R/W
5
IrCKS1
0
R/W
4
IrCKS0
0
R/W
3
KBADE
0
R/W
0
KBCH0
0
R/W
2
KBCH2
0
R/W
1
KBCH1
0
R/W
Bit
Initial value
Read/Write
KBCOMP is an 8-bit readable/writable r e gister that selects the functions of SCI2 and the A/D
converter.
KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—IrD A Enable ( IrE): Specifies normal SCI operation or IrDA operation for SCI2
input/output.
Bit 7
IrE Description
0 The TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2 (Initial value
)
1 The TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD
Bits 6 to 4—IrDA Clock Select 2 to 0 (IrCKS2 to IrCKS0): These bits specify the high pulse
width in IrTxD output pulse encoding when the IrDA function is enabled.
Bit 6 Bit 5 Bit 4
IrCKS2 IrCKS1 IrCKS0 Description
000B × 3/16 (3/16 of the bit rate) (Initial value)
1φ/2
10φ/4
1φ/8
100φ/16
1φ/32
10φ/64
1φ/128
Bits 3 to 0—Keyboard Comparator Control: See the description in section 20, A/D converter.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 453 of 1130
REJ09B0327-0400
15.3 Operation
15.3.1 Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using SMR
as shown in table 15.8. The SCI clock is determined by a combination of the C/A bit in SMR and
the CKE1 and CKE0 bits in SCR, as shown in table 15.9.
Asynchronous Mode:
• Data length: Choice of 7 or 8 bits
• Choice of p a r ity addition, multiprocesso r bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI clock source
When internal clock is selected:
The SCI operates on the baud rate generator clock and a clock with the same frequency as
the bit rate can be output
When external clock is selected:
A clock with a fr eque ncy of 16 times the bit rate must be input (the built-in bau d rate
generator is not used)
Synchronous Mode:
• Transfer format: Fixed 8-bit data
• Detection of overrun errors during reception
• Choice of internal or external clock as SCI clock source
When internal clock is selected:
The SCI operates on the baud rate generator clock and a serial clock is output off-chip
When external clock is selected:
The built-in baud rate generator is not used, and the SCI operates on the input ser ial clo c k
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 454 of 1130
REJ09B0327-0400
Table 15.8 SMR Settings and Serial Transfer Format Selection
SMR Settings SCI Transfer Format
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
C/A
AA
ACHR MP PE STOP Mode Data
Length
Multi-
processor
Bit Parity
Bit Stop Bit
Length
00000 8-bit dataNo No1 bit
1
Asynchronous
mode 2 bits
10 Yes1 bit
12 bits
1 0 0 7-bit data No 1 bit
12 bits
10 Yes1 bit
12 bits
01—0 8-bit data Yes No 1 bit
—12 bits
1 — 0 7-bit data 1 bit
— 1
Asynchronous
mode (multi-
processor f ormat)
2 bits
1————Synchronous mode 8-bit data No None
Table 15.9 SMR and SCR Settings and S CI Clock Source Selection
SMR SCR Setting SCI Transfer Clock
Bit 7 Bit 1 Bit 0
C/A
AA
ACKE1 CKE0 Mode Clock
Source SCK Pin Function
0 0 0 Internal SCI does not use SCK pin
1Asynchronous
mode Outputs clock with same frequency as bit
rate
10 External
1Inputs clock with frequency of 16 times
the bit rate
1 0 0 Intern al Outputs serial cl oc k
1Synchronous
mode
1 0 External Inputs serial clock
1
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 455 of 1130
REJ09B0327-0400
15.3.2 Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCI, the tran smitter and receive r are independ ent un its, en abling full-d uplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written du ring transmission or reception, en abling continuous data
transfer.
Figure 15.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchro nous mode, the SCI perfor m s sy nchronization at the fallin g edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit(s)
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data Parity
bit
1 bit 1 or
2 bits
7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 456 of 1130
REJ09B0327-0400
Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected by settings in SMR.
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings Serial Transfer Format and Frame Length
CHRPEMPSTOP 123456789101112
0000 S 8-bit data STOP
0001 S 8-bit data STOP STOP
0100 S 8-bit data PSTOP
0101 S 8-bit data PSTOP STOP
1000 S 7-bit data STOP
1001 S 7-bit data STOP STOP
1100 S 7-bit data PSTOP
1101 S 7-bit data PSTOP STOP
0 — 1 0 S 8-bit data MPB STOP
0 — 1 1 S 8-bit data MPB STOP STOP
1 — 1 0 S 7-bit data MPB STOP
1 — 1 1 S 7-bit data MPB STOP STOP
Legend:
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 457 of 1130
REJ09B0327-0400
Clock
Either an internal clock generated by the built-in baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table
15.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequen cy of the clock output in this case is equ al to the bit rate, and the phase is such th at the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
Figure 15.3 Relation between Output Clock and Transfer Data Phase
(Asynchrono us Mo de)
Data Transfer Operations
SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, first clear the
TE and RE bits in SCR to 0, then in itialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clear ing the RE bit to 0 does no t ch ange the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, sin ce operation is uncer tain.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 458 of 1130
REJ09B0327-0400
Figure 15.4 shows a sample SCI initialization flowchart.
Wait
<Initialization completed>
Start initialization
Set data transfer format in
SMR and SCMR
[1]
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits [4]
1-bit interval elapsed?
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. This is not
necessary if an external clock is
used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Figure 15.4 Sample SCI Initialization Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 459 of 1130
REJ09B0327-0400
Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for
serial tr a nsmission .
The following procedure should be used for serial data transmission.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1?
All data transmitted?
TEND = 1?
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
frame of 1s is output and
transmission is enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Figure 15.5 Sample Serial Transmission Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 460 of 1130
REJ09B0327-0400
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transf ers the data from TDR to TSR.
2. After tran sferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit d ata empty interrupt (TXI) is gene r a ted.
The serial transmit d a ta is sent from the TxD pin in th e follo wing order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Parity bit or multiprocessor bit:
One parity bit (even or odd parity) , or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is o utput can also be
selected.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously u ntil the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is clear ed to 0, the data is transferred from TDR to TSR, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a TEI interrupt request is generated.
Figure 15.6 shows an ex ample of the operation for transmission in asynchronous mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 461 of 1130
REJ09B0327-0400
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
DataStart
bit Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
TXI interrupt
request generated Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt handling routine TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 462 of 1130
REJ09B0327-0400
Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error handling
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER ∨ FER ∨ ORER = 1?
RDRF = 1?
All data received?
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
Receive error handling and
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
handling, ensure that the ORER,
PER, and FER flags are all
cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC is activated by an
RXI interrupt and the RDR value
is read.
[1]
[2] [3]
[4]
[5]
Figure 15.7 Sample Serial Reception Data Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 463 of 1130
REJ09B0327-0400
<End>
[3]
Error handling
Parity error handling
No
Yes
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error handling
No
Yes
Overrun error handling
ORER = 1?
FER = 1?
Break?
PER = 1?
Clear RE bit in SCR to 0
Figure 15.7 Sample Serial Reception Data Flowchart (cont)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 464 of 1130
REJ09B0327-0400
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in RSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
a. Parity check:
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
b. Stop bit check:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
c. Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred fro m RSR to RDR.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error* is detected in the error check, the operation is as shown in table 15.11.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE b it in SCR is set to 1 when the ORER, PER, or FER flag ch anges to 1, a
receive-error interrupt (ERI) request is generated.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 465 of 1130
REJ09B0327-0400
Table 15.11 Receive Errors and Conditions for Occurrence
Receive Error Abbreviation Occurrence Condition Data Transfer
Overrun error ORER When the next data reception is
completed while the RDRF flag
in SSR is set to 1
Receive data is not
transferred from RSR to
RDR
Framing error FER When the stop bit is 0 Receive data is tran sferre d
from RSR to RDR
Parity error PER When the received data differs
from the parity (even or odd) set
in SMR
Receive data is transferre d
from RSR to RDR
Figure 15.8 shows an example of the operation for reception in asynchronous mode.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
DataStart
bit Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
RXI interrupt
request
generated ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 466 of 1130
REJ09B0327-0400
15.3.3 Multiprocessor Communication Function
The multipr ocessor communication fun c tio n performs serial communicatio n using a
multipro cessor format, in wh ich a multiprocessor bit is ad ded to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharin g transm ission lines.
When multipro cessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiv in g station, and a data transmission cycle. The multiprocessor bit is used
to differentiate b e tween the ID transmission cycle and the data tran sm ission cycle.
The transmitting statio n first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multipr ocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station sk ips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multip rocessor bit is received, the receiving statio n compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multip rocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 15.9 shows an example of in ter-processor communication using a multip r ocessor format.
Data Transfer Format
There are four data transfer formats.
When a multiprocessor for m at is specified, the parity bit specif ication is invalid .
For details, see table 1 5.10.
Clock
See the section on asynchronous mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 467 of 1130
REJ09B0327-0400
Transmitting
station
Receiving
station A
(ID = 01)
Receiving
station B
(ID = 02)
Receiving
station C
(ID = 03)
Receiving
station D
(ID = 04)
Serial communication line
Serial
data
ID transmission cycle:
receiving station
specification
Data transmission cycle:
data transmission to
receiving station specified
by ID
(MPB = 1)
(MPB = 0)
H'01 H'AA
Legend:
MPB: Multiprocessor bit
Figure 15.9 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Statio n A)
Data Transfer Operations
Multiprocessor Serial Data Transmission: Figure 15.10 shows a sample flowchart for
multiprocessor serial da ta transmission .
The following procedure should be used for multiprocessor serial data transmission.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 468 of 1130
REJ09B0327-0400
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1?
All data transmitted?
TEND = 1?
Break output?
Clear TDRE flag to 0
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
frame of 1s is output and
transmission is enabled.
SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit-
data-empty interrupt (TXI)
request, and data is written to
TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
[1]
[2]
[3]
[4]
Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 469 of 1130
REJ09B0327-0400
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transf ers the data from TDR to TSR.
2. After tran sferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit-data-empty interrup t (TXI) is generated.
The serial transmit d a ta is sent from the TxD pin in th e follo wing order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Multiprocessor bit
One multipr ocessor bit (MPBT valu e) is output.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously u ntil the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is clear ed to 0, data is transferred from TDR to TSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a transmit-end interrupt (TEI) request is generated.
Figure 15.11 shows an exam ple of SCI oper ation for transmission using a multipr ocessor format.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 470 of 1130
REJ09B0327-0400
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
DataStart
bit
Multi-
proce-
ssor
bit Stop
bit Start
bit Data Multi-
proces-
sor bit Stop
bit
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt handling
routine
TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 15.11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.12 shows a sample flowchart for
multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 471 of 1130
REJ09B0327-0400
Yes
<End>
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR to 0
Error handling
(Continued on
next page)
[5]
No
Yes
FER ∨ ORER = 1?
RDRF = 1?
All data received?
Read MPIE bit in SCR [2]
Read ORER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
This station’s ID?
Read ORER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER ∨ ORER = 1?
Read receive data in RDR
RDRF = 1?
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
ID reception cycle:
Set the MPIE bit in SCR to 1.
SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
[1]
[2]
[3]
[4]
[5]
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 472 of 1130
REJ09B0327-0400
<End>
Error handling
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error handling
Overrun error handling
ORER = 1?
FER = 1?
Break?
Clear RE bit in SCR to 0
[5]
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 473 of 1130
REJ09B0327-0400
Figure 15.13 sh o ws an examp le of SCI op eration for multiprocessor format reception.
MPIE
RDR
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
1 1
Data (ID1)Start
bit MPB Stop
bit Start
bit Data (Data1) MPB Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
Idle state
(mark state)
RDRF
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
ID1
(a) Data does not match station’s ID
MPIE
RDR
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
1 1
Data (ID2)Start
bit
MPB Stop
bit Start
bit Data (Data2) MPB Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
Idle state
(mark state)
RDRF
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt handling routine
MPIE bit set to 1
again
ID2
(b) Data matches station’s ID
Data2ID1
Figure 15.13 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 474 of 1130
REJ09B0327-0400
15.3.4 Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, makin g
it suitable for high-speed serial communication.
Inside the SCI, the tran smitter and receive r are independ ent un its, en abling full-d uplex
communication by use of a common clock. Both the transmitter and th e receiver also h ave a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 15.14 shows the general format for synchronous serial communication.
Don’t
care
Don’t
care
One unit of transfer data (character or frame)
Bit 0
Serial
data
Serial
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
*
Note: * High except in continuous transfer
*
Figure 15.14 Data Format in Synchronous Communication
In synchronous serial commu nication, data on the transmission line is output from one falling ed ge
of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.
In synchronous serial communication, one character consists of data output starting with the LSB
and ending with the MSB. After the MSB is output, the transmission line holds the MSB state.
In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial
clock.
Data Transfer Format
A fixed 8-bit data format is used.
No parity or m ultiprocessor bits are added.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 475 of 1130
REJ09B0327-0400
Clock
Either an internal clock generated by the built-in baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1
and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive
operations in units of on e character, select an external clock as the clock source.
Data Transfer Operations
SCI Initializa tion (Synchro nous Mode): Before transmitting and receiving data, first clear the
TE and RE bits in SCR to 0, then in itialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clear ing the RE bit to 0 does no t ch ange the
settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 15.15 shows a sample SCI initialization f lowchart.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 476 of 1130
REJ09B0327-0400
Wait
<Transfer start>
Start initialization
Set data transfer format in
SMR and SCMR
No
Yes
Set value in BRR
Note: In simultaneous transmit and receive operations, the TE bit and RE bit should both be cleared
to 0 or set to 1 simultaneously.
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits [4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0) [1]
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the bit
rate to BRR. This is not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Figure 15.15 Sa mple SCI Initialization Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 477 of 1130
REJ09B0327-0400
Serial Data Transmission (Synchronous Mo de): Figure 15.16 shows a sample flowchart for
serial tr a nsmission .
The following procedure should be used for serial data transmission.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
Clear TE bit in SCR to 0
TDRE = 1?
All data transmitted?
TEND = 1?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR.
Figure 15.16 Sample Serial Transmission Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 478 of 1130
REJ09B0327-0400
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transf ers the data from TDR to TSR.
2. After tran sferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission . If the TIE bit is set to 1 at this time, a transmit- data-empty interrup t (TXI) is
generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7 ) .
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sen t, an d the
TxD pin maintains its state.
If the TEIE bit in SCR is set to 1 at this time, a tran smit-end inter rupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is held in a constant state.
Figure 15.17 shows an example of SCI operation in transmission.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 479 of 1130
REJ09B0327-0400
Transfer direction
Bit 0
Serial data
Serial clock
1 frame
TDRE
TEND
Bit 1 Bit 7 Bit 0 Bit 1 Bit 7Bit 6
Data written to TDR
and TDRE flag
cleared to 0 in TXI
interrupt handling routine
TEI interrupt
request generated
TXI interrupt
request generated
TXI interrupt
request generated
Figure 15.17 Example of SCI Operation in Transmission
Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to synchronous, be sure to check that the
ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not b e set if the FER or PER flag is set to 1 , and neither transmit nor receive
operatio ns will be possible.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 480 of 1130
REJ09B0327-0400
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Error handling
(Continued below)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1?
RDRF = 1?
All data received?
Read ORER flag in SSR
[1]
[2] [3]
[4]
[5]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
Receive error handling:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DTC is
activated by a receive-data-full
interrupt (RXI) request and the
RDR value is read.
<End>
Error handling
Overrun error handling
[3]
Clear ORER flag in SSR to 0
Figure 15.18 Sample Serial Reception Flowchart
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 481 of 1130
REJ09B0327-0400
In serial reception, the SCI operates as described below.
1. The SCI p erforms internal initialization in synchronization with serial clo ck input or output.
2. The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 15.19 shows an example of SCI operation in reception.
Bit 7
Serial
data
Serial
clock
1 frame
RDRF
ORER
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RXI interrupt request
generated RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated ERI interrupt request
generated by overrun
error
Figure 15.19 Example of SCI Operation in Reception
Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20
shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 482 of 1130
REJ09B0327-0400
Yes
<End>
[1]
No
Initialization
Start transmission/reception
[5]
Error handling
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1?
All data received?
[2]
Read TDRE flag in SSR
No
Yes
TDRE = 1?
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
RDRF = 1?
Read ORER flag in SSR
[4]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
[1]
[2]
[3]
[4]
[5]
SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
Receive error handling:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to
1.
SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR and clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC is activated by a receive-data-
full interrupt (RXI) request and the
RDR value is read.
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 483 of 1130
REJ09B0327-0400
15.3.5 IrDA Operation
Figure 15.21 shows a block diagram of the IrDA function.
When the IrDA function is enabled with bit IrE in KBCOMP, the SCI channel 2 TxD2 and RxD2
signals are subjected to waveform encoding/decoding conforming to IrDA specification version
1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is
possible to implement infrared transmission/reception conforming to the IrDA specification
version 1.0 system.
In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600
bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in the this
LSI does not include a function for varying the transfer rate automatically, th e tr ansfer rate setting
must be changed by software.
IrDA
Pulse encoder
Pulse decoder
KBCOMP
TxD2/IrTxD
RxD2/IrRxD
SCI2
TxD
RxD
Figure 15.21 Block Diagram of IrDA Function
Transmission
In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the
IrDA interface (see figure 15.22).
When the serial data is 0, a high-level pulses of 3/16 the bit rate (interval equivalent to the width
of one bit) is output (initial value). The high-level pulse can be varied according to the setting of
bits IrCKS2 to I rCKS0 in KBCOMP.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 484 of 1130
REJ09B0327-0400
The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) ×
bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set as the
minimum high-level pulse width at 1.41 µs or above.
When the serial data is 1, no pulse is output.
0000 0
UART frame
IR frame
Data
Data
Start
bit Stop
bit
Start
bit Stop
bit
11 111
0000 011 111
Pulse width is 1.6 µs
to 3/16 bit interval
Transmission Reception
Bit
interval
Figure 15.22 IrDA Transmit/Receive Operations
Reception
In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the
SCI.
When a high-level pulse is detected, 0 data is output, and if there is no pulse during a one-bit
interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will
be identified as a 0 signal.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 485 of 1130
REJ09B0327-0400
High-Level Pulse Width Selection
Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this
LSI operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit
rate in tran sm ission.
Table 15.12 Bit IrCKS2 to IrCKS0 Set tings
Bit Rate (bps) (Upper Row) / Bit Interval ×
××
× 3/16 (µs) (Lower Row)
2400 9600 19200 38400 57600 115200
Operating
Frequency
φ
φφ
φ (MHz) 78.13 19.53 9.77 4.88 3.26 1.63
2 010 010 010 010 010 —
2.097152 010 010 010 010 010 —
2.4576 010 010 010 010 010 —
3 011 011 011 011 011 —
3.6864 011 011 011 011 011 011
4.9152 011 011 011 011 011 011
5 011 011 011 011 011 011
6 100 100 100 100 100 100
6.144 100 100 100 100 100 100
7.3728 100 100 100 100 100 100
8 100 100 100 100 100 100
9.8304 100 100 100 100 100 100
10 100 100 100 100 100 100
12 101 101 101 101 101 101
12.288 101 101 101 101 101 101
14 101 101 101 101 101 101
14.7456 101 101 101 101 101 101
16 101 101 101 101 101 101
16.9344 101 101 101 101 101 101
17.2032 101 101 101 101 101 101
18 101 101 101 101 101 101
19.6608 101 101 101 101 101 101
20 101 101 101 101 101 101
Legend:
—: An SCI bit rate setting cannot be mode.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 486 of 1130
REJ09B0327-0400
15.4 SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 15.13 shows the interrup t so urces and their relative pr iorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of
interrup t r eque st is sent to the interr upt contr oller independently.
When the TDRE flag in SSR is set to 1, a TXI inter rupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt reque st is g e nerated. A TXI interrupt can activate th e DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC. The DTC cannot be activated by a TEI interrupt request.
When the RDRF flag in SSR is set to 1, an RXI interru pt request is gener a ted. Wh en the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is ge nerated. An RXI interrupt can
activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data
transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
Table 15.13 SCI Interrupt Sources
Channel Interrupt
Source Description DTC Activation Priority*
0 ERI Receive error (ORER, FER, or PER) Not possible High
RXI Receive data register full (RDRF) Possib le
TXI Transmit data regi ster empty (TDRE) Possible
TEI Transmit end (TEND) Not possible
1 ERI Receive error (ORER, PER, or PER) Not possible
RXI Receive data register full (RDRF) Possib le
TXI Transmit data regi ster empty (TDRE) Possible
TEI Transmit end (TEND) Not possible
2 ERI Receive error (ORER, PER, or PER) Not possible
RXI Receive data register full (RDRF) Possib le
TXI Transmit data regi ster empty (TDRE) Possible
TEI Transmit end (TEND) Not possible Low
Note: *The table shows the initial state immediately after a reset. Relative channel priorities
can be changed by the interrupt controller.
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 487 of 1130
REJ09B0327-0400
TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance,
and the TDRE flag and TEND flag may be cleared . Note that th e TEI inter rupt will n ot be
accepted in this case.
15.5 Usage Notes
The following points should be noted when using the SCI.
Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data f r om TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR r e g ardless of the state of the TDRE flag. Ho wev e r, if n ew data is
written to TDR when the TDRE flag is cleared to 0, the data sto r ed in TDR will be lost since it has
not yet been tran sf erred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before wr iting transmit data to TDR.
Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR is as
shown in table 15.14. If there is an overrun error, data is not transferred from RSR to RDR, and
the receive data is lost.
Table 15.14 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags Receive Data Transfer
RDRF ORER FER PER RSR to RDR Receive Errors
1100X Overrun error
0 0 1 0 O Framing error
0001O Parity error
1 1 1 0 X Overrun error + framing error
1 1 0 1 X Overrun error + parity error
0 0 1 1 O Framing error + parity error
1 1 1 1 X Overrun error + framing error +
parity error
Notes: O: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 488 of 1130
REJ09B0327-0400
Break Detection and Processing
When a framing error (FER) is detected, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
parity error flag (PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the FER
flag is cleared to 0, it will be set to 1 again.
Sending a Break
The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by
DR and DDR. This feature can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced
by the value of DR (the pin does not functio n as the TxD pin until the TE bit is set to 1).
Consequently, DDR and DR for the port corresponding to the TxD pin should first be set to 1.
To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.
When the TE bit is clear ed to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from th e TxD pin.
Receive Error Flags and Transmit Operations (Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the base clo ck, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
base clock. Th is is illustrated in fig ure 1 5.23.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 489 of 1130
REJ09B0327-0400
Internal base
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode
Thus the receive margin in asynchronous mode is given by equation (1) below.
M = 0.5 –
1
2N D – 0.5
N
– (L – 0.5)F –
(1 + F) × 100%
.......... (1)
Where M: Receive margin (%)
N: Ratio of bit rate to clo ck (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in equation (1), a receive marg in of 46.875% is given by
equation (2) below.
When D = 0.5 and F = 0,
M = 1
2 × 16 × 100%
= 46.875%
0.5 –
.......... (2)
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.
Section 15 Seri al Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 490 of 1130
REJ09B0327-0400
Restrictions on Use of DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24)
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receive-
data-full in terrupt (RXI).
t
D0
LSB
Serial data
SCK
D1 D3 D4 D5D2 D6 D7
Note: When operating on an external clock, set t > 4 states.
TDRE
Figure 15.24 Example of Synchronous Transmission by DTC
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 491 of 1130
REJ09B0327-0400
Section 16 I2C Bus Interface [Option]
A two-channel I2C bus interface is available as an option in the H8S/2148 Group and H8S/2147N.
The I2C bus interface is not available for the H8S/2144 Group. Observe the following notes when
using this option.
1. For mask-ROM versions, a W is added to the part number in products in which this optional
function is used.
Examples: HD6432147SWFA
2. The product number is identical for F-ZTAT versions. However, be sure to inform your
Renesas sales representative if you will be using this option.
16.1 Overview
A two-channel I2C bus interface is available fo r the H8S/2148 Group and H8S/2147N as an
option. The I2C bus interface conforms to and provides a subset o f the Philips I2C bus (inter-IC
bus) interface functions. The register configuration that controls the I2C bus differs partly from the
Philips con f iguration, howev er.
Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer
data, saving board and connector space.
16.1.1 Features
• Selection of addressing format or non-addressing format
I2C bus format: addressing format with acknowledge bit, for master/slave operation
Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philip s I2C bus interface (I2C bus fo rmat)
• Two ways of setting slave address (I2C bus format)
• Start and stop conditions generated automatically in master mode (I2C bus format)
• Selection of acknowledge output levels when receiving (I2C bus format)
• Automatic loading of acknowledge bit when transmitting (I2C bus format)
• Wait function in master mode (I 2C bus format)
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 492 of 1130
REJ09B0327-0400
• Wait function in slave mode (I 2C bus fo rmat)
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
Data transfer end (including transmission mode transition with I2C bus format and address
reception after loss of master arbitration)
Address match: when any slave address matches or the general call address is received in
slave receive mode (I2C bus format)
Stop con dition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pins)
Two pins—P52/SCL0 and P97/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
Two pins—P86/SCL1 and P42/SDA1—(normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
• Automatic switchin g from formatless mode to I2C bus format (channel 0 only)
Formatless operation ( no star t/stop conditions, non-addressin g mode) in slav e mode
Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL)
Automatic switching from formatless mode to I2C bus format on the fall of the SCL pin
16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the I2C bus interface.
Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and
channel 1 I/O pins differ in structure, and have different sp ecifications for permissible applied
voltages. For details, see section 26, Electrical Characteristics.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 493 of 1130
REJ09B0327-0400
φPS
Noise
canceler
Noise
canceler
Clock
control
Formatless dedicated
clock (channel 0 only)
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Address
comparator
SAR, SARX
Interrupt
generator
ICDRS
ICDRR
ICDRT
ICSR
ICMR
ICCR
Internal data bus
Interrupt
request
SCL
SDA
Legend:
ICCR:
ICMR:
ICSR:
ICDR:
SAR:
SARX:
PS:
I
2
C bus control register
I
2
C bus mode register
I
2
C bus status register
I
2
C bus data register
Slave address register
Second slave address register X
Prescaler
Figure 16.1 Block Diagram of I2C Bus Interfac e
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 494 of 1130
REJ09B0327-0400
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 1)
SCL
SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 2)
SCL
SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Master)
H8S/2148 Group and
H8S/2147N chip
SCL
SDA
Vcc
VCC
SCL
SDA
Figure 16.2 I2C Bus Interface Connections
(Example: H8S/2148 Group and H8S/2147N Chip as Master)
16.1 .3 Input/Output Pins
Table 16.1 summarizes the input/output pins used by the I2C bus interface.
Table 16.1 I2C Bus Interface Pins
Channel Name Abbreviation*I/O Function
0 Serial clock SCL0 I/O IIC0 serial clock input/output
Serial data SDA0 I/O IIC0 serial data input/output
Formatle ss seri al
clock VSYNCI Input IIC0 formatless serial clock input
1 Serial clock SCL1 I/O IIC1 serial clock input/output
Serial data SDA1 I/O IIC1 serial data input/output
Note: *In the text, the channel subscript is omitted, and only SCL and SDA are used.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 495 of 1130
REJ09B0327-0400
16.1.4 Register Configuration
Table 16.2 summarizes the registers of the I2C bus interface.
Table 16.2 Register Configuration
Channel Name Abbreviation R/W Initial Value Address*1
0I
2C bus control register ICCR0 R/W H'01 H'FFD8
I2C bus status register ICSR0 R/W H'00 H'FFD9
I2C bus data register ICDR0 R/W — H'FFDE*2
I2C bus mode register ICMR0 R/W H'00 H'FFDF*2
Slave address register SAR0 R/W H'00 H'FFDF*2
Second slave address
register SARX0 R/W H'01 H'FFDE*2
1I
2C bus control register ICCR1 R/W H'01 H'FF88
I2C bus status register ICSR1 R/W H'00 H'FF89
I2C bus data register ICDR1 R/W — H'FF8E*2
I2C bus mode register ICMR1 R/W H'00 H'FF8F*2
Slave address register SAR1 R/W H'00 H'FF8F*2
Second slave address
register SARX1 R/W H'01 H'FF8E*2
Common Serial/timer control
register STCR R/W H'00 H'FFC3
DDC switch register DDCSWR R/W H'0F H'FEE6
MSTPCRH R/W H'3F H'FF86Module stop contro l
register MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. The register that can be written or read depends on the ICE bit in the I2C bus control
register. The slave address register can be accessed when ICE = 0, and the I2C bus
mode register can be accessed when ICE = 1.
The I2C bus interface registers are assigned to the same addresses as other registers.
Register selection is performed by means of the IICE bit in the serial/timer control
register (STCR).
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 496 of 1130
REJ09B0327-0400
16.2 Register Descriptions
16.2.1 I2C Bus Data Register (ICDR)
Bit
Initial value
Read/Write
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
• ICDRR
Bit
Initial value
Read/Write
7
ICDRR7
—
R
6
ICDRR6
—
R
5
ICDRR5
—
R
4
ICDRR4
—
R
3
ICDRR3
—
R
0
ICDRR0
—
R
2
ICDRR2
—
R
1
ICDRR1
—
R
• ICDRS
Bit
Initial value
Read/Write
7
ICDRS7
—
—
6
ICDRS6
—
—
5
ICDRR5
—
—
4
ICDRS4
—
—
3
ICDRS3
—
—
0
ICDRS0
—
—
2
ICDRS2
—
—
1
ICDRS1
—
—
• ICDRT
Bit
Initial value
Read/Write
7
ICDRT7
—
W
6
ICDRT6
—
W
5
ICDRT5
—
W
4
ICDRT4
—
W
3
ICDRT3
—
W
0
ICDRT0
—
W
2
ICDRT2
—
W
1
ICDRT1
—
W
• TDRE, RDRF (in t ernal flags)
Bit
Initial value
Read/Write
—
RDRF
0
—
—
TDRE
0
—
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 497 of 1130
REJ09B0327-0400
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally in to a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or
written by th e CPU, ICDRR is read-on ly, and ICDRT is write-only. Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF.
If IIC is in tran sm it mode and the next data is in ICDRT (the TDRE f lag is 0) following
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF
flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred
automatically f rom ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differ ently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR is assigned to the same addr ess as SARX, and can be written and r e ad only when the ICE
bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 498 of 1130
REJ09B0327-0400
TDRE Description
0 The next transmit data is in ICDR (ICDRT), or transmission cannot (Initial value)
be started
[Clearing cond iti ons ]
• When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
• When a stop conditi on is dete cted in the bus lin e state after a stop con dition is
issued with the I2C bus format or serial format selected
• When a stop condition is detected with the I2C bu s format sele cted
• In receive mode (TRS = 0)
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowle dge bit)
1 The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
• In transmit mode (TRS = 1), when a start condition is detected in the bus line state
after a start condition is issued in master mode with the I2C bus format or serial
format selected
• At the first transmit mode setting (TRS = 1) (first transmit mode setting only) after
the mode is switched from I2C bus mode to formatless mode
• When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
• When detecting a start condition and then switching from sl ave receive mode (TRS
= 0) state to transmit mode (TRS = 1) (first transmit mode switching only).
RDRF Description
0 The data in ICDR (ICDRR) is invalid (Initial value)
[Clearing cond iti on]
When ICDR (ICDRR) receive data is read in receive mode
1 The ICDR (ICDRR) receive data can be read
[Setting condition]
When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and
RDRF = 0)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 499 of 1130
REJ09B0327-0400
16.2.2 Slave Address Register (SAR)
Bit
Initial value
Read/Write
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the ch ip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, an d can be written and read only when the ICE b it is clear ed to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I2C bus.
Bit 0—Format Select (FS): Used together with the FSX bit in SARX and the SW bit in
DDCSWR to select the communication format.
• I2C bus format: addressing format with acknowledge bit
• Synchronous serial form at: non-addressing format without acknowledge bit, for master mode
only
• Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit,
slave mode only, start/stop conditions not detected
The FS bit also specifies whether or not SAR slave address r ecognition is per formed in slave
mode.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 500 of 1130
REJ09B0327-0400
DDCSWR
Bit 6 SAR
Bit 0 SARX
Bit 0
SW FS FSX Operating Mode
000 I
2C bus format
• SAR and SARX slav e addresses recognized
1I
2C bus format (Initial value)
• SAR slave address recognized
• SARX slave address ignored
10 I
2C bus format
• SAR slave address ignored
• SARX slave address recognized
1 Synchronous serial form at
• SAR and SARX slav e addresses ignored
10
0
1
0
1
0
Formatless mode (start/stop conditions not detected)
• Acknowledge bit used
1 1 Formatless mode* (s tart/stop conditions not detected)
• No acknowledge bit
Note: *Do not set this mode when automatic switching to the I2C bus format is performed by
means of the DDCSWR setting.
16.2.3 Second Slave Address Register (SARX)
Bit
Initial value
Read/Write
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the ch ip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when th e ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode .
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 501 of 1130
REJ09B0327-0400
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique ad dress in bits SVAX6 to
SVAX0, differing from the addresses of other slave devices connected to the I2C bus.
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in
DDCSWR to select the communication format.
• I2C bus format: addressing format with acknowledge bit
• Synchronous serial form at: non-addressing format without acknowledge bit, for master mode
only
• Formatless mode: non-addressing fo rmat with or without acknowledge bit, slave mode only,
start/stop conditions not detected
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. Fo r details, see the descriptio n of the FS bit in SAR.
16.2.4 I2C Bus Mode Register (ICMR)
Bit
Initial value
Read/Write
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to th e same address as SAR. ICMR can be wr itten and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB- first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differ ently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
Do not set this b it to 1 when the I2C bus form at is used.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 502 of 1130
REJ09B0327-0400
Bit 7
MLS Description
0 MSB-first (Initial value)
1 LSB-first
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
and the acknowled g e bit, in master mode with the I2C bus format. When WAIT is set to 1, after the
fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a w a it state begins
(with SCL a t the low level). Whe n the IRIC flag is clea red to 0 in ICCR, the wait en ds and the
acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred
consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledg e bit transfer, regardless of the
WAIT setting.
The setting of this bit is invalid in slave m ode.
Bit 6
WAIT Description
0 Data and acknowledge bits transferred consecutively (Initial value)
1 Wait inserted between data and acknowledge bits
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 503 of 1130
REJ09B0327-0400
Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel
1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode.
They should be set according to the required transfer rate.
STCR
Bit 5 or 6 Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock φ
φφ
φ =
5 MHz φ
φφ
φ =
8 MHz φ
φφ
φ =
10 MHz φ
φφ
φ =
16 MHz φ
φφ
φ =
20 MHz
0000φ/28 179 kHz 286 kHz 357 kHz 571 kHz*714 kHz*
1φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz*
10φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz*
1φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz
100φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1φ/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz
10φ/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz
1φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1000φ/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz
1φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
10φ/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz
1φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
100φ/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz
1φ/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz
10φ/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz
1φ/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz
Note: *Outside the I2C bus interface specification range (normal mode: max. 100 kHz; high-
speed mode: max. 400 kHz).
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specif y the number of bits to be
transferred next. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an in terval b etween transfer frames. If bits BC2 to BC0 are set to a v a lue other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 504 of 1130
REJ09B0327-0400
Bit 2 Bit 1 Bit 0 Bits/Frame
BC2 BC1 BC0 Synchronous Serial Format I2C Bus Format
0 0 0 8 9 (Initial value)
11 2
10 2 3
13 4
100 4 5
15 6
10 6 7
17 8
16.2.5 I2C Bus Control Register (ICCR)
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
acknowledgement, confirms the I2C bus interface bus status, issues start/stop conditions, and
performs in ter rupt flag confirma tion.
ICCR is initialized to H'01 by a reset and in h ardware standby mode.
Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I2C bus interface module is halted and its
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 505 of 1130
REJ09B0327-0400
Bit 7
ICE Description
0I
2C bus interface module disabled, with SCL and SDA signal pins set to port function
(Initial value)
I2C bus interface module internal states initialized
SAR and SARX can be accessed
1I
2C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
Bit 6—I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C
bus interface to the CPU.
Bit 6
IEIC Description
0 Interrupts disabled (Initial value)
1 Interrupts enabled
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I2C bus interface operates in master mode or slave mode.
TRS selects whether the I2C bus interface operates in transmit mode or receive mode.
In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both re set by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the fir st fr ame after a start condition .
Modification of the TRS bit during transfer is deferred until transf er of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 506 of 1130
REJ09B0327-0400
Bit 5 Bit 4
MST TRS Operating Mode
0 0 Slave receive mode (Initial value)
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Bit 5
MST Description
0 Slave mode (Initial value)
[Clearing cond iti ons ]
1. When 0 is written by software
2. When bus arbitration is lost after transmission is started in I2C bus format master
mode
1 Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
Bit 4
TRS Description
0 Receive mode (Initial value)
[Clearing cond iti ons ]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3)
3. When bus arbitration is lost after transmission is started in I2C bus format master
mode
4. When the SW bit in DDCSWR changes from 1 to 0
1 Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3
and 4)
3. When a 1 is received as the R/W bit of the first frame in I2C bus format slave mode
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 507 of 1130
REJ09B0327-0400
Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
In the H8S/2148 Group and H8S/2147N, the DTC can be used to perform continuous transfer. The
DTC is activated when th e IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the
other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on
completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE
bit is 1, the TDRE, IRIC, and IRTR flags are set on co mpletion of data tr ansmission when the
acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the
acknowledge bit is 1.
When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified
number of data transfers have been executed. Consequently, interrupts are not generated during
continuous da ta tr ansfer, but if data transmission is completed with a 1 acknowledge bit when the
ACKE bit is set to 1, the DTC is not activated and an interrupt is genera ted, if enabled.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for instance, or may be fixed at 1 and have no
significance.
Bit 3
ACKE Description
0 The value of the acknowledge bit is ignored, and continuous transfer
is performed (Initial value)
1 If the acknowledge bit is 1, continuous transfer is interrupted
Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I2C bus (S CL, SDA)
is busy or free. In master mode, this bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, use a MOV instru ction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a sto p condition, use a MOV instru ction to
write 0 in BBSY and 0 in SCP. It is not p ossible to write to BBSY in slave mode; th e I2C bus
interface must be set to master transmit mode before issuing a start condition. MST and TRS
should both be set to 1 before writing 1 in BBSY and 0 in SCP.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 508 of 1130
REJ09B0327-0400
Bit 2
BBSY Description
0 Bus is free (Initial value)
[Clearing cond iti on]
When a stop condition is detected
1Bus is busy
[Setting condition]
When a start condition is detected
Bit 1—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has
issued an inter r upt request to the CPU. IRIC is set to 1 at the end of a data tran sf er , when a slave
address or general call address is detected in slave receive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depend ing on the FS bit in SAR and the WAIT bit in ICMR. See section 1 6.3.6, IRIC Setting
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by read ing I RIC after it has been set to 1, then writing 0 in I RIC.
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 509 of 1130
REJ09B0327-0400
Bit 1
IRIC Description
0 Wait i ng for transfer, or transfer in progress (Initial value)
[Clearing condit i ons]
1. When 0 is written in IRIC after reading IRIC = 1
2. When ICDR is written or read by the DTC
(When the TDRE or RDRF flag is cleared to 0)
(This is not always a clearing conditi on; s ee the description of DTC operation for details)
1 Int errupt requested
[Setting conditions]
• I2C bus format master mode
1. When a start condition is detected in the bus line state aft er a start condition is issued
(when the TDRE flag is set to 1 because of first frame transmissi on)
2. When a wait is inserted between the data and acknowledge bit when WAIT = 1
3. At the end of data transfer
(at the rise of the 9th transmit/receive cl ock pul se when no wait is inserted, (WAIT=0) and,
when a wait is inserted (WAIT=1), at the fall of the 8th transmit/rec eiv e clock pulse)
4. When a slave address is received after bus arbitrati on is l ost
(when the AL flag is set to 1)
5. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
• I2C bus format slave mode
1. When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1)
and at the end of data transfer up to the subsequent retransmission start c onditi on or stop
conditi on detecti on
(when the TDRE or RDRF flag is set to 1)
2. When the general call address is detected
(when FS = 0 and the ADZ flag is set to 1)
and at the end of data transfer up to the subsequent retransmission start c onditi on or stop
conditi on detecti on
(when the TDRE or RDRF flag is set to 1)
3. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
4. When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
•Synchronous seri al form at, and form atless mode
1. At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
2. When a start condition is detected with serial form at selected
3. When the SW bit is set to 1 in DDCSWR
Except the above, when the conditions to set the TDRE or RDRF internal flag to 1 is generated
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 510 of 1130
REJ09B0327-0400
When, with the I 2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. Th e
IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a
retransmission start condition or stop condition after a slave address (SVA) or general call address
match in I2C bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in
continuous transfer using the DTC. The TDRE or RDRF flag is cleared, ho wever, since the
specified number of ICDR reads or writes have been completed.
Table 16.3 shows the relationship between the flags and the transfer states.
Table 16.3 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State
1/0 1/0 0 0 0 0 0 0 0 0 0 Idl e state (flag clearing
required)
1 1 0 0 0 0 0 0 0 0 0 Start condition issuance
1 1 1 0 0 1 0 0 0 0 0 Start condition established
1 1/ 0 1 0 0 0 0 0 0 0 0/1 Master mode wait
1 1/ 0 1 0 0 1 0 0 0 0 0/1 Master mode transmit/
receive end
0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost
0 0 1 0 0 0 0 0 1 0 0 SAR match b y first frame in
slave mode
0 0 1 0 0 0 0 0 1 1 0 General call address match
0010001 0000 SARX match
0 1/ 0 1 0 0 0 0 0 0 0 0/1 S l ave mode
transmit/ receive end
(except after SARX matc h)
0
0
1/0
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
Slave mode
transmit/receive end (after
SARX match)
0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 Stop condition detected
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 511 of 1130
REJ09B0327-0400
Bit 0—Star t Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, wr ite 1 in BBSY and 0 in SCP. A retr ansmit
start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1 . I f 1 is written , the data is not stored.
Bit 0
SCP Description
0 Writing 0 issues a start or stop condition, in combination with the BBSY flag
1 Reading always returns a value of 1 (Initial value)
Writing is ignored
16.2.6 I2C Bus Status Register (ICSR)
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flags.
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset and in hardware standby mode.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 512 of 1130
REJ09B0327-0400
Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
detected during frame transfer in I2C bus format slave mode.
Bit 7
ESTP Description
0 No error stop condition (Initial value)
[Clearing cond iti ons ]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
1• In I2C bus format slave mode
Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
• In other modes
No meaning
Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been
detected after completion of frame transfer in I2C bus format slave mode.
Bit 6
STOP Description
0 No normal stop condition (Initial value)
[Clearing cond iti ons ]
1. When 0 is written in STOP after reading STOP = 1
2. When the IRIC flag is cleared to 0
1• In I2C bus format slave mode
Normal stop condition detected
[Setting condition]
When a stop condition is detected after completion of frame transfer
• In other modes
No meaning
Bit 5—I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
(IRTR): Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the
source is completion of reception/transmission of one frame in continuous transmission/reception
for which DTC activation is possible. When the IRTR flag is set to 1 , the IRIC flag is also set to 1
at the same time.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 513 of 1130
REJ09B0327-0400
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writin g 0 in IRTR. IRTR is also cleared autom a tically
when the IRIC flag is cleared to 0.
Bit 5
IRTR Description
0 Waiting for transfer, or transfer in progress (Initial value)
[Clearing cond iti ons ]
1. When 0 is written in IRTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
1 Continuous transfer state
[Setting conditions]
• In I2C bus interface slave mode
When the TDRE or RDRF flag is set to 1 when AASX = 1
• In other modes
When the TDRE or RDRF flag is set to 1
Bit 4—Second Sla ve Address Recognition Flag (AASX): In I2C bus format slave receive mode,
this flag is set to 1 if th e first frame following a start condition match es bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared auto m a tically when a start condition is detected.
Bit 4
AASX Description
0 Second slave address not recognized (Initial value)
[Clearing cond iti ons ]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
1 Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode while FSX = 0
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 514 of 1130
REJ09B0327-0400
Bit 3—Arbitration Lost (AL): This flag indicates that arbitratio n was lost in master mode. Th e
I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition , AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL Description
0 Bus arbitration won (Initial value)
[Clearing cond iti ons ]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AL after reading AL = 1
1 Arbitration lost
[Setting conditions]
1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
2. If the internal SCL line is high at the fall of SCL in master transmit mode
Bit 2—Slave Address Recognition Flag (AAS): In I2C bus format slave receive mode, this flag is
set to 1 if the f ir st fr ame f ollowing a start condition matches bits SVA6 to SVA0 in SAR, or if th e
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition , AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 515 of 1130
REJ09B0327-0400
Bit 2
AAS Description
0 Slave address or general call address not recognized (Initial value)
[Clearing cond iti ons ]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AAS after reading AAS = 1
3. In master mode
1 Slave address or general call address recognized
[Setting condition]
When the slave addres s or general call address is detected in slave receive mode while
FS = 0
Bit 1—General Call Address Recognit ion Flag (ADZ): In I2C bus format slave receive mode,
this flag is set to 1 if the first fram e following a start conditio n is the general call address ( H'00).
ADZ is cleared by read ing ADZ after it has b een set to 1, then writing 0 in ADZ. In addition , ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1
ADZ Description
0 General call address not reco gni zed (Initial val ue)
[Clearing cond iti ons ]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in ADZ after reading ADZ = 1
3. In master mode
1 General call address recognized
[Setting condition]
When the general call address is detected in slave receive mode while FSX = 0 or FS = 0
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 516 of 1130
REJ09B0327-0400
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the
receiving device receives data, it retu rns acknowledge data, and this data is loaded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is r ead, in transmission (when TRS = 1), th e valu e loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
When this bit is written to, the acknowledge d ata transmitted at the receipt is rewritten regardless
of the TRS value. The data loaded fo m the receiving device is retained, therefore take care of
using bit-manipulation instructions.
Bit 0
ACKB Description
0 Receive mode: 0 is output at acknowledge output timing (Initial value)
Transmit mode: Indicates that the receiving device has acknowledged the data (signal
is 0)
1 Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the data
(signal is 1)
16.2.7 Serial/Timer Control Register (STCR)
Bit
Initial value
Read/Write
7
IICS
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
STCR is an 8-bit readable/writable register that controls register access, the I2C interface operating
mode (when the on-chip IIC option is included), and on-chip flash memory (F-ZTAT versions),
and selects the TCNT input clock source. For details of functions not related to the I2C bus
interface, see section 3.2.4, Serial Timer Control Register (STCR), and the descriptions of the
relevant modules. If a modu le controlled by STCR is not used, do no t write 1 to the corresponding
bit.
STCR is initialized to H'00 by a reset and in hardware standby mod e .
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 517 of 1130
REJ09B0327-0400
Bit 7—I2C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of
output buffer as SCL and SDA. This bit is used when implementing the I2C interface by software
only.
Bit 7
IICS Description
0 PA7 to PA4 are normal I/O pins (Initial value)
1 PA7 to PA4 are I/O pins with bus driving capability
Bits 6 and 5—I2C Transfer Select 1 and 0 (IICX1 and 0): This bit, together with bits CKS2 to
CKS0 in ICMR, selects the transfer ra te in master mod e. For details, see section 16.2.4, I2C Bus
Mode Register (ICMR).
Bit 4—I2C Master Enable (IICE): Controls CPU access to the I2C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 4
IICE Description
0 CPU access to I2C bu s interface data and control regi ster s is dis able d (Initial value)
1 CPU access to I2C bu s int erfa ce data and co ntrol regi ster s is enab led
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting modu le
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details.
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, togeth er with
bits CKS2 to CKS0 in TCR, select the clock input to the timer coun ters (TCNT). For details, see
section 12.2.4, Timer Control Register (TCR).
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 518 of 1130
REJ09B0327-0400
16.2.8 DDC Switch Register (DDCSWR)
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
7
SWE
0
R/W
6
SW
0
R/W
5
IE
0
R/W
4
IF
0
R/(W)*
1
3
CLR3
1
W*
2
0
CLR0
1
W*
2
2
CLR2
1
W*
2
1
CLR1
1
W*
2
DDCSWR is an 8-bit readab le/wr itable register that is used to initialize IIC and contr o ls IIC
internal latch clearance.
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bit 7—DDC Mode Switch Enable (SWE): Selects the fu nction for auto matically switching IIC
channel 0 fro m fo rmatless m ode to the I2C bus format.
Bit 7
SWE Description
0 Automatic switching of IIC channel 0 from formatless mode to I2C bus format is
disabled (Initial value)
1 Automatic switching of IIC channel 0 from formatless mode to I2C bus format is
enabled
Bit 6—DDC Mode Switch (SW): Selects either f ormatless mod e or the I2C bus format for IIC
channel 0.
Bit 6
SW Description
0 IIC channel 0 is used with the I2C bus format (Initial value)
[Clearing cond iti ons ]
1. When 0 is written by software
2. When a falling edge is detected on the SCL pin when SWE = 1
1 IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 519 of 1130
REJ09B0327-0400
Bit 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to
the CPU when automatic format switching is executed for IIC channel 0.
Bit 5
IE Description
0 Interrupt when automatic format switching is executed is disabled (Initial value)
1 Interrupt when automatic format switching is executed is enabled
Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the
CPU when autom atic format switching is executed for IIC channel 0.
Bit 4
IF Description
0 No interrupt is requested when automatic format switching is executed (Initial value)
[Clearing cond iti on]
When 0 is written in IF after reading IF = 1
1 An interrupt is requested when automatic format switching is executed
[setting con dit ion]
When a falling edge is detected on the SCL pin when SWE = 1
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initializatio n of the internal
state of IIC0 and IIC1.
These bits can on ly be written to; if read they will always return a value of 1.
When a write op e r ation is performed on th ese b its, a clear signal is generated for the internal latch
circuit of th e corr esponding module(s), and the internal state of the IIC mo dule( s) is initialized.
The write data for these bits is not retained . To p erform I I C clear ance, bits CLR3 to CLR0 must be
written to simu ltaneously using an MOV instruction. Do not use a bit-manipulation instruction
such as BCLR.
When clearing is req u ired again, all the b its must be written to in accordance with the setting.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 520 of 1130
REJ09B0327-0400
Bit 3 Bit 2 Bit 1 Bit 0
CLR3 CLR2 CLR1 CLR0 Description
00——Setting prohibited
1 0 0 Setting prohibited
1 IIC0 internal latch cleared
1 0 IIC1 internal latch cleared
1 IIC0 and IIC1 internal latches cleared
1———Invalid setting
16.2.9 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at
the end of the bus cycle, and a transition is made to module stop mode. For details, see section
25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 4—Module Stop (MSTP4): Specifies IIC channel 0 module stop mode.
MSTPCRL
Bit 4
MSTP4 Description
0 IIC channel 0 module stop mode is cleared
1 IIC channel 0 module stop mode is set (Initial value)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 521 of 1130
REJ09B0327-0400
MSTPCR L Bit 3— Module Stop (MSTP3): Specifies IIC channel 1 module stop mode.
MSTPCRL
Bit 3
MSTP3 Description
0 IIC channel 1 module stop mode is cleared
1 IIC channel 1 module stop mode is set (Initial value)
16.3 Operation
16.3.1 I2C Bus Data Forma t
The I2C bus interface has serial and I2C bus fo rmats.
The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures
16.3 (a) and (b). The first frame following a start condition always consists of 8 bits.
IIC channel 0 only is capable of formatless operation, as shown in figure 16.4.
The serial format is a non-addressing format with no acknowledge bit. Although start and stop
conditions must be issued, this format can be used as a synchronous serial format. This is shown in
figure 16.5.
Figure 16.6 shows the I2C bus timin g.
The symbols used in figures 16.3 to 16.6 are explained in table 16.4.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 522 of 1130
REJ09B0327-0400
S SLA R/WA DATA A A/AP
1111
n7
1 m
(a) I2C bus format (FS = 0 or FSX = 0)
(b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0)
n: transfer bit count
(n = 1 to 8)
Legend:
Legend:
m: transfer frame count
(m ≥ 1)
S SLA R/WA DATA
111
n17
1m1
S SLA R/WA DATA A/AP
111
n27
1m2
111
A/A
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
11
Figure 16.3 I2C Bus Data Formats (I2C Bus For mats)
IIC0 only, FS = 0 or FSX = 0
DATA A ADATA
11
n8
1m
1
A/A
n: transfer bit count (n = 1 to 8)
m: transfer frame count (m ≥ 1)
Legend:
Figure 16.4 Formatless
S DATA DATA P
11
n8
1 m
FS = 1 and FSX = 1
n: transfer bit count
(n = 1 to 8)
Legend:
m: transfer frame count
(m ≥ 1)
Figure 16.5 I2C Bus Data Format (Serial Format)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 523 of 1130
REJ09B0327-0400
SDA
SCL
S
1-7
SLA
8
R/W
9
A
1-7
DATA
89 1-7 89
A DATA PA/A
Figure 16.6 I2C Bus Timing
Table 16.4 I2C Bus Data Forma t Symbols
Legend
S Start condition. The master device drives SDA from high to low while SCL is high
SLA Slave address, by which the master device selects a slave device
R/WIndicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
DATA Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
P Stop condition. The master device drives SDA from low to high while SCL is high
16.3.2 Master Transmit Operation
In I2C bus format master tran smit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The transmissio n procedure and ope r a tions by which data is sequen tially transmitted in
synchronization with ICDR write operations, are described below.
(1) Set the ICE bit in ICCR to l. Set b its MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
in STCR, according to the operation mode.
(2) Read the BBSY flag to confirm that the bus is free.
(3) Set the M ST and TRS b its to 1 in ICCR to select ma ste r transm it mode.
(4) Write 1 to BBSY and 0 to SCP. This switches SDA f rom high to low wh en SCL is high, and
generates the start cond ition.
(5) When the start con dition is generated , the IRIC and IRTR flags are set to 1. If the IEI C bit in
ICCR has been set to l, an interrupt request is sen t to the CPU.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 524 of 1130
REJ09B0327-0400
(6) Write data to ICDR (slave ad dress + R/W)
With the I2C bu s format (when the FS bit in SAR or the FSX bit in SARX is 0), the first fr ame
data following the start condition indicates the 7-bit slave address and transmit/receive
direction.
Then clear the IRIC flag to indicate the end of transfer.
Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no
interrup t is in serted.
If a period of time th at is equal to transfer one byte ha s elap sed by the time the IRlC flag is
cleared, the end of transfer cannot be identified.
The master device sequentially sends the transmit clock and the data wr itten to ICDR with the
timing shown in figure 16.7. The selected slave device (i.e., the slave device with the
matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge sign al.
(7) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame h a s been transmitted, SCL is au tomatically fixed low in
synchronization with the internal clock until the next transmit data is written.
(8) Read the ACKB bit to confirm that ACKB is 0. When the slave device has not returned an
acknowledge sign al and ACKB remains 1, execute the transmit end processing described in
step (12) and perform transmit operation again.
(9) Write the next data to b e transm itted in ICDR. To indicate the end of da ta tr ansfer, clear the
IRIC flag to 0.
As described in step (6) above, writing to ICDR and clearing of the IRIC flag must be
executed continu ously so that no interrupt is inser ted.
The next frame is tran smitted in synchronizatio n with the internal clock .
(10)When on e frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame h a s been transmitted, SCL is au tomatically fixed low in
synchronization with the internal clock until the next transmit data is written.
(11)Read the ACKB bit of ICSR. Confirm that the slave device has returned an acknowledge
signal and ACKB is 0. When mo r e data is to be transmitted, r e turn to step (9) to execute next
transmit operation. If the slave device has not returned an acknowledge signal and ACKB is 1,
execute the transmit end processing described in step (12).
(12)Clear the IRIC flag to 0. Write BBSY and SCP of ICCR to 0. By doing so, SDA is changed
from low to high while SCL is high and the transmit stop condition is generated.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 525 of 1130
REJ09B0327-0400
SDA
(master output)
SDA
(slave output)
21
R/W
43658712
9
A
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6
IRIC
IRTR
ICDR
SCL
(master output)
Start condition
generation
Slave address Data 1
[9] ICDR write
[9] IRIC clear
[6] ICDR write [6] IRIC clear
address + R/W
[7]
[5]
Note: Data write
timing in ICDR
ICDR Writing
prohibited
[4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
ICDR Writing
enable
Data 1
User processing
Figure 16.7 Example of Master Transmit Mode Operation Timing
(MLS = WAIT = 0)
16.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data.
The receive procedure and op erations by which data is sequentially received in synchronization
with ICDR read operations, are described below.
(1) Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
(2) When ICDR is read (dummy data read), reception is started and the receive clock is output,
and data is received, in synchronization with the internal clock. To indicate the wait, clear the
IRIC flag to 0.
Reading from ICDR and clearing of the IRIC f1ag must be executed continuously so that no
interrup t is in serted.
If a period of time that is equal to transfer one byte ha s elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 526 of 1130
REJ09B0327-0400
(3) The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this
point , if the IEIC bit of ICCR is set to 1, an interrupt request is gene rated to the CPU .
SCL is automatically f ixed low in synchronization with the in ter nal clock until the IRIC flag
is cleared. If the first frame is the final reception frame, execute the end processing as
described in (l0).
(4) Clear the IRIC flag to 0 to release from the wait state.
The master device outputs the 9th receive clock pulse, sets SDA to low, and returns an
acknowledge sign al.
(5) When one fr ame of data h a s been transmitted, th e IRIC and IRTR flags are set to 1 at the rise
of the 9th transmit clock pulse.
The master device continues to output the receive clock for the next receive data.
(6) Read the ICDR receive data.
(7) Clear the IRIC flag to indicate the next wait.
From clearing of the IRIC flag to completion of data transmission as described in steps (5),
(6), and (7), must be performed within the time taken to transfer one byte, because releasing
of the wait state as described in step (4) (or (9)).
(8) The IRIC flag is set to 1 at the fall of the 8th one-frame reception clock pulse. SCL is
automatically f ixed low in synchron ization with the internal clock until th e I RIC flag is
cleared. If this frame is the final reception frame, execute the end processing as described in
(l0).
(9) Clear the IRIC flag to 0 to release from the wait state. The master device outputs the 9th
reception clock pulse, sets SDA to low, and returns an acknowledge signal.
By repeating steps (5) to (9) above, more data can be received.
(l0) Set the ACKB bit of ICSR to 1 and set the acknowledge data for the final reception.
Set the TRS bit of I CCR to 1 to chan ge receive mode to transmit mode.
(11)Clear the IRIC flag to release from the wait state.
(12)When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
reception clock pulse.
(13)Clear the WAIT bit of ICMR to 0 to cancel wait mode. Read the ICDR receive data and clear
the IRIC flag to 0.
Clear the IRIC flag only when WAIT = 0.
(If the stop-condition generation command is executed after clearing the IRIC flag to 0 and
then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition can not be
generated.)
(14)Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and
generates the stop condition.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 527 of 1130
REJ09B0327-0400
9
A Bit7
Master receive modeMaster transmit mode
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
[2] ICDR read
(dummy read) [2] IRIC clear [4] IRIC clear [6] ICDR read
(Data 1) [7] IRIC clear
Bit6 Bit5 Bit4 Bit3 Bit7 Bit6 Bit5 Bit4 Bit3Bit2 Bit1 Bit0
1234 56 78
[3] [5]
A
912 345
Data 1 Data 2
Data 1
Figure 16.8 (a) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
8
Bit0
Data 2
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing [9] IRIC clear [6] ICDR read
(Data 2) [7] IRIC clear [9] IRIC Clear [6] ICDR read
(Data 3) [7] IRIC clear
Bit7
[8] [5]
A
Bit6 Bit5 Bit4 Bit7 Bit6Bit3 Bit2 Bit1 Bit0
9123 45 67
[8] [5]
A
8912
Data 3 Data 4
Data 3Data 2Data 1
Figure 16.8 (b) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 528 of 1130
REJ09B0327-0400
16.3.4 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an ackno wledge signal. The reception procedure and operations in slave
receive mode are described below.
[1] Set the I CE bit in ICCR to 1. Set the M LS bit in ICMR and the M ST a nd TRS bits in ICCR
according to the operating mode.
[2] When the start conditio n output by the master device is detected, the BBSY flag in ICCR is set
to 1.
[3] When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
[4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1 . If the IEI C bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive op eration continues. If the RDRF internal flag
has been set to 1 , the slave d evice drives SCL low from the fall of the receive clock until data
is read into I CDR.
[5] Read ICDR and c lear the IRIC flag in ICCR to 0 . The RDRF flag is clea red to 0.
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed fro m low to high when SCL is high, and the sto p con d ition is detected, the BBSY flag in
ICCR is cleared to 0.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 529 of 1130
REJ09B0327-0400
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(master output)
Start condition
generation
SCL
(slave output)
Interrupt request
generation
Address + R/W
Address + R/W
[5] ICDR read [5] IRIC clear
User processing
Slave address Data 1
[4]
A
R/W
Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 530 of 1130
REJ09B0327-0400
SDA
(master output)
SDA
(slave output)
214365879879
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(master output)
SCL
(slave output)
Interrupt
request
generation
Interrupt
request
generation
Data 2
Data 2
Data 1
Data 1
[5] ICDR read [5] IRIC clear
User processing
Data 2
Data 1 [4] [4]
A A
Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 531 of 1130
REJ09B0327-0400
16.3.5 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
[1] Set the I CE bit in ICCR to 1. Set the M LS bit in ICMR and the M ST a nd TRS bits in ICCR
according to the operating mode.
[2] When the slave address matche s in the first frame followin g detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At
the same time, the IRIC flag in ICCR is set to 1 . If the I EIC bit in ICCR h a s been set to 1, an
interrupt r equ est is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to
1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set
to 1. The slave dev ice driv es SCL low from the fall o f the tran sm it clock until ICDR data is
written.
[3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0.
The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR
flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The
slave device sequ entially sends the data written into ICDR in accordance with the clo ck output
by the master device at the timing shown in figure 16.11.
[4] When one f rame of data has been transm itted, the IRIC flag in ICCR is set to 1 at the rise of
the 9th tran sm it clock pulse. If the TDRE internal f lag ha s been set to 1, this slave de vice
drives SCL low f r om the fall of the transm it clock until data is written to ICDR. The master
device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this
acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine
whether the tr ansfer operation was perfo r med normally. When th e TDRE internal flag is 0, the
data written into ICDR is transferre d to ICDRS, transmissio n is started, and the TDRE internal
flag and the IRIC and IRTR flags are set to 1 again.
[5] To continue transmission, clear the IRIC flag to 0, then write the next data to be tr ansmitted
into ICDR. The TDRE internal flag is cleared to 0.
Transmit operations can be performed continuously by repeating steps [4] and [5]. To end
transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from
low to h i gh when SCL is high, and the stop condition is detected , the BBSY flag in ICCR is
cleared to 0.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 532 of 1130
REJ09B0327-0400
SDA
(slave output)
SDA
(master output)
SCL
(slave output)
21 21436587998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRT
TDRE
SCL
(master output)
Interrupt
request
generation
Interrupt
request
generation
Slave receive mode Slave transmit mode
Data 1 Data 2
[3] IRIC
clear [5] IRIC
clear
[3] ICDR write [3] ICDR write [5] ICDR write
User processing
Data 1
Data 1 Data 2
Data 2
A
R/W
A
[3]
[2]
Interrupt
request
generation
Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 533 of 1130
REJ09B0327-0400
16.3.6 IRIC Setting Timing and SCL Control
The interrupt request f lag (IRIC) is set at dif f erent times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If th e TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one fram e has been transferred; this timing is synchronized with the
internal clock. Figure 16.12 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
SCL
SDA
IRIC
User processing Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
1A8
1
1
A
7
1897
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I
2
C bus format, wait inserted)
SCL
SDA
IRIC
User processing Clear
IRIC
Clear
IRIC Write to ICDR (transmit)
or read ICDR (receive)
SCL
SDA
IRIC
User processing
(c) When FS = 1 and FSX = 1 (synchronous serial format)
Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
8
89
8
71
8
71
Figure 16. 12 IRIC Setting Timing and SCL Control
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 534 of 1130
REJ09B0327-0400
16.3.7 Automatic Switching from Formatless Mode to I2C Bus Format
Setting the SW b it to 1 in DDCSWR en ables formatless m ode to be selected as the IIC0 ope rating
mode. Switching from formatless mode to the I2C bus format (slave mode) is performed
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
• A common data pin (SDA) for formatless and I2C bus format operation
• Separate clock pins for fo rmatless operation (VSYNCI) and I2C bus format operation (SCL)
• A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)
• Settings of bits othe r than TRS in I CCR that allow I 2C bus format operation
Automatic switching is performed from formatless m ode to the I2C bus format when th e SW bit in
DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching
from the I2C bus format to formatless mode is achieved by having software set the SW bit in
DDCSWR to 1.
In formatless mode, bits (such as MSL and TRS) that control the I2C bus interface operating mode
must not be modified. When switching from the I2C bus format to form atless mode, set the TRS
bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless
mode, then set th e SW bit to 1. After automatic switching from f orm atless mode to the I2C bus
format (slave mode), in order to wait for slave address reception, the TRS bit is automatically
cleared to 0.
If a falling edge is detected on the SCL pin during formatless operation, the I2C bus interface
operating mode is switched to the I2C bus format without waiting for a stop condition to be
detected.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 535 of 1130
REJ09B0327-0400
16.3.8 Operation Using the DTC
The I2C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 16.5 shows some examples of processing using the DTC. These examples assume that the
number of tran sfer data bytes is known in slave mode.
Table 16.5 Examples of Operation Using the DTC
Item Master Transmit
Mode Master Receive
Mode Slave Transmit
Mode Slave Receive
Mode
Slave address +
R/W bit
transmission/
reception
Transmiss ion by
DTC (ICDR write) Transmission by
CPU (ICDR write) Reception by
CPU (ICDR read) Reception by CPU
(ICDR read)
Dummy d ata
read —Processing by
CPU (ICDR read) ——
Actual data
transmission/
reception
Transmiss ion by
DTC (ICDR write) Reception by
DTC (ICDR read) Transmission by
DTC (ICDR write) Reception by DTC
(ICDR read)
Dummy d ata
(H'FF) write ——Processing by
DTC (ICDR write) —
Last frame
processing Not necessary Reception by
CPU (ICDR read) Not necessary Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
2nd time: End
condition issuance
by CPU
Not necessary Automatic clearing
on detection of end
condition during
transmissi on of
dummy data (H'FF)
Not necessary
Setting of
number of DTC
transfer data
frames
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Reception: Actual
data count Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Reception: Actual
data count
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 536 of 1130
REJ09B0327-0400
16.3.9 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
System clock
period
Sampling clock
C
DQ
Latch
C
DQ
Latch
SCL or
SDA input
signal Match
detector Internal
SCL or
SDA
signal
Sampling
clock
Figure 16.13 Block Diagram of Noise Canceler
16.3.10 Sample Flowcharts
Figures 16.14 to 16.17 show sample flowcharts for using the I2C bus interface in each mode.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 537 of 1130
REJ09B0327-0400
Start
Initialize
Read BBSY in ICCR
No BBSY = 0?
Yes
Yes
Set MST = 1 and
TRS = 1 in ICCR
Write BBSY = 1
and SCP = 0 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
No
Yes
IRIC = 1?
Write transmit data in ICDR
Read ACKB in ICSR
ACKB = 0? No
Yes No
Yes
Transmit mode?
Write transmit data in ICDR
Read IRIC in ICCR
IRIC = 1?
No
Yes
Clear IRIC in ICCR
Read ACKB in ICSR
End of transmission
or ACKB = 1?
No
Yes
Write BBSY = 0
and SCP = 0 in ICCR
End
Master receive mode
Read IRIC in ICCR
No IRIC = 1?
Clear IRIC in ICCR
[1] Initialize
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte (slave
address + R/W).
(After writing ICDR, clear IRIC
immediately)
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit, transferred from
slave device.
[10] Wait for 1 byte to be transmitted.
[11] Test for end of transfer
[12] Stop condition issuance
[9] Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC
immediately)
Figure 16.14 Flowchart for Master Transmit Mode (Example)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 538 of 1130
REJ09B0327-0400
Master receive operation
Read ICDR
Clear IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Read IRIC in ICCR
IRIC = 1?
Last receive ?
Yes Yes
No
No
No
Yes
Yes
Yes
No
Yes
Read ICDR
Read IRIC in ICCR
Clear IRIC in ICCR
IRIC = 1?
Last receive ?
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Read ICDR
Write BBSY = 0
and SCP = 0 in ICCR
End
No
IRIC = 1?
No
Set TRS = 0 in ICCR
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
Read IRIC in ICCR
[1] Select receive mode
[2] Start receiving. The first read is a dummy
read. After reading ICDR, please clear
IRIC immediately.
[3] Wait for 1 byte to be received.
(8th clock falling edge)
[4] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[5] Wait for 1 byte to be received.
(9th clock risig edge)
[6] Read the receive data.
[7] Clear IRIC
[8] Wait for the next data to be received.
(8th clock falling edge)
[9] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[10] Set ACKB = 1 so as to return no
acknowledge, or set TRS = 1 so as not
to issue extra clock.
[12] Wait for 1 byte to be received.
[14] Stop condition issuance.
[13] Set WAIT = 0.
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0.)
[11] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Figure 16.15 Flowchart for Master Receive Mode (Example)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 539 of 1130
REJ09B0327-0400
Start
Initialize
Set MST = 0
and TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Read IRIC in ICCR
IRIC = 1? Yes
No
Clear IRIC in ICCR
Read AAS and ADZ in ICSR
AAS = 1
and ADZ = 0?
Read TRS in ICCR
TRS = 0?
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Last receive?
Read ICDR
Read IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Set ACKB = 0 in ICSR
Read ICDR
Read IRIC in ICCR
Read ICDR
IRIC = 1?
Clear IRIC in ICCR
End
General call address processing
* Description omitted
Slave transmit mode
[1] Select slave receive mode.
[2] Wait for the first byte to be received (slave
address).
[3] Start receiving. The first read is a dummy read.
[4] Wait for the transfer to end.
[5] Set acknowledge data for the last receive.
[6] Start the last receive.
[7] Wait for the transfer to end.
[8] Read the last receive data.
Figure 16.16 Flowchart for Slave Receive Mode (Example)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 540 of 1130
REJ09B0327-0400
Slave transmit mode
Write transmit data in ICDR
Read IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read ACKB in ICSR
Set TRS = 0 in ICCR
End
of transmission
(ACKB = 1)?
Yes
No
No
Yes
End
[1]
[2]
[3]
Read ICDR [5]
[4]
[1] Set transmit data for the second and
subsequent bytes.
[2] Wait for 1 byte to be transmitted.
[3] Test for end of transfer.
[4] Select slave receive mode.
[5] Dummy read (to release the SCL line).
Figure 16.17 Flowchart for Slave Transmit Mode (Example)
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 541 of 1130
REJ09B0327-0400
16.3.11 Initialization of Internal State
The IIC has a functio n for forcible initialization of its in ter nal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR reg ister or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 16.2.8, DDC
Switch Register (DDCSWR).
Scope of Initia lization:
The initialization executed by this functio n covers the following item s:
• TDRE an d RDRF inter nal flags
• Transmit/receive sequencer and internal op erating clo ck counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clo c k , data
output, etc.)
The following items are n ot initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR)
• Internal latche s used to retain register r e ad infor m ation for setting/clear ing f lag s in the ICMR,
ICCR, ICSR, and DDCSWR registers
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Init ialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
• Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
• When initialization is perform ed by means of the DDCSWR register, the write data for bits
CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written
to simultaneously using an MOV instruction. Do not use a bit-manipulation instruction such as
BCLR. Similarly, when clearing is required again, all the bits must be written to
simultaneously in accordance with the setting.
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., mu st be carried out as
necessary to enable correct communication as a system.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 542 of 1130
REJ09B0327-0400
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and r elease timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing th e I IC state.
1. Execute in itialization of the intern al state by setting of bit CLR3 to CLR0 or by clearing ICE
bit.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execu te initialization of the internal state by setting of bit CLR3 to CLR0 or by clearing
ICE bit.
4. Initialize ( r e-set) the IIC r egisters.
16.4 Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive star t and stop cond itions, af ter issuing the in str uction that generates th e star t
condition , read th e relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transf er. Pay attention to these
conditions when reading or writing to ICDR.
Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 543 of 1130
REJ09B0327-0400
Table 16.6 I2C Bus Timing (SCL an d SDA Output)
Item Symbol Output Timing Unit Notes
SCL output cycle time tSCLO 28tcyc to 256tcyc ns
SCL output high pulse width tSCLHO 0.5tSCLO ns Figure 26.28
(reference)
SCL output low pulse width tSCLLO 0.5tSCLO ns
SDA output bus free time tBUFO 0.5tSCLO –1tcyc ns
Start condition output hold time tSTAHO 0.5tSCLO –1tcyc ns
Retransmi ss ion start condi tion out put
setup time tSTASO 1tSCLO ns
Stop condition output setup time tSTOSO 0.5tSCLO +2tcyc ns
Data output setup time (master) tSDASO 1tSCLLO –3tcyc ns
Data output setup time (slave) 1tSCLL –(6tcyc or 12tcyc*)
Data output hold time tSDAHO 3tcyc ns
Note: *6tcyc when IICX is 0, 12tcyc when 1.
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in I2C Bus Timing in section 26,
Electrical Characteristics, and as shown in table 26.10. Note that the I2C bus interface AC
timing specif icatio ns will not be met with a system clock frequen cy of less than 5 MHz.
• The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-
speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
the time determined by the input clock of the I2C bus interface, th e high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at th e set transfer rate, adjust the pull- up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 544 of 1130
REJ09B0327-0400
Table 16.7 P ermiss ible SCL Rise Time (tSr) Values
Time Indication
IICX tcyc
Indication
I2C Bus
Specification
(Max.) φ
φφ
φ =
5 MHz φ
φφ
φ =
8 MHz φ
φφ
φ =
10 MHz φ
φφ
φ =
16 MHz φ
φφ
φ =
20 MHz
07.5t
cyc Standard
mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns
High-speed
mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
1 17.5tcyc Standard
mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns
High-speed
mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
• The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. Th e I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
table 16.6. However, because of the rise and fall times, the I2C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
tBUFO fails to meet the I2C bus interface specifications at any frequency. Th e solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select d e vices whose input timing
permits this output timing for use as slave devices connected to the I2C bus.
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisf y the I2C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated
include (a ) adjusting the rise and fall tim es by means of a pull-u p resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing per mits this output timin g for use as slave devices connected to the I2C bus.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 545 of 1130
REJ09B0327-0400
Table 16.8 I2C Bus Timing (with Maximum Inf luence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
Item tcyc
Indication
tSr/tSf
Influence
(Max.)
I2C Bus
Specifi-
cation
(Min.) φ
φφ
φ =
5 MHz φ
φφ
φ =
8 MHz φ
φφ
φ =
10 MHz φ
φφ
φ =
16 MHz φ
φφ
φ =
20 MHz
tSCLHO 0.5tSCLO
(–tSr)Standard
mode –1000 4000 4000 4000 4000 4000 4000
High-speed
mode –300 600 950 950 950 950 950
tSCLLO 0.5tSCLO
(–tSf ) Standard
mode –250 4700 4750 4750 4750 4750 4750
High-speed
mode –250 1300 1000*11000*11000*11000*11000*1
tBUFO Standard
mode –1000 4700 3800*13875*13900*13938*13950*1
0.5tSCLO
–1tcyc (–tSr ) High-speed
mode –300 1300 750*1825*1850*1888*1900*1
tSTAHO Standard
mode –250 4000 4550 4625 4650 4688 47000.5tSCLO
–1tcyc (–tSf ) High-speed
mode –250 600 800 875 900 938 950
tSTASO 1tSCLO (–tSr ) Standard
mode –1000 4700 9000 9000 9000 9000 9000
High-speed
mode –300 600 2200 2200 2200 2200 2200
tSTOSO Standard
mode –1000 4000 4400 4250 4200 4125 41000.5tSCLO
+2tcyc (–tSr ) High-speed
mode –300 600 1350 1200 1150 1075 1050
tSDASO
(master) Standard
mode –1000 250 3100 3325 3400 3513 3550
1tSCLLO*3
–3tcyc (–tSr ) High-speed
mode –300 100 400 625 700 813 850
tSDASO
(slave) Standard
mode –1000 250 1300 2200 2500 2950 3100
1tSCLL*3
–12tcyc*2
(–tSr ) High-speed
mode –300 100 –1400*1–500*1–200*1250 400
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 546 of 1130
REJ09B0327-0400
Time Indication (at Maximum Transfer Rate) [ns]
Item tcyc
Indication
tSr/tSf
Influence
(Max.)
I2C Bus
Specifi-
cation
(Min.) φ
φφ
φ =
5 MHz φ
φφ
φ =
8 MHz φ
φφ
φ =
10 MHz φ
φφ
φ =
16 MHz φ
φφ
φ =
20 MHz
tSDAHO 3tcyc Standard
mode 0 0 600 375 300 188 150
High-speed
mode 0 0 600 375 300 188 150
Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore whether or not the I 2C bus interface specifications are
met must be determined in acc orda nc e with the act ual set ting co nditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL
−6tcyc).
3. Calculated using th e I2C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
• Note on ICDR Read at End of Master Reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will n ot be transferred to
ICDR, and so it will no t b e possible to read the second b yte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop cond ition has been g ener a ted, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance o f the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmissio n.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 547 of 1130
REJ09B0327-0400
Clearing of the MST bit after comp letion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
SDA
SCL
Internal clock
BBSY bit
Master receive mode
ICDR reading
prohibited
Bit 0 A
89
Stop condition
(a)
Start condition
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
issuance
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data
• Notes on Start Condition Issuance for Retransmission
Figure 16.19 shows th e timing of start cond ition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After start
condition issuance is done and d etermined the start conditio n, write the transmit da ta to ICDR,
as shown below.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 548 of 1130
REJ09B0327-0400
Read SCL pin
Write transmit data to ICDR
Clear IRIC in ICSR
Write BBSY = 1,
SCP = 0 (ICSR)
IRIC = 1 ? No
SCL = Low ? No
Yes
Start condition
issuance?
No
[1]
[2]
[3]
[4]
[5]
Note: Program so that processing from [3] to [5] is
executed continuously.
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue restart condition instruction for retransmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/W)
Other processing
Yes
Yes
IRIC = 1 ? No
Yes
Start condition
(retransmission)
SCL
bit 7ACK
9
IRIC
[1] IRIC determination Determination
of SCL = low
[2]
[3] Start condition
instruction issuance [4] IRIC
determination
[5]
SDA
ICDR write
(next transmit data)
Figure 16.19 Flowchart and Timing of Start Condition Instruction Issuance for
Retransmission
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 549 of 1130
REJ09B0327-0400
• Notes on I2C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising
of the 9th SCL clock, issue the stop condition instruction after reading SCL and determining it
to be low, as shown below.
Stop condition
SCL
IRIC
[1] Determination of SCL = low
9th clock
VIH High period secured
[2] Stop condition instruction issuance
SDA
As waveform rise is late,
SCL is detected as low
Figure 16.20 Timing of Stop Condition Issuance
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 550 of 1130
REJ09B0327-0400
• Notes on WAIT Function
Conditions to cause this ph e nomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clo c k fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
and the fall of the 8th clock.
Error phenomenon
Normally, WAIT State will be cancelled by clear ing th e IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT State will b e can celled right after WAIT inser tio n on 8th clock fall.
Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turn ed to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.21.)
SCL
BC2–BC0
Transmit/receive data A
ASD
7 6 5 4 3 2 1 0 7 6 5
1 2 3 4 5 6 7 8 9 1 2 3
0
IRIC flag clear unavailable
IRIC flag clear available IRIC flag clear available
9
A
IRIC
(operation
example)
SCL =
‘L’ confirm
IRIC clear When BC2-0 ≥ 2
IRIC clear
Transmit/receive
data
Figure 16.21 IRIC Flag Clear Timing on WAIT Operation
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 551 of 1130
REJ09B0327-0400
• Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
In a transmit operation in the slave mode of the I2C bus interface, do not read the ICDR register
or read or write to the ICCR register during the period indicated by the shaded portion in figure
16.22.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or read ing or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
ICCR register, is completed before the next slave address receive operation starts.
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
SDA R/W
Waveforms if
problem occurs
Bit 7
ICDR write
Data transmission
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Detection of 9th clock
cycle rising edge
A
89
SCL
TRS Address received
Figure 16.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 552 of 1130
REJ09B0327-0400
• Notes on TRS Bit Setting in Slave Mode
From the de tection of the rising edge of the 9th clock cy cle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.23)
in the slave mode of the I2C bus interface, the value set in the TRS bit in the ICCR register is
effective immediately.
However, at other times (indicated as (b) in figure 16.23) the value set in the TRS bit is put on
hold until the ne xt rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual intern al value of the TRS bit remain ing 1 (transmit mode ) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 16.23.
To cancel the holding of th e SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
SDA
SCL
A
(a) TRS bit
Detection of rise of 9th
transmit/receive clock
Address reception
Data
transmission
89 123456789
(a) (b)
TRS bit setting value
TRS bit effective value
Period in which TRS bit setting is retained
Resumption condition
(b) TRS bit
Detection of rise of 9th
transmit/receive clock
Figure 16.23 TRS Bit Setting Timing in Slave Mode
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 553 of 1130
REJ09B0327-0400
• Notes on Arbitration Lost in Master Mode
The I2C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is comp ared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I2C bus interface erroneously recognizes that the address call has occurred. (See
figure 16.24.)
In multi-m aster mode, a bus conflict could happen. When Th e I2C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted o r received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
S SLA R/W
S SLA R/WADATA2
S SLA R/WASLA R/W
A
DATA3
A
DATA4
DATA1
I
2
C bus interface
(Master transmit mode)
Transmit data match
Transmit timing match
• Receive address is ignored • Automatically transferred to slave
receive mode
• Receive data is recognized as
an address
• When the receive data matches to
the address set in the SAR or SARX
register, the I
2
C bus interface operates
as a slave device
• Arbitration is lost
• The AL flag in ICSR is set to 1
Transmit data does not match
Other device
(Master transmit mode)
I
2
C bus interface
(Slave receive mode)
Data contention
A
A
A
Figure 16.24 Diagram of Erroneous Operation when Arbitration is Lost
Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In mu lti-master mode , pay atten tion to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(b) Set the MST bit to 1.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 554 of 1130
REJ09B0327-0400
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR reg i ste r is 0 imme diately a fter the M ST bit has been
set.
• Notes on Interrupt Occurrence after ACKB Reception
Conditions to cause this failure
The IRIC flag is set to 1 when both of the following conditions are satisfied.
• 1 is received as the acknowledge bit for transmit data and the ACKB bit in ICSR is set
to 1
• Rising edge of the 9th transmit/receive clock is input to the SCL pin
When the above two conditions are satisfied in slave receive mode, an unnecessary
interrupt occu rs.
Figure 16.25 shows the note on interrupt occurrence in slave mode after receiving 1 as the
acknowledge bit (ACKB = 1).
(1) For the last transmit data in master transmit mode or slave transmit mode, 1 is received
as the acknowledge bit.
If the A CKE bit in ICCR is set to 1 at this time, the A CKB bit in ICSR is se t to 1.
(2) After switching to slave receive mode, th e start condition is input, and address
reception is performed next.
(3) Even if the received address does not match the address set in SAR or SARX, the IRIC
flag is set to 1 at the rise o f the 9th transmit/receive clock, thus causing an interrupt to
occur.
Note that if the slav e ad dress m atches, an interrupt is to be generated at the rise of the 9th
transmit/receive clock as n ormal op eration, so this is not erroneous operation.
Restriction
In a transmit oper ation of the I2C bus interface module, carry out the following
countermeasures.
(1) After 1 is received as the acknowledge bit for transmit data, clear the ACKE bit in
ICCR to 0 to clear the ACKB bit to 0.
(2) To enable acknowledge bit reception afterwards, set the ACKE bit to 1 again.
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 555 of 1130
REJ09B0327-0400
SDA
SCL
A
ACKB bit
(1) Acknowledge bit is received
and the ACKB bit is set to 1.
89 123456789
IRIC flag
Start
condition
12
N
Stop
condition
Stop condition
detection
Data
(2) Address that does not match is received.
Master transmit mode or
slave transmit mode
Countermeasure:
Clear the ACKE bit to 0 to clear
the ACKB bit.
Slave reception mode
Address
(3) Unnecessary interrupt occurs
(received address is invalid).
Figure 16.25 Note on Interrupt Occurrence in Slave Mode after ACKB = 1 Reception
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 556 of 1130
REJ09B0327-0400
• Notes on TRS Bit Setting and ICDR Register Access
Conditions to cause this failure
Low-fixation of the SCL pins is cancelled incorr ectly when the following conditions are
satisfied.
Master mode
Figure 16.26 shows the notes on ICDR reading (TRS = 1) in master mode.
(1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full).
(2) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)
(3) Sets to receive mode (TRS = 0), after transmitting Rev.1 frame of issued start condition
by master mode.
Slave mode
Figure 16.27 shows the notes on ICDR writing (TRS = 0) in slave mode.
(1) Writes ICDR register in receive mode (TRS = 0), after entering the start condition by
slave mode (TDRE = 0 state).
Address match with Rev.1 frame, receive 1 by R/W bit, and switches to transmit mode
(TRS = 1).
When these conditions are satisfied, the low fixation of the SCL pins is cancelled
without ICDR register access after Rev.1 frame is transferred.
Restriction
Please carry out the following countermeasures when transmitting/receiving via the IIC bus
interface module.
(1) Please read the ICDR registers in receive mode, and write them in transmit mode.
(2) In receiving operation with master mode, please issue the start condition after clearing
the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the
DDCSWR register on bus-free state (BBSY = 0).
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 557 of 1130
REJ09B0327-0400
SDA
SCL
A
TRS bit
Detection of 9th clock rise
(TRS = 1)
Address
8
RDRF bit
Start condition
12
A
3
Stop condition
ICDR read TRS = 0 setting
Data
ICDRS data
full
Along with ICDRS: ICDRR transfer
Cancel condition of SCL =
Low fixation is set.
(3) TRS = 0
(2) RDRF = 0
(1) ICDRS data full
9123456789
Figure 16.26 Notes on ICDR Reading with TRS = 1 Setting in Master Mode
SDA
SCL
A
TRS bit
TRS = 0 setting
Address
89 89
TDRE bit
Start condition
12
A
3
Stop condition
ICDR write
Data
(2) TRS = 1
(1) TDRE = 0
4
Automatic TRS = 1 setting by
receiving R/W = 1
Along with ICDRS: ICDRR transfer
Cancel condition of SCL =
Low fixation
1234567
Figure 16.27 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode
Section 16 I2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 558 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 559 of 1130
REJ09B0327-0400
Section 17 Keyboard Bu ffer Contr oller
Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group.
17.1 Overview
The H8S/2148 Group and H8S/2147N have three on-chip keyboard buffer controller channels,
designated 0, 1, and 2. The keyboard buffer controller is provided with functions conforming to
the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line,
providing economical use of connectors, board surface area, etc. Figure 17.1 shows how the
keyboard buffer controller is connected.
17.1.1 Features
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 560 of 1130
REJ09B0327-0400
Vcc
KCLK in
KCLK out
KD in
KD out
Keyboard buffer controller
(H8S/2148 Group and
H8S/2147N chip)
System side
KCLK in
KCLK out
KD in
KD out
I/F
Keyboard side
Vcc
Clock
Data
Figure 17.1 Keyboard Buffer Controller Connection
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 561 of 1130
REJ09B0327-0400
17.1.2 Block Diagram
Figure 17.2 shows a block diagram of the keyboard buffer controller.
KD
(PS2AD,
PS2BD,
PS2CD)
KDI
KCLKI
KDO
KCLKO
Parity
Register counter value
KB interrupt
KCLK
(PS2AC,
PS2BC,
PS2CC)
Legend:
KD: KBC data I/O pin
KCLK: KBC clock I/O pin
KBBR: Keyboard data buffer register
KBCRH: Keyboard control register H
KBCRL: Keyboard control register L
Control
logic
KBBR
KBCRH
KBCRL
Bus interface
Internal
data bus
Module data bus
Figure 17.2 Block Diagram of Keyboard Buffer Controller
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 562 of 1130
REJ09B0327-0400
17.1 .3 Input/Output Pins
Table 17.1 lists the input/output pins used by the keyboard buffer controller.
Table 17.1 Key board Buffer Controller Input/Output Pins
Channel Name Abbreviation*I/O Function
0 KBC clock I/O pin (KCLK0) PS2AC I/O KBC clock input/output
KBC data I/O pin (KD0) PS2AD I/O KBC data input/output
1 KBC clock I/O pin (KCLK1) PS2BC I/O KBC clock input/output
KBC data I/O pin (KD1) PS2BD I/O KBC data input/output
2 KBC clock I/O pin (KCLK2) PS2CC I/O KBC clock input/output
KBC data I/O pin (KD2) PS2CD I/O KBC data input/output
Note: *These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK
and data I/O pins as KD, omitting the channel designations.
17.1.4 Register Configuration
Table 17.2 lists the registers of the keyboard buffer controller.
Table 17.2 Keyboard Buffer Controller Registers
Channel Name Abbreviation R/W Initial Value Address*1
0 Keyboard control register H KBCRH0 R/(W)*2H'70 H'FED8
Keyboard control r egi ster L KBCRL0 R/W H'70 H ' FED9
Keyboard data buffer register KBBR0 R H'00 H'FEDA
1 Keyboard control register H KBCRH1 R/(W)*2H'70 H'FEDC
Keyboard control r egi ster L KBCRL1 R/W H'70 H ' FEDD
Keyboard data buffer register KBBR1 R H'00 H'FEDE
2 Keyboard control register H KBCRH2 R/(W)*2H'70 H'FEE0
Keyboard control r egi ster L KBCRL2 R/W H'70 H' FEE1
Keyboard data buffer register KBBR2 R H'00 H'FEE2
Common Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bits 2 and 1, to clear the flags.
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 563 of 1130
REJ09B0327-0400
17.2 Register Descriptions
17.2.1 Keyboard Control Register H (KBCRH)
Bit 76543210
KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS
Initial value01110000
Read/Write R/W R R R/W R/W R/(W)*R/(W)*R
Note: *Only 0 can be written, to clear the flags.
KBCRH is an 8-bit readable/writable register that indicates the operating status of the keyboard
buffer controller.
KBCRH is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode. Bits 6, 5, and 2 to 0 are also initialized when KBIOE is
cleared to 0.
Bit 7—Keyboard In/Out Enable (KBIOE): Selects whether or not the keyboard buffer
controller is used. When KBIOE is set to 1 , the keyboard buffer controller is en abled f or
transmission and reception and the port pins function as KCLK and KD I/O pins. When KBIOE is
cleared to 0, the keyboard buffer controller stops functioning and the port pins go to the high-
impedance state.
Bit 7
KBIOE Description
0 The keyboard buffer controller is non-operational (KCLK and KD signal pins have
port functions) (Initial value)
1 The keyboard buffer controller is enabled for transmission and reception (KCLK and
KD signal pins are in the bus drive state)
Bit 6—Keyboard Clock In (KCLKI): Monitors the KCLK I/O pin. This bit cannot be modified.
Bit 6
KCLKI Description
0 KCLK I/O pin is low
1 KCLK I/O pin is high (Initial value)
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 564 of 1130
REJ09B0327-0400
Bit 5—Keyboard Data In (KDI): Monitors the KDI I/O pin. This bit cannot be modified.
Bit 5
KDI Description
0 KD I/O pin is low
1 KD I/O pin is high (Initial value)
Bit 4—Keyboard Buffer Register Full Select (KBFSEL): Selects whether the KBF bit is used
as the keyboard bu ffer register full flag or as the KCLK fall interrupt flag, When KBFSEL is
cleared to 0, the KBE bit in the KBCRL register should be cleared to 0 to disable reception.
Bit 4
KBFSEL Description
0 KBF bit is used as KCLK fall interrupt flag
1 KBF bit is used as keyboard buffer register full flag (Initial value)
Bit 3—Keyboard Interrupt Enable (KBIE): Enables or disables interrupts from the keyboard
buffer con troller to the CPU.
Bit 3
KBIE Description
0 Interrupt requests are disabled (Initial value)
1 Interrupt requests are enabled
Bit 2—Keyboard Buffer Register Full (KBF): Indicates that data reception has been completed
and the received data is in the keyboard data buffer register (KBBR).
Bit 2
KBF Description
0 [Clearing condition] (Initial value)
Read KBF when KBF =1, then write 0 in KBF
1 [Setting conditions]
• When data has been received normally and has been transferred to KBBR
(keyboard buffer register full flag)
• When a KCLK falling edge is detected (while KBFSEL = 0) (KCLK interrupt flag)
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 565 of 1130
REJ09B0327-0400
Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred.
Bit 1
PER Description
0 [Clearing condition] (Initial value)
Read PER when PER =1, then write 0 in PER
1 [Setting condition]
When an odd parity error occurs
Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1.
Bit 0
KBS Description
0 0 stop bit received (Initial value)
1 1 stop bit received
17.2.2 Keyboard Control Register L (KBCRL)
Bit 76543210
KBE KCLKO KDO — RXCR3 RXCR2 RXCR1 RXCR0
Initial value01110000
Read/Write R/W R/W R/W — RRRR
KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls
the keyboard buffer controller pin output.
KBCRL is initialized to H'70 by a reset, and in standby m ode, watch mod e , su bactive mode,
subsleep mode, and module stop mode.
Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard
data buffer register (KBBR).
Bit 7
KBE Description
0 Loading of receive data into KBBR is disabled (Initial value)
1 Loading of receive data into KBBR is enabled
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 566 of 1130
REJ09B0327-0400
Bit 6—Keyboard Clock Out (KCLKO): Controls KBC clock I/O pin output.
Bit 6
KCLKO Description
0 Keyboard buffer controller clock I/O pin is low
1 Keyboard buffer controller cloc k I/O pin is high (Initial value)
Bit 5—Keyboard Data Out (KDO): Controls KBC data I/O pin output.
Bit 5
KDO Description
0 Keyboard buffer controller data I/O pin is low
1 Keyboard buffer controller data I/O pin is high (Initial value)
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
Bits 3 to 0—Receive Counter (RXCR3 to RXCR0): These bits indicate the received data bit.
Their value is incremented on the fall of KCLK. These bits cannot be modified.
The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its valu e return s
to 0000 after a stop bit is received.
Bit 3 Bit 2 Bit 1 Bit 0
RXCR3 RXCR2 RXCR1 RXCR0 Receive Data Contents
0 0 0 0 — (Initial value)
1 Start bit
1 0 KB0
1 KB1
1 0 0 KB2
1 KB3
1 0 KB4
1 KB5
1000KB6
1 KB7
1 0 Parity bit
1—
1 ———
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 567 of 1130
REJ09B0327-0400
17.2.3 Keyboard Data Buffer Register (KBBR)
Bit 76543210
KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Initial value00000000
Read/Write RRRRRRRR
KBBR is a read-only register that stores receive data. Its value is valid only when KBF = 1.
KBBR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode, and when KBIOE is cleared to 0.
17.2.4 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable register, performs module stop mode control.
When the MSTP2 bit is set to 1, the keyboard buffer controller halts and enters module stop mode.
See section 25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCR L Bit 2— Module Stop (MSTP2): Specifies keyboard buffer controller module stop
mode.
MSTPCRL
Bit 2
MSTP2 Description
0 Keyboard buffer controller module sto p mode is cl eared
1 Keyboard buffer controller module sto p mode is set (Initial value)
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 568 of 1130
REJ09B0327-0400
17.3 Operation
17.3.1 Receive Operation
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and
inputs on the H8S/2148 Group chip (system) side. KD receives a start bit, 8 data bits (LSB-first),
an odd parity bit, and a stop b it, in that order. The KD value is valid when KCLK is low. A sample
receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 569 of 1130
REJ09B0327-0400
Start
Set KBIOE bit
Read KBCRH
KCLKI
and KDI bits both
1?
Set KBE bit
Receive enabled state
KBF = 1?
PER = 0?
KBS = 1?
Read KBBR
Receive data processing
Clear KBF flag
(receive enabled state)
Keyboard side in data
transmission state.
Execute receive abort
processing.
Error handling
[1] Set the KBIOE bit to 1 in
KBCRL.
[2] Read KBCRH, and if the
KCLKI and KDI bits are
both 1, set the KBE bit
(receive enabled state).
[3] Detect the start bit output
on the keyboard side and
receive data in
synchronization with the fall
of KCLK.
[4] When a stop bit is received,
the keyboard buffer
controller drives KCLK low
to disable keyboard
transmission (automatic I/O
inhibit).
If the KBIE bit is set to 1 in
KBCRH, an interrupt
request is sent to the CPU
at the same time.
[5] Perform receive data
processing.
[6] Clear the KBF flag to 0 in
KBCRL. At the same time,
the system automatically
drives KCLK high, setting
the receive enabled state.
The receive operation can be
continued by repeating steps
[3] to [6].
[1]
[2]
[3]
[4]
[5]
[6]
Yes
No
Yes
Yes
Yes
No
No
No
Figure 17.3 Sample Receive Processing Flowchart
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 570 of 1130
REJ09B0327-0400
123
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
KB7 to KB0
PER
KBS
KBF
Start
bit
Parity bit
Stop bit
Receive processing/
error handling
Automatic I/O inhibit
Previous data Receive data
Flag cleared
9 10 11
701
KB0 KB1
[1] [2] [3] [4] [5] [6]
Figure 17.4 Receive Timing
17.3.2 Transmit Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the H8S/2148 Group and H8S/2147N chip (system) side. KD outputs a start bit, 8 data
bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK
is high. A sam ple transmit processin g flowchart is sh own in figure 17.5, and th e transmit timing in
figure 17.6.
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 571 of 1130
REJ09B0327-0400
Start
Set KBIOE bit
KCLKI = 0?
Read KBCRH
KCLKI
and KDI bits both
1?
Set I/O inhibit (KCLKO = 0)
KBE = 0
(KBBR reception disabled)
KDO remains at 1
Wait
Set start bit (KDO = 0)
Set I/O inhibit (KCLKO = 1)
KCLKO remains at 0
KDO remains at 0
i = 0
Read KBCRH
Set transmit data
(KDO = D(i))
Read KBCRH
KCLKI = 1?
i = i + 1
i > 9?
Read KBCRH
KCLKI = 1?
Yes
No
Notes: i = 0 to 7: Transmit data
i = 8: Parity bit
i = 9: Stop bit
No
Yes
Yes
Yes
Yes
No
No
No
1
2
[1] Set the KBE bit to 1 in KBCRH, and the
KBIOE bit to 1 in KBCRL.
[2] Read KBCRH, and if the KCLKI and
KDI bits are both 1, write 0 in the
KCLKO bit (set I/O inhibit).
[3] Write 0 in the KBE bit (disable KBBR
receive operation).
[4] Write 0 in the KDO bit (set start bit).
[5] Write 1 in the KCLKO bit (clear I/O
inhibit).
[6] Read KBCRH, and when KCLKI = 0,
set the transmit data in the KDO bit
(LSB-first). Next, set the parity bit and
stop bit in the KDO bit.
[7] After transmitting the stop bit, read
KBCRL and confirm that KDI = 0
(receive completed notification from the
keyboard).
[8] Read KBCRH. Confirm that the KCLKI
and KDI bits are both 1.
The transmit operation can be continued
by repeating steps [2] to [8].
[1]
[2]
[3]
[4]
[5]
[6]
Figure 17.5 Sample Transmit Processing Flowchart
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 572 of 1130
REJ09B0327-0400
Read KBCRH
Transmit end state
(KCLK = high, KD = high)
Yes
Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low.
1
KCLKI = 0? No
KDI = 0?
Read KBCRH
KCLK = 1?
Yes
Yes
No
No Error handling
To receive operation or
transmit operation
Keyboard side in data
transmission state.
Execute receive abort
processing.
2
*
[7]
[8]
Figure 17.5 Sample Transmit Processing Flowchart (cont)
1
01
01
7
7
2891011
KCLK
(pin state)
KD
(pin state)
KCLK
(output)
KD
(output)
KCLK
(input)
KD
(input)
Start bit
Start bit
Parity bit Stop bit
Parity bit Stop bit
I/O inhibit
Receive
completed
notification
[1] [2] [3] [4] [5] [6] [7] [8]
Figure 17.6 Transmit Timing
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 573 of 1130
REJ09B0327-0400
17.3.3 Receive Abort
The H8S/2148 Group and H8S/2147N device (system side) can forcibly abort transmission from
the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the
system holds the clock low. During reception, the keyboard also outputs a clock for
synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is
low at this time, the keyboard judges that there is an abort request from the system, and data
transmission from the keyboard is aborted. Thus the system can abort reception by holding the
clock low for a certain period. A sample receive abort processing flowchart is shown in figure
17.7, and the receive abort timing in figure 17.8.
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 574 of 1130
REJ09B0327-0400
Read KBCRL
KBF = 0?
RXCR3 to RXCR0 ≥
B'1001?
Disable receive abort
requests
Yes
Start
Receive state
Read KBCRH Processing 1
KCLKO = 0
(receive abort request)
Retransmit
command transmission
(data)?
KBE = 0
(disable KBBR reception
and clear receive counter)
Set start bit
(KDO = 0)
Clear I/O inhibit
(KCLKO = 1)
Transmit data
To transmit operation
KBE = 0
(disable KBBR reception
and clear receive counter)
KBE = 1
(enable KB operation)
Clear I/O inhibit
(KCLKO = 1)
To receive operation
[1] Read KBCRL, and if KBF = 1,
perform processing 1.
[2] Read KBCRH, and if the value of
bits RXCR3 to RXCR0 is less than
B'1001, write 0 in KCLKO to abort
reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
[3] If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
request following parity bit
reception is disabled. Wait until
stop bit reception is completed,
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
Yes
No
No
No
Yes
[1]
[2][3]
Figure 17.7 Sample Receive Abort Processing Flowchart
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 575 of 1130
REJ09B0327-0400
Receive data processing
Clear KBF flag
(KCLK = H)
Processing 1
Receive operation ends
normally [1] On the system side, drive the KCLK pin low,
setting the I/O inhibit state.
[1]
Transmit enabled state.
If there is transmit data,
the data is transmitted.
Figure 17.7 Sample Receive Abort Processing Flowchart (cont)
Keyboard side monitors clock during
receive operation (transmit operation
as seen from keyboard), and aborts
receive operation during this period.
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
KD
(input)
KD
(output)
Reception in progress Receive abort request
Transmit operation
Start bit
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover)
Timing
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 576 of 1130
REJ09B0327-0400
17.3.4 KCLKI and KDI Read Timing
Figure 17.9 shows the KCLKI and KDI read timing.
T1 T2
φ
*
Internal read
signal
KCLK, KD
(pin state)
KCLKI, KDI
(register)
Internal data bus
(read data)
Note: *
The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.9 KCLKI and KDI Read Timing
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 577 of 1130
REJ09B0327-0400
17.3.5 KCLKO and KDO Write Timing
Figure 17 .10 shows the KLCKO and KDO write timing and the KCLK and KD pin states.
Internal write
signal
φ*
KCLKO, KDO
(register)
KCLK, KD
(pin state)
Note: *The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
T1 T2
Figure 17.10 KCLKO and KDO Write Timing
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 578 of 1130
REJ09B0327-0400
17.3.6 KBF Setting Timing and KCLK Cont rol
Figure 17.11 shows the KBF setting timing and the KCLK pin states.
KCLK
(pin)
φ*
Internal
KCLK
Falling edge
signal
RXCR3 to
RXCR0
KCLK
(output)
KBF
11th fall
Automatic I/O inhibit
H'000H'010
Note: *The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17. 11 KBF Setting and KCLK Auto matic I/O Inhibit Generation Ti ming
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 579 of 1130
REJ09B0327-0400
17.3.7 Receive Timing
Figure 17.12 shows the receive timing.
N + 1 N + 2N
KCLK (pin)
Note: *The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active
mode.
KD (pin)
Internal
KCLK (KCLKI)
Falling edge
signal
RXCR3 to
RXCR0
Internal KD
(KDI)
KBBR7 to
KBBR0
φ*
Figure 17.12 Receive Counter and KBBR Data Load Timing
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 580 of 1130
REJ09B0327-0400
17.3.8 KCLK Fall Interrupt Operation
In this device, clearing the KBFSEL bit to 0 in KBCR H enables the KBF bit in KBCRL to be used
as a flag for the interrupt generated by the fall of KCLK input.
Figure 17.13 shows the setting method and an example of operation.
Start
Set KBIOE
KBF = 1
(interrupt generated)
KBE = 0
(KBBR reception
disabled)
Interrupt handling
Clear KBF
KCLK pin
fall detected?
KBFSEL = 0
KBIE = 1
(KCLK falling edge
interrupts enabled)
Yes
No
KCLK
(pin state)
KBF bit
Interrupt
generated Interrupt
generated
Cleared
by software
Note: The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit
generation in figure 17.11. When the KBF bit is used as the KCLK input fall interrupt flag, the
automatic I/O inhibit function does not operate.
Figure 17.13 Example o f KCLK Input Fall Interrupt Operatio n
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 581 of 1130
REJ09B0327-0400
17.3.9 Usage Note
When KBIOE is 0, the internal KCLK and in ternal KD settin gs are fixed at 1.
Therefore, if the KCLK p in is low when the KBIOE bit is set to 1, the edge detection circu it
operates and the KCLK falling edge is detected.
If the KBFSEL bit an d KBE bit are both 0 at this time, th e KBF bit is set. Figure 17.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
T1 T2
φ
KCLK (pin)
Internal KCLK
(KCLKI)
Falling edge
signal
KBIOE
KBFSEL
KBE
KBF
Figure 17.14 KBIOE Setting and KCLK Falling Edg e Det ection Timing
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 582 of 1130
REJ09B0327-0400
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 583 of 1130
REJ09B0327-0400
Section 18 Host Interface
Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group.
18.1 Overview
The H8S/2148 Group and H8S/2147N have an on-chip host interface (HIF) that enables
connection to an ISA bus, widely used as the internal bus in personal computers. The host
interface provides a four-channel parallel interface between the on-chip CPU and a host processor.
The host interface is available only when the HI12E bit is set to 1 in SYSCR2. This mode is called
slave mode, because it is designed for a master-slave communication system in which the
H8S/2148 Group and H8S/2147N chip is slaved to a host processor.
18.1.1 Features
The features of the host interface are summarized below.
The host interface consists of 8-byte data registers, 4-byte status registers, a 2-byte control
register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via
seven control signals from the host processor (CS1, CS2 or ECS2, CS3, CS4, HA0, IOR, and
IOW), six output signals to the host processor (GA20, HIRQ1, HIRQ11, HIRQ12, HIRQ3, and
HIRQ4), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The CS1, CS2 (or
ECS2), CS3, and CS4 signals select one of the four interface channels.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 584 of 1130
REJ09B0327-0400
18.1.2 Block Diagram
Figure 18.1 shows a block diagram of the host interface.
Internal interrupt signals
IBF2 IBF1
Control logic
HDB7 to HDB0
IDR3
ODR3
STR3
IDR4
ODR4
STR4
HICR2
Module data bus
Host data bus
Host
interrupt
request
Fast
A20 gate
control
Port 4, port 8, port B
Internal data bus Bus
interface
CS1
C
S2/ECS2
CS3
CS4
IOR
IOW
HA0
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
HIFSD
IDR1
ODR1
STR1
IDR2
ODR2
STR2
HICR
IBF4 IBF3
Legend:
IDR1:
IDR2:
ODR1:
ODR2:
STR1:
STR2:
HICR:
Input data register 1
Input data register 2
Output data register 1
Output data register 2
Status register 1
Status register 2
Host interface control register 1
IDR3:
IDR4:
ODR3:
ODR4:
STR3:
STR4:
HICR2:
Input data register 3
Input data register 4
Output data register 3
Output data register 4
Status register 3
Status register 4
Host interface control register 2
Figure 18.1 Block Diagram of Host Interface
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 585 of 1130
REJ09B0327-0400
18.1 .3 Input and Output Pins
Table 18.1 lists the input and output pins of the host interface module.
Table 18.1 Ho st Interface Input/Output Pins
Name Abbreviation Port I/O Function
I/O read IOR P93 Input Host interface read signal
I/O write IOW P94 Input Host interface write signal
Chip select 1 CS1 P95 Input Host interface chip select sig nal for IDR1,
ODR1, STR1
Chip select 2*CS2 P81 Input
ECS2 P90 Host interface chip select signal for IDR2,
ODR2, STR2
Chip select 3 CS3 PB2 Input Host interf ace ch ip sele ct sig nal for IDR3,
ODR3, STR3
Chip select 4 CS4 PB3 Input Host interf ace ch ip sele ct sig nal for IDR4,
ODR4, STR4
Command/data HA0 P80 Input Host interface address select signal.
In host read access, this signal selects the
status registers (STR1 to STR4) or data
registers (ODR1 to ODR4). In host write
access to the data registers (IDR1 to IDR3,
and IDTR4), this signal indicates whether
the host is writing a command or data.
Data bus HDB7 to HDB0 P37 to
P30 I/O Host interface data bus
Host interrupt 1 HIRQ1 P44 Output Interrupt output 1 to host
Host interrupt 11 HIRQ11 P43 Output Interrupt output 11 to host
Host interrupt 12 HIRQ12 P45 Output Interrupt output 12 to host
Host interrupt 3 HIRQ3 PB0 Output Interrupt output 3 to host
Host interrupt 4 HIRQ4 PB1 Output Interrupt output 4 to host
Gate A20 GA20 P81 Output A20 gate control signal output
HIF shutdown HIFSD P82 Input Host interface shutdown control signal
Note: *Selection of CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in
HICR. Host interface channel 2 and the CS2 pin can be used when CS2E = 1. When
CS2E = 1, CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this
manual, both are referred to as CS2.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 586 of 1130
REJ09B0327-0400
18.1.4 Register Configuration
Table 18.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,
ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 18.2 Host Interface Registers
R/W Master Address*4
Name Abbrevia-
tion Slave Host Initial
Value Slave
Address*3CS1
CS1CS1
CS1 CS2
CS2CS2
CS2 CS3
CS3CS3
CS3 CS4
CS4CS4
CS4 HA0
System control register SYSCR R/W*1— H'09 H'FFC4 — — ———
System control regist er 2 SYSCR2 R/W — H' 00 H'FF83 — — ———
Host interface control
register 1 HICR R/W — H'F8 H'FFF0 — — ———
Host interface control
register 2 HICR2 R/W — H'F8 H'FE80 — — ———
Input data register 1 I DR1 R W — H'FFF4 0 1 110/1*5
Output data register 1 ODR1 R/W R — H'FFF5 01110
Status regist er 1 STR1 R/(W)*2R H'00 H'FFF6 01111
Input data register 2 I DR2 R W — H'FFFC 10110/1
*5
Output data register 2 ODR2 R/W R — H'FFFD 10110
Status regist er 2 STR2 R/(W)*2RH'00H'FFFE 10111
Input data regist er 3 IDR3 R W — H'FE84 11010/1
*5
Output data register 3 ODR3 R/W R — H'FE85 11010
Status regist er 3 STR3 R/(W)*2RH'00H'FE86 11011
Input data regist er 4 IDR4 R W — H'FE8C 11100/1
*5
Output data register 4 ODR4 R/W R — H'FE8D 11100
Status regist er 4 STR4 R/(W)*2RH'00H'FE8E 11101
Module stop control MSTPCRH R/W — H'3F H'FF86 —————
register MSTPCRLR/W — H'FFH'FF87 —————
Notes: 1. Bits 5 and 3 are read-only bits.
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
processor.
3. Address when accessed from the slave processor. The lower 16 bits of the address are
shown.
4. Pin inputs used in access from the host processor.
5. The HA0 input discr im inat es betw ee n writ ing of com m ands and data .
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 587 of 1130
REJ09B0327-0400
18.2 Register Descriptions
18.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
SYSCR is an 8-bit readable/writable register which controls H8S/2148 Group chip operations. Of
the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be
accessed when the HIE bit is set to 1. HICR2, IDR3, ODR3, STR3, IDR4, ODR4, and STR4 can
be accessed regardless o f the setting of the HIE bit. The host interface CS2 and ECS2 pins are
controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System
Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information
on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware stan dby mode.
Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E b it in HICR to select the pin
that performs the CS2 function.
SYSCR
Bit 7 HICR
Bit 0
CS2E FGA20E Description
00CS2 pin function halted (CS2 fixed high internally) (Initial value)
1
10CS2 pin function selected for P81/CS2 pin
1CS2 pin function selected for P90/ECS2 pin
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 588 of 1130
REJ09B0327-0400
Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to the host interface
registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2,
and STR2) can be accessed.
Bit 1
HIE Description
0 Ho st interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is disabled (Initial value)
1 Ho st interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is enabled
18.2.2 System Control Register 2 (SYSCR2)
Bit 76543210
KWUL1 KWUL0 P6PUE —SDE CS4E CS3E HI12E
Initial value0000000 0
Read/Write R/W R/W R/W —R/W R/W R/W R/W
SYSCR2 is an 8- bit readable/writable r egister wh ich controls chip operatio ns. Host interface
functions are enabled or disabled by the HI12E bit in SYSCR2. The number of channels that can
be used can be extended to a maximum of four by means of the CS3E bit and CS4E bit. SYSCR2
is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be
set and changed by software. For details see section 8, I/O Ports.
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see
section 8, I/O Ports.
Bit 4—Reserved: Do not write 1 to this bit.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 589 of 1130
REJ09B0327-0400
Bit 3—Shutdo wn Enab le (SDE): Enables or disables the host interface pin shutdown function.
When this function is enabled, host interface pin functions can be halted, and the pins placed in the
high-impedance state, accord ing to the state of the HIFSD pin.
Bit 3
SDE Description
0 Host interface pin shutdown function disabled (Initial value)
1 Host interface pin shutdown function enabled
Bit 2—CS4 Enable (CS4E): Enables or disables host interface channel 4 functions in slave mode.
When these functions are en abled, channel 4 pins are enabled and processing can be performed for
data transfer between the slave and the host.
Bit 2
CS4E Description
0 Host interf ace pin chann el 4 functi ons di sab led (Initial value)
1 Host interface pin channel 4 functions enabled
Bit 1—CS3 Enable (CS3E): Enables or disables host interface channel 3 functions in slave mode.
When these functions are en abled, channel 3 pins are enabled and processing can be performed for
data transfer between the slave and the host.
Bit 1
CS3E Description
0 Host interf ace pin chann el 3 functi ons di sab led (Initial value)
1 Host interface pin channel 3 functions enabled
Bit 0—Host Interface Enable Bit (HI12E): Enables or disables host interface functions in
single-chip mode. When the host interface functions are enabled, slave mode is entered and
processing is performed for data transfer between the slave and host.
Bit 0
HI12E Description
0 Host interface functions are disabled (Initi al val ue)
1 Host interface functions are enabled
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 590 of 1130
REJ09B0327-0400
18.2.3 Host Interface Control Register (HICR)
• HICR
Bit
Initial value
Slave Read/Write
Host Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
FGA20E
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
• HICR2
Bit
Initial value
Slave Read/Write
Host Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
—
0
—
—
2
IBFIE4
0
R/W
—
1
IBFIE3
0
R/W
—
HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts
and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host
interface channel 3 and 4 interrupts. HICR and HICR2 are in itialized to H'F8 by a reset and in
hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
HICR Bits 2 and 1—I nput Data Register Full Interrupt Ena ble 2 and 1 (IBFIE2, IBFIE1)
HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3)
These bits enable o r disable the IBF1, IBF2, IBF3, and IBF4 inter r upts to the internal CPU.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 591 of 1130
REJ09B0327-0400
HICR2
Bit 2 HICR2
Bit 1 HICR
Bit 2 HICR
Bit 1
IBFIE4 IBFIE3 IBFIE2 IBFIE1 Description
———0 Input data register (IDR1) reception completed interrupt
request disabled (Initial value)
———1 Input data register (IDR1) reception completed interrupt
request enabled
——0 — Input data register (IDR2) reception completed interrupt
request disabled (Initial value)
——1 — Input data register (IDR2) reception completed interrupt
request enabled
— 0 ——Input data register (IDR3) reception completed interrupt
request disabled (Initial value)
— 1 ——Input data register (IDR3) reception completed interrupt
request enabled
0———Input data register (IDR4) reception completed interrupt
request disabled (Initial value)
1———Input data register (IDR4) reception completed interrupt
request enabled
HICR Bit 0—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate
function. Wh en the fast A20 gate is disabled, the normal A20 gate can be implemented byte
firmware operation of the P81 output.
HICR
Bit 0
FGA20E Description
0 Fast A20 gate function disabled (Initial value)
1 Fast A20 gate function enabled
HICR2 Bit 0—Reserved: Do not set this b it to 1.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 592 of 1130
REJ09B0327-0400
18.2.4 Input Data Register 1 (IDR1)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CSn (n = 1 to 4) is low, information on th e host data bus is written into
IDRn at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STRn to indicate
whether the wr itten info rmation is a command or data.
The initial values of IDR1 after a reset and in stand by m ode ar e undetermined.
18.2.5 Output Data Register 1 (ODR)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register
to the host processor. The ODRn contents are output on the host data bus when HA0 is low, CSn
(n = 1 to 4) is low, and IOR is low.
The initial values of ODR1 after a reset and in standby mode are undetermined.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 593 of 1130
REJ09B0327-0400
18.2.6 Status Register (STR)
Bit
Initial value
Slave Read/Write
Host Read/Write
Note: * Only 0 can be written, to clear the flag.
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R/(W)*
R
2
DBU
0
R/W
R
1
IBF
0
R
R
STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface
processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors.
STR is initialized to H'00 by a reset and in hardwar e stan dby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D
DD
D): Receives the HA0 input when the host processor writes to IDR1,
and indicates whether IDR1 contains data or a command.
Bit 3
C/D
DD
DDescription
0 Contents of input data register (IDR1) are data (Initial value)
1 Contents of input data register (IDR1) are a command
Bit 1—Input Buffer Full (IBF): Set to 1 when the host p rocesso r writes to IDR1. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR1.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 18.7.
Bit 1
IBF Description
0 [Clearing condition]
When the slave processor reads IDR (Initial value)
1 [Setting condition]
When the host processor writes to IDR
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 594 of 1130
REJ09B0327-0400
Bit 0—Output Buffe r Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to
0 when the host processor reads ODR.
Bit 0
OBF Description
0 [Clearing condition]
When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value)
1 [Setting condition]
When the slave proces sor write s to ODR
Table 18.3 shows the conditions for setting and clearing the STR flags.
Table 18.3 Set/Clear Timing for STR Flags
Flag Setting Condition Clearing Condition
C/DRising edge of host’s write signal
(IOW) when HA0 is high Rising edge of host’s write signal (IOW) when
HA0 is low
IBF*Rising edge of host’s write signal
(IOW) when writing to IDR1 Falling edge of slave’s internal read signal (RD)
when reading IDR1
OBF Falling edge of slave’s internal write
signal (WR) when writing to ODR1 Rising edge of host’s read signal (IOR) when
reading ODR1
Note: *The IBF flag setting and clearing conditions are different when the fast A20 gate is
used. For details see table 18.7.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 595 of 1130
REJ09B0327-0400
18.2.7 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section
25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCR L Bit 2— Module Stop (MSTP2): Specifies host interface module stop mode.
MSTPCRL
Bit 2
MSTP2 Description
0 Host interface module stop mode is cleared
1 Host interface module stop mode is set (Initial value)
18.3 Operation
18.3.1 Host Interface Activation
The HIF (slave mo de) is activated by setting the HI 12E bit (bit 0) in SYSCR2 to 1 in single-ch ip
mode. When the HIF (slave mode) is activated , all related I/O ports (data por t 3, contro l por ts 8
and 9, and host interrup t request port 4) become dedicated host interface ports. Setting the CS3E
bit and CS4E bit to 1 enables the numb er of HIF chan nels to be extended to a four, and mak e s the
channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated
host interface port.
Table 18.4 shows HIF host interface channel selection and pin operation.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 596 of 1130
REJ09B0327-0400
Table 18.4 Host Interface Channel Selectio n and Pin Operatio n
HI12E CS2E CS3E CS4E Operation
0———Host interface fun ctio ns hal ted
1 0 0 0 Host interface channel 1 only operating
Operation of channe ls 2 to 4 halted
(No operation as CS2 or ECS2, CS3, and CS4 inputs. Pins
P43, P81, P90, and PB0 to PB3 operate as I/O ports.)
1 Host interface channel 1 and 4 functions operating
Operation of channels 2 and 3 halted
(No operation as CS2 or ECS2 and CS3 inputs. Pins P43, P81,
P90, PB0, and PB2 operate as I/O ports.)
1 0 Host interface channel 1 and 3 functions operating
Operation of channels 2 and 4 halted
(No operation as CS2 or ECS2 and CS4 inputs. Pins P43, P81,
P90, PB1, and PB3 operate as I/O ports.)
1 Host interface channel 1, 3, and 4 functions operating
Operation of channel 2 halted
(No operation as CS2 or ECS2 input. Pins P43, P81, and P90
operate as I/O ports.)
1 0 0 Host interface channel 1 and 2 functions operating
Operation of channels 3 and 4 halted
(No operation as CS3 and CS4 inputs. Pins PB0 to PB3
operate as I/O ports.)
1 Host interface channel 1, 2, and 4 functions operating
Operation of channel 3 halted
(No operation as CS3 input. Pins PB0 and PB2 operate as I/O
ports.)
1 0 Host interface ch anne l 1 to 3 functions oper ating
Operation of channel 4 halted
(No operation as CS4 input. Pins PB1 and PB3 operate as I/O
ports.)
1 Host interface ch anne l 1 to 4 functions oper ating
For host read/write timing, see section 26.7.5, Timing of On-Chip Supporting Modules.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 597 of 1130
REJ09B0327-0400
18.3.2 Control States
Table 18.5 shows host interface operations from the HIF host, and slave operation.
Table 18.5 Host Interface Operations from HIF Host, and Slave Operation
Other than
CSn
CSnCSn
CSn CSn
CSnCSn
CSn IOR
IORIOR
IOR IOW
IOWIOW
IOW HA0 Operation
1 0000Setting prohibited
1 Setting prohibited
1 0 Data read from output data register n (ODRn)
1 Status read from status register n (STRn)
1 0 0 Data written to input data register n (IDRn)
1 Command written to input data register n (IDRn)
10Idle state
1 Idle state
Note: n = 1 to 4
18.3.3 A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be
output under firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0)
to 1 in HICR (H'FFF0).
Note: * Intel microprocessor.
Regular A20 Gate Operation
Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the
slave processor receives data, it normally uses an interrupt routin e activated by the IBF1 interrupt
to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs
it at the gate A20 pin.
Fast A20 Gate Operation
When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit
P81DDR must be set to 1 to assig n this pin for outp ut. The initial output from this pin will be a
logic 1, which is the initial value. Afterward, th e host pr ocessor can manipulate the outp ut from
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 598 of 1130
REJ09B0327-0400
this pin by sending commands and data. This function is available only when register IDR1 is
accessed using CS1. Slave logic decodes the commands input from the host processor. When an
H'D1 host command is detected, bit 1 of the data following the host command is output from the
GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the
regular processing using interrupts. Table 18.6 lists the conditions that set and clear GA20 (P81).
Figure 18.2 shows the GA20 output in flowchart form. Table 18.7 indicates the GA20 output
signal values.
Table 18.6 GA20 (P81) Set/Clear Timing
Pin Name Setting Condition Clearing Condition
GA20
(P81) Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 1
and the data follows an H'D1 host
command
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 0
and the data follows an H'D1 host
command
Also, when bit FGA20E in HICR is cleared
to 0
Start
Host write
H'D1 command
received?
Wait for next byte
Host write
Yes
Data byte?
Write bit 1 of data byte
to DR bit of P81/GA20
Yes
No
No
Figure 18.2 GA20 Output
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 599 of 1130
REJ09B0327-0400
Table 18.7 Fast A20 Gate Output Signal
HA0 Data/Command Internal CPU
Interrupt Flag GA20
(P81) Remarks
1
0
1
H'D1 command
1 data*1
H'FF command
0
0
0
Q
1
Q (1)
Turn-on sequence
1
0
1
H'D1 command
0 data*2
H'FF command
0
0
0
Q
0
Q (0)
Turn-off sequence
1
0
1/0
H'D1 command
1 data*1
Command other than H'FF
and H'D1
0
0
1
Q
1
Q (1)
Turn-on sequence
(abbreviated form)
1
0
1/0
H'D1 command
0 data*2
Command other than H'FF
and H'D1
0
0
1
Q
0
Q (0)
Turn-off sequence
(abbreviated form)
1
1H'D1 command
Command other than H'D1 0
1Q
QCancelled sequence
1
1H'D1 command
H'D1 command 0
0Q
QRetriggered seq uen ce
1
0
1
H'D1 command
Any data
H'D1 command
0
0
0
Q
1/0
Q(1/0)
Consecut ive ly executed
sequences
Notes: 1. Arbitrary data with bit 1 set to 1.
2. Arbitrary data with bit 1 cleared to 0.
18.3.4 Host Interface Pin Shutdown Function
Host interface output can be placed in the high-impedance state according to the state of the
HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register enab les the HIFSD pin is slave m ode.
The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface
output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the high-impedance state.
At the same time, the host interface input pins (CS1, CS2 or ECS2, CS3, CS4, IOW, IOR, and
HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the
signals of th e multiplexed function s o f these pin s (in put block) are similarly fixed internally. As a
result, the host interface I/O pins (HDB7 to HDB0) also go to the high-impedance state.
This state is maintained while the HIFSD pin is low, and when the HIFSD p in returns to the high-
level state, the pins are restored to their normal operation as host interface pins.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 600 of 1130
REJ09B0327-0400
Table 18.8 shows the scope of HIF pin shutdown in slave mode.
Table 18.8 Scope of HIF Pin Shutdown in Slave Mo de
Abbreviation Port
Scope of
Shutdown in
Slave Mode I/O Selection Conditions
IOR P93 O Input Slave mode
IOW P94 O Input Slave mode
CS1 P95 O Input Slave mode
CS2 P81 ∆Input Slave mode and CS2E = 1 and FGA20E = 0
ECS2 P90 ∆Input Slave mode and CS2E = 1 and FGA20E = 1
CS3 PB2 ∆Input Slave mode and CS3E = 1
CS4 PB3 ∆Input Slave mode and CS4E = 1
HA0 P80 O Input Slave mode
HDB7 to
HDB0 P37 to
P30 O I/O Slave mode
HIRQ11 P43 ∆Output Slave mode and CS2E = 1 and P43DDR = 1
HIRQ1 P44 ∆Output Slave mode and P44DDR = 1
HIRQ12 P45 ∆Output Slave mode and P45DDR = 1
HIRQ3 PB0 ∆Output Slave mode and CS3E = 1 and PB0DDR = 1
HIRQ4 PB1 ∆Output Slave mode and CS4E = 1 and PB1DDR = 1
GA20 P81 ∆Output Slave mode and FGA20E = 1
HIFSD P82 —Input Slave mode and SDE = 1
Legend:
O: Pins shut down by shutdown function
The IRQ2/ADTRG input signal is also fixed in the case of P90 shutdown, the TMCI1/HSYNCI
signal in the case of P43 shutdown, and the TMRI/CSYNCI in the case of P45 shutdown.
∆: Pins shut down only when the HIF function is selected by means of a register setting
—: Pin not shut down
Note: Slave mode: Single-chip mode and HI12E = 1
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 601 of 1130
REJ09B0327-0400
18.4 Interrupts
18.4.1 IBF1, IBF2, IBF3, IBF4
The host interface can issue two interrupt requests to the slave CPU: IBF1, IBF2, IBF3, and IBF4.
They are input buf fer full interrupts for input data registers IDR1 , I D R2, IDR3, and I D R4
respectively. Each interrupt is enabled when the co rresponding enable bit is set.
Table 18.9 Input Buffer Full Interrupts
Interrupt Description
IBF1 Requested when IBFIE1 is set to 1 and IDR1 is full
IBF2 Requested when IBFIE2 is set to 1 and IDR2 is full
IBF3 Requested when IBFIE3 is set to 1 and IDR3 is full
IBF4 Requested when IBFIE4 is set to 1 and IDR4 is full
18.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4
In slave mode (single-chip mode, with HI12E = 1 in SYSCR2), bits P45DR to P43DR in the port
4 data register (P4DR) and bits PB1ODR and PB0ODR in the port B data register (PBODR) can
be used as host interrupt request latches
The corresponding bits in P4DR are cleared to 0 by the host processor’s read signal (IOR). If CS1
and HA0 are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared
to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to
0. The corresponding bit in PBODR is cleared to 0 by the host’s read signal (IOR). If CS3 and
HA0 are low, when IOR goes low and the host reads ODR3, HIRQ3 is cleared to 0. If CS4 and
HA0 are low, when IOR goes low and the host reads ODR4, HIRQ4 is cleared to 0. To generate a
host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing
the interru pt, the host’s interrupt handling routine reads the output data register ( ODR1, ODR2,
ODR3, or ODR4) and this clears th e host interrupt latch to 0.
Table 18.10 indicates how these bits are set and cleared. Figure 18.3 shows the processing in
flowchart form.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 602 of 1130
REJ09B0327-0400
Table 18.1 0 HIRQ Setting/Clearing Conditio ns
Host Interrupt
Signal Setting Condition Clearing Condition
HIRQ11
(P43) Internal CPU reads 0 from bit P43DR,
then writes 1 In ternal CPU writes 0 in bit P43DR, or
host reads output data register 2
HIRQ1
(P44) Internal CPU reads 0 from bit P44DR,
then writes 1 In ternal CPU writes 0 in bit P44DR, or
host reads output data register 1
HIRQ12
(P45) Internal CPU reads 0 from bit P45DR,
then writes 1 In ternal CPU writes 0 in bit P45DR, or
host reads output data register 1
HIRQ3
(PB0) Internal CPU reads 0 from bit PB0ODR,
then writes 1 In ternal CPU writes 0 in bit PB0ODR,
or host reads output data register 3
HIRQ4
(PB1) Internal CPU reads 0 from bit PB1ODR,
then writes 1 In ternal CPU writes 0 in bit PB1ODR,
or host reads output data register 4
Slave CPU Master CPU
Write to ODR
Write 1 to P4DR
P4DR = 0?
Yes
No
No
Yes
All bytes
transferred?
HIRQ output high
HIRQ output low
Interrupt initiation
ODR read
Hardware operations
Software operations
Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 603 of 1130
REJ09B0327-0400
HIRQ Setting/Clea r ing Contention
If there is contention between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11,
HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held
pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is
executed after comp letion of the read/write.
18.5 Usage Note
The following points require attention when using the host interface.
(1) Host and slave transmission/reception procedures
The host interface provides buffering of asynchronous data from the host and slave processors,
but an interface protocol must be followed to implement necessary functions and avoid data
contention. For example, if the host and slave processors try to access the same input or output
data register simultaneously, the data will b e corrupted. Interrupts can be used to design a
simple and effective protocol.
(2) Preventing data contention on the HDB
When the HIF function is used (HI12E = 1 in SYSCR2) and channel 3 or channel 4 has been
set as deselected (CS3E = 0 or CS4E = 0 in SYSCR2), apply either of the following usage
conditions.
1. Ensure th at the CS pin for the deselected channel is fixed high.
2. Do not perform port B reads.
(3) Preventing through-current in pins CS1 to CS4
Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attemp ting IDR or
ODR access, signal contention will occur within the chip, and a through-current may result.
This usage must therefore be avoided.
Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 604 of 1130
REJ09B0327-0400
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 605 of 1130
REJ09B0327-0400
Section 19 D/A Converter
19.1 Overview
This LSI have an on-chip D/A converter module with two channels.
19.1.1 Features
Features of the D/A converter module are listed below.
• Eight-bit resolution
• Two-channel outp ut
• Maximum conversion time: 10 µs (with 20-pF load capacitance)
• Output voltage: 0 V to AVref
• D/A output retention in software standby mode
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 606 of 1130
REJ09B0327-0400
19.1.2 Block Diagram
Figure 19.1 shows a block diagram of the D/A converter.
Bus interface
Module data bus Internal data bus
8-bit D/A
DADR0
DADR1
DACR
Control
circuit
AVref
AVCC
DA0
DA1
AVSS
Legend:
DACR:
DADR0:
DADR1:
D/A control register
D/A data register 0
D/A data register 1
Figure 19.1 Block Diagram of D/A Converter
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 607 of 1130
REJ09B0327-0400
19.1 .3 Input and Output Pins
Table 19.1 lists the input and output pins used by the D/A converter module.
Table 19.1 Input and O ut put Pins of D/A Converter Module
Name Abbreviation I/O Function
Analog supply voltage AVCC Input Power supply for analog circuits
Analog ground AVSS Input Ground and reference voltage for analog
circuits
Analog output 0 DA0 Output Analog output channel 0
Analog output 1 DA1 Output Analog output channel 1
Reference volt age pin AVref Input Referen ce volt age for anal og circ uits
19.1.4 Register Configuration
Table 19.2 lists the registers of the D/A converter module.
Table 19.2 D/A Converter Registers
Name Abbreviation R/W Initial Value Address*
D/A data register 0 DADR0 R/W H'00 H'FFF8
D/A data register 1 DADR1 R/W H'00 H'FFF9
D/A control register DACR R/W H'1F H'FFFA
MSTPCRH R/W H'3F H'FF86Module stop contro l
register MSTPCRL R/W H'FF H'FF87
Note: *Lower 16 bits of the address.
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 608 of 1130
REJ09B0327-0400
19.2 Register Descriptions
19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1 )
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
D/A data registers 0 and 1 (DADR0 and DADR1) are 8-b it read able/writable reg isters th at store
data to be converted. When analog output is enabled, the value in the D/A data register is
converted and output continuously at the analog output pin.
The D/A data registers are initialized to H'00 by a reset and in hardware standby mode.
19.2.2 D/A Control Register (DACR)
Bit
Initial value
Read/Write
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
DACR is an 8-b it readable/writable register th at controls the operation of the D/A converter
module.
DACR is initialized to H'1F by a reset and in hardware standby mode.
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7
DAOE1 Description
0 Analog output DA1 is disabled (Initial value)
1 D/A conversion is enabled on channel 1. Analog output DA1 is enabled
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 609 of 1130
REJ09B0327-0400
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0 Description
0 Analog output DA0 is disabled (Initial value)
1 D/A conversion is enabled on channel 0. Analog output DA0 is enabled
Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and
DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0.
Channels 0 and 1 are controlled together when DAE = 1.
Output of the converted results is always con tro lled independently by DAOE0 and DAOE1 .
Bit 7 Bit 6 Bit 5
DAOE1 DAOE0 DAE D/A conversion
00*Disabled on channels 0 and 1
1 0 Enabled on channel 0
Disabled on cha nnel 1
1 Enabled on channels 0 and 1
1 0 0 Disabled on channel 0
Enabled on channel 1
1 Enabled on channels 0 and 1
1*Enabled on channels 0 and 1
Legend:
*: Don’t care
If the chip enters software standby mode while D/A conversion is enabled, the D/A output is
retained and the analog power supply current is the same as during D/A conversion. If it is
necessary to reduce the analog power supply current in software standby mode, disable D/A
output by clearing the DAOE0, DAOE1 , and DAE bits to 0.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 610 of 1130
REJ09B0327-0400
19.2.3 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP10 bit is set to 1, the D/A converter halts and enters module stop mode at the end
of the bus cycle. See section 25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 2—Module Stop (M STP10): Specifies D/A converter module stop mode.
MSTPCRH
Bit 2
MSTP10 Description
0 D/A converter module stop mode is cleared
1 D/A converter module stop mode is set (Initial value)
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 611 of 1130
REJ09B0327-0400
19.3 Operation
The D/A converter module has two built-in D/A converter circuits that can operate independently.
D/A conversion is performed continuously when ever enabled by the D/A control register (DACR).
When a new va lu e is written in DADR0 or DADR1 , conversion of the new value begins
immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1.
An example of conversion on channel 0 is given next. Figure 19.2 shows the timing.
• Software writes the data to be converted in DADR0.
• D/A conversion begins when the DAOE0 bit in DACR is set to 1. After the elapse of the
conversion time, analog output appears at the DA0 pin. The output value is AVref × (DADR
value)/256.
This outpu t contin ues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.
• If a new value is written in DADR0, conversion begins immediately. Output of the converted
result begins after the conversion time.
• When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
DADR0
write cycle DACR
write cycle DADR0
write cycle DACR
write cycle
Address
φ
DADR0
DAOE0
DA0
Conversion data (1) Conversion data (2)
High-impedance state
Conversion result (1) Conversion result (2)
t
DCONV
t
DCONV
t : D/A conversion time
Legend:
DCONV
Figure 19.2 D/A Conversion (Example)
Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 612 of 1130
REJ09B0327-0400
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 613 of 1130
REJ09B0327-0400
Section 20 A/D Converter
20.1 Overview
This LSI incorporate a 10-bit successive-approximations A/D converter that allows up to eight
analog input channels to be selected.
In addition to the eight analog input channels, up to 16 channels of digital input can be selected fo r
A/D conversion. Since the conversion precision falls when digital input is selected, digital input is
ideal for use by a co mparator identifying multi-valued inputs, fo r example.
20.1.1 Features
A/D converter features are listed below.
• 10-b it resolution
• Eight (analog) or 16 (digital) input channels
• Settable analog conversion voltage range
The analog conversion voltage range is set using the reference power supply voltage pin
(AVref) as the analog reference vo ltage
• High-speed conversion
Minimum conversion time: 6.7 µs per channel (at 20-MHz operation)
• Choice of single mode or scan mode
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on 1 to 4 channels
• Four data registers
Conversion results are held in a 16-bit data register for each channel
• Sample and hold fun c tion
• Three kinds of conversion start
Choice of so f twar e or tim er conversion start trigg e r (8- bit timer), or ADTRG pin
• A/D conversion end interrupt generation
An A/D conversion end interrupt (ADI) request can be generated at the end of A/D
conversion
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 614 of 1130
REJ09B0327-0400
20.1.2 Block Diagram
Figure 20.1 shows a block diagram of the A/D converter.
Module data bus
Control circuit
Internal
data bus
10-bit D/A
Comparator
+
–
Sample-and-
hold circuit
φ/8
φ/16
ADI interrupt
signal
Bus interface
ADCSR
ADCR
ADDRD
ADDRC
ADDRB
ADDRA
AVCC
AVref
AVSS
AN0
AN1
AN2
AN3
AN4
AN5
AN6/CIN0 to CIN7
AN7/CIN8 to CIN15
ADTRG Conversion start
trigger from 8-bit
timer
Successive approximations
register
Multiplexer
Legend:
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 20.1 Block Diagram of A/D Converter
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 615 of 1130
REJ09B0327-0400
20.1.3 Pin Configuration
Table 20.1 summarizes the input pins used by the A/D converter.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.
Table 20.1 A/D Converter Pins
Pin Name Symbol I/O Function
Analog power supply pin AVCC Input Analog block power supply
Analog ground pin AVSS Input Analog block ground and A/D conversion
reference voltag e
Reference power supply pin AVref Input A/D conversion reference voltage
Analog input pin 0 AN0 Input Analog input channel 0
Analog input pin 1 AN1 Input Analog input channel 1
Analog input pin 2 AN2 Input Analog input channel 2
Analog input pin 3 AN3 Input Analog input channel 3
Analog input pin 4 AN4 Input Analog input channel 4
Analog input pin 5 AN5 Input Analog input channel 5
Analog input pin 6 AN6 Input Analog input channel 6
Analog input pin 7 AN7 Input Analog input channel 7
A/D external trigger input pin ADTRG Input External trigger input for starting A/D
conversion
Expansion A/D input pins
0 to 15 CIN0 to
CIN15 Input Expansion A/D conversion input (digital
input pin) channels 0 to 15
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 616 of 1130
REJ09B0327-0400
20.1.4 Register Configuration
Table 20.2 summarizes the registers of the A/D conv erter.
Table 20.2 A/D Converter Registers
Name Abbreviation R/W Initial Value Address*1
A/D data register AH ADDRAH R H'00 H'FFE0
A/D data register AL ADDRAL R H'00 H'FFE1
A/D data register BH ADDRBH R H'00 H'FFE2
A/D data register BL ADDRBL R H'00 H'FFE3
A/D data register CH ADDRCH R H'00 H'FFE4
A/D data register CL ADDRCL R H'0 0 H'FFE5
A/D data register DH ADDRDH R H'00 H'FFE6
A/D data register DL ADDRDL R H'0 0 H'FFE7
A/D control/status register ADCSR R/(W)*2H'00 H'FFE8
A/D control register ADCR R/W H'3F H'FFE9
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Keyboard compara tor contr ol
register KBCOMP R/W H'00 H'FEE4
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bit 7, to clear the flag.
20.2 Register Descriptions
20.2.1 A/D Da ta Registers A to D (ADDRA to ADDRD)
15
AD9
0
R
Bit
Initial value
Read/Write
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
—
0
R
4
—
0
R
3
—
0
R
2
—
0
R
1
—
0
R
0
—
0
R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to sto r e the results of
A/D conversion.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 617 of 1130
REJ09B0327-0400
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are tran sferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
20.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower by te, data tran sfer is performed via a temporary register ( TEMP) . For details, see section
20.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode,
subactive mode, subsleep mode, and module stop mode.
Table 20.3 Analo g Input Channels a nd Corresponding ADDR Registers
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 or CIN0 to CIN7 ADDRC
AN3 AN7 or CIN8 to CIN15 ADDRD
20.2.2 A/D Control/Status Register (ADCSR)
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Bit
Initial value
Read/Write
Note: * Only 0 can be written in bit 7, to clear the flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
ADCSR is initialized to H'00 by a reset, and in standby mode, watch mode, sub active mode,
subsleep mode, and module stop mode.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 618 of 1130
REJ09B0327-0400
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing conditions] (Initial value
)
• When 0 is written in the ADF flag after reading ADF = 1
• When the DTC is activated by an ADI interrupt and ADDR is read
1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE Description
0 A/D conversion end interrupt (ADI) request is disabled (Initial value
)
1 A/D conversion end interrupt (ADI) request is enabled
Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1
during A/D conversion.
The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external
trigger input pin (ADTRG).
Bit 5
ADST Description
0 A/D conversion stopped (Initial value
)
1 Single mode: A/D conversion is started. Cleared to 0 automatically when conversion
on the specified channel ends
Scan mode: A/D conversion is started. Conversion continues sequentially on the
selected channels until ADST is cleared to 0 by software, a rese t, or a
transition to standby mode or module stop mode
Bit 4—Scan Mo de (SCAN): Selects single mode or scan mode as the A/D conversion operating
mode. See section 20 .4, Operation, for single mode and scan mode operation. Only set the SCAN
bit while conversion is stopped.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 619 of 1130
REJ09B0327-0400
Bit 4
SCAN Description
0 Single mode (Initial value
)
1 Scan mode
Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time
while ADST = 0.
Bit 3
CKS Description
0 Conversion time = 266 states (max.) (Initial value
)
1 Conversion time = 134 states (max.)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, th ese bits select
the analog input channel(s).
One analog input channel can be switched to digital input.
Only set the input channel while conversion is stopped.
Group
Selection Channel Selection Description
CH2 CH1 CH0 Single Mode Scan Mode
0 0 0 AN 0 (Initial value) AN0
1 AN1 AN0, AN1
1 0 AN2 AN0 to AN2
1 AN3 AN0 to AN3
100AN4 AN4
1 AN5 AN4, AN5
1 0 AN6 or CIN0 to CIN7 AN4, AN5,
AN6 or CIN0 to CIN7
1 AN7 or CIN8 to CIN15 AN4 , AN5,
AN6 or CIN0 to CIN7
AN7 or CIN8 to CIN15
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 620 of 1130
REJ09B0327-0400
20.2.3 A/D Control Register (ADCR)
7
TRGS1
0
R/W
6
TRGS0
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or
disabling of the start of A/D conv ersion by a trigger signal. Only set bits TRGS1 and TRGS0
while conversion is stopped.
Bit 7 Bit 6
TRGS1 TRGS0 Description
0 0 Start of A/D conversion by external trigge r is disabled (Initial value)
1 Start of A/D conversion by external trigger is disabled
1 0 Start of A/D conversion by external trigger (8-bit timer) is enabled
1 Start of A/D conversion by external trigger pin is enabled
Bits 5 to 0—Reserved: Should always be written with 1.
Note: So m e of these bits are readable/wr itable in products other th an the HD6 4F2148,
HD64F2147N, HD64F2144, HD64F2142R and HD6432142, however, wh en writing, be
sure to write 1 here for software compatib ility.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 621 of 1130
REJ09B0327-0400
20.2.4 Keyboard Comparator Control Register (KBCOMP)
Bit 76543210
IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
KBCOMP is an 8-bit readable/writable r egister that controls the SCI 2 IrDA function and selects
the CIN input channels for A/D conversion.
KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—IrDA Control: See the description in section 15.2.11, Keyboard Comparator Control
Register (KBCOMP).
Bit 3—Keyboard A/D Enable (KBADE): Selects either analog input pins (AN6, AN7) or digital
input pins (CIN0 to CIN7, CIN8 to CIN15) for A/D converter channel 6 and channel 7 input.
Bits 2 to 0—Keyboard A/D Channel Select 2 to 0 (KBCH2 to KBCH0): These bits select the
channels for A/D conversion from among the digital input pins. Only set the input channel while
A/D conversion is stopped.
Bit 3 Bit 2 Bit 1 Bit 0
KBADE KBCH2 KBCH1 KBCH0 A/D Conve rte r
Channel 6 Input A/D Converter
Channel 7 Input
0———AN6 AN7
1 0 0 0 CIN0 CIN8
1 CIN1 CIN9
1 0 CIN2 CIN10
1 CIN3 CIN11
1 0 0 CIN4 CIN12
1 CIN5 CIN13
1 0 CIN6 CIN14
1 CIN7 CIN15
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 622 of 1130
REJ09B0327-0400
20.2.5 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of th e bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 1—Module Stop (M STP9): Specifies the A/D converter module stop mode.
MSTPCRH
Bit 1
MSTP9 Description
0 A/D converter module stop mode is cleared
1 A/D converter module stop mode is set (Initial value
)
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 623 of 1130
REJ09B0327-0400
20.3 Interface to Bus Master
ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte
value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADDR, always read the upper byte before the lower byte. It is possible to read only
the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 20.2 shows the data flow for ADDR access.
Bus master
(H'AA)
ADDRnH
(H'AA) ADDRnL
(H'40)
Lower byte read
ADDRnH
(H'AA) ADDRnL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
(n = A to D)
(n = A to D)
Module data bus
Module data bus
Bus interface
Upper byte read
Bus master
(H'40) Bus interface
Figure 20.2 ADDR Access Operation (Reading H'AA40)
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 624 of 1130
REJ09B0327-0400
20.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
20.4.1 Single Mode (SCAN = 0)
Single mode is selected when A/D conversion is to be performed on a single channel only. A/D
conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion, and is auto m a tically cleared to 0 when
conversion ends.
On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an
ADI interrup t r equest is generated. The ADF flag is clear ed by writing 0 after reading ADCSR.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit
can be set at the same time as the operating mode or input channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure
20.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the
A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time the
ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D inter r upt handling routine star ts.
5. The routine reads ADCSR, then writes 0 to the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Executio n of the A/D interrupt handling ro utine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 625 of 1130
REJ09B0327-0400
ADIE
ADST
ADF
State of channel 0 (AN0)
A/D
conversion
starts
2
1
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
Note:
*
Vertical arrows ( ) indicate instructions executed by software.
Set
*
Set
*
Clear
*
Clear
*
A/D conversion result 1
A/D conversion
A/D conversion result 2
Read conversion result
Read conversion result
Idle
Idle
Idle
Idle
Idle Idle
A/D conversion
Set
*
Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 626 of 1130
REJ09B0327-0400
20.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or mo re channels
are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR
registers corresponding to the channels.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit
can be set at the same time as the operating mode or input channel is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 20.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), an alog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1)
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again . I f the ADIE bit is set to 1 at this
time, an ADI interrupt is requested after A/D conversion ends.
5. Steps 2 to 4 are repeated as long as the ADST b it remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 627 of 1130
REJ09B0327-0400
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 0 (AN0)
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
Set*
1
Clear*
1
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
Clear*
1
Idle
Idle
A/D conversion time
Idle
Continuous A/D conversion execution
A/D conversion 1
Idle Idle
Idle
Idle
Idle
Transfer
*
2
A/D conversion 3
A/D conversion 2 A/D conversion 5
A/D conversion 4
A/D conversion result 1
A/D conversion result 2
A/D conversion result 3
A/D conversion result 4
Figure 20.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 628 of 1130
REJ09B0327-0400
20.4.3 Input Sampling and A/D Co nversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D
conversion timing. Table 20.4 indicates the A/D conversion time.
As indicated in figure 20.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 20.4.
In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
(2)
t
D
t
SPL
t
CONV
A
ddress
φ
Write signal
Input sampling
timing
A
DF
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 20.5 A/D Conversion Timing
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 629 of 1130
REJ09B0327-0400
Table 20.4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max
A/D conversion start delay tD10 —17 6 — 9
Input sampling tim e tSPL —63 ——31 —
A/D conversion time tCONV 259 —266 131 —134
Note: Values in the table are the number of states.
20.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are th e same as when the ADST bit is set to 1 by software. Figure 20 .6 shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 20.6 External Trigger Input Timing
20.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 630 of 1130
REJ09B0327-0400
20.6 Usage Notes
The following points should be noted when using the A/D converter.
Setting Rang e of Analog Power Supply and Other P ins
1. Analog input voltage range
The voltage applied to the ANn analog input pins during A/D conversion should be in the
range AVSS ≤ ANn ≤ AVref (n = 0 to 7).
2. Digital input voltage range
The voltage applied to the CINn digital input pins should be in the range AVSS ≤ CINn ≤ AVref
and VSS ≤ CINn ≤ VCC (n = 0 to 15).
3. Relation between AVCC, AVSS and VCC, VSS
As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is
not used, the AVCC and AVSS pins must on no account be left open.
4. Setting Range of AVref Pin:
The reference voltage supplied via the AVref pin should be in the range AVref ≤ AVCC.
If conditions 1 to 4 above are not m et, the reliability of the device may be adversely affected.
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circu itry must be isolated from the analog input sign als ( AN0 to AN7), analog
reference power supply (AVref), and analog power supply (AVCC) by the analog ground (AVSS).
Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS)
on the board.
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN7) or analog reference power supply pin (AVref) should
be connected between AVCC and AVSS as shown in figure 20.7.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 631 of 1130
REJ09B0327-0400
Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0
to AN7 must be connected to AVSS.
If a filter capacitor is connected as shown in figure 20.7, the input currents at the analog input pins
(AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed
frequently, as in scan mode, if the current charged and discharged by the capacitance of the
sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required
when deciding the circuit constants.
AVCC
*1
AVref
AN0 to AN7
AVSS
Notes: Figures are reference values.
1.
2. Rin: Input impedance
*1Rin*2100 Ω
0.1 µF
0.01 µF10 µF
Figure 20.7 Example o f Analog Input Pr otection Circuit
Table 20. 5 Analog Pin Rati ngs
Item Min Max Unit
Analog input capacitance —20 pF
Permissible signal source impedance —10*kΩ
Note: *When VCC = 4.0 to 5.5 V and φ ≤ 12 MHz.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 632 of 1130
REJ09B0327-0400
AN0 to AN7 10 kΩ
20 pF
To A/D converter
Note: Numeric values are reference values.
Figure 20.8 Analog Input Pin Equiva lent Circuit
A/D Conversion Precision Definitions
The A/D conversion precision in this LSI is defined as follows.
• Resolution
The number of A/D converter digital output codes
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 20.10).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'111111111 (H'3FF) (see
figure 20.11).
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 20.9).
• Nonlinearity er ror
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.
• Absolute pr ecision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 633 of 1130
REJ09B0327-0400
H'3FF
H'3FE
H'3FD
H'004
H'003
H'002
H'001
H'000 1
1024 2
1024 1023
1024
1022
1024 FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
Figure 20.9 A/D Conversion Precision Definitions (1)
FS
Offset error
Nonlinearity
error
Actual A/D conversion
characteristic
Analog
input voltage
Digital output
Ideal A/D conversion
characteristic
Full-scale error
Figure 20.10 A/D Conversion Precision Definitions (2)
Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 634 of 1130
REJ09B0327-0400
Permissible Signal Source Impedance
Analog input in this LSI is designed so that conversion precision is guaranteed for an input signal
for which the signal source impedance is 10 kΩ (AVcc = 4.0 to 5.5 V, when φ ≤ 12 MHz) or less.
This specification is provided to enable the A/D converter’s sample-and-hold circuit input
capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ
(AVcc = 4.0 to 5.5 V, when φ ≤ 12 MHz), charging may be insufficient and it may not be possible
to guarantee the A/D conversion precision.
However, if a large cap acitance is provided externally, the in put load will essentially compr ise
only the in ternal input resistance of 10 kΩ, and the signal source impedance is ignored.
But since a low-p a ss f ilter effect is obtaine d in this case, it may not be possible to follow an an alog
signal with a large differential coefficient (e.g., 5 mV/µsec or greater).
When converting a high-speed analog signal, a low-impedance buffer should be inserted.
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVSS.
Care is also required to in sure that filter circuits d o not communicate with digital signals on th e
mounting board, so acting as antennas.
A/D converter
equivalent circuit
This LSI
20 pF
Cin =
15 pF
10 kΩ
Low-pass
filter
C to 0.1 µF
Sensor output
impedance,
up to 10 kΩ
Sensor input
Note: Values are reference values.
Figure 20.11 Example of Ana log Input Circuit
Section 21 RAM
Rev. 4.00 Sep 27, 2006 page 635 of 1130
REJ09B0327-0400
Section 21 RAM
21.1 Overview
The H8S/2148, H8S/2144, and H8S/2143 have 4 kbytes of on-chip high-speed static RAM, and
the H8S/2147, H8S/2147N, and H8S/2142 have 2 kbytes. The on-chip RAM is connected to the
CPU by a 16-bit data bus, enabling both by te data and word data to be accessed in one state. This
makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the
system control register (SYSCR).
21.1.1 Block Diagram
Figure 21.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFE080
H'FFE082
H'FFE084
H'FFEFFE
H'FFE081
H'FFE083
H'FFE085
H'FFEFFF
H'FFFF00
H'FFFF7E
H'FFFF01
H'FFFF7F
Figure 21.1 Block Diagram of RAM (H8S/2148, H8S/2144, H8S/2143)
Section 21 RAM
Rev. 4.00 Sep 27, 2006 page 636 of 1130
REJ09B0327-0400
21.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21.1 shows the register configuration.
Table 21.1 Register Configuration
Name Abbreviation R/W Initial Value Address*
System control register SYSCR R/W H'09 H'FFC4
Note: *Lower 16 bits of the address.
21.2 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
The on-chip RAM is en abled or disabled by the RAME b it in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RA M Enable ( R AME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in sof twar e stan dby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value
)
Section 21 RAM
Rev. 4.00 Sep 27, 2006 page 637 of 1130
REJ09B0327-0400
21.3 Operation
21.3.1 Expanded Mode (Modes 1, 2, 3 (EXPE = 1))
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to
H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the off-chip address space.
Since the on-chip RAM is connected to the bu s master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
21.3.2 Single-Chip Mode (Mode s 2 and 3 (EXPE = 0))
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed.
Undefined values are read from these bits, and writing is invalid.
Since the on-chip RAM is connected to the bus ma ster by a 1 6-b it data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Section 21 RAM
Rev. 4.00 Sep 27, 2006 page 638 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 639 of 1130
REJ09B0327-0400
Section 22 ROM
(Mask ROM Version, H8S/2148 F-ZTAT,
H8S/2147N F-ZTAT, H8S/2144 F-ZT AT,
and H8S/2142 F-ZTAT)
22.1 Overview
The H8S/2148 and H8S/2144 have 128 kbytes of on-chip ROM (flash memory or mask ROM),
the H8S/2143 has 96 kbytes, the H8S/2147, H8S/2147N, and H8S/2142 have 64 kbytes. The
ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in
one state, enabling faster instruction fetches and higher processing speed.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM.
The flash memory versions of the H8S/2148, H8S/2147N, H8S/2144, and H8S/2142 can be erased
and programmed on -board as well as with a general-purpose PROM programmer.
22.1.1 Block Diagram
Figure 22.1 shows a block diagram of the ROM.
H'000000
H'000002
H'01FFFE
H'000001
H'000003
H'01FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 22.1 ROM Block Diagram (H8S/2148, H8S/2144)
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 640 of 1130
REJ09B0327-0400
22.1.2 Register Configuration
This group on-chip ROM is controlled by the operating mode and register MDCR. The register
configuration is shown in table 22.1.
Table 22.1 ROM Register
Register Name Abbreviation R/W Initial Value Address*
Mode control register MDCR R/W Undefined
Depends on the operating mode H'FFC5
Note: *Lower 16 bits of the address.
22.2 Register Descriptions
22.2.1 Mode Control Register (MDCR)
Bit
Initial value
Read/Write
7
EXPE
—*
R/W*
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
—
0
—
1
MDS1
—*
R
Note: * Determined by the MD1 and MD0 pins.
MDCR is an 8-bit register used to set this group operating mode and monitor the current operating
mode.
The EXPE bit is initialized in accordance with the mode pin states by a reset and in hard ware
standby mode.
Bit 7—Expanded Mo de Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1
and cannot be modified. In mod es 2 and 3, EXPE ha s an initial valu e of 0 and can be read or
written.
Bit 7
EXPE Description
0 Single-chip mode selected
1 Expanded mode selected
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 641 of 1130
REJ09B0327-0400
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the
input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0
correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
When MDCR is read , the input levels of m ode pins MD1 and MD0 are latched in these bits.
22.3 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data is
accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the
lower 8 bits. Word data must start at an even address.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM, as shown in table 22.2.
In normal mode, the maximum amount of ROM that can be used is 56 kbytes.
Table 22.2 Opera ting Modes and ROM
Operating Mode
Mode Pins MDCR
MCU
Operating
Mode
CPU
Operating
Mode Description MD1 MD0 EXPE On-Chip ROM
Mode 1 Normal Expanded mode with
on-chip ROM disabled 01 1Disabled
Mode 2 Advanced Single-chip mode 1 0 0 Enabled*
Advanced Expanded mode with
on-chip ROM enabled 1
Mode 3 Normal Single-chip mode 1 0
Normal Expanded mode with
on-chip ROM enabled 1Enabled
(max. 56 kbytes)
Note: *128 kbytes in the H8S/2148 and H8S/2144, 96 kbytes in the H8S/2143, 64 kbytes in the
H8S/2147, H8S/2147N, and H8S/2142.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 642 of 1130
REJ09B0327-0400
22.4 Overview of Flash Memory
22.4.1 Features
The features of the flash memory are summarized below.
• Four flash memo ry operating modes
Program mode
Erase mode
Program-verif y mode
Erase-verify mode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in
single-bloc k units). When erasin g multiple blocks, the individual blocks must be erased
sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-
kbyte, and 32-kbyte blocks.
• Programm ing/er a se times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogram ming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
Boot mode
User program mode
• Automatic bit r a te ad justment
With data transfer in boot mode, the bit rate of the chip can be autom a tically adjusted to match
the transfer bit rate of the host.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 643 of 1130
REJ09B0327-0400
22.4.2 Block Diagram
Module bus
Bus interface/controller
Flash memory
(128 kbytes/64 kbytes)
Operating
mode
FLMCR2
Internal address bus
Internal data bus (16 bits)
Mode pins
EBR1
EBR2
FLMCR1 *
*
*
*
Legend:
FLMCR1: Flash memory control register 1
FLMCR2: Flash memory control register 2
EBR1: Erase block register 1
EBR2: Erase block register 2
Note: * These registers are used only in the flash memory version. In the mask ROM version,
a read at any of these addresses will return an undefined value, and writes are invalid.
Figure 22.2 Block Diagram of Flash Memory
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 644 of 1130
REJ09B0327-0400
22.4.3 Flash Memory Operating Modes
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of
the operating modes shown in figure 22.3. In user mode, flash memory can be read but not
programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
Boot mode
On-board programming mode
User
program mode
User mode with
on-chip ROM
enabled
Reset state
Programmer
mode
RES = 0
SWE = 1 SWE = 0 *
2
*1
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1
2. MD0 = MD1 = 0, P92 = P91 = P90 = 1
RES = 0
RES = 0
RES = 0
MD1 = 1
Figure 22.3 Flash Memory Mode Transitions
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 645 of 1130
REJ09B0327-0400
On-Board Programming Modes
• Boot mode
Flash memory
The chip
RAM
Host
Programming control
program
SCI
Application program
(old version)
Programming control
program
New application
program
Programming control
program
New application
program
Flash memory
The chip
RAM
Host
SCI
Application program
(old version)
Boot program area
New application
program
Flash memory
The chip
RAM
Host
SCI
Flash memory
erase
Boot program
Flash memory
The chip
Program execution state
RAM
Host
SCI
New application
program
Boot program
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data
is being rewritten. The user should prepare the
programming control program and new
application program beforehand in the host.
2. SCI communication check
When boot mode is entered, the boot program in
the chip (originally incorporated in the chip) is
started, an SCI communication check is carried
out, and the boot program required for flash
memory erasing is automatically transferred to
the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM by SCI communication is
executed, and the new application program in the
host is written into the flash memory.
Boot programBoot program
Boot program area Programming
control program
Figure 22.4 Boot Mode
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 646 of 1130
REJ09B0327-0400
• User program mode
Flash memory
The chip
RAM
Host
Programming/
erase control program
SCI
Boot program
New application
program
Flash memory
The chip
RAM
Host
SCI
New application
program
Flash memory
The chip
RAM
Host
SCI
Flash memory
erase
Boot program
New application
program
Flash memory
The chip
Program execution state
RAM
Host
SCI
Boot program
Boot program
Application program
(old version)
New application
program
1. Initial state
(1) The program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand.
(2) The programming/erase control program
should be prepared in the host or in the flash
memory.
2. Programming/erase control program transfer
Executes the transfer program in the flash
memory, and transfers the programming/erase
control program to RAM.
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Programming/
erase control program
Programming/
erase control program
Programming/
erase control program
Transfer program
Application program
(old version)
Transfer program
Transfer program
Transfer program
Figure 22.5 User Program Mode (Example)
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 647 of 1130
REJ09B0327-0400
Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode
Entire memory erase Yes Ye s
Block erase No Yes
Programming contr ol program *Program/program-verify Program/program-verify
Erase/erase-verify
Note: *To be provided by the user, in accordance with the recommended algorithm.
Block Configuration
The flash memory is divided into two 32-kbyte blocks (128-kbyte version only), two 8-kbyte
blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Address H'00000
Address H'0FFFF
Address H'00000
1 kbyte
1 kbyte
1 kbyte
1 kbyte
Address H'1FFFF
128 kbytes
32 kbytes
(b) 64-kbyte version(a) 128-kbyte version
32 kbytes
8 kbytes
8 kbytes
16 kbytes
28 kbytes
1 kbyte
1 kbyte
1 kbyte
1 kbyte
8 kbytes
8 kbytes
16 kbytes
28 kbytes
64 kbytes
Figure 22.6 Flash Memory Block Configuration
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 648 of 1130
REJ09B0327-0400
22.4.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 22.3 .
Table 22.3 Flash Memory Pins
Pin Name Abbreviation I/O Function
Reset RES Input Reset
Mode 1 MD1 Input Sets MCU operating mode
Mode 0 MD0 Input Sets MCU operating mode
Port 92 P92 Input Sets MCU operating mode when MD1 = MD0 = 0
Port 91 P91 Input Sets MCU operating mode when MD1 = MD0 = 0
Port 90 P90 Input Sets MCU operating mode when MD1 = MD0 = 0
Transmit data TxD1 Output Serial transmit data output
Receive data RxD1 Input Serial receive data input
22.4.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 22.4.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 22.4 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address*1
Flash memory control register 1 FLMCR1*5R/W*3H'80 H'FF80*2
Flash memory control register 2 FLMCR2*5R/W*3H'00*4H'FF81*2
Erase block regi ster 1 EBR1*5R/W*3H'00*4H'FF82*2
Erase block regi ster 2 EBR2*5R/W*3H'00*4H'FF83*2
Serial/timer control register STCR R/W H'00 H'FFC3
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
performed by the FLSHE bit in the serial/timer control register (STCR).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invali d.
4. The SWE bit in FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states. These registers are used only in the
flash memory version. In the mask ROM version, a read at any of thes e addresses will
return an undefined value, and writes are invalid.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 649 of 1130
REJ09B0327-0400
22.5 Register Descriptions
22.5.1 Flash Memory Control Register 1 (FLMCR1)
Bit 76543210
FWE SWE ——EV PV E P
Initial value10000000
Read/Write R R/W ——R/W R/W R/W R/W
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to
1, then settin g the PSU bit in FLMCR2, and f inally setting the P bit. Erase mode is enter ed by
setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is
initialized to H'80 by a reset, and in hardware standby m ode, software standby mode, subactive
mode, sub sleep mod e , and watch mod e . When on-chip flash memory is disabled , a r e ad will retu r n
H'00, and writes are in valid.
Writes to the EV and PV bits in FLMCR1 are enab led only when SWE=1; writes to the E bit only
when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1.
Bit 7—Flash Write Enable (FWE): Controls programming and erasing of the on-chip flash
memory. This bit cannot be modified and is always read as 1.
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE
should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be
cleared at the same time as these bits.
Bit 6
SWE Description
0 Writes disabled (Initial value)
1 Writes enabled
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 650 of 1130
REJ09B0327-0400
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3
EV Description
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode
[Setting condition]
When SWE = 1
Bit 2—Program-Verify (PV): Selects program-verify mode tran sition or clearing. Do not set the
SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2
PV Description
0 Program-verify mode cleared (Initial value)
1 Transition to program-verify mode
[Setting condition]
When SWE = 1
Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV,
PV, or P bit at the sam e time.
Bit 1
E Description
0 Erase mode cleared (Initial value)
1 Transition to erase mode
[Setting condition]
When SWE = 1, and ESU = 1
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 651 of 1130
REJ09B0327-0400
Bit 0—Program (P): Selects prog ram mode transition or clearing. Do not set the SWE, PSU,
ESU, EV, PV, or E bit at the same time.
Bit 0
P Description
0 Program mode cleared (Initial val ue)
1 Transition to program mode
[Setting condition]
When SWE = 1, and PSU = 1
22.5.2 Flash Memory Control Register 2 (FLMCR2)
Bit 76543210
FLER —————ESU PSU
Initial value00000000
Read/Write R —————R/W R/W
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memo ry program/erase
protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2
is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared
to 0 in software standby mode, subactive mode, subsleep mode, and watch mode.
When on- chip flash memory is disabled , a read will r eturn H'00, and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occu rred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 652 of 1130
REJ09B0327-0400
Bit 7
FLER Description
0 Flash memory is operating normally (Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing cond iti on]
Reset or hardware stan db y mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 22.8.3, Error Protection
Bits 6 to 2—Reserved: Always write 0 when wr iting to these bits.
Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 1
ESU Description
0 Erase setup cleared (Initial value)
1 Erase setup
[Setting condition]
When SWE = 1
Bit 0—Program Setup (PSU): Prepares for a tran sition to program mod e . Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same tim e.
Bit 0
PSU Description
0 Program setup cleared (Initial value)
1 Program setup
[Setting condition]
When SWE = 1
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 653 of 1130
REJ09B0327-0400
22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit 76543210
EBR1 ——————EB9/—*2EB8/—*2
Initial value00000000
Read/Write ——————R/W*1 *2R/W*1 *2
Bit 76543210
EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value00000000
Read/Write R/W*1R/W R/W R/W R/W R/W R/W R/W
Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.
2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they must not be set to 1.
EBR1 and EBR2 are registers that specify the flash memo ry erase area block by block; bits 1 and
2 in EBR1 (128 kB versions only) and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and
EBR2 are each initialized to H'00 by a reset, in hardware standby mode, software standby mode,
subactive mode, subsleep mode, and watch mode, and the SWE bit in FLMCR1 is not set. When a
bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are erase-
protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). When on-chip
flash memor y is disab led , a read will return H'00, and writes are inv a lid.
The flash memory block configuration is shown in table 22.5.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 654 of 1130
REJ09B0327-0400
Table 22.5 Flash Memory Erase Blocks
Block (Size)
128-kbyte Versions 64-kbyte Versions Address
EB0 (1 kbyte) EB0 (1 kbyte) H'(00)0000 to H'(00)03FF
EB1 (1 kbyte) EB1 (1 kbyte) H'(00)0400 to H'(00)07FF
EB2 (1 kbyte) EB2 (1 kbyte) H'(00)0800 to H'(00)0BFF
EB3 (1 kbyte) EB3 (1 kbytes) H'(00)0C00 to H'(00)0FFF
EB4 (28 kbytes) EB4 (28 kbytes) H'(00)1000 to H'(00)7FFF
EB5 (16 kbytes) EB5 (16 kbytes) H'(00)8000 to H'(00)BFFF
EB6 (8 kbytes) EB6 (8 kbytes) H'(00)C000 to H'(00)DFFF
EB7 (8 kbytes) EB7 (8 kbytes) H'00E000 to H'00FFFF
EB8 (32 kbytes) —H'010000 to H'017 FFF
EB9 (32 kbytes) —H'018000 to H'01F FFF
22.5.4 Serial/Timer Control Register (STCR)
Bit 76543210
IICS IICX1 IICX0 IICE FLSHE —ICKS1 ICKS0
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory control (in F-ZTAT
versions), and also selects the TCNT input clock. For details on functions not related to on-chip
flash memory, see section 3.2.4, Serial Timer Control Register (STCR), and descriptions of
individual modules. If a module controlled by STCR is not used, do not write 1 to the
correspondi ng bit .
STCR is initialized to H'00 by a reset and in hardware standby mod e .
Bits 7 to 4—I2C Control (IICS, IICX1, IICX0 , IICE): When the on-chip IIC option is included,
these bits contr ol the operation of the I2C bus in ter f ace. For details, see section 16, I2C Bus
Interface.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 655 of 1130
REJ09B0327-0400
Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables
read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE Description
0 Flash memory control registers deselected (Initial value)
1 Flash memory control registers selected
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer
operation. See section 12, 8-Bit Timers, for details.
22.6 On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on -board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
22.6. For a diagram of the transitions to the various flash memory modes, see figure 22.3.
Only advanced mode setting is possible for boot mode.
In the case of user program mode, established in advanced mode or normal mode, depending on
the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash
memory is possible.
Table 22.6 Setting On-Board Programming Modes
Mode
Mode Name CPU Operating Mode MD1 MD0 P92 P91 P90
Boot mode Advanced mode 0 0 1*1*1*
User program mode Advanced mode 1 0 ———
Normal mode 1 ———
Note: *Can be used as I/O ports after boot mode is initiated.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 656 of 1130
REJ09B0327-0400
22.6.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after this group MCU’s pins have been set to boot mode, the boot
progr am built into the MCU is started and the programming control p rogram prepared in the ho st
is serially transmitted to the MCU via the SCI . I n the MCU, the progr ammin g control program
received via the SCI is written into the p r ogramming control program area in on-chip RAM. After
the transfer is completed, control branches to the start address of the programming control
program area and the programming control program execution state is entered (flash memory
programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 22.7, and the boot program mode
execution procedure in figure 22.8.
RxD1
TxD1 SCI1
This group chip
Flash memory
Write data reception
Verify data transmission
Host
On-chip RAM
Figure 22.7 System Configuration in Boot Mode
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 657 of 1130
REJ09B0327-0400
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Start
Set pins to boot program mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
MCU measures low period
of H'00 data transmitted by host
MCU calculates bit rate and
sets value in bit rate register
After bit rate adjustment, transmits
one H'00 data byte to host to
indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
MCU transfers part of boot
program to RAM
Host transmits number
of user program bytes (N),
upper byte followed by lower byte
MCU transmits received
number of bytes to host as verify
data (echo-back)
n = 1
Host transmits user program
sequentially in byte units
MCU transmits received user
program to host as verify data
(echo-back)
Transfer received programming
control program to on-chip RAM
n = N? No
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
MCU transmits one H'AA data
byte to host
Transmit one H'AA data byte to host,
and execute programming control
program transferred to on-chip RAM
n + 1 → n
Figure 22.8 Boot Mode Execution Procedure
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 658 of 1130
REJ09B0327-0400
Automatic SCI Bit Rate Adjustment
Start
bit Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
Figure 22.9 RxD1 Input Signal when Using Automatic SCI Bit Rate Adjustment
When boot mode is initiated, this group MCU measures the low period of the asynchronous SCI
communication data (H'00) transmitted contin uously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no par ity. The MCU calcu lates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the MCU’s system clock frequency, there will
be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation,
the host’s transfer bit rate should be set to (2400, 4800, or 9600) bps.
Table 22.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 22.7 System Clock Frequencies for which Automatic Adjustment of This G r oup Bit
Rate Is Possible
Host Bit Rate System Clock Frequency for which Automatic Adjustment
of This Group Bit Rate Is Possible
9600 bps 8 MHz to 20 MHz
4800 bps 4 MHz to 20 MHz
2400 bps 2 MHz to 18 MHz
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 659 of 1130
REJ09B0327-0400
On-Chip RAM Area Divisions in Boot Mode
In boot mode, the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot
program, as shown in figure 22.10. The area to which the programming control program is
transferred is H'(FF)E080 to H'(FF)EFFF (3968 bytes) in the 128-kbyte versions, or H'(FF)E880 to
H'(FF)EFFF (1920 bytes) in the 64-kby te versions. The boot program area can be used when the
programming control program transferred into RAM enters the execution state. A stack area
should be set up as required.
H'(FF)E080
H'(FF)EFFF
Programming
control program
area
(3,968 bytes)
H'(FF)FF00
H'(FF)FF7F
Boot program
area*
(128 bytes)
(a) 128-kbyte versions
H'(FF)E880
H'(FF)EFFF
Programming
control program
area
(1,920 bytes)
H'(FF)FF00
H'(FF)FF7F
Boot program
area*
(128 bytes)
(b) 64-kbyte versions
Note: * The boot program area cannot be used until a transition is made to the execution state
for the programming control program transferred to RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
Figure 22.10 RAM Areas in Boot Mode
Notes on Use of User Mode
• When the chip comes o ut of reset in boot mode, it measu res the low period of the input at the
SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the RxD1 input.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 660 of 1130
REJ09B0327-0400
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'(FF)E080 (128-kbyte
versions) or H'(FF)E880 (64-kbyte versions)), the chip terminates transmit and receive
operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but
the adjusted bit rate value remain s set in BRR. The transmit d ata output pin, TxD1, goes to the
high-level output state (P84DDR = 1, P84DR = 1).
The contents of the CPU’s internal general registers ar e undefined at this time, so these
registers must be initialized immediately after branching to the prog r ammin g control program.
In particular, since th e stack pointer (SP) is used imp licitly in subroutin e calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip register s ar e not changed.
• Boot mode can be entered by making the pin settings shown in table 22.6 and executing a
reset-start.
When the chip detects the boot mode setting at reset release*1, P92, P91, and P90 can be used
as I/O ports.
Boot mod e can be cleared by driving the reset pin low, waitin g at least 20 states, then setting
the mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT
overflow reset.
The mode pin input levels must not be changed in boot mode.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of por ts with multiplexed address functions and bu s control output pins (AS, RD, WR)
will change according to the ch ange in the microcomputer’s operating mode*2.
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins d uring a reset, or to prevent collisio n with signals outside the micro com puter.
Notes: 1. Mode pin input must satisfy the mode programming setup time (tMDS = 4 states) with
respect to the reset release timing .
2. Ports with multiplexed address fu nctions will ou tput a low level as the addr ess signal if
mode pin setting is for mode 1 is entered du ring a reset. In other modes, the port pins
go to the high-imp edance state. The bus control output signals will output a high lev el
if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins
go to the high-impedan ce state.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 661 of 1130
REJ09B0327-0400
22.6.2 User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board supp ly of programming data, and storing a
program/erase control program in part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3).
In this mode, on-chip supporting modules other than flash memory operate as they normally
would in mode 2 and 3.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform progr amming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Figure 22.11 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Branch to flash memory application
program
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Transfer program/erase control
program to RAM
MD1, MD0 = 10, 11
Reset-start
Write the transfer program (and the program/
erase control program if necessary) beforehand
Note: The watchdog timer should be activated to prevent overprogramming or overerasing
due to program runaway, etc.
Figure 22.11 User Program Mode Execution Procedure
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 662 of 1130
REJ09B0327-0400
22.7 Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/r esetting of the SWE, EV, PV, E, and P bits in
FLMCR1, and the ESU and PSU bits in FLMCR2 , is executed by a program in flash
memory.
2. Perfo r m programming in the erased state. Do no t p erfo rm additional programming on
previously pro grammed address e s.
22.7.1 Program Mode
Follow the procedure shown in the prog ram/program-verify flowchart in figure 21.12 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrif icing program data reliability. Programming should be carried out 32 bytes at a
time.
For the wait times (x, y, z, α, β, γ, ε, η) after setting/clearing individual bits in flash memory
control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N), see
section 26.2.6, Flash Memory Characteristics.
Following the elapse of (x) µs or more after the SWE b it is set to 1 in flash m emor y control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the reprogram data area written consecutively to the write add r esses.
The lower 8 bits of th e first addr ess written to must be H'00, H'20, H'40, H'6 0, H'80 , H'A0, H'C0,
or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 32-byte data tran sfer must be performed even if
writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z + α + β) µs as the WDT overflow period. After this, preparation for
program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 663 of 1130
REJ09B0327-0400
FLMCR1. The time during which the P bit is set is the flash memory prog r ammin g time. Make a
program setting so that the time for one programming operation is within the range of (z) µs.
22.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the prog ramming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least (α) µs later). The watchd og
timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-
verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data
is read in 16-b it u nits), the data at the latched address is r ead. Wait at least (ε) µs after the dummy
write before perf ormin g this read operation. Next, the originally wr itten data is compared with the
verify data, and reprogram data is computed (see figure 22.12) and transferred to the reprogram
data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least (η)
µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again,
and repeat the program/program-verify sequence as befo re. However, ensure that the
program/program-verify sequen ce is not r epeated more than (N) tim es on th e same bits.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 664 of 1130
REJ09B0327-0400
Set SWE bit in FLMCR1
Wait (x) µs
n = 1
m = 0
Write 32-byte data in RAM reprogram data
area consecutively to flash memory
Enable WDT
Set PSU bit in FLMCR2
Wait (y) µs
Set P bit in FLMCR1
Wait (z) µs
Start of programming
Clear P bit in FLMCR1
Wait (α) µs
Wait (β) µs
NG
NG
NG NG
OK
OK
OK
Wait (γ) µs
Wait (ε) µs
*5
*3
*4
*2
*5
*5
*5
*5
*5
*5
*5
Store 32-byte program data in program
data area and reprogram data area *4
*1
*5
Wait (η) µs
Clear PSU bit in FLMCR2
Disable WDT
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Reprogram data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
End of programming
Program data =
verify data?
End of 32-byte
data verification?
m = 0?
Increment address
Programming failure
OK
Clear SWE bit in FLMCR1
n ≥ N?
n ← n + 1
Notes: 1. Data transfer is performed by byte transfer. The lower
8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer
must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. If a bit for which programming has been completed in the 32-byte
programming loop fails the following verify phase, additional
programming is performed for that bit.
4. An area for storing program data (32 bytes) and reprogram data
(32 bytes) must be provided in RAM. The contents of the latter
are rewritten as programming progresses.
5. See section 26.2.6, Flash Memory Characteristics, for the values
of x, y, z, α, β, γ, ε, η, and N.
Start
Program
Data Reprogram
Data Comments
Reprogramming is not
performed if program data
and verify data match
Programming incomplete;
reprogram
—
Still in erased state;
no action
RAM
Program data storage
area (32 bytes)
Reprogram data storage
area (32 bytes)
Transfer reprogram data to reprogram
data area
Verify
Data 1
0
1
1
0
1
0
1
0
0
1
1
End of programming
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Figure 22.12 Program/Program-Verify Flowchart
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 665 of 1130
REJ09B0327-0400
22.7.3 Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 22.13.
The wait times (x, y, z, α, β, γ, ε, η) after setting/clearing individual bits in flash memory control
registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erases (N), see section
26.2.6, Flash Memory Characteristics.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in
erase block register 1 or 2 (EBR1 or EBR2 ) at least (x) µs after setting the SWE bit to 1 in flash
memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in
the event of program runaway, etc. Set a value greater than (y + z + α + β) ms as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to
erase mode by settin g the E bit in FLMCR1. The time d uring which the E bit is set is the flash
memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With f lash memory er asing, preprogramming (setting all data in the memory to be erased
to 0) is not necessary before starting the erase procedure.
22.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit in FLMCR2 is cleared at least (α) µs later), the watchdog timer is cleared after the elapse
of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in
FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more.
When the flash m e m ory is read in this state (verify data is read in 16-bit units), th e data at the
latched add r ess is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data has no t been erased, set erase mode again, and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times. When verification is completed, exit erase-
verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks,
clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR1 or
EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the
same way.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 666 of 1130
REJ09B0327-0400
End of erasing
Start
Set SWE bit in FLMCR1
Set ESU bit in FLMCR2
Set E bit in FLMCR1
Wait (x) µs
Wait (y) µs
n = 1
Set EBR1, EBR2
Enable WDT
*5
*5
*3
Wait (z) ms *5
Wait (α) µs*5
Wait (β) µs*5
Wait (γ) µs
Set block start address to verify address
*5
Wait (ε) µs*5
*2
*5
Wait (η) µs
*5
*5
*4
Start of erase
Clear E bit in FLMCR1
Clear ESU bit in FLMCR2
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait (η) µs
Clear EV bit in FLMCR1
Clear SWE bit in FLMCR1
Disable WDT
Halt erase
*1
Verify data = all 1?
Last address of block?
End of
erasing of all erase
blocks?
Erase failure
Clear SWE bit in FLMCR1
n ≥ N?
NG
NG
NG NG
OK
OK
OK OK
n ← n + 1
Increment
address
Notes: 1. Preprogramming (setting erase block data to all 0) is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
5. See section 26.2.6, Flash Memory Characteristics, for the values of x, y, z, α, β, γ, ε, η, and N.
Figure 22.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 667 of 1130
REJ09B0327-0400
22.8 Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
22.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 22.8.)
Table 22.8 Hardware Protection
Functions
Item Description Program Erase
Reset/standby
protection • In a reset (including a WDT overflow re set),
software standby mode, subactive mode,
subsleep mode, and watch mode, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized,
and the program/erase-protected state is
entered.
• In a reset via the RES pin, the reset state is
not entered unless the RES pin is held low
until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the
RES pin low for the RES pulse width specified
in the AC Characteristics section.
Yes Yes
22.8.2 Software Protection
Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block
registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode. (See table 22.9.)
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 668 of 1130
REJ09B0327-0400
Table 22.9 Software Protection
Functions
Item Description Program Erase
SWE bit protection • Clearing the SWE bit to 0 in FLMCR1 sets the
program/erase-protected state for all bloc ks.
(Execute in on-chip RAM or external me mory.)
Yes Yes
Block specification
protection • Erase protection can be set for individual block s
by settings in erase block registers 1 and 2
(EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all blocks
in the erase-protected state.
—Yes
22.8.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malf unctions during flash memory progr amming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,
PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (transition to software standby, sleep, subactive, subsleep, or watch
mode) is executed during programming/erasing
• When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 22.14 shows the flash memory state transition diagram.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 669 of 1130
REJ09B0327-0400
RD VF PR ER FLER = 0
Error
occurrence*
1
RES = 0 or STBY = 0
RES = 0 or
STBY = 0
RD VF PR ER FLER = 0
Program mode
Erase mode Reset or hardware standby
(hardware protection)
RD VF*
4
PR ER FLER = 1 RD VF PR ER FLER = 1
Error protection mode Error protection
mode (software standby,
sleep, subsleep, and watch )
Software standby,
sleep, subsleep, and
watch mode
FLMCR1, FLMCR2 (except
FLER bit), EBR1, EBR2
initialization state*
3
FLMCR1,
FLMCR2,
EBR1, EBR2
initialization
state
Software standby,
sleep, subsleep, and
watch mode release
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Legend:
RES = 0 or
STBY = 0
Error occurrence*
2
Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is
executed for a transition to subactive mode
2. When an error occurs due to a SLEEP instruction (except subactive mode)
3. Except sleep mode
4. VF in subactive mode
Figure 22.14 Flash Memory State Transitions
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 670 of 1130
REJ09B0327-0400
22.9 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or erased
(when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1,
to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*2, possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be po ssible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests, including NMI input, must
therefore be disabled inside and outside the MCU when programming or erasing flash memory.
Interrupt is also disabled in the erro r -protection state while the P or E bit remains set in FLMCR1.
Notes: 1. Interr upt r e quests must b e disabled inside and outside the MCU until th e pro gra m ming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash m em ory is r ead while being programmed or erased (while the P or E bit is
set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt
exception h andling will not be executed correctly.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 671 of 1130
REJ09B0327-0400
22.10 Flash Memory Programmer Mode
22.10.1 Programmer Mode Setting
Programs an d data can be written and erased in programmer mode as well as in the on-b oard
programming modes. In programmer mode, the on-chip ROM can be freely programmed using a
PROM programmer that supports Renesas Technology microcomputer device types with 128-
kbyte*1 *3 or 64-kbyte*2 *3 on-chip flash memory. Flash memory read mode, auto-program mode,
auto-erase mode, and status read mode are supported with these device types. In auto-program
mode, auto-erase mode, and status read mode, a status polling proc edure is used, and in status read
mode, detailed internal signals are output after execution of an auto-program or auto-erase
operation.
Table 22.10 shows programmer mode pin settings.
Notes: 1. Applies to the H8S/2148 and H8S/2144.
2. Applies to the H8/2147N and H8S/2142.
3. Use products other than the A-mask version of the H8S/2148, H8S/2147N, H8/2144,
and H8S/2142 (in either 5-V or 3-V version) with the writing voltage for the PROM
programmer set to 5.0 V. Do not use the A-mask version with a 5.0-V PROM
programmer setting.
Table 22.10 Programmer Mode Pin Settings
Pin Names Setting/External Circuit Connection
Mode pins: MD1, MD0 Low-level input to MD1, MD0
STBY pin High-level input
(Hardware standby mode not set)
RES pin Power-on reset circuit
XTAL and EXTAL pins Oscillation circuit
Other setting pins: P97, P92, P91, P90, P67 Low-level input to P92, P67,
high-level input to P97, P91, P90
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 672 of 1130
REJ09B0327-0400
22.10.2 Socket Adapters and Memory Map
In programmer mode, a socket adapter is mounted on the writer programmer to match the package
concerned. Socket adapters are available for each writer manufacturer supporting Renesas
Technology microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory.
Figure 22.15 shows the memory map in programmer mode. For pin names in programmer mode,
see section 1.3.2, Pin Functions in Each Operating Mode.
H8S/2148
H8S/2144 H8S/2147N
H8S/2142
H'000000
MCU mode Programmer
mode
H'01FFFF
H'00000
H'1FFFF
On-chip
ROM area
H'000000
MCU mode Programmer
mode
H'00000
H'1FFFF
H'00FFFF H'0FFFF
On-chip
ROM area
Undefined value
output
Figure 22.15 Memory Map in Programmer mode
22.10.3 Programmer Mode Operation
Table 22.11 shows how the different operating modes are set when using programmer mode, and
table 22.12 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode
Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto-erasing.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the FO6 signal. In status read mode, error information is output if an
error occurs.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 673 of 1130
REJ09B0327-0400
Table 22.11 Settings for Each Operating Mode in Programmer Mode
Pin Names
Mode CE
CECE
CE OE
OEOE
OE WE
WEWE
WE FO0 to FO7 FA0 to FA17
Read L L H Data output Ain
Output disable L H H Hi-Z X
Command write L H L Data input Ain*2
Chip disable*1HXXHi-Z X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
Table 22.12 Programmer Mode Commands
1st Cycle 2nd Cycle
Command Name Number
of Cycles Mode Address Data Mode Address Data
Memory read mode 1 + n Write X H'00 Read RA Dout
Auto-program mode 129 Write X H'40 Write WA Din
Auto-erase mode 2 Write X H'20 W rite X H'20
Status read mode 2 Write X H'71 Write X H'71
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
22.10.4 Memory Read Mode
• After the end of an auto-program, auto-erase, or status read operation, the command wait state
is entered. To read memory contents, a transition must be made to memory read mode by
means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 674 of 1130
REJ09B0327-0400
Table 22.13 AC Characteristics in Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
FA17 to FA0
FO7 to FO0
OE
WE
Command write
t
wep
t
ceh
t
dh
t
ds
t
f
t
r
t
nxtc
Note: Data is latched on the rising edge of WE.
t
ces
Memory read mode
Address stable
Data
Data
Figure 22.16 Memory Read Mode Timing Waveforms after Command Write
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 675 of 1130
REJ09B0327-0400
Table 22.14 AC Characteristics when Entering Another Mode from Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
FA17 to FA0
FO7 to FO0 H'XX
OE
WE
Other mode command writeMemory read mode
t
wep
t
ceh
t
dh
t
ds
t
nxtc
t
ces
Address stable
Data
t
f
t
r
Note: Do not enable WE and OE at the same time.
Figure 22.17 Timing Waveforms when Entering Another Mode from Memory Read Mode
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 676 of 1130
REJ09B0327-0400
Table 22.15 AC Characteristics in Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Access tim e tacc —20 µs
CE output delay time tce —150 ns
OE output delay ti me toe —150 ns
Output disable delay time tdf —100 ns
Data output hold time toh 5 — ns
CE
FA17 to FA0
FO7 to FO0
VIL
VIL
VIH
OE
WE t
acc
t
acc
Address stable Address stable
Data
Data
t
oh
t
oh
Figure 22.18 Timing Waveforms for CE
CECE
CE/OE
OEOE
OE Enable State Read
CE
FA17 to FA0
FO7 to FO0
VIH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
Address stable Address stable
Data Data
t
df
Figure 22.19 Timing Waveforms for CE
CECE
CE/OE
OEOE
OE Clocked Read
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 677 of 1130
REJ09B0327-0400
22.10.5 Auto-Program Mode
AC Characteristics
Table 22.16 AC Characteristics in Auto-Program Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time twsts 1 — ms
Status polling access time tspa —150 ns
Address setup time tas 0 — ns
Address hold time tah 60 —ns
Memory write time twrite 1 3000 ms
WE rise time tr—30 ns
WE fall time tf—30 ns
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 678 of 1130
REJ09B0327-0400
Data
CE
FA17 to FA0
FO7 to FO0
FO6
FO7
OE
WE
tnxtc
twsts
tnxtc
tces
tdstdh
twep
tas tah
tceh
Address
stable
Programming wait
Data transfer
1 byte to 128 bytes
H'40 Data
FO0 to FO5 = 0
t
f
t
r
t
spa
t
write (1 to 3000 ms)
Programming normal
end identification signal
Programming operation
end identification signal
Figure 22.20 Auto-Program Mode Timing Waveforms
Notes on Use of Auto-Program Mode
• In auto-program mode, 128 bytes are programmed simultaneously. This shou ld be carried out
by executing 128 consecutive byte transfers.
• A 128-byte data transfer is necessary even when programming fewer than 128 by tes. In this
case, H'FF data must be wr itten to the extra addr esses.
• The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective
address is input, processing will switch to a memory write operation but a write error will be
flagged.
• Memory address transfer is performed in the second cycle (figure 22.20). Do not perform
transfer after the second cy cle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
• Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode
can also be used for this purpose (FO7 status polling uses the auto-program operation end
identification pin).
• The status polling FO6 and FO7 pin infor mation is retained until the n ext com mand write.
Until the next command write is perfor med, reading is possib le b y enabling CE and OE.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 679 of 1130
REJ09B0327-0400
22.10.6 Auto-Erase Mode
AC Characteristics
Table 22.17 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5 °C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time tests 1 — ms
Status polling access time tspa —150 ns
Memory erase time terase 100 40000 ms
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
FA17 to FA0
FO7 to FO0
FO6
FO7
OE
WE
t
ests
t
nxtc
t
nxtc
t
ces
t
ceh
t
dh
CL
in
DL
in
t
wep
FO0 to FO5 = 0
H'20 H'20
Erase normal end
confirmation signal
t
f
t
r
t
ds
t
spa
t
erase
(100 to 40000 ms)
Erase end identification
signal
Figure 22.21 Auto-Erase Mode Timing Waveforms
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 680 of 1130
REJ09B0327-0400
Notes on Use of Erase-Program Mode
• Auto-erase mode supports only entire memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also
be used for this purpose (FO7 status polling uses the auto-erase operation end identification
pin).
• The status polling FO6 and FO7 pin infor mation is retained until the n ext com mand write.
Until the next command write is perfor med, reading is possib le b y enabling CE and OE.
22.10.7 Status Read Mode
• Status read mode is used to identify what type of abnormal end has occurred. Use this mode
when an abnormal end occurs in auto-program mode or auto-erase mode.
• The return code is retained until a co m m a nd write f or o th er than status read mode is
performed.
Table 22.18 AC Characteristics in Status Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
OE output delay ti me toe —150 ns
Disable delay time tdf —100 ns
CE output delay time tce —150 ns
WE rise time tr—30 ns
WE fall time tf—30 ns
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 681 of 1130
REJ09B0327-0400
CE
FA17 to FA0
FO7 to FO0
OE
WE t
ces
t
nxtc
t
nxtc
t
df
Note: FO2 and FO3 are undefined.
t
ces
t
dh
t
wep
t
wep
Data
t
dh
t
oe
t
ce
t
nxtc
H'71
t
f
t
r
t
f
t
r
t
ceh
t
ds
t
ds
H'71
t
ceh
Figure 22.22 Status Read Mode Timing Waveforms
Table 22.19 Status Read Mode Return Commands
Pin Name FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0
Attribute Normal
end
identification
Command
error Program-
ming error Erase
error ——Program-
ming or
erase count
exceeded
Effective
address
error
Initial va lu e 0 0 0 0 0 0 0 0
Indications Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise: 0
Program-
ming
error: 1
Otherwise: 0
Erase
error: 1
Otherwise: 0
——Count
exceeded: 1
Otherwise: 0
Effective
address
error: 1
Otherwise: 0
Note: FO2 and FO3 are undefined.
22.10.8 Stat us Po lling
• The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode.
• The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase
mode.
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 682 of 1130
REJ09B0327-0400
Table 22. 20 Status Polling Out put Truth Table
Pin Names Internal Operation
in Progress Abnormal End — Normal End
FO7 0 1 0 1
FO6 0 0 1 1
FO0 to FO5 0 0 0 0
22.10.9 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 22.21 Command Wait State Transition Time Specifications
Item Symbol Min Max Unit
Standby release (oscillation stabilization time) tosc1 20 —ms
Programmer mode setup time tbmv 10 —ms
VCC hold time tdwn 0 — ms
VCC
RES Memory read
mode
Command wait
state
Command reception
Command
wait state
Normal/
abnormal end
identification
Auto-program mode
Auto-erase mode
tosc1 tbmv tdwn
Don't care
Figure 22.23 Oscilla t ion Stabilization Time, Pro grammer Mode Setup Time, and Power
Supply Fall Sequence
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 683 of 1130
REJ09B0327-0400
22.10.10 Notes on Memory Programming
• When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
• When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-pr ogramming.
Notes: 1. The flash me mory is initially in th e er ased state when the device is shipp ed by Renesas.
For other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
22.11 Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode and programmer mode are
summarized below.
Use the specified v oltages and timing for pro gramming and erasing.
Applied voltages in excess of the rating can permanently damage the device. For a PROM
programmer, use Renesas Technology microcomputer device types with 128-kbyte or 64-kbyte
on-chip flash memory that support a 5.0-V programming voltage.
Do not select the HN28F101 or use a programming voltage of 3.3 V for the PROM programmer,
and only use the sp ecif ied sock et adapter. Incorrect use will result in damaging the device.
Powering on and off
When applying or disconnecting VCC, fix the RES pin low and place the flash memory in the
hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or
E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program
runaway, etc.
Do not set or clear the SWE bit during program execution in flash memory.
Clear the SWE bit before executing a program or reading data in flash memory. When the SWE
bit is set, data in flash memory can be rewritten, but flash memory shou ld only be accessed fo r
verify operations (verification during programming/erasing).
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZT AT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 684 of 1130
REJ09B0327-0400
Do not use interrupt s while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled to give priority to program/erase
operations.
Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 32-byte programming
unit block. In programmer mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer socket,
socket adapter, and chip are not correctly aligned.
Do not to uch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
22.12 Note on Switching from F-ZTAT Version to Mask ROM Version
The mask ROM version does not have the internal registers for flash memory control that are
provided in the F-ZTAT version. Table 22.22 lists the registers that are present in the F-ZTAT
version but not in the mask ROM version. If a register listed in table 22.22 is read in the mask
ROM version, an undefined value will be return ed, Therefore, if application software develop ed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure
that the registers in table 22.22 have no effect.
Table 22.22 Registers Present in F-ZTAT Version but Absent in Mask ROM Ver sion
Register Abbreviation Address
Flash memory control register 1 FLMCR1 H'FF80
Flash memory control register 2 FLMCR2 H'FF81
Erase block register 1 EBR1 H'FF82
Erase block register 2 EBR2 H'FF83
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 685 of 1130
REJ09B0327-0400
Section 23 ROM
(H8 S/2148 F-ZTA T A-Mask Version,
H8S/2147 F-ZTAT A-Mask Version,
H8S/2144 F-ZTAT A-Mask Version)
23.1 Overview
H8S/2148 F-ZTAT A-mask version and H8S/2144 F-ZTAT A-mask version have 128 kbytes, and
H8S/2147 F-ZTAT A-mask version has 64 kbytes of on-chip flash memory. The flash memory is
connected to the bus master by a 16-bit data bus. The bus master accesses both byte and word data
in one state, enabling faster instruction fetches and higher processing speed.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM.
The flash memory versions of this group can be erased and programmed on-board as well as with
a general-purpose PROM programmer.
23.1.1 Block Diagram
Figure 23.1 shows a block diagram of the ROM.
H'000000
H'000002
H'01FFFE
H'000001
H'000003
H'01FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 23.1 ROM Block Diagram
(A-mask versions of the H8S/2148 F-ZTAT and H8S/2144 F-ZTAT)
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 686 of 1130
REJ09B0327-0400
23.1.2 Register Configuration
This group on-chip ROM is controlled by the operating mode and register MDCR. The register
configuration is shown in table 23.1.
Table 23.1 ROM Register
Register Name Abbreviation R/W Initial Value Address*
Mode control register MDCR R/W Undefined
Depends on the operating mode H'FFC5
Note: *Lower 16 bits of the address.
23.2 Register Descriptions
23.2.1 Mode Control Register (MDCR)
Bit
Initial value
Read/Write
7
EXPE
—*
R/W*
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
—
0
—
1
MDS1
—*
R
Note: * Determined by the MD1 and MD0 pins.
MDCR is an 8-bit read-only register used to set this group operating mode and monitor the current
operating mode.
The EXPE bit is initialized in accordance with the mode pin states by a reset and in hard ware
standby mode.
Bit 7—Expanded Mo de Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1
and cannot be modified. In mod es 2 and 3, EXPE ha s an initial valu e of 0 and can be read or
written.
Bit 7
EXPE Description
0 Single-chip mode selected
1 Expanded mode selected
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 687 of 1130
REJ09B0327-0400
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the
input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0
correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
When MDCR is read, the input levels of mode pins MD1 and MD0 are latched in these bits.
23.3 Operation
The on-chip flash memory is connected to the CPU by a 16-bit data bus, and both byte and word
data is accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses
to the lower 8 bits. Wo r d data must start at an even address.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM, as shown in table 23.2.
In normal mode, the maximum amount of ROM that can be used is 56 kbytes.
Table 23.2 Opera ting Modes and ROM
Operating Mode
Mode Pins MDCR
MCU
Operating
Mode
CPU
Operating
Mode Description MD1 MD0 EXPE On-Chip ROM
Mode 1 Normal Expanded mode with
on-chip ROM disabled 01 1Disabled
Mode 2 Advanced Single-chip mode 1 0 0 Enabled*
Advanced Expanded mode with
on-chip ROM enabled 1
Mode 3 Normal Single-chip mode 1 0
Normal Expanded mode with
on-chip ROM enabled 1Enabled
(56 kbytes)
Note: *H8S/2148 F-ZTAT A-mask version and H8S/2144 F-ZTAT A-mask version have
128 kbytes, and H8S/2147 F-ZTAT A-mask version has 64 kbytes of on-chip ROM.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 688 of 1130
REJ09B0327-0400
23.4 Overview of Flash Memory
23.4.1 Features
The features of the flash memory are summarized below.
• Four flash memo ry operating modes
Program mode
Erase mode
Program-verif y mode
Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in
single-bloc k units). When erasin g multiple blocks, the individual blocks must be erased
sequentially. Block erasing can be performed as required on 1-kbyte, 28-kbyte, 16-kbyte, 8-
kbyte, and 32-kbyte blocks.
• Programm ing/er a se times
The flash memory programming time is 10 ms (typ.) fo r simultaneous 128-byte programming,
equivalent to approximately 80 µs (typ.) per by te, and the erase time is 100 ms (typ.) per block.
• Reprogram ming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
Boot mode
User program mode
• Automatic bit r a te ad justment
With data transfer in boot mode, the bit rate of the chip can be autom a tically adjusted to match
the transfer bit rate of the host.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 689 of 1130
REJ09B0327-0400
23.4.2 Block Diagram
Module bus
Bus interface/controller
Flash memory
(128 kbytes/64 kbytes)
Operating
mode
FLMCR2
Internal address bus
Internal data bus (16 bits)
Mode pins
EBR1
EBR2
FLMCR1 *
*
*
*
Legend:
FLMCR1: Flash memory control register 1
FLMCR2: Flash memory control register 2
EBR1: Erase block register 1
EBR2: Erase block register 2
Note: * These registers are used only in the flash memory version. In the mask ROM version,
a read at any of these addresses will return an undefined value, and writes are invalid.
Figure 23.2 Block Diagram of Flash Memory
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 690 of 1130
REJ09B0327-0400
23.4.3 Flash Memory Operating Modes
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of
the operating modes shown in figure 23.3. In user mode, flash memory can be read but not
programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
Boot mode
On-board programming mode
User
program mode
User mode with
on-chip ROM
enabled
Reset state
Programmer
mode
RES = 0
SWE = 1 SWE = 0 *1
*
2
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. MD0 = MD1 = 0, P92 = P91 = P90 = 1
2. MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1
RES = 0
RES = 0
RES = 0
MD1 = 1
Figure 23.3 Flash Memory Mode Transitions
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 691 of 1130
REJ09B0327-0400
On-Board Programming Modes
• Boot mode
Flash memory
The chip
RAM
Host
Programming control
program
SCI
Application program
(old version)
Programming control
program
New application
program
New application
program
Flash memory
The chip
RAM
Host
SCI
Application program
(old version)
Boot program area
Programming control
program
New application
program
Flash memory
The chip
RAM
Host
SCI
Flash memory
erase
Boot program
Flash memory
The chip
Program execution state
RAM
Host
SCI
New application
program
Boot program
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data
is being rewritten. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the chip (originally incorporated in the chip) is
started, an SCI communication check is carried
out, and the boot program required for flash
memory erasing is automatically transferred to
the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM by SCI communication is
executed, and the new application program in the
host is written into the flash memory.
Boot programBoot program
Boot program area
Programming control
program
Boot program
area
Programming
control program
Figure 23.4 Boot Mode
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 692 of 1130
REJ09B0327-0400
• User program mode
Flash memory
The chip
RAM
Host
Programming/
erase control program
SCI
Boot program
New application
program
Flash memory
The chip
RAM
Host
SCI
New application
program
Flash memory
The chip
RAM
Host
SCI
Flash memory
erase
Boot program
New application
program
Flash memory
The chip
Program execution state
RAM
Host
SCI
Boot program
Boot program
Application program
(old version)
New application
program
1. Initial state
(1) the program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand. (2) The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
The transfer program in the flash memory is
executed, and the programming/erase control
program is transferred to RAM.
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Programming/
erase control program
Programming/
erase control program
Programming/
erase control program
Transfer program
Application program
(old version)
Transfer program
Transfer program
Transfer program
Figure 23.5 User Program Mode (Example)
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 693 of 1130
REJ09B0327-0400
Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode
Entire memory erase Yes Yes
Block erase No Yes
Programming contr ol program *Program/program-verify Program/program-verify
Erase/erase-verify
Notes *To be provided by the user, in accordance with the recommended algorithm.
Block Configuration
The flash memory is divided into two 32-kbyte blocks (128-kbyte version only), two 8-kbyte
blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Address H'00000
Address H'1FFFF
1 kbyte
1 kbyte
1 kbyte
1 kbyte
8 kbytes
8 kbytes
16 kbytes
32 kbytes
28 kbytes
128 kbytes
32 kbytes
(a) 128-kbyte version
(b) 64-kbyte version
Address H'00000
Address H'0FFFF
1 kbyte
1 kbyte
1 kbyte
1 kbyte
8 kbytes
8 kbytes
16 kbytes
28 kbytes
64 kbytes
Figure 23.6 Flash Memory Block Configuration
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 694 of 1130
REJ09B0327-0400
23.4.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 23.3.
Table 23.3 Flash Memory Pins
Pin Name Abbreviation I/O Function
Reset RES Input Reset
Mode 1 MD1 Input Sets MCU operating mode
Mode 0 MD0 Input Sets MCU operating mode
Port 92 P92 Input Sets MCU operating mode when MD1 = MD0 = 0
Port 91 P91 Input Sets MCU operating mode when MD1 = MD0 = 0
Port 90 P90 Input Sets MCU operating mode when MD1 = MD0 = 0
Transmit data TxD1 Output Serial transm it data outpu t
Receive data RxD1 Input Serial receive data input
23.4.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 23.4.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 23.4 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address*1
Flash memory control register 1 FLMCR1*5R/W*3H'80 H'FF80*2
Flash memory control register 2 FLMCR2*5R/W*3H'00*4H'FF81*2
Erase block regi ster 1 EBR1*5R/W*3H'00*4H'FF82*2
Erase block regi ster 2 EBR2*5R/W*3H'00*4H'FF83*2
Serial/timer control register STCR R/W H'00 H'FFC3
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
performed by the FLSHE bit in the serial/timer control register (STCR).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invali d.
4. When the SWE bit in FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 695 of 1130
REJ09B0327-0400
23.5 Register Descriptions
23.5.1 Flash Memory Control Register 1 (FLMCR1)
Bit 76543210
FWE SWE ——EV PV E P
Initial value10000000
Read/Write R R/W ——R/W R/W R/W R/W
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to
1, then settin g the PSU bit in FLMCR2, and f inally setting the P bit. Erase mode is enter ed by
setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is
initialized to H'80 by a reset, and in hardware standby m ode, software standby mode, subactive
mode, sub sleep mod e , and watch mod e . When on-chip flash memory is disabled , a r e ad will retu r n
H'00, and writes are in valid.
Writes to the EV and PV bits in FLMCR1 are enab led only when SWE=1; writes to the E bit only
when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1.
Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing. This bit cannot be modified and is always read as 1.
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE
should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be
cleared at the same time as these bits.
Bit 6
SWE Description
0 Writes disabled (Initial value)
1 Writes enabled
Bit 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 696 of 1130
REJ09B0327-0400
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3
EV Description
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode
[Setting condition]
When SWE = 1
Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the
SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2
PV Description
0 Program-verify mode cleared (Initial value)
1 Transition to program-verify mode
[Setting condition]
When SWE = 1
Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV,
PV, or P bit at the sam e time.
Bit 1
E Description
0 Erase mode cleared (Initial value)
1 Transition to erase mode
[Setting condition]
When SWE = 1, and ESU = 1
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 697 of 1130
REJ09B0327-0400
Bit 0—Program (P): Selects prog ram mode transition or clearing. Do not set the SWE, PSU,
ESU, EV, PV, or E bit at the same time.
Bit 0
P Description
0 Program mode cleared (Initial val ue)
1 Transition to program mode
[Setting condition]
When SWE = 1, and PSU = 1
23.5.2 Flash Memory Control Register 2 (FLMCR2)
Bit 76543210
FLER —————ESU PSU
Initial value00000000
Read/Write R —————R/W R/W
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memo ry program/erase
protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2
is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared
to 0 in software standby mode, subactive mode, subsleep mode, and watch mode.
When on- chip flash memory is disabled , a read will r eturn H'00 and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occu rred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 698 of 1130
REJ09B0327-0400
Bit 7
FLER Description
0 Flash memory is operating normally (Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing cond iti on]
Reset or hardware stan db y mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 23.8.3, Error Protection
Bits 6 to 2—Reserved: Always write 0 when wr iting to these bits.
Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 1
ESU Description
0 Erase setup cleared (Initial val ue)
1 Erase setup
[Setting condition]
When SWE = 1
Bit 0—Program Setup (PSU): Prepares for a tran sition to program mod e . Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same tim e.
Bit 0
PSU Description
0 Program setup cleared (Initial value)
1 Program setup
[Setting condition]
When SWE = 1
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 699 of 1130
REJ09B0327-0400
23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit 76543210
EBR1 ——————EB9/—*2EB8/—*2
Initial value00000000
Read/Write ——————R/W*1 *2R/W*1 *2
Bit 76543210
EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value00000000
Read/Write R/W*1R/W R/W R/W R/W R/W R/W R/W
Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.
2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they must not be set to 1.
EBR1 and EBR2 are registers that specify the flash memo ry erase area block by block; bits 1 and
0 in EBR1 and bits 7 to 0 in EBR2 are readable/writable b its. EBR1 and EBR2 are each in itialized
to H'00 by a reset, in hardware standby mode, software standby mode, subactive mode, subsleep
mode, and watch mode, and when the SWE bit in FLMCR1 is not set. When a bit in EBR1 and
EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one
bit in EBR1 and EBR2 (more than one bit cannot be set). When on-chip flash memory is disabled,
a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 23.5.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 700 of 1130
REJ09B0327-0400
Table 23.5 Flash Memory Erase Blocks
Block (Size)
128-kbyte Version 64-kbyte Version Address
EB0 (1 kbyte) EB0 (1 kbyte) H'(00)0000 to H'(00)03FF
EB1 (1 kbyte) EB1 (1 kbyte) H'(00)0400 to H'(00)07FF
EB2 (1 kbyte) EB2 (1 kbyte) H'(00)0800 to H'(00)0BFF
EB3 (1 kbytes) EB3 (1 kbytes) H'(00)0C00 to H'(00)0FFF
EB4 (28 kbytes) EB4 (28 kbytes) H'(00)1000 to H'(00)7FFF
EB5 (16 kbytes) EB5 (16 kbytes) H'(00)8000 to H'(00)BFFF
EB6 (8 kbytes) EB6 (8 kbytes) H'(00)C000 to H'(00)DFFF
EB7 (8 kbytes) EB7 (8 kbytes) H'00E000 to H'00FFFF
EB8 (32 kbytes) —H'010000 to H'017FFF
EB9 (32 kbytes) —H'018000 to H'01F FFF
23.5.4 Serial/Timer Control Register (STCR)
Bit 76543210
IICS IICX1 IICX0 IICE FLSHE —ICKS1 ICKS0
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT
input clock. For details on functions not related to on-chip flash memory, see section 3.2.4,
Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module
controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mod e .
Bits 7 to 4—I2C Control (IICS, IICX1, IICX0 , IICE): These bits con trol the operation of the I2C
bus interface for the I2C on-chip op tion. For details, see section 16, I2C Bus Interface.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 701 of 1130
REJ09B0327-0400
Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables
read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE Description
0 Flash memory control registers deselected (Initial value)
1 Flash memory control registers selected
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer
operation. See section 12, 8-Bit Timers, for details.
23.6 On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
23.6. For a diagram of the transitions to the various flash memory modes, see figure 23.3.
Only advanced mode setting is possible for boot mode.
In the case of user program mode, established in advanced mode or normal mode, depending on
the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash
memory is possible.
Table 23.6 Setting On-Board Programming Modes
Mode
Mode Name CPU Operating Mode MD1 MD0 P92 P91 P90
Boot mode Advanced mode 0 0 1 *1*1*
User program mode Advanced mode 1 0 ———
Normal mode 1 ———
Note: *Can be used as I/O ports after boot mode is initiated.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 702 of 1130
REJ09B0327-0400
23.6.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after the chip pins have been set to boot mode, the boot program
built into the chip is started and the progr a m ming control program prepared in th e host is serially
transmitted to the chip via the SCI. In the chip, the programming control program received via the
SCI is written into the programmin g control program area in on-chip RAM. After the transfer is
completed, control branches to the start address of the programming control program area and th e
programming control program execution state is entered (flash memory programming is
performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 23.7, and the boot program mode
execution procedure in figure 23.8.
RxD1
TxD1 SCI1
The chip
Flash memory
Write data reception
Verify data transmission
Host
On-chip RAM
Figure 23.7 System Configuration in Boot Mode
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 703 of 1130
REJ09B0327-0400
n = N?
Yes
No
Yes
No
Set pins to boot mode and execute reset-start
n = 1
n + 1 → n
Host transfers data (H'00) continuously at prescribed
bit rate
The chip measures low period of H'00 data transmitted
by host
After bit rate adjustment, transmits one H'00 data byte
to host to indicate end of adjustment
Host confirms normal reception of bit rate adjustment
end indication (H'00), and transmits one H'55 data byte
After receiving H'55, trransmit one H'AA data byte
to host
Host transmits number of user program bytes (N),
upper byte followed by lower byte
The chip transmits received number of bytes to host as
verify data (echo-back)
Host transmits programming control program
sequentially in byte units
The chip transmits received programming control
program to host as verify data (echo-back)
Transfer received programming control program
to on-chip RAM
End of transmission
Check flash memory data, and if data has already
been written, erase all blocks
Check that all flash memory data has been erased
Check the starting ID code of the area to which the
programming control program is to be transferred
Execute programming control program transffered
to on-chip RAM
The chip transmits one H'AA data byte to the host
Start
The chip calculates bit rate and sets value in bit rate
register
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and
the erase operation and subsequent operations are halted.
ID code match?
The chip transmits one H'FF
data byte as an ID code error
and stops the subsequent
operations
Figure 23.8 Boot Mode Execution Procedure
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 704 of 1130
REJ09B0327-0400
Automatic SCI Bit Rate Adjustment
Start
bit Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
Figure 23.9 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the ch ip measures the low period of the asynchronous SCI
communication data (H'00) transmitted contin uously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no par ity. The chip calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Dependin g on the host’s transmission bit rate and th e chips system clock fr e quency, there will be a
discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the
host’s transfer bit rate should be set to (4800, 9600, or 19200) bps.
Table 23.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the chips bit rate is possible. The boot program should be executed within this
system clock range.
Table 23.7 System Clock Frequencies for Which Automatic Adjustment of t he Chips Bit
Rate Is Possible
Host Bit Rate System Clock Frequency for Which Automatic Adjustment
of Bit Rate Is Possible
19200 bps 8 MHz to 20 MHz
9600 bps 4 MHz to 20 MHz
4800 bps 2 MHz to 18 MHz
On-Chip RAM Area Divisions in Boot Mode
In boot mode, th e 1920- byte area from H'(FF)E880 to H'(FF) EFFF and the 128-byte area from
H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot program, as shown in figure 23.10. The
area to which the programming control program is transferred is H'(FF)E080 to H'(FF)E87F (2048
bytes). In the 64-kbyte version, this is a reserved area that is used only during the boot mode.
However, the 8-byte area from H'(FF)E080 to H'(FF)E087 is reserved for ID codes as shown in
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 705 of 1130
REJ09B0327-0400
Figure 23.10. The boot program area can be used when the programming control program
transferred into the RAM enters the execution state. A stack area should be set up as required.
H'(FF)E080
H'(FF)E088
H'(FF)EFFF
H'(FF)E880
Programming
control program
area*
1
(2040 bytes)
ID code area*
1
H'(FF)FF00
H'(FF)FF7F
Boot program
area*
2
(128 bytes)
Boot program
area*
2
(1920 bytes)
Notes: 1. In the 64-kbyte version, this is a reserved area that is used only during the boot mode.
Do not use this area for other purposes.
2. The boot program area cannot be used until a transition is made to the execution state
for the programming control program transferred to the RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
Figure 23.10 RAM Areas in Boot Mode
In the boot mode of this chip, the content in the 8-byte ID code area shown below is confirmed so
that whether or not there is a programming control program that corresponds to the chip can be
checked.
H'(FF)E080 40 FE 64 66 32 31 34 39
↑ (product identification ID)
H'(FF)E088 and above Instruction code for write control program
When a new programming control program for use in boot mode is created, add the 8-byte ID
code described above to the head of the program.
Notes on Use of Boot Mode
• When the chip comes o ut of reset in boot mode, it measu res the low period of the input at the
SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the RxD1 input.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 706 of 1130
REJ09B0327-0400
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'(FF)E088), the chip
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE
and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data
output pin, TxD1, goes to the high-level output state (P84DDR = 1, P84DR = 1).
The contents of the CPU’s internal general registers ar e undefined at this time, so these
registers must be initialized immediately after branching to the prog r ammin g control program.
In particular, since th e stack pointer (SP) is used imp licitly in subroutin e calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip register s ar e not changed.
• Boot mode can be entered by making the pin settings shown in table 23.6 and executing a
reset-start.
When the chip detects the boot mode setting at reset release*1, P92, P91, and P90 can be used
as I/O ports.
Boot mod e can be cleared by driving the reset pin low, waitin g at least 20 states, then setting
the mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT
overflow reset. The mode pin input levels must not be changed in boot mode.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of por ts with multiplexed address functions and bu s control output pins (AS, RD, HWR)
will change according to the ch ange in the microcomputer’s operating mode*2.
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins d uring a reset, or to prevent collisio n with signals outside the micro com puter.
Notes: 1. Mode pins input must satisfy the mode programming setup time (tMDS = 4 states) with
respect to the reset release timing .
2. Ports with multiplexed address fu nctions will ou tput a low level as the addr ess signal if
mode pin setting is for mode 1 is entered du ring a reset. In other modes, the port pins
go to the high-imp edance state. The bus control output signals will output a high lev el
if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins
go to the high-impedan ce state.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 707 of 1130
REJ09B0327-0400
23.6.2 User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing an on-board means of supplying programming data, and
storing a program/erase control program in part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3).
In this mode, on-chip supporting modules other than flash memory operate as they normally
would in mode 2 and 3.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform progr amming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Figure 23.11 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Branch to flash memory application
program
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Transfer program/erase control
program to RAM
MD1, MD0 = 10, 11
Reset-start
Write the transfer program
(and the program/erase control program
if necessary) beforehand
Note: The watchdog timer should be activated to prevent overprogramming or overerasing
due to program runaway, etc.
Figure 23.11 User Program Mode Execution Procedure
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 708 of 1130
REJ09B0327-0400
23.7 Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/r esetting of the SWE, EV, PV, E, and P bits in
FLMCR1, and the ESU and PSU bits in FLMCR2 , is executed by a program in flash
memory.
2. Perfo r m programming in the erased state. Do no t p erfo rm additional programming on
previously pro grammed address e s.
23.7.1 Program Mode
Follow the procedure shown in the prog ram/program-verify flowchart in figure 23.12 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
The wait times (x, y, z1, z2, z3, α, ß, γ, ε, η, θ) after setting/clearing individual bits in flash
memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N),
see section 26.2.6, Flash Memory Characteristics.
Following the elapse of (x) µs or more after the SWE b it is set to 1 in flash m emor y control
register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram
data area, and the 128-byte data in the repro gram data area written consecutively to the write
addresses. The lo wer 8 bits of the first address written to must be H'00 or H'80 . 128 consecutive
byte data transfers are performed. The program address and program data are latched in the flash
memory . A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this
case, H'FF data must be wr itten to the extra addr esses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z2 + α + β) µs as the WDT ov erflow period. After th is, prep aration
for program mode (program setup) is carried out by setting the PSU bit in FLMCR2 , and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory prog r ammin g time. Make a
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 709 of 1130
REJ09B0327-0400
program setting so that the time for one programming operation is within the range of (z1), (z2) or
(z3) µs.
23.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the prog ramming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least (α) µs later). The watchd og
timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-
verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data
is read in 16-b it u nits), the data at the latched address is r ead. Wait at least (ε) µs after the dummy
write before perf ormin g this read operation. Next, the originally wr itten data is compared with the
verify data, and reprogram data is computed (see figure 23.12) and transferred to the reprogram
data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least
(η) µs. If the programming count is less than 6, the 128-byte data in the additional program data
area should be written consecutively to the write addresses, and additional programming
performed. Next clear the SWE bit in FLMCR1, and wait at least (θ) µs. If reprogramming is
necessary, set program mode again, and repeat the prog ram/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times on
the same bits.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 710 of 1130
REJ09B0327-0400
Start
End of programming
End sub
Set SWE bit in FLMCR1
Wait (x) µs
n = 1
m = 0
Sub-routine-call See Note 7 for pulse width
Note 7: Write Pulse Width
Start of programming
Sub-routine write pulse
Set PSU bit in FLMCR1
Enable WDT
Set P bit in FLMCR1
Wait (y) µs
Clear P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Clear PSU bit in FLMCR2
Wait (α) µs
Disable WDT
Wait (β) µs
Write pulse application subroutine
NG
NG
NG NG
OK
OK
Wait (γ) µs
Wait (ε) µs
*2
*4
*6
*6
*6
*6
*6
*6
*6*6
*5
*6
*6
*6
*1
Wait (η) µs
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Program data =
verify data?
Transfer additional program data
to additional program data area
Additional program data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
End of 128-byte
data verification?
m = 0?
Increment address
Programming failure
OK
Original Data (D)
0
1
Verify Data (V)
0
1
0
1
Comments
Write 128-byte data in RAM reprogram data
area consecutively to flash memory
Write pulse
(z1) µs or (z2) µs
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
.
998
999
1000
Write Time (z*6) µsec
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
.
.
.
z2
z2
z2
Reprogram data computation
Transfer reprogram data to reprogram data area
*4
*3
6 ≥ n? NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
Additional write pulse (z3) µs
Wait (θ) µs
*1
Note: Use a (z3) µs write pulse for additional
programming.
Program Data Computation Chart
Additional program data
storage area (128 kbytes)
OK
OK NG
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*4
n ← n + 1
n ≥ 1000?
Clear SWE bit in FLMCR1
Wait (θ) µs
6 ≥ n?
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even
if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent
verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in
RAM. The reprogram and additional program data contents are modified as programming proceeds.
5. The write pulse of (z1) µs or (z2) µs is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional
program data is executed, a (z3) µs write pulse should be applied. Reprogram data X means reprogram data when the write pulse is applied.
6. See section 26.2.6, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N.
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Reprogram Data (X')
0
1
Verify Data (V)
0
1
0
1
Additional Program Data (Y)
0
1
1
1
Comments
Additional Program Data Computation Chart
Additional programming executed
Additional programming not executed
Additional programming not executed
Reprogram Data (X)
1
0
1
1
Figure 23.12 Program/Program-Verify Flowchart
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 711 of 1130
REJ09B0327-0400
23.7.3 Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 23.13.
The wait times (x, y, z, α, β, γ, ε, η, θ) after setting/clearing individual bits in flash memory
control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erase (N), see section
26.2.6, Flash Memory Characteristics.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in
erase block register 1 or 2 (EBR1 or EBR2 ) at least (x) µs after setting the SWE bit to 1 in flash
memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in
the event of program runaway, etc. Set a value greater than (y + z + α + β) ms as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to
erase mode by settin g the E bit in FLMCR1. The time d uring which the E bit is set is the flash
memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With f lash memory er asing, preprogramming (setting all data in the memory to be erased
to 0) is not necessary before starting the erase procedure.
23.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit in FLMCR2 is cleared at least (α) µs later), the watchdog timer is cleared after the elapse
of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in
FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more.
When the flash m e m ory is read in this state (verify data is read in 16-bit units), th e data at the
latched add r ess is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data has no t been erased, set erase mode again, and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times. When verification is completed, exit erase-
verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks,
clear the SWE bit in FLMCR1 , and wait (θ) µs. If there are any unerased blocks, make a 1 bit
setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify
sequence in the same way.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 712 of 1130
REJ09B0327-0400
End of erasing
Start
Set SWE bit in FLMCR1
Set ESU bit in FLMCR2
Set E bit in FLMCR1
Wait (x) µs
Wait (y) µs
n = 1
Set EBR1, EBR2
Enable WDT
*
5
*
5
*
3
Wait (z) ms *
5
Wait (α) µs*
5
Wait (β) µs*
5
Wait (γ) µs
Set block start address to verify address
*
5
Wait (ε) µs*
5
*
2
*
5
Wait (η) µs
*
5
*
5
*
4
Start of erase
Clear E bit in FLMCR1
Clear ESU bit in FLMCR2
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait (η) µs
Clear EV bit in FLMCR1
Clear SWE bit in FLMCR1
Disable WDT
Halt erase
*
1
Verify data = all 1?
Last address of block?
End of
erasing of all erase
blocks?
Erase failure
Clear SWE bit in FLMCR1
n ≥ N?
NG
NG
NG NG
OK
OK
OK OK
n ← n + 1
Increment
address
Wait (θ)
µs Wait (θ) µs
Notes: 1. Preprogramming (setting erase block data to all 0) is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
5. See
section 26.2.6, Flash Memory Characteristics, for the values of x, y, z, α, β, γ, ε, η,
θ
,
and N.
Figure 23.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 713 of 1130
REJ09B0327-0400
23.8 Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
23.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 23.8.)
Table 23.8 Hardware Protection
Functions
Item Description Program Erase
Reset/standby
protection • In a reset (including a WDT overflow re set)
and in hardware standby mode, software
standby mode, subactive mode, subs leep
mode, and watch mode, FLMCR1, FLMCR2,
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered.
• In a reset via the RES pin, the reset state is
not entered unless the RES pin is held low
until oscillation stabilizes after powering on.
In the case of a reset during operation, hold
the RES pin low for the RES pulse width
specified in the AC Characteristics section.
Yes Yes
23.8.2 Software Protection
Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block
registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode. (See table 23.9.)
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 714 of 1130
REJ09B0327-0400
Table 23.9 Software Protection
Functions
Item Description Program Erase
SWE bit protection • Clearing the SWE bit to 0 in FLMCR1 sets the
program/erase-protected state for all bloc ks.
(Execute in on-chip RAM or external me mory.)
Yes Yes
Block specification
protection • Erase protection can be set for individual block s
by settings in erase block registers 1 and 2
(EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-prot ect ed state.
—Yes
23.8.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malf unctions during flash memory progr amming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,
PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby, sleep, subactive, subsleep and watch
mode) is executed during programming/erasing
• When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 23.14 shows the flash memory state transition diagram.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 715 of 1130
REJ09B0327-0400
RD VF PR ER FLER = 0
Error
occurrence*
1
RES = 0 or STBY = 0
RES = 0 or
STBY = 0
RD VF PR ER FLER = 0
Normal operation mode
Program mode
Erase mode
Reset or hardware standby
(hardware protection)
RD VF*
4
PR ER FLER = 1 RD VF PR ER FLER = 1
Error protection mode Error protection
mode (software standby,
sleep, subsleep, and watch )
Software standby,
sleep, subsleep, and
watch mode
FLMCR1, FLMCR2 (except
FLER bit), EBR1, EBR2
initialization state*
3
FLMCR1,
FLMCR2,
EBR1, EBR2
initialization
state
Software standby,
sleep, subsleep, and
watch mode release
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Legend:
RES = 0 or
STBY = 0Error occurrence*
2
Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is
executed for a transition to subactive mode
2. When an error occurs due to a SLEEP instruction (except subactive mode)
3. Except sleep mode
4. VF in subactive mode
Figure 23.14 Flash Memory State Transitions
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 716 of 1130
REJ09B0327-0400
23.9 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or erased
(when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1,
to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*2, possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be po ssible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests, including NMI input, must
therefore be disabled inside and outside the MCU when programming or erasing flash memory.
Interrupt is also disabled in the erro r -protection state while the P or E bit remains set in FLMCR1.
Notes: 1. Interr upt r e quests must b e disabled inside and outside the MCU until th e pro gra m ming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash m em ory is r ead while being programmed or erased (while the P or E bit is
set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt
exception h andling will not be executed correctly.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 717 of 1130
REJ09B0327-0400
23.10 Flash Memory Programmer Mode
23.10.1 Programmer Mode Setting
Programs an d data can be written and erased in programmer mode as well as in the on-b oard
programming modes. In programmer mode, the on-chip ROM can be freely programmed using a
PROM programmer that supports Renesas Technology microcomputer device types with 128-
kbyte or 64-kbyte on-chip flash memory*. See section 23.10.10, Notes on Memory Programming
and section 23.11, Flash Memory Programming and Erasing Precautions, for notes on programmer
mode. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are
supported with these device types. In auto-program mode, auto-erase mode, and status read mode,
a status polling procedure is used, and in status read mode, detailed internal signals are output after
execution of an auto-program or auto-erase operation.
Table 23.10 shows programmer mode pin settings.
Note: * Use products of the H8S/2148 A-mask version, H8S/2147 A-mask version, and
H8S/2144 A-mask version (in either 5-V or 3-V version) with the writing voltage for
PROM programmer set to 3.3 V. Do not use products other than the A-mask version
with 3.3V PROM programmer setting.
Table 23.10 Programmer Mode Pin Settings
Pin Names Setting/External Circuit Connection
Mode pins: MD1, MD0 Low-level input to MD1, MD0
STBY pin High-level input (Hardware standby mode not set)
RES pin Power-on reset circuit
XTAL and EXTAL pins Oscillation circuit
Other setting pins: P97, P92, P91,
P90, P67 Low-level input to p92, p67, high-level input to P97,
P91, P90
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 718 of 1130
REJ09B0327-0400
23.10.2 Socket Adapters and Memory Map
In programmer mode, a socket adapter is mounted on the writer programmer to match the package
concerned. Socket adapters are available for each writer manufacturer supporting Renesas
Technology microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory
(VPP = 3.3 V).
Figure 23.15 shows the memory map in programmer mode. For pin names in programmer mode,
see section 1.3.2, Pin Functions in Each Operating Mode.
H'000000
MCU mode Programmer mode
H'00000
H'1FFFF
H'0FFFF
H'00FFFF
On-chip
ROM area
Undefined
value output
H8S/2147 A-mask version
H'000000
MCU mode Programmer mode
H'00000
H'1FFFF
H'01FFFF
On-chip
ROM area
H8S/2148 A-mask version
H8S/2144 A-mask version
Figure 23.15 Memory Map in Programmer Mode
23.10.3 Programmer Mode Operation
Table 23.11 shows how the different operating modes are set when using programmer mode, and
table 23.12 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode
Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto-erasing.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the FO6 signal. In status read mode, error information is output if an
error occurs.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 719 of 1130
REJ09B0327-0400
Table 23.11 Settings for Each Operating Mode in Programmer Mode
Pin Names
Mode CE
CECE
CE OE
OEOE
OE WE
WEWE
WE FO0 to FO7 FA0 to FA17
Read L L H Data output Ain
Output disable L H H Hi-Z X
Command write L H L Data input Ain*2
Chip disable*1HXXHi-Z X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
Table 23.12 Programmer Mode Commands
1st Cycle 2nd Cycle
Command Name Number
of Cycles Mode Address Data Mode Address Data
Memory read mode 1 + n Write X H'00 Read RA Dout
Auto-program mode 129 Write X H'40 Write WA Din
Auto-erase mode 2 Write X H'20 W rite X H'20
Status read mode 2 Write X H'71 Write X H'71
Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
23.10.4 Memory Read Mode
• After the end of an auto-program, auto-erase, or status read operation, the command wait state
is entered. To read memory contents, a transition must be made to memory read mode by
means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 720 of 1130
REJ09B0327-0400
Table 23.13 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
FA17 to FA0
FO7 to FO0 Data
OE
WE
Command write
t
wep
t
ceh
t
dh
t
ds
t
f
t
r
t
nxtc
Note: Data is latched on the rising edge of WE.
t
ces
Memory read mode
Address stable
Data
Figure 23.16 Memory Read Mode Timing Waveforms after Command Write
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 721 of 1130
REJ09B0327-0400
Table 23.14 AC Characteristics when Entering Another Mode from Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
FA17 to FA0
FO7 to FO0 H'XX
OE
WE
Other mode command writeMemory read mode
twep tceh
tdh
tds
tnxtc tces
Address stable
Data
tftr
Note: Do not enable WE and OE at the same time.
Figure 23.17 Timing Waveforms when Entering Another Mode from Memory Read Mode
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 722 of 1130
REJ09B0327-0400
Table 23.15 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Access tim e tacc —20 µs
CE output delay time tce —150 ns
OE output delay ti me toe —150 ns
Output disable delay time tdf —100 ns
Data output hold time toh 5 — ns
CE
FA17 to FA0
FO7 to FO0
VIL
VIL
VIH
OE
WE t
acc
t
acc
Address stable Address stable
Data
Data
t
oh
t
oh
Figure 23.18 Timing Waveforms for CE
CECE
CE/OE
OEOE
OE Enable State Read
CE
FA17 to FA0
FO7 to FO0
VIH
OE
WE
t
ce
tacc
toe
toh toh
tdf
tce
tacc
toe
Address stable Address stable
Data Data
tdf
Figure 23.19 Timing Waveforms for CE
CECE
CE/OE
OEOE
OE Clocked Read
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 723 of 1130
REJ09B0327-0400
23.10.5 Auto-Program Mode
AC Characteristics
Table 23.16 AC Characteristics in Auto-Program Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time twsts 1 — ms
Status polling access time tspa —150 ns
Address setup time tas 0 — ns
Address hold time tah 60 —ns
Memory write time twrite 1 3000 ms
WE rise time tr—30 ns
WE fall time tf—30 ns
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 724 of 1130
REJ09B0327-0400
Data
CE
FA17 to FA0
FO7 to FO0
FO6
FO7
OE
WE
tnxtc
twsts
tnxtc
tces
tdstdh
twep
tas tah
tceh
Address
stable
Programming wait
Data transfer
1 byte to 128 bytes
H'40 Data
FO0 to FO5 = 0
t
f
t
r
t
spa
t
write (1 to 3000 ms)
Programming normal
end identification signal
Programming operation
end identification signal
Figure 23.20 Auto-Program Mode Timing Waveforms
Notes on Use of Auto-Program Mode
• In auto-program mode, 128 bytes are programmed simultaneously. This shou ld be carried out
by executing 128 consecutive byte transfers.
• A 128-byte data transfer is necessary even when programming fewer than 128 by tes. In this
case, H'FF data must be wr itten to the extra addr esses.
• The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective
address is input, processing will switch to a memory write operation but a write error will be
flagged.
• Memory address transfer is performed in the second cycle (figure 23.20). Do not perform
transfer after the second cy cle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
• Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode
can also be used for this purpose (FO7 status polling uses the auto-program operation end
identification pin).
• The status polling FO6 and FO7 pin infor mation is retained until the n ext com mand write.
Until the next command write is perfor med, reading is possib le b y enabling CE and OE.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 725 of 1130
REJ09B0327-0400
23.10.6 Auto-Erase Mode
AC Characteristics
Table 23.17 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time tests 1 — ms
Status polling access time tspa —150 ns
Memory erase time terase 100 40000 ms
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
FA17 to FA0
FO7 to FO0
FO6
FO7
OE
WE
t
ests
t
nxtc
t
nxtc
t
ces
t
ceh
t
dh
CL
in
DL
in
t
wep
FO0 to FO5 = 0
H'20 H'20
Erase normal end
confirmation signal
t
f
t
r
t
ds
t
spa
t
erase
(100 to 40000 ms)
Erase end identification
signal
Figure 23.21 Auto-Erase Mode Timing Waveforms
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 726 of 1130
REJ09B0327-0400
Notes on Use of Auto-Erase-Program Mode
• Auto-erase mode supports only entire memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also
be used for this purpose (FO7 status polling uses the auto-erase operation end identification
pin).
• The status polling FO6 and FO7 pin infor mation is retained until the n ext com mand write.
Until the next command write is perfor med, reading is possib le b y enabling CE and OE.
23.10.7 Status Read Mode
• Status read mode is used to identify what type of abnormal end has occurred. Use this mode
when an abnormal end occurs in auto-program mode or auto-erase mode.
• The return code is retained until a co m m a nd write f or o th er than status read mode is
performed.
Table 23.18 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
OE output delay ti me toe —150 ns
Disable delay time tdf —100 ns
CE output delay time tce —150 ns
WE rise time tr—30 ns
WE fall time tf—30 ns
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 727 of 1130
REJ09B0327-0400
CE
FA17 to FA0
FO7 to FO0
OE
WE t
ces
t
nxtc
t
nxtc
t
df
Note: FO2 and FO3 are undefined.
t
ces
t
dh
t
wep
t
wep
Data
t
dh
t
oe
t
ce
t
nxtc
H'71
t
f
t
r
t
f
t
r
t
ceh
t
ds
t
ds
H'71
t
ceh
Figure 23.22 Status Read Mode Timing Waveforms
Table 23.19 Status Read Mode Return Commands
Pin Name FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0
Attribute Normal
end
identification
Command
error Program-
ming error Erase
error ——Program-
ming or
erase count
exceeded
Effective
address
error
Initial va lu e 0 0 0 0 0 0 0 0
Indications Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise: 0
Program-
ming
error: 1
Otherwise: 0
Erase
error: 1
Otherwise: 0
——Count
exceeded: 1
Otherwise: 0
Effective
address
error: 1
Otherwise: 0
Note: FO2 and FO3 are undefined.
23.10.8 Stat us Po lling
• The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode.
• The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase
mode.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 728 of 1130
REJ09B0327-0400
Table 23. 20 Status Polling Out put Truth Table
Pin Names Internal Operation
in Progress Abnormal End — Normal End
FO7 0 1 0 1
FO6 0 0 1 1
FO0 to FO5 0 0 0 0
23.10.9 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 23.21 Command Wait State Transition Time Specifications
Item Symbol Min Max Unit
Standby release (oscillation
stabilization time) tosc1 20 —ms
Programmer mode setup time tbmv 10 —ms
VCC hold time tdwn 0 — ms
VCC
RES Memory read
mode
Command wait
state
Command
wait state
Normal/
abnormal end
identification
Auto-program mode
Auto-erase mode
tosc1 tbmv tdwn
Don't care
Command acceptance
Figure 23.23 Oscilla t ion Stabilization Time, Pro grammer Mode Setup Time, and Power
Supply Fall Sequence
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 729 of 1130
REJ09B0327-0400
23.10.10 Notes on Memory Programming
• When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
• When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-pr ogramming.
Notes: 1. The flash me mory is initially in th e er ased state when the device is shipp ed by Renesas.
For other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
23.11 Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode and programmer mode are
summarized below.
Use the specified v oltages and timing for pro gramming and erasing.
Applied voltages in excess of the rating can permanently damage the device. For a PROM
programmer, use Renesas Technology microcomputer device types with 128-kbyte or 64-kbyte
on-chip flash memory that support a 3.3-V programming voltage.
Do not select the HN28F101, or use a programming voltage of 5.0 V for the PROM programmer,
and only use the sp ecif ied sock et adapter. Incorrect use will result in damaging the device.
Powering on and off
When applying or disconnecting VCC, fix the RES pin low and place the flash memory in the
hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress o r sacrificing p rog ram data reliability. When setting the P or
E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program
runaway, etc.
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 730 of 1130
REJ09B0327-0400
Do not set or clear the SWE bit during program execution in flash memory.
Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in
flash memor y. When the SWE bit is set, data in flash m e m ory can be r e wr itten, but when SWE =
1 the flash memory can only be read in program-verify or erase-verify mode. Flash memory
should only be accessed for verify operations (verification during programming/erasing). Do not
clear the SWE bit during a program, erase, or verify operation.
Do not use interrupt s while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled when programming and erasing flash
memory to give priority to program /erase operations.
Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 128-byte programming
unit block. In programmer mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer socket,
socket adapter, and chip are not correctly aligned.
Do not to uch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
23.12 Note on Switching from F-ZTAT Version to Mask ROM Version
The mask ROM version does not have the internal registers for flash memory control that are
provided in the F-ZTAT version. Table 23.22 lists the registers that are present in the F-ZTAT
version but not in the mask ROM version. If a register listed in table 23.22 is read in the mask
ROM version, an undefined value will be return ed. Therefore, if application software develop ed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure
that the registers in table 23.22 have no effect
Table 23.22 Registers Present in F-ZTAT Version but Absent in Mask ROM Version
Register Abbreviation Address
Flash memory control register 1 FLMCR1 H'FF80
Flash memory control register 2 FLMCR2 H'FF81
Erase block register 1 EBR1 H'FF82
Erase block register 2 EBR2 H'FF83
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 731 of 1130
REJ09B0327-0400
Section 24 Clock Pulse Generator
24.1 Overview
This LSI have a built- in clock pulse gen erator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse gen er a tor consists of an oscillator circuit, a duty adju stment circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input
circuit, and waveform shaping circuit.
24.1.1 Block Diagram
Figure 24.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator Duty
adjustment
circuit
EXCL Subclock
input circuit
Waveform
shaping
circuit
Medium-speed
clock divider
System clock
To φ pin
WDT1 count clock
Internal clock
To supporting
modules
Bus master cloc
k
To CPU, DTC
φ/2 to φ/32
φ
SUB
φ
Bus master
clock
selection
circuit
Clock
selection
circuit
Figure 24.1 Block Diagram of Clock Pulse Generator
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 732 of 1130
REJ09B0327-0400
24.1.2 Register Configuration
The clock pulse generator is controlled by the standby control register (SBYCR) and low-power
control register (LPWRCR). Table 24.1 shows the register configuration.
Table 24.1 CPG Registers
Name Abbreviation R/W Initial Value Address*
Standby contro l register SBYCR R/W H'00 H'FF84
Low-power control r egi ster LPWRCR R/W H'00 H'FF85
Note: *Lower 16 bits of the address.
24.2 Register Descriptions
24.2.1 Standby Control Register (SBYCR)
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
Read/Write
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 to 2 are described here. For a description of the other bits, see section 25.2.1, Standby
Control Regi ste r (SBYCR).
SBYCR is in itialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock
for high-speed mode and medium-speed mode.
When ope r a tin g the device after a transition to su bactive mode or watch mode bits SCK2 to SCK0
should all be cleared to 0.
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 733 of 1130
REJ09B0327-0400
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master is in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-spe ed clo ck is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-spe ed clo ck is φ/16
1 Medium-speed clock is φ/32
1——
24.2.2 Low-Po wer Co ntrol Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
EXCLE
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
Only bit 4 is described here. For a description of the other bits, see section 25.2.2, Low-Power
Control Register (LPWRCR).
LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin.
Bit 4
EXCLE Description
0 Subclock input from EXCL pin is disabled (Initial value)
1 Subclock input from EXCL pin is enabled
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 734 of 1130
REJ09B0327-0400
24.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
24.3.1 Connecting a Crystal Resonator
Circuit Configura tion
A crystal resonator can be connected as shown in the example in figure 24.2. Select the damping
resistance Rd according to table 24.2. An AT-cut parallel-resonance crystal should be used.
EXTAL
XTAL R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22 pF
Figure 24.2 Connection of Crystal Resonator (Example)
Table 24.2 Damping Resistance Value
Frequency (MHz) 2 4 8 10 12 16 20
Rd (Ω
ΩΩ
Ω)1k 500 200 0 0 0 0
Crystal resonator
Figure 24.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has
the characteristics shown in table 24.3 and the same frequency as the system clock (φ).
XTAL
C
L
AT-cut parallel-resonance type
EXTAL
C
0
LR
s
Figure 24.3 Crystal Resonator Equivalent Circuit
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 735 of 1130
REJ09B0327-0400
Table 24.3 Crystal Resonator Parameters
Frequency (MHz) 2 4 8 10 12 16 20
RS max (Ω
ΩΩ
Ω)500 120 80 70 60 50 40
C0 max (pF) 7777777
Note on Board Design
When a crystal resonator is conn ected, the following points should be noted.
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 24. 4.
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the XTAL and EXTAL pins.
C
L2
Signal A Signal B
C
L1
This LSI
XTAL
EXTAL
Avoid
Figure 24.4 Example of Incorrect Board Design
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 736 of 1130
REJ09B0327-0400
24.3.2 External Clock Input
Circuit Configura tion
An external clock signal can be input as shown in the examples in figure 24.5. If the XTAL pin is
left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode, subactive mode,
subsleep mode, and watch mode.
EXTAL
XTAL
External clock input
Open
(a) XTAL pin left open
EXTAL
XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 24.5 External Clock Input (Ex amples)
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 737 of 1130
REJ09B0327-0400
External Clock
The external clock signal should have the same frequency as the system clock (φ).
Table 24.4 and figure 24.6 show the input conditions for the external clock.
Table 24.4 External Clock Input Conditions
VCC = 2.7 to 5.5 V VCC = 5.0 V ±10%
Item Symbol Min Max Min Max Unit Test Conditions
External clock
input low pulse
width
tEXL 40 —20 —ns Figure 24.6
External clock
input high pulse
width
tEXH 40 —20 —ns
External clock
rise time tEXr —10 —5ns
External clock
fall time tEXf —10 —5ns
tCL 0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz Figure 26.5Cloc k low
pulse width 80 —80 —ns φ < 5 MHz
tCH 0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHzClock high
pulse width 80 —80 —ns φ < 5 MHz
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 24. 6 External Clock Input Timing
Table 24.5 shows the external clock output settling delay time, and figure 24.7 shows the external
clock ou tput settlin g delay timing. Th e oscillator and duty adjustment cir c uit have a function for
adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock
signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 738 of 1130
REJ09B0327-0400
external clock output settling delay tim e (tDEXT). As the clock signal output is not fixed during the
tDEXT period, the reset signal should be driven low to maintain the reset state.
Table 24.5 External Clock Output Settling Delay Time
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V
Item Symbol Min Max Unit Notes
External clock
output settling
delay time
tDEXT*500 —µs Figure 24.7
Note: *tDEXT includes RES pulse width (tRESW).
t
DEXT
*
RES
(internal or external)
EXTAL
STBY
V
CC
2.7V
V
IH
φ
Note: * t
DEXT
includes RES pulse width (t
RESW
).
Figure 24.7 Ex ternal Clock Output Settling Delay Timing
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 739 of 1130
REJ09B0327-0400
24.4 Duty Adjustment Circuit
When the oscillato r f requency is 5 MHz or higher , the duty adjustment circuit adjusts the duty
cycle of the clock sig nal from the oscillator to g enera te th e system clock (φ).
24.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32
clocks.
24.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of
bits SCK2 to SC K0 in SBYCR.
24.7 Subclock Input Circuit
The subclock input circuit controls the subclock input from the EXCL pin.
Inputting the Subclock
When a subclock is used, a 32.768 kHz external clock sh ould be input from the EXCL pin. In this
case, clear bit P96DDR to 0 in P9DDR and set b it EXCLE to 1 in LPWRCR.
The subclock input conditions are shown in table 24.6 and figure 24.8.
Table 24.6 Subclock Input Condit ions
VCC = 2.7 to 5.5 V
Item Symbol Min Typ Max Unit Test Conditions
Subclock input low pulse
width tEXCLL —15.26 —µs Figure 24.8
Subclock input high pulse
width tEXCLH —15.26 —µs
Subclock input rise time tEXCLr —— 10 ns
Subclock input fall time tEXCLf —— 10 ns
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 740 of 1130
REJ09B0327-0400
t
EXCLH
t
EXCLL
t
EXCLr
t
EXCLf
V
CC
× 0.5
EXCL
Figure 24.8 Subclock Input Timing
When Subclock Is Not Needed
Do not enable subclock input when the subclock is not needed
Note on Subclock Usa ge
In transiting to power-down mode, if at least two cycles of the 32-kHz clock are not input after the
32-kHz clock input is enabled (EXCLE = 1) until the SLEEP instruction is executed (power-down
mode tran sition), the subclock input cir cuit is not initialized and an erro r may occur in the
microcomputer.
Before power-down mode is entered with using the subclock, at least two cycle of the 32-kHz
clock should be input after the 32-kHz clock input is enabled (EXCLE = 1).
As described in the hardware manual (clock pulse generator/subclock input circuit), when the
subclock is not used, the subclock inpu t should not be enabled (EXCLE = 0).
24.8 Subclock Waveform Shaping Circuit
To eliminate noise in the subclock input from the EXCL pin, this circuit samples the clock using a
clock obtained by dividing the φ clock. The sampling frequency is set with the NESEL bit in
LPWRCR. For details, see sections 24.2.2 and 25.2.2, Low-Power Control Register (LPWRCR).
The clock is not sampled in subactive mode, subsleep mode, or watch mode.
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 741 of 1130
REJ09B0327-0400
24.9 Clock Selection Circuit
This circuit selects the system clock used in the MCU.
The clock signal generated in the EXTAL/XTAL pin oscillator is selected as the system clock
when MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, or
standby mode.
In sub-active mode, sub-sleep mode, and watch mode, the sub-clock signal input from EXCL pin
is selected as the system clock. In these modes, modules such as CPU, TMR0, TMR1, WDT0,
WDT1, and I/O ports operate on the φ SUB clock. The count clock for each timer is a clock
obtained by driving the φ SUB clock.
Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 742 of 1130
REJ09B0327-0400
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 743 of 1130
REJ09B0327-0400
Section 25 Power-Down State
25.1 Overview
In addition to the normal program execution state, this LSI have a power-down state in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-po w er
operation can be achieved by individually controlling the CPU, on-chip supporting modules, and
so on.
This LSI has the following operating modes:
1. High-speed mode
2. Medium-speed mode
3. Subactive mode
4. Sleep mode
5. Subsleep mode
6. Watch mode
7. Module stop mode
8. Software standby mode
9. Hardware standby mode
Of these, 2 to 9 are power-down modes. Sleep mode and subsleep mode are CPU modes, medium-
speed mode is a CPU and bus master mode, subactive mode is a CPU, bus master, and on-chip
supporting module mode, and module stop mode is an on-chip supporting module mode
(including bus masters other than the CPU). Certain combinations of these modes can be set.
After a reset, the MCU is in high-speed mode and module stop mode (excluding th e DTC).
Table 25.1 shows the internal chip states in each mode, and table 25.2 shows the conditions for
transition to the various modes. Figure 25.1 shows a mode transition diagram.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 744 of 1130
REJ09B0327-0400
Table 25.1 Internal States in Each Mode
Function High-
Speed Medium-
Speed Sleep Module
Stop Watch Subactive Subsleep Software
Standby Hardware
Standby
System clock
oscillator Function-
ing Function-
ing Function-
ing Function-
ing Halted Halted Halted Halted Halted
Subclock input Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Halted Halted
Instruc-
tions Function-
ing Medium-
speed Halted Function-
ing Halted Subclock
operation Halted Halted HaltedCPU
operation
Registers Function-
ing Medium-
speed Retained Function-
ing Retained Subclock
operation Retained Retained Undefined
NMI
IRQ0
IRQ1
External
interrupts
IRQ2
Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Halted
DTC Function-
ing Medium-
speed Function-
ing Function-
ing/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained) Halted
(reset)
WDT1 Function-
ing Function-
ing Function-
ing Function-
ing Subclock
operation Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
WDT0 Function-
ing Function-
ing Function-
ing Function-
ing Halted
(retained) Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
TMR0, 1 Functi o n-
ing Function-
ing Function-
ing Function-
ing/halted
(retained)
Halted
(retained) Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
FRT
TMRX, Y
Timer
connec-
tion
IIC0
IIC1
Function-
ing Function-
ing Function-
ing Function-
ing/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained) Halted
(reset)
SCI0
SCI1
SCI2
PWM
PWMX
HIF, PS2
D/A
A/D
Function-
ing Function-
ing Function-
ing Function-
ing/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
RAM Function-
ing Function-
ing Function-
ing (DTC) Function-
ing Retained Function-
ing Retained Retained Retained
On-chip
supporting
module
operation
I/O Function-
ing Function-
ing Function-
ing Function-
ing Retained Function-
ing Retained Retained High
impedance
Notes: “Halted (retained)” means that internal register values are retained. The internal state is “operation suspended.”
“Halted (reset)” means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 745 of 1130
REJ09B0327-0400
Hardware
standby mode
STBY pin = low
Notes: When a transition is made between modes by means of an interrupt, transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
When a transition is made to watch mode or subactive mode, high-speed mode must be set.
Sleep mode
(main clock)
SSBY = 0, LSON = 0
Software
standby mode
SSBY = 1
PSS = 0, LSON = 0
Watch mode
(subclock)
SSBY = 1
PSS = 1, DTON = 0
Subsleep mode
(subclock)
SSBY = 0
PSS = 1, LSON = 1
Medium-speed
mode
(main clock)
Subactive mode
(subclock)
High-speed
mode
(main clock)
Reset state STBY pin = high
RES pin = low
RES pin = high
Program execution state
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
Clock switching
exception handling
after oscillation
setting time
(STS2 to STS0)
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception handling
SCK2 to
SCK0 ≠ 0
SCK2 to
SCK0 = 0
Program-halted state
SLEEP
instruction
Any interrupt*
3
SLEEP
instruction
External
interrupt*
4
SLEEP
instruction
Interrupt*
1
,
LSON bit = 0
SLEEP
instruction
Interrupt*
1
,
LSON bit = 1
Interrupt*
2
SLEEP instruction
: Transition after exception handling : Power-down mode
1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts
2. NMI, IRQ0 to IRQ7, and WDT0 interrupts, WDT1 interrupt, TMR0 interrupt, TMR1 interrupt
3. All interrupts
4. NMI, IRQ0 to IRQ2, IRQ6, IRQ7
Figure 25.1 Mo de Transitions
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 746 of 1130
REJ09B0327-0400
Table 25.2 Power-Down Mode Transition Conditions
Control Bit States
at Time of Transition
State before
Transition SSBY PSS LSON DTON State after Transition
by SLEEP Instruction State after Return
by Interrupt
High-speed/
medium-speed 0*0*Sleep High-speed/
medium-speed
0*1*——
100*Software standby High-spee d/
medium-speed
101*——
1 1 0 0 Watch High-speed
1 1 1 0 Watch Subactive
1101——
1 1 1 1 Subactive —
Subactive 0 0 **——
010*——
011*Subsleep Subactive
10**——
1 1 0 0 Watch High-speed
1 1 1 0 Watch Subactive
1 1 0 1 High-speed —
1111——
Legend:
*:Don’t care
—: Do not set.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 747 of 1130
REJ09B0327-0400
25.1.1 Register Configuration
The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR
registers. Table 25.3 summarizes these registers.
Table 25.3 Power-Down State Registers
Name Abbreviation R/W Initial Value Address*1
Standby contro l register SBYCR R/W H'00 H'FF84*2
Low-power control r egi ster LPWRCR R/W H'00 H'FF85*2
Timer control/status register
(WDT1) TCSR R/W H'00 H'FFEA
Module stop control register MSTPCRH R/W H'3F H'FF86*2
MSTPCRL R/W H'FF H'FF87*2
Notes: 1. Lower 16 bits of the address.
2. Some power down state registers are assigned to the same address as other registers.
In this case, register selection is performed by the FLSHE bit in the serial timer control
register (STCR).
25.2 Register Descriptions
25.2.1 Standby Control Register (SBYCR)
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
Read/Write
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is in itialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 748 of 1130
REJ09B0327-0400
Bit 7—Software Standby (SSBY): Determines the operatin g mode, in combination with other
control bits, when a power-down mode transition is made by executing a SLEEP instruction. The
SSBY setting is not changed by a mode transition due to an interrupt, etc.
Bit 7
SSBY Description
0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or
medium-speed mode (Initial value)
Transition to subsleep mode after execution of SLEEP instruction in subactive mode
1 Transition to software standby mode, subactive mode, or watch mode after execution
of SLEEP instruction in high-speed mode or medium-speed mode
Transition to watch mode or high-speed mode after execution of SLEEP instruction in
subactive mode
Bits 6 to 4— St andby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU
waits for the clock to stabilize when software standby mode, watch mode, or subactive mode is
cleared and a transition is made to high-speed mode or medium-speed mode by means of a
specific interrupt or instruction. With cr ystal oscillation, refer to table 25.4 and make a selection
according to the operating frequency so th at the standby time is at least 8 ms (the o scillatio n
settling time). With an external clock, any selection can be made.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Standby time = 8192 states (Initial value
)
1 Standby time = 16384 states
1 0 Standby time = 32768 states
1 Standby time = 65536 states
1 0 0 Standby time = 131072 states
1 Standby time = 262144 states
10Reserved
1 Standby time = 16 states*
Note: *This setting must not be us ed in the flash memory version.
Bit 3—Reserved: This bit cannot be modified and is always read as 0.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 749 of 1130
REJ09B0327-0400
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus
master in high-speed mode and medium-speed mod e. When operating the device after a tran sition
to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master is in high-speed mode (Initial value
)
1 Medium-spe ed clock is φ/2
1 0 Medium-speed clock is φ/4
1 Medium-spe ed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-spe ed clock is φ/32
1——
25.2.2 Low-Po wer Co ntrol Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
EXCLE
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between
high-speed mode, medium-speed mode, and subactive mode when making a power-down
transition by executing a SLEEP instruction. The operating mode to which the transition is made
after SLEEP instruction execution is determined by a combination of other control bits.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 750 of 1130
REJ09B0327-0400
Bit 7
DTON Description
0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode (Initial value)
1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or software standby mode
When a SLEEP instruction is executed in subactive mode, a transition is made directly
to high-speed mode, or a transition is made to subs leep mode
Note: *When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
Bit 6—Low-Speed On Flag (LSON): Determines the operating mode in combination with oth er
control bits when making a power-down transition by executing a SLEEP instruction. Also
controls whether a transition is made to high-speed mode or to subactive mode when watch mode
is cleared.
Bit 6
LSON Description
0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode, or directly to high-speed mode
After watch mode is cleared, a transition is made to high-speed mode (Initial value)
1 When a SLEEP instruction is executed in high-speed mode a transition is made to
watch mode or subactive mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watc h mode
After watch mode is cleared, a transition is made to subactive mode
Note: *When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
Bit 5—Noise Elimination Sampling Frequency Select (NESEL): Select s the frequency at which
the subclock (φSUB) input from th e EXCL pin is sampled with the clock (φ) generated by the
system clock oscillator. When φ = 5 MHz or higher, clear this bit to 0.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 751 of 1130
REJ09B0327-0400
Bit 5
NESEL Description
0 Sampling at φ divided by 32 (Initial value)
1 Sampling at φ divided by 4
Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin.
Bit 4
EXCLE Description
0 Subclock input from EXCL pin is disabled (Initial value)
1 Subclock input from EXCL pin is enabled
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 0.
25.2.3 Timer Control/Status Register (TCSR)
TCSR1
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Note: * Only 0 can be written in bit 7, to clear the flag.
TCSR1 is an 8-bit readable/writable register that performs selection of the WDT1 TCNT input
clock, mode, etc.
Only bit 4 is described here. For details of the other bits, see section 14.2.2, Timer Control/Status
Register (TCSR).
TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 4—Prescaler Select (PSS): Selects the WDT1 TCNT input clock.
This bit also con tr ols the operation in a power-down m ode tr ansition. The operating mode to
which a transition is made after execution of a SLEEP instruction is determined in combination
with other control bits.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 752 of 1130
REJ09B0327-0400
For details, see the description of Clo c k Select 2 to 0 in section 14.2.2, Timer Control/Status
Register (TCSR).
Bit 4
PSS Description
0 TCNT counts φ-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode or software standby mode (Initial value)
1 TCNT counts φSUB-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, watch mode*, or subactive mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode, watch mode, or high-speed mode
Note: *When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
25.2.4 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTRCRH and MSTPCRL Bits 7 to 0—Module Stop (MSTP 15 to MSTP 0): These bits
specify module stop mode. See table 25.4 for the method of selecting on-chip supporting modules.
MSTPCRH, MSTPCRL
Bits 7 to 0
MSTP15 to MSTP0 Description
0 Module stop mode is cle ared (Initial val ue of MSTP15, MSTP14)
1 Module stop mode is set (Initial value of MSTP13 to MSTP0)
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 753 of 1130
REJ09B0327-0400
25.3 Medium-Speed Mode
When the SCK2 to SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU
operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/3 2) specified by the SCK2 to SCK0 bits.
The bus master other than the CPU (the DTC) also operates in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR
are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt,
medium-speed mode is restored.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in
LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0, a transition is made to software
standby mode. When software standby mode is cleared by an external interrupt, medium-speed
mode is restored.
When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is
cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 25.2 shows the timing for transition to and clearance of medium-speed mode.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 754 of 1130
REJ09B0327-0400
Bus master clock
φ,
supporting module
clock
Internal address
bus
Internal write signal
Medium-speed mode
SBYCRSBYCR
Figure 25.2 Medium-Speed Mode Transition and Clearance Timing
25.4 Sleep Mode
25.4.1 Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR
are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU’s internal registers are retained. Other supporting modules do not stop.
25.4.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or with the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and
interrupt exception handling is started. Sleep mode will not be clear ed if interrupts are disabled, or
if interrupts other than NMI have been masked by the CPU.
Clearing with the RES
RESRES
RES Pin: When the RES pin is driven low, the reset state is entered. When the
RES pin is driven high after the prescribed reset input period, the CPU begins reset exception
handling.
Clearing with the STBY
STBYSTBY
STBY Pin: When the STBY pin is driven low, a transition is made to ha rdware
standby mode.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 755 of 1130
REJ09B0327-0400
25.5 Module Stop Mode
25.5.1 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 25.4 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating again at the end of the bus cycle. In module stop mode, the internal states of
modules other than the SCI, A/D converter, 8-bit PWM module, and 14-bit PWM module, are
retained.
After reset release, all modules other than the DTC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 756 of 1130
REJ09B0327-0400
Table 25.4 MSTP Bits and Corre sponding On-Chip Supporting Modules
Register Bit Module
MSTPCRH MSTP15 —
MSTP14*Data transfer controller (DTC)
MSTP13 16-bit free-running timer (FRT)
MSTP12 8-bit timer (TMR0, TMR1)
MSTP11 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX)
MSTP10 D/A converter
MSTP9 A/D converter
MSTP8 8-bit timers (TMRX, TMRY), timer connection
MSTPCRL MSTP7 Serial communicat ion inter face 0 (SCI0)
MSTP6 Serial communi cation interface 1 (SCI1)
MSTP5 Serial communi cation interface 2 (SCI2)
MSTP4*I2C bus interface (IIC) channel 0 (option)
MSTP3*I2C bus interface (IIC) channel 1 (option)
MSTP2 Host interface (HIF), keyboard matrix interrupt mask register (KMIMR,
KMIMRA), port 6 MOS pull-up control register (KMPCR), keyboard
buffer controller (PS2)
MSTP1*—
MSTP0*—
Notes: Do not set bit 15 to 1. Bits 1 and 0 can be read or written to, but do not affect operation.
*Must be set to 1 in the H8S/2144 Group and H8S/2147N.
25.5.2 Usage Note
If there is conflict between DTC module stop mode setting and a DTC bus request, the bus request
has priority and the MSTP bit will n ot be set to 1.
Write 1 to the MSTP bit again after the DTC bus cycle.
When using the H8S/2144 Group and H8S/2147N, the MSTP bits for nonexistent modules must
be set to 1.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 757 of 1130
REJ09B0327-0400
25.6 Software Standby Mode
25.6.1 Software Standby Mo de
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in
LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained.
In this mo de the oscillator stops, and therefore power dissipation is significantly reduced.
25.6.2 Clearing So ftware Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pin IRQ0, IRQ1, IRQ2,
IRQ6, or IRQ7), or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt request
signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in
SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and
interrupt exception handling is started.
Software standby mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if
the corresponding enable bit has been cleared to 0 or has been masked by the CPU.
Clearing with the RES
RESRES
RES Pin: When the RES pin is driven low, clock oscillation is started. At th e
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin
must be he ld low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins
reset exception handling.
Clearing with the STBY
STBYSTBY
STBY Pin: When the STBY pin is driven low, a transition is made to ha rdware
standby mode.
25.6.3 Setting Oscillat ion Settling Time after Clearing Soft w are Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 758 of 1130
REJ09B0327-0400
Using a Crysta l Oscillator
Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time).
Table 25.5 shows the standby times for different operating frequencies and settings of bits STS2 to
STS0.
Table 25.5 Oscilla tion Settling Time Settings
STS2 STS1 STS0 Standby Time 20
MHz 16
MHz 12
MHz 10
MHz 8
MHz 6
MHz 4
MHz 2
MHz Unit
0 0 0 8192 states 0.41 0.51 0.65 0.8 1.0 1.3 2.0 4.1 ms
1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2
1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4
1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8
1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5
1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2
10Reserved ———————— µs
1 16 states*0.8 1.0 1.3 1.6 2.0 2.7 4.0 8.0
: Recommended time setting
Note: *This setting must not be used in the flash memory version.
Using an External Clock
Any value can be set. Normally, use of the minimum time is recommended.
25.6.4 Softwa re Standby Mode Applica tion Example
Figure 25.3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 759 of 1130
REJ09B0327-0400
Oscillator
φ
NMI
NMIEG
SSBY
NMI
exception
handling
NMIEG = 1
SSBY = 1
SLEEP instruction
Software standby mode
(power-down state) Oscillation
settling time
tOSC2
NMI exception
handling
Figure 25.3 Software Standby Mode Application Exa mple
25.6.5 Usage Note
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
Current dissipation in cr eases while waiting for oscillation to settle.
25.7 Hardware Standby Mode
25.7.1 Hardwa re Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I /O ports are set to the high -impedance state.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 760 of 1130
REJ09B0327-0400
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD1 and MD0) while the chip is in hardware standby
mode.
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set an d clock oscillation is started.
Ensure that th e RES pin is held low until the clock oscillation settles (at least 8 ms—the oscillation
settling time—when using a crystal oscillator ) . When the RES pin is subsequently driven high, a
transition is made to the program execution state via the reset exception handling state.
25.7.2 Hardware Standby Mode Timing
Figure 25.4 shows an ex ample of hardware standby mode timing.
When the STBY pin is dr iven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation settling time, then changin g the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
settling time Reset exception
handling
Figure 25.4 Hardware Standby Mode Timing
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 761 of 1130
REJ09B0327-0400
25.8 Watch Mode
25.8.1 Watch Mode
If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in
SBYCR is set to 1, the DTON bit in L PWRCR is cleared to 0, and the PSS bit in TCSR (WDT1)
is set to 1, the CPU m a kes a transition to watch mode.
In this mode, the CPU and all on-chip supporting modules except WDT1 stop. As long as the
prescribed voltage is supplied, the contents of some of the CPU’s internal registers and on-chip
RAM are retained, an d I/O ports retain their states prior to the transition .
25.8.2 Clearing Watch Mode
Watch mode is cleared by an interrupt (WOVI1 interrupt, NMI pin, or pin IRQ0, IRQ1, IRQ2,
IRQ6, or IRQ7), or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and
a transition is mad e to high- speed mode or medium-speed mod e if the LSON bit in LPWRCR is
cleared to 0, or to sub active mode if the LSON bit is set to 1. When making a transition to high-
speed mod e , after th e elapse of the time set in bits STS2 to STS0 in SBYCR, stable clock s are
supplied to the entire chip, and interrupt ex ception handling is started.
Watch mode cannot b e clear ed with an I RQ0, IRQ1, IRQ2, IRQ6, o r IRQ7 interr upt if th e
corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if
acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by
the CPU.
See section 25. 6.3, Setting Oscillation Settlin g Time after Clearing Software Standby Mode, for
the oscillation settling time setting when making a transition from watch mode to high-speed
mode.
Clearing with the RES
RESRES
RES Pin: See “Clearing with the RES Pin” in section 25.6.2, Clearing
Software Standby Mode.
Clearing with the STBY
STBYSTBY
STBY Pin: When the STBY pin is driven low, a transition is made to ha rdware
standby mode.
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 762 of 1130
REJ09B0327-0400
25.9 Subsleep Mode
25.9 .1 Subsleep Mode
If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,
the LSON bit in LPWRCR is set to 1, and the PSS bit in T CSR ( WDT1 ) is set to 1, the CPU
makes a transition to subsleep mode.
In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and
WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU’s
internal reg ister s and on-chip RAM are retained, and I/O ports retain their states prior to the
transition.
25.9.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, NMI pin, or pin
IRQ0 to IRQ7), or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared
and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to
IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting
module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable
register or masked by the CPU.
Clearing with the RES
RESRES
RES Pin: See “Clearing with the RES Pin” in section 25.6.2, Clearing
Software Standby Mode.
Clearing with the STBY
STBYSTBY
STBY Pin: When the STBY pin is driven low, a transition is made to ha rdware
standby mode
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 763 of 1130
REJ09B0327-0400
25.10 Subactive Mode
25.10.1 Subact ive Mode
If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON
bit in LPWRCR, an d the PSS bit in TCSR (WDT1) are all set to 1, the CPU make s a tr ansition to
subac tive mode. When an inte rrupt is generated in watch mode, if the LSON bit in LPWRCR is
set to 1, a transition is made to subactive mode. When an interrupt is ge nerated in subsleep m ode,
a transition is m a de to subactive mode.
In subactive mode, the CPU performs sequential program execution at low speed on the subclock.
In this mode, all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop.
When ope r a tin g the device in subactive mode , bits SCK2 to SCK0 in SBYCR must all be clear ed
to 0.
25.10.2 Clearing Subactive Mode
Subsleep mode is cleared by a SLEEP instruction, or by means of the RES pin or STBY pin.
Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit
in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in T CSR
(WDT1) is set to 1, su bactive mode is cleared and a tran sition is made to watch mode. When a
SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in
LPWRCR is set to 1, and the PSS bit in TCSR ( WDT1 ) is set to 1, a transition is made to subsleep
mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the
DTON bit is set to 1 an d the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR
(WDT1) is set to 1, a tr ansition is made directly to high-speed mode.
Fort details of direct transition, see section 25.11, Direct Transitio n.
Clearing with the RES
RESRES
RES Pin: See “Clearing with the RES Pin” in section 25.6.2, Clearing
Software Standby Mode.
Clearing with the STBY
STBYSTBY
STBY Pin: When the STBY pin is driven low, a transition is made to ha rdware
standby mode
Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 764 of 1130
REJ09B0327-0400
25.11 Direct Transition
25.11.1 Overview of Direct Transition
There are three operating modes in which the CPU executes programs: high-speed mode, medium-
speed mode, and subactive mode. A transition between high-speed mode and subactive mode
without halting the program is called a direct transition. A direct transition can be carried out by
setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition,
direct transition interrupt exception handling is started.
Direct Transition from High-Speed Mode to Subactive Mo de: If a SLEEP instruction is
executed in high -speed mode while the SSBY bit in SBYCR, the LSON bit an d DTON bit in
LPWRCR, and the PSS bit in TSCR (WDT1) are all set to 1, a transition is made to sub active
mode.
Direct Transition from Subactive Mode to High-Speed Mode: If a SLEEP instruction is
executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0
and the DTON b it is set to 1 in LPWRCR, and the PSS bit in TSC R (WDT1) is set to 1, after the
elapse of the tim e set in bits STS2 to STS0 in SBYCR, a transition is m a de to directly to high-
speed mode.
25.12 Usage Notes
1. When making a transition to subactive mode or watch mode, set the DTC to enter module stop
mode (wr ite 1 to th e relevant bits in MSTPCR), and then read the relevant bits to confirm that
they are set to 1 before mode tr ansition. Do not clear module stop mode (write 0 to the relevant
bits in MSTPCR) until a transition f r om subactive mode to high -speed mode or medium-speed
mode has been performed.
If a DTC activation source occurs in sub-activ e mod e , the DTC will be activated only after
module stop mode has been cleared and high-speed mode or medium-speed mode has been
entered.
2. The on-chip peripheral modules (DTC and TPU) which halt operation in subactive mode
cannot clear an interrupt in subactive mode. Therefore, if a transition is made to sub-active
mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the
interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter
subactive mode or watch mode.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 765 of 1130
REJ09B0327-0400
Section 26 Electrical Characteristics
26.1 Voltage of Power Supply and Operating Range
The power supply voltage and operating range (shaded part) for each product are shown in table
26.1.
Table 26.1 Power Supply Voltage and Operating Range (1) (F-ZTAT P r oducts)
Product/
Power supply 5-V version Product/
Power supply 3-V versi on
HD64F2148
HD64F2144
HD64F2142R
VCC
5.5 V
4.5 V
4.0 V
2 MHz 16 MHz
fop 20 MHz
Flash
Memory
Select 5.0 V ±0.5 V for
programming condition
in PROM programmer
Programming
HD64F2148V
HD64F2144V
HD64F2142RV
V
CC
5.5 V
3.6 V
3.0 V
2 MHz 10 MHz
fop
Flash Memory
Programming
Select 5.0 V ±0.5 V for
programming condition
in PROM programmer
VCC1 pin
VCC2 pin VCC = 5.0 V ±10% (fop = 2 to 20 MHz)
VCC = 4.0 V to 5.5 V (fop = 2 to 16 MHz) VCC1 pin
VCC2 pin VCC = 3.0 V to 5.5 V (fop = 2 to 10 MHz)
VCCB pin*VCCB = 5.0 V ±10% (fop = 2 to 20 MHz)
VCCB = 4.0 V to 5.5 V (fop = 2 to 16 MHz) VCCB pin*VCCB = 3.0 V to 5.5 V (fop = 2 to 10 MHz)
AVCC pin AVCC = 5.0 V ±10% (fop = 2 to 20 MHz)
AVCC = 4.0 V to 5.5 V (fop = 2 to 16 MHz) AVCC pin AVCC = 3.0 V to 5.5 V (fop = 2 to 10 MHz)
Note: *Available only in the H8S/2148 Group.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 766 of 1130
REJ09B0327-0400
Table 26.1 Power Supply Voltage and Operating Range (2) (F-ZTAT P r oducts)
Product/
Power supply 5-V version Product/
Power supply 3-V versi on
HD64F2147N
VCC
5.5 V
4.5 V
2 MHz 16 MHz
fop 20 MHz
Flash
Memory
Programming
HD64F2147NV
V
CC
5.5 V
3.6 V
3.0 V
2 MHz 10 MHz
fop
Flash Memory
Programming
Select 5.0 V ±0.5 V for
programming condition
in PROM programmer
VCC1 pin
VCC2 pin VCC = 5.0 V ±10% (fop = 2 to 20 MHz) VCC1 pin
VCC2 pin VCC = 3.0 V to 5.5 V (fop = 2 to 10 MHz)
VCCB pin VCCB = 5.0 V ±10% (fop = 2 to 20 MHz) VCCB pin VCCB = 3.0 V to 5.5 V (fop = 2 to 10 MHz)
AVCC pin AVCC = 5.0 V ±10% (fop = 2 to 20 MHz) AVCC pin AVCC = 3.0 V to 5.5 V (fop = 2 to 10 MHz)
Table 26.1 Power Supply Voltag e and Operating Ra nge (3) (F -ZTAT A-Mask P r oducts)
Product/
Power supply 5-V version Product/
Power supply 3-V versi on
HD64F2148A
HD64F2147A
HD64F2144A
V
CC
5.5 V
4.5 V
4.0 V
2 MHz 16 MHz
fop 20 MHz
Flash
Memory
Programming
Select 3.3 V ±0.3 V for
programming condition
in PROM programmer
HD64F2148AV
HD64F2147AV
HD64F2144AV
V
CC
5.5 V
3.6 V
3.0 V
2.7 V 2 MHz 10 MHz
fop
Flash Memory
Programming
Select 3.3 V ±0.3 V for
programming condition
in PROM programmer
VCC1 pin VCC = 5.0 V ±10% (fop = 2 to 20 MHz)
VCC = 4.0 V to 5.5 V (fop = 2 to 16 MHz) VCC1 pin VCC = 2.7 V to 3.6 V (fop = 2 to 10 MHz)
(CIN in use VCC = 3.0 V to 3.6 V)
VCL pin (VCC2) VCL = C connect VCL pin (VCC2) VCL = VCC connect
VCCB pin*VCCB = 5.0 V ±10% (fop = 2 to 20 MHz)
VCCB = 4.0 V to 5.5 V (fop = 2 to 16 MHz) VCCB pin*VCCB = 2.7 V to 5.5 V (fop = 2 to 10 MHz)
(CIN in use VCCB = 3.0 V to 5.5 V)
AVCC pin AVCC = 5.0 V ±10% (fop = 2 to 20 MHz)
AVCC = 4.0 V to 5.5 V (fop = 2 to 16 MHz) AVCC pin AVCC = 2.7 V to 3.6 V (fop = 2 to 10 MHz)
(CIN in use AVCC = 3.0 V to 3.6 V)
Note: *Available only in the H8S/2148 Group.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 767 of 1130
REJ09B0327-0400
Table 26.1 Power Supply Voltag e and Operating Range (4) (Mask ROM Products)
Product/
Power supply 5-V version 4-V version 3-V version
HD6432148S
HD6432148SW
HD6432147S
HD6432147SW
HD6432144S
HD6432143S
VCC
5.5 V
4.5 V
2 MHz fop 20 MHz
VCC
5.5 V
4.0 V
2 MHz 16 MHz
fop
V
CC
2.7 V
3.6 V
2 MHz 10 MHz
fop
VCC1 pin VCC = 5.0 V ±10% VCC = 4.0 V to 5.5 V VCC = 2.7 V to 3.6 V
(CIN in use VCC = 3.0 V to 3.6 V)
VCL pin (VCC2) VCL = C connect VCL = C connect VCL = VCC connect
VCCB pin*VCCB = 5.0 V ±10% VCCB = 4.0 V to 5.5 V VCCB = 2.7 V to 5.5 V
(CIN in use VCCB = 3.0 V to 5.5 V)
AVCC pin AVCC = 5.0 V ±10% AVCC = 4.0 V to 5.5 V AVCC = 2.7 V to 3.6 V
(CIN in use AVCC = 3.0 V to 3.6 V)
Note: *Available only in the H8S/2148 Group.
Table 26.1 Power Supply Voltag e and Operating Range (5) (Mask ROM Products)
Product/
Power supply 5-V version 4-V version 3-V version
HD6432142
VCC
5.5 V
4.5 V
2 MHz fop 20 MHz
VCC
5.5 V
4.0 V
2 MHz 16 MHz
fop
V
CC
2.7 V
5.5 V
2 MHz 10 MHz
fop
VCC1 pin
VCC2 pin VCC = 5.0 V ±10% VCC = 4.0 V to 5.5 V VCC = 2.7 V to 5.5 V
AVCC pin AVCC = 5.0 V ±10% AVCC = 4.0 V to 5.5 V AVCC = 2.7 V to 5.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 768 of 1130
REJ09B0327-0400
26.2 Electrical Characteristics of H8S/2148 F-ZTAT
26.2.1 Absolute Maximum Ratings
Table 26.2 lists the ab solute maximum ratings.
Table 26.2 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage*VCC –0.3 to +7.0 V
Input/output buffer pow er sup ply
(power supply for the port A) VCCB –0.3 to +7.0 V
Input voltage (except ports 6, 7,
and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port 6) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port A) Vin –0.3 to VCCB +0.3 V
Input voltage (CIN input selected
for port 6) Vin –0.3 V to lower of voltages VCC +0.3 and
AVCC +0.3 V
Input voltage (CIN input selected
for port A) Vin –0.3 V to lower of voltages VCCB +0.3 and
AVCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Reference supply voltage AVref –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Topr Regular specifications: 0 to +75 °COperating temperature (flash
memory programming/erasing) Wide-range specifications: 0 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Note: *Power supply voltage for VCC1 and VCC2 pins .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 769 of 1130
REJ09B0327-0400
26.2.2 DC Characteristics
Table 26.3 lists the DC characteristics. Permitted output current values and bus drive
characteristics are shown in tables 26.4 and 26.5, respectively.
Table 26.3 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC*1 = 5.0 V ±10%,
AVref*1 = 4.5 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*11 (regular
specifications), Ta = –40 to +85°C*11 (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7
VCCB × 0.7
Schmitt
trigger input
voltage
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–0.4 — —
VT–VCC × 0.3 — — V
VT+——V
CC × 0.7
P67 to P60
(KWUL = 01)
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —
VT+——V
CC × 0.8
P67 to P60
(KWUL = 10)
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —
VT+——V
CC × 0.9
Schmitt
trigger input
voltage
(in level
switching)*6
P67 to P60
(KWUL = 11)
VT+ – VT–0.05 — —
RES, STBY,
NMI, MD1, MD0 (2) VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3
PA7 to PA0*7VCCB × 0.7 — VCCB +0.3
Input high
voltage
Port 7 2.0 — AVCC +0.3
Input pins except
(1) and (2)
above
2.0 — VCC +0.3
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 770 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97, and
P52*4)*5 *83.5 — — V IOH = –1 mA
P97, P52*42.5 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µA Vin = 0.5 to
VCC –0.5 V
Input
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB –0.5 V
Ports 1 to 3 –IP50 — 300 µA Vin = 0 VInput
pull-up
MOS
current
Ports A*8, B,
Port 6
(P6PUE = 0)
60 — 500 µA
Port 6
(P6PUE = 1) 15 — 150 µA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 771 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
RES (4) Cin — — 80 pF
NMI — — 50 pF
Input
capacitance
P52, P97,
P42, P86
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins except
(4) above — — 15 pF
Normal operation ICC — 85 120 mA f = 20 MHzCurrent
dissipation*9Sleep mode — 70 100 mA f = 20 MHz
Standby mode*10 — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC= 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref= 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.5 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 772 of 1130
REJ09B0327-0400
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. Port A characteristics depends on VCCB (or on VCC when other pins are in output mode).
9. Current dissipation values are for VIH min = VCC –0.5 V, VCCB –0.5 V, and VIL max = 0.5 V
with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC × 0.9, VCCB × 0.9, and VIL max =
0.3 V.
11.For flash memory program/erase operations, the applicable range is Ta = 0 to +75°C
(regular specifications) or Ta = 0 to +85°C (wide-range specifications).
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 773 of 1130
REJ09B0327-0400
Table 26.3 DC Characteristics (2)
Conditions: VCC = 4.0 V to 5.5 V*11, VCCB = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V,
AVref*1 = 4.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*11 (regular
specifications), Ta = –40 to +85°C*11 (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7
VCCB × 0.7 V
VT+ – VT–0.4 — — V
VCC = 4.5 V to
5.5 V,
VCCB = 4.5 V
to 5.5 V
VT–0.8 — — V
VT+——V
CC × 0.7
VCCB × 0.7 VVCC < 4.5 V,
VCCB < 4.5 V
Schmitt
trigger input
voltage
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–0.3 — — V
VT–VCC × 0.3 — — V
VT+——V
CC × 0.7 VCC = 4.0 V to
5.5 V
P67 to P60
(KWUL = 01)
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —
VT+——V
CC × 0.8
P67 to P60
(KWUL = 10)
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —
Schmitt
trigger input
voltage
(in level
switching)*6
VT+——V
CC × 0.9
P67 to P60
(KWUL = 11)
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
PA7 to PA0*7VCCB × 0.7 — VCCB + 0.3 V
Port 7 2.0 — AVCC +0.3 V
Input pins
except (1) and
(2) above
2.0 — VCC +0.3 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 774 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0 V VCCB = 4.5 V
to 5.5 V
–0.3 — 0.8 V VCCB < 4.5 V
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8 V
VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAOutput high
voltage All output pins
(except P97,
and P52*4)*5 *83.5 — — V IOH = –1 mA,
VCC = 4.5 V to
5.5 V,
VCCB = 4.5 V
to 5.5 V
3.0 — — V IOH = –1 mA,
VCC < 4.5 V,
VCCB < 4.5 V
P97, P52*42.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6
Ports 8, 9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB −0.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 775 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Ports 1 to 3 –IP50 — 300 µAInput
pull-up
MOS
current
Ports A*8, B
Port 6
(P6PUE = 0)
60 — 500 µA
Port 6
(P6PUE = 1) 15 — 150
Vin = 0 V,
VCC = 4.5 V to
5.5 V,
VCCB = 4.5 V
to 5.5 V
Ports 1 to 3 30 — 200 µA
Ports A*8, B
Port 6
(P6PUE = 0)
40 — 400 µA
Port 6
(P6PUE = 1) 10 — 110
Vin = 0 V,
VCC ≤ 4.5 V,
VCCB ≤ 4.5 V
RES (4) Cin — — 80 pF
NMI — — 50 pF
P52, P97, P42,
P86, PA7 to PA2 — — 20 pF
Input
capacitance
Input pins
except (4) above — — 15 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Normal operation I CC — 70 100 mA f = 16 MHzCurrent
dissipation*9Sleep mode — 60 85 mA f = 16 MHz
Standby mode*10 — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.0 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 776 of 1130
REJ09B0327-0400
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
9. Current dissipation values are for VIH min = VCC –0.5 V, VCCB –0.5 V, and VIL max =
0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 4.0 V, VIH min = VCC × 0.9, VCCB × 0.9, and VIL max =
0.3 V.
11.For flash memory program/erase operations, the applicable ranges are VCC = 4.5 V to
5.5 V and Ta = 0 to +75°C (regular specifications) or Ta = 0 to +85°C (wide-range
specifications).
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 777 of 1130
REJ09B0327-0400
Table 26.3 DC Characteristics (3)
Conditions: VCC = 3.0 V to 5.5 V*11, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 5.5 V,
AVref = 3.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*11
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–VCC × 0.2
VCCB × 0.2 —— V
VT+——V
CC × 0.7
VCCB × 0.7 V
Schmitt
trigger input
voltage
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–V
CC
× 0.05
VCCB ×
0.05
—— V
VT–VCC × 0.3 — — VP67 to P60
(KWUL = 01) VT+——V
CC × 0.7
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —
Schmitt
trigger input
voltage
(in level
swiching)*6P67 to P60
(KWUL = 10) VT+——V
CC × 0.8
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —P67 to P60
(KWUL = 11) VT+——V
CC × 0.9
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC × 0.9 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
PA7 to PA0*7VCCB × 0.7 — VCCB +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Input pins
except (1) and
(2) above
VCC × 0.7 — VCC +0.3 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 778 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — VCC × 0.1 V
PA7 to PA0 –0.3 — VCCB × 0.2 V VCCB < 4.0 V
0.8 V VCCB = 4.0 V
to 5.5 V
–0.3 — VCC × 0.2 V VCC < 4.0 VNMI, EXTAL,
input pins except
(1) and (3)
above
0.8 V VCC = 4.0 V to
5.5 V
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97,
and P52*4)*5 *8VCC –1.0
VCCB –1.0 —— VI
OH = –1 mA
(VCC < 4.0 V,
VCCB < 4.0 V)
P97, P52*41.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 5 mA
(VCC < 4.0 V),
IOL = 10 mA
(4.0 V ≤ VCC ≤
5.5 V)
RESO ——0.4VI
OL = 1.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB –0.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 779 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Ports 1 to 3 –IP10 — 150 µAInput pull-
up MOS
current Ports A*8, B,
Port 6
(P6PUE = 0)
30 — 250 µA
Port 6
(P6PUE = 1) 3 — 70 µA
Vin = 0 V,
VCC = 3.0 V to
3.6 V,
VCCB = 3.0 V
to 3.6 V
RES (4) Cin — — 80 pFInput
capacitance NMI — — 50 pF
P52, P97,
P42, P86,
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation ICC — 50 70 mA f = 10 MHz
Sleep mode — 40 60 mA f = 10 MHz
Standby mode*10 — 0.01 5.0 µA Ta ≤ 50°C
Current
dissipation*9
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 3.0 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 780 of 1130
REJ09B0327-0400
4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
9. Current dissipation values are for VIH min = VCC –0.5 V, VCCB –0.5 V, and VIL max =
0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 3.0 V, VIH min = VCC × 0.9, VCCB × 0.9, and VIL max =
0.3 V.
11.For flash memory program/erase operations, the applicable ranges are VCC = 3.0 V to
3.6 V and Ta = 0 to +75°C.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 781 of 1130
REJ09B0327-0400
Table 26.4 Permiss ible Output Currents
Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) SCL1, SCL0, SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4 (bus drive
function se lec ted)
IOL ——20mA
Ports 1, 2, 3 — — 10 mA
RESO ——3 mA
Other output pi ns — — 2 mA
Total of ports 1, 2, and 3 ∑ IOL ——80mAPermissible output
low current (total) Total of all output pins,
including the above — — 120 mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——40mA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 782 of 1130
REJ09B0327-0400
Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) SCL1, SCL0, SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4 (bus drive
function se lec ted)
IOL ——10mA
Ports 1, 2, 3 — — 2 mA
RESO ——1 mA
Other output pi ns — — 1 mA
Total of ports 1, 2, and 3 ∑ IOL ——40mAPermissible output
low current (total) Total of all output pins,
including the above ——60mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——30mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 26.4.
2. When driving a Darlington pair or LED, alwa ys ins ert a current-limiting resistor in the
output line, as show in figure s 26.1 and 26.2 .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 783 of 1130
REJ09B0327-0400
2 kΩ
This chip
Port
Darlington pair
Figure 26.1 Darlington Pair Drive Circuit (Example)
600 Ω
This chip
Ports 1 to 3
LED
Figure 26.2 LED Drive Circuit (Example)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 784 of 1130
REJ09B0327-0400
Table 26.5 Bus Drive Characteristics
Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V
Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected)
Item Symbol Min Typ Max Unit Test Conditions
VT–VCC × 0.3 —— VV
CC = 3.0 V to 5.5 VSchmitt trigger
input voltage VT+——VCC × 0.7 VCC = 3.0 V to 5.5 V
VT+ – VT–VCC × 0.05 —— VCC = 3.0 V to 5.5 V
Input high voltage VIH VCC × 0.7 — VCC +0.5 V VCC = 3.0 V to 5.5 V
Input low voltage VIL –0.5 — VCC × 0.3 VCC = 3.0 V to 5.5 V
Output low voltage VOL ——0.8 V IOL = 16 mA,
VCC = 4.5 V to 5.5 V
——0.5 IOL = 8 mA
——0.4 IOL = 3 mA
Input capacitan ce Cin ——20 pF Vin = 0 V, f = 1 MHz,
Ta = 25°C
Three-state leakage
current (off state) | ITSI | ——1.0 µA Vin = 0.5 to VCC –0.5 V
SCL, SDA output
fall time tOf 20 + 0.1 Cb —250 ns VCC = 3.0 V to 5.5 V
Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V
Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive
function selected)
Item Symbol Min Typ Max Unit Test Conditions
Output low voltage VOL ——0.8 V IOL = 16 mA,
VCCB = 4.5 V to 5.5 V
——0.5 IOL = 8 mA
——0.4 IOL = 3 mA
26.2.3 AC Characteristics
Clock timing, control signal timing, bus timing, and timing of on-chip supporting modules list the
following.
Figure 26.4 shows the test conditions for th e AC character istics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 785 of 1130
REJ09B0327-0400
(1) Clock Timing
Table 26.6 shows the clock timing. The clock timing specified here covers clock (φ) outp ut and
clock pulse generator (crystal) and exter nal clock input (EXTAL pin) oscillation settling times.
For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock
Pulse Generator.
Table 26.6 Clock Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 50 500 62.5 500 100 500 ns Figure 26.5
Clock high pulse
width tCH 17 —20 —30 —ns Figure 26.5
Clock low pulse
width tCL 17 —20 —30 —ns
Clock rise time tCr —8 —10 —20 ns
Clock fall time tCf —8 —10 —20 ns
Oscillati on sett ling
time at reset
(crystal)
tOSC1 10 —10 —20 —ms Figure 26.6
Figure 26.7
Oscillati on sett ling
time in software
standby (cr ysta l)
tOSC2 8 — 8 — 8 — ms
External clock
output stabilization
delay time
tDEXT 500 —500 —500 —µs
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 786 of 1130
REJ09B0327-0400
(2) Control Signal Timing
Table 26.7 shows the control signal timing. The only ex ternal interrupts that can operate on the
subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7.
Table 26.7 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
RES setup time tRESS 200 —200 —300 —ns Figure 26.8
RES pulse width tRESW 20 —20 —20 — tcyc
NMI setup time
(NMI) tNMIS 150 —150 —250 —ns Figure 26.9
NMI hold time
(NMI) tNMIH 10 —10 —10 —ns
NMI pulse width
(NMI) (exiting
software standby
mode)
tNMIW 200 —200 —200 —ns
IRQ setup time
(IRQ7 to IRQ0)tIRQS 150 —150 —250 —ns
IRQ hold time
(IRQ7 to IRQ0)tIRQH 10 —10 —10 —ns
IRQ pulse width
(IRQ7, IRQ6,
IRQ2 to IRQ0)
(exiting sof t war e
standby mode)
tIRQW 200 —200 —200 —ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 787 of 1130
REJ09B0327-0400
(3) Bus Timing
Table 26.8 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (φ = 32.768 kHz).
Table 26. 8 Bus Timing (1 ) (Nomal Mode)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Address
delay time tAD —20 —30 —40 ns
Address
setup time tAS 0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —0.5 ×
tcyc –30 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD —20 —30 —40 ns
AS delay
time tASD —30 —45 —60 ns
RD delay
time 1 tRSD1 —30 —45 —60 ns
RD delay
time 2 tRSD2 —30 —45 —60 ns
Read data
setup time tRDS 15 —20 —35 —ns
Read data
hold time tRDH 0 — 0 — 0 — ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 788 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Read data
access
time 1
tACC1 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —1.0 ×
tcyc –60 ns Figure 26.10
to
figure 26.14
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –35 —1.5 ×
tcyc –50 ns
Read data
access
time 3
tACC3 —2.0 ×
tcyc –30 —2.0 ×
tcyc –40 —2.0 ×
tcyc –60 ns
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –35 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –30 —3.0 ×
tcyc –40 —3.0 ×
tcyc –60 ns
WR delay
time 1 tWRD1 —30 —45 —60 ns
WR delay
time 2 tWRD2 —30 —45 —60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –30 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD —30 —45 —60 ns
Write data
setup time tWDS 0 — 0 — 0 — ns
Write data
hold time tWDH 10 —15 —20 —ns
WAIT
setup time tWTS 30 —45 —60 —ns
WAIT hold
time tWTH 5 — 5 — 10 —ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 789 of 1130
REJ09B0327-0400
Table 26.8 Bus Timing (2) (Advanced mo de)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Address
delay time tAD —30 —45 —60 ns
Address
setup time tAS 0.5 ×
tcyc –25 —0.5 ×
tcyc –35 —0.5 ×
tcyc –50 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD —30 —45 —60 ns
AS delay
time tASD —30 —45 —60 ns
RD delay
time 1 tRSD1 —30 —45 —60 ns
RD delay
time 2 tRSD2 —30 —45 —60 ns
Read data
setup time tRDS 15 —20 —35 —ns
Read data
hold time tRDH 0 — 0 — 0 — ns
Read data
access
time 1
tACC1 —1.0 ×
tcyc –40 —1.0 ×
tcyc –55 —1.0 ×
tcyc –80 ns
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –35 —1.5 ×
tcyc –50 ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 790 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Read data
access
time 3
tACC3 —2.0 ×
tcyc –40 —2.0 ×
tcyc –55 —2.0 ×
tcyc –80 ns Figure 26.10
to
figure 26.14
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –35 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –40 —3.0 ×
tcyc –55 —3.0 ×
tcyc –80 ns
WR delay
time 1 tWRD1 —30 —45 —60 ns
WR delay
time 2 tWRD2 —30 —45 —60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –30 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD —30 —45 —60 ns
Write data
setup time tWDS 0 — 0 — 0 — ns
Write data
hold time tWDH 10 —15 —20 —ns
WAIT
setup time tWTS 30 —45 —60 —ns
WAIT hold
time tWTH 5 — 5 — 10 —ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 791 of 1130
REJ09B0327-0400
(4) Timing of On-Chip Supporting Modules
Tables 26.9 to 26.11 show the on-chip supporting module timing. The only on-chip supporting
modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external
interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and
1).
Table 26. 9 Timing of On-Chip Supporting Modules (1 )
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
I/O
ports Output data delay
time tPWD —50 —50 —100 ns Figure
26.15
Input data setup
time tPRS 30 —30 —50 —
Input data hold
time tPRH 30 —30 —50 —
FRT Timer output de lay
time tFTOD —50 —50 —100 ns Figure
26.16
Timer input setup
time tFTIS 30 —30 —50 —
Timer clock input
setup time tFTCS 30 —30 —50 —Figure
26.17
Single
edge tFTCWH 1.5 —1.5 —1.5 — tcyc
Timer
clock
pulse
width Both
edges tFTCWL 2.5 —2.5 —2.5 —
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 792 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
TMR Timer output
delay time tTMOD —50 —50 —100 ns Figure
26.18
Timer reset input
setup time tTMRS 30 —30 —50 —Figure
26.20
Timer clock input
setup time tTMCS 30 —30 —50 —Figure
26.19
Single
edge tTMCWH 1.5 —1.5 —1.5 —tcyc
Timer
clock
pulse
width Both
edges tTMCWL 2.5 —2.5 —2.5 —
PWM,
PWMX Pulse output
delay time tPWOD —50 —50 —100 ns Figure
26.21
SCI Asynchro-
nous tScyc 4 — 4 — 4 — tcyc Figure
26.22
Input
clock
cycle Synchro-
nous 6 — 6 — 6 —
Input clock pulse
width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc
Input clock rise
time tSCKr —1.5 —1.5 —1.5 tcyc
Input clock fall
time tSCKf —1.5 —1.5 —1.5
Transmit data
delay time
(synchronous)
tTXD —50 —50 —100 ns Figure
26.23
Receive data set up
time (synchronous) tRXS 50 —50 —100 —ns
Receive data hol d
time (synchronous) tRXH 50 —50 —100 —ns
A/D
conver-
ter
Trigger input setup
time tTRGS 30 —30 —50 —ns Figure
26.24
WDT RESO output delay
time tRESD —100 —120 —200 ns Figure
26.25
RESO output pulse
width tRESOW 132 —132 —132 — tcyc
Note: *Only supporting modules that can be used in subc lock operation
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 793 of 1130
REJ09B0327-0400
Table 26. 9 Timing of On-Chip Supporting Modules (2 )
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
HIF read
cycle CS/HA0 setup
time tHAR 10 —10 —10 —ns Figure
26.26
CS/HA0 hold time tHRA 10 —10 —10 —ns
IOR pulse width tHRPW 120 —120 —220 —ns
HDB delay time tHRD —100 —100 —200 ns
HDB hold time t HRF 025 025040ns
HIRQ delay time tHIRQ —120 —120 —200 ns
HIF writ e
cycle CS/HA0 setup
time tHAW 10 —10 —10 —ns
CS/HA0 hold time tHWA 10 —10 —10 —ns
IOW pulse width tHWPW 60 —60 —100 —ns
HDB
setup
time
Fast A20
gate not
used
tHDW 30 —30 —50 —ns
Fast A20
gate used 45 —55 —85 —ns
HDB hold time t HWD 15 —15 —25 —ns
GA20 delay time tHGA —90 —90 —180 ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 794 of 1130
REJ09B0327-0400
Table 26.10 Keyboard Buffer Controller Timing
Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Ratings
Item Symbol Min Typ Max Unit Test
Conditions Notes
KCLK, KD output
fall time tKBF 20 + 0.1 Cb —250 ns Figure 26.27
KCLK, KD input
data hold time tKBIH 150 —— ns
KCLK, KD input
data setup time tKBIS 150 —— ns
KCLK, KD output
delay time tKBOD ——450 ns
KCLK, KD
capacitive load Cb——400 pF
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 795 of 1130
REJ09B0327-0400
Table 26.11 I2C Bus Timing
Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency
Ratings
Item Symbol Min Typ Max Unit Test Conditions Notes
SCL input cycle
time tSCL 12 ——tcyc Figure 26.28
SCL input high
pulse width tSCLH 3——tcyc
SCL input low
pulse width tSCLL 5——tcyc
SCL, SDA input
rise time tSr ——7.5*tcyc
SCL, SDA input
fall time tSf ——300 ns
SCL, SDA input
sp ike pulse
elimination time
tSP ——1t
cyc
SDA input bus
free time tBUF 5——tcyc
Start condition
input hold time tSTAH 3——tcyc
Retransmission
start condit ion
input setup time
tSTAS 3——tcyc
Stop condition
input setup time tSTOS 3——tcyc
Data input setup
time tSDAS 0.5 ——tcyc
Data input hold
time tSDAH 0——ns
SCL, SDA
capacitive load Cb——400 pF
Note: *17.5tcyc can be set according to the clock selected for use by the I2C module. For details,
see section 16.4, Usage Notes.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 796 of 1130
REJ09B0327-0400
26.2.4 A/D Conversion Characteristics
Tables 26.12 and 26.13 list the A/D conversion characteristics.
Table 26.12 A/D Conversion Characteristics
(AN7 to AN0 Input: 134/266-St ate Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*5——6.7 ——8.4 ——13.4 µs
Analog input
capacitance ——20 ——20 ——20 pF
——10*3——10*3——10*1kΩPermissible signal-
source
impedance 5*45*45*2
Nonlinearity error ——±3.0 ——±3.0 ——±7.0 LSB
Offset error ——±3.5 ——±3.5 ——±7.5 LSB
Full-scale error ——±3.5 ——±3.5 ——±7.5 LSB
Quantization error ——±0.5 ——±0.5 ——±0.5 LSB
Absolute accuracy ——±4.0 ——±4.0 ——±8.0 LSB
Notes: 1. When 4.0 V ≤ AVCC ≤ 5.5 V
2. When 3.0 V ≤ AVCC < 4.0 V
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
5. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 797 of 1130
REJ09B0327-0400
Table 26.13 A/D Conversion Characteristics
(CIN15 to CIN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*5——6.7 ——8.4 ——13.4 µs
Analog input
capacitance ——20 ——20 ——20 pF
——10*3——10*3——10*1kΩPermissible signal-
source
impedance 5*45*45*2
Nonlinearity error ——±5.0 ——±5.0 ——±11.0 LSB
Offset error ——±5.5 ——±5.5 ——±11.5 LSB
Full-scale error ——±5.5 ——±5.5 ——±11.5 LSB
Quantization error ——±0.5 ——±0.5 ——±0.5 LSB
Absolute accuracy ——±6.0 ——±6.0 ——±12.0 LSB
Notes: 1. When 4.0 V ≤ AVCC ≤ 5.5 V
2. When 3.0 V ≤ AVCC < 4.0 V
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
5. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 798 of 1130
REJ09B0327-0400
26.2.5 D/A Conversion Characteristics
Table 26.14 lists the D/A conversion characteristics.
Table 26.14 D/A Conversion Characteristics
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 888 888 888 Bits
Conversion
time With 20-pF
load
capacitance
——10 ——10 ——10 µs
Absolute
accuracy With 2-MΩ
load
resistance
—±1.0 ±1.5 —±1.0 ±1.5 —±2.0 ±3.0 LSB
With 4-MΩ
load
resistance
——±1.0 ——±1.0 ——±2.0
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 799 of 1130
REJ09B0327-0400
26.2.6 Flash Memory Characteristics
Table 26.15 shows the flash memory characteristics.
Table 26.15 Flash Memory Characteristics (Programming/erasing operating range)
Conditions (5 V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications),
Ta = 0 to +85°C (wide-range specifications)
(3 V version): VCC = 3.0 V to 3.6V, VSS = 0 V, Ta = 0 to +75°C
Item Symbol Min Typ Max Unit Test
Condition
Programming time*1 *2 *4tP —10 200 ms/
32 bytes
Erase time*1 *3 *6tE —100 1200 ms/
block
Reprogramming count NWEC 100*810000*9—Times
Data retention time*10 tDRP 10 ——Years
Programming Wai t time after SWE-bit setting*1x10——µs
Wait time after PSU-bit setting*1y50——µs
Wait time after P-bit setting*1 *4z 150 —200 µs
Wait time after P-bit clear*1α10 ——µs
Wait time after PSU-bit clear*1β10 ——µs
Wait time after PV-bit setting*1γ4——µs
Wait time after dummy write*1ε2——µs
Wait time after PV-bit clear*1η4——µs
Maximum programming
count*1 *4 *5N—— 1000 Times z = 200 µs
Erase Wait time after SWE-bit setting*1x10——µs
Wait time after ESU-bit setting*1y 200 ——µs
Wait time after E-bit setting*1 *6z5—10 ms
Wait time after E-bit clear*1α10 ——µs
Wait time after ESU-bit clear*1β10 ——µs
Wait time after EV-bit setting*1γ20 ——µs
Wait time after dummy write*1ε2——µs
Wait time after EV-bit clear*1η5——µs
Maximum erase count*1 *6 *7N—— 120 Times z = 10 ms
Notes: 1. Set the times according to the program /era se alg orithm s .
2. Programming time per 32 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time .)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 800 of 1130
REJ09B0327-0400
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximu m programming time (tP (max))
tP(max) = wait time after P-bit setting (z) × maximum programming count (N)
5. Number of times when the wait time after P-bit setting (z) = 200 µs.
The number of writes should be set according to the actual set value of (z) to allow
programming within the maximum programming time (tP(max)).
6. Maximum erase time (tE (max))
tE(max) = wait time after E-bit setting (z) × maximum erase count (N)
7. Number of times when the wait time after E-bit setting (z ) = 10 ms.
The number of erases should be set according to the actual set value of (z) to allow
erasing within the maximum erase ti me (tE(max)).
8. Minimum number of times for which all characteristics are guaranteed after rewriting
(Guarantee range is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should normally function up to this
value).
10.Data retention characteristic when rewriting is performed within the specification range,
including the minimum value.
26.2.7 Usage Note
(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference
values for electrical characteristics shown in this manual. However, actual performance
figures, operating margins, noise margins, and other properties may vary due to differences in
the manufacturing process, on-chip ROM, layout patterns, etc.
When system ev aluation testing is car ried out using the F-ZTAT version, the same evaluation
tests should also be conducted for the mask ROM version when changing over to that version.
(2) On-chip power supply step-down circuit
The H8S/2148 F-ZTAT does not incorporate an internal power supply step-down circuit.
When changing over to F-ZTAT versions or mask ROM versions incorporating an internal
step-down circuit, the VCC2 pin has the same pin location as the VCL pin in a step-down
circuit.
Therefore, note that the circuit patterns differ between these two types of products.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 801 of 1130
REJ09B0327-0400
External capacitor for
stabilizing power supply By-pass
capacitor Product not
incorporating
step-down
circuit
Product
incorporating
internal
step-down
circuit
VCL
VSS
VCC2
V
CC
power supply
VSS
0.47 µF
one or two
connected
in group 10 µF 0.01 µF
For products incorporating an internal step-down
circuit, do not connect the VCL pin to the VCC
power supply. (The VCC1 pin must be connected
to the VCC power supply as usual.)
The power supply stabilization capacitor must be
connected to the VCL pin. Use a monolithic
ceramic capacitor of 0.47 µF(one or two
connected in group) and locate it near the pins.
In case the power supply voltage is lower than
3.6 V, connect the capacitor in the same way as
the case with no step-down circuit incorporated.
<Products incorporating internal step-down
circuit>
HD6432148S, HD6432148SW,
HD6432147S, HD6432147SW
HD6432144S, HD6432143S,
HD64F2148A, HD64F2147A,
HD64F2144A
The location of the VCC2 (V
CC
power supply)
pin in the product not incorporating an internal
step-down circuit, is the same as the VCL pin in
a product incorporating an internal step-down
circuit.
It is recommended that the by-pass capacitors
are connected to the power supply terminal
(these are reference values).
<Products not incorporating internal step-down
circuit>
HD64F2148(V), HD64F2147N(V),
HD64F2144(V), HD64F2142(V),
HD6432142,
HD6432148SV, HD6432148SVW,
HD6432147SV, HD6432147SVW,
HD6432144SV, HD6432143SV,
HD64F2148AV, HD64F2147AV,
HD64F2144AV
Figure 26.3 Connection of External Capacitor (Mask ROM Type Incorporating Step-Down
Circuit and Product Not Incorporating Step-Down Circuit)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 802 of 1130
REJ09B0327-0400
26.3 Electrical Characteristics of H8S/2148 F-ZTAT (A-mask version),
H8S/2147 F-ZTAT (A-mask version), and Mask ROM Versions of
H8S/2148 and H8S/2147
26.3.1 Absolute Maximum Ratings
Table 26.16 lists th e absolute maximum ratings.
Table 26.16 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage*1VCC –0.3 to +7.0 V
Input/output buffer pow er sup ply
(power supply for the port A) VCCB –0.3 to +7.0 V
Power supply voltage*1
(3 V version) VCC –0.3 to +4.3 V
Power supply voltage*2
(VCL pin) VCL –0.3 to +4.3 V
Input voltage (except ports 6, 7,
and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port 6) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port A) Vin –0.3 to VCCB +0.3 V
Input voltage (CIN input selected
for port 6) Vin –0.3 V to lower of voltages VCC +0.3 and
AVCC +0.3 V
Input voltage (CIN input selected
for port A) Vin –0.3 V to lower of voltages VCCB +0.3 and
AVCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Reference supply voltage AVref –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog power supply voltage
(3 V version) AVCC –0.3 to +4.3 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 803 of 1130
REJ09B0327-0400
Item Symbol Value Unit
Topr Regular specifications: –20 to +75 °COperating temperature (flash
memory programming/erasing) Wide-range specifications: –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: 1. Permanent damage to the chip may result if absolute maximum ratings are
exceeded.
2. Never apply more than 7.0 V to any of the pins of the 5- or 4-V version or 4.3 V to
any of the pins (except port A) of the 3-V version
Notes: 1. Power supply voltage for VCC1 pin
Never exceed the maximum rating of VCL in the low-power version (3-V version)
because both the VCC1 and VCL pins are connected to the VCC power supply.
2. It is an operating power supply voltage pin on the chip.
Never apply power supply voltage to the VCL pin in the 5- or 4-V version.
Always connect an external capacitor between the VCL pin and ground for internal
voltage sta bil iza tion.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 804 of 1130
REJ09B0327-0400
26.3.2 DC Characteristics
Table 26.17 lists the DC ch aracteristics. Permitted output current valu es and b us drive
characteristics are shown in tables 26.18 and 26.19, respectively.
Table 26.17 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC*1 = 5.0 V ±10%,
AVref*1 = 4.5 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7
VCCB × 0.7
Schmitt
trigger input
voltage
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–0.4 — —
VT–VCC × 0.3 — — VP67 to P60
(KWUL = 01) VT+——V
CC × 0.7
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —
Schmitt
trigger input
voltage
(in level
switching)*6P67 to P60
(KWUL = 10) VT+——V
CC × 0.8
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —P67 to P60
(KWUL = 11) VT+——V
CC × 0.9
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1,
MD0
(2) VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3
PA7 to PA0*7VCCB × 0.7 — VCCB +0.3
Port 7 2.0 — AVCC +0.3
Input pins except
(1) and (2)
above
2.0 — VCC +0.3
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 805 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97, and
P52*4)*5 *83.5 — — V IOH = –1 mA
P97, P52*42.0 — — V IOH = –200 µA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB –0.5 V
Ports 1 to 3 –IP30 — 300 µA Vin = 0 VInput
pull-up
MOS
current
Ports A*8, B,
Port 6
(P6PUE = 0)
60 — 600 µA
Port 6
(P6PUE = 1) 15 — 200 µA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 806 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
RES (4) Cin — — 80 pF
NMI — — 50 pF
Input
capacitance
P52, P97,
P42, P86
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins except
(4) above — — 15 pF
Normal operation ICC — 55 70 mA f = 20 MHzCurrent
dissipation*9Sleep mode — 36 55 mA f = 20 MHz
Standby mode*10 —1.05.0µAT
a ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC= 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mAReference
power
supply
current
During A/D, D/A
conversion —2.05.0mA
Idle — 0.01 5.0 µA AVref= 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.5 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 807 of 1130
REJ09B0327-0400
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. Port A characteristics depends on VCCB (or on VCC when other pins are in output mode).
9. Current dissipation values are for VIH min = VCC –0.2 V, VCCB –0.2 V, and VIL max = 0.2 V
with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC –0.2 V, VCCB –0.2 V, and VIL max =
0.2 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 808 of 1130
REJ09B0327-0400
Table 26.17 DC Characteristics (2)
Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V,
AVref*1 = 4.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7
VCCB × 0.7 V
VT+ – VT–0.4 — — V
VCC = 4.5 V to
5.5 V,
VCCB = 4.5 V
to 5.5 V
Schmitt
trigger input
voltage
VT–0.8 — — V
VT+——V
CC × 0.7
VCCB × 0.7 V
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–0.3 — — V
VCC = 4.0 V to
4.5 V,
VCCB = 4.0 V
to 4.5 V
VT–VCC × 0.3 — — VP67 to P60
(KWUL = 01) VT+——V
CC × 0.7 VCC = 4.0 V to
5.5 V
VT+ – VT–VCC × 0.05 — —
Schmitt
trigger input
voltage
(in level
switching)*6VT–VCC × 0.4 — —P67 to P60
(KWUL = 10) VT+——V
CC × 0.8
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —P67 to P60
(KWUL = 11) VT+——V
CC × 0.9
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
PA7 to PA0*7VCCB × 0.7 — VCCB + 0.3 V
Port 7 2.0 — AVCC +0.3 V
Input pins
except (1) and
(2) above
2.0 — VCC +0.3 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 809 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0 V VCCB = 4.5 V
to 5.5 V
–0.3 — 0.8 V VCCB = 4.0 V
to 4.5 V
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8 V
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97,
and P52*4)*5 *83.5 — — V IOH = –1 mA,
VCC = 4.5 V to
5.5 V,
VCCB = 4.5 V
to 5.5 V
3.0 — — V IOH = –1 mA,
VCC = 4.0 V to
4.5 V,
VCCB = 4.0 V
o 4.5 V
P97, P52*41.5 — — V IOH = –200 µA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µA
STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Input
leakage
current
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB −0.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 810 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Ports 1 to 3 –IP30 — 300 µA
Ports A*8, B
Port 6
(P6PUE = 0)
60 — 600 µA
Port 6
(P6PUE = 1) 15 — 200
Vin = 0 V,
VCC = 4.5 V to
5.5 V,
VCCB = 4.5 V
to 5.5 V
Input
pull-up
MOS
current
Ports 1 to 3 20 — 200 µA
Ports A*8, B
Port 6
(P6PUE = 0)
40 — 500 µA
Port 6
(P6PUE = 1) 10 — 150
Vin = 0 V,
VCC = 4.0 V to
4.5 V,
VCCB = 4.0 V
to 4.5 V
RES (4) Cin — — 80 pFInput
capacitance NMI — — 50 pF
P52, P97, P42,
P86, PA7 to PA2 — — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation I CC — 45 58 mA f = 16 MHzCurrent
dissipation*9Sleep mode — 30 46 mA f = 16 MHz
Standby mode*10 —1.05.0µAT
a ≤ 50°C
— — 20.0 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.0 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 811 of 1130
REJ09B0327-0400
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
9. Current dissipation values are for VIH min = VCC –0.2 V, VCCB –0.2 V, and VIL max =
0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 4.0 V, VIH min = VCC –0.2 V, VCCB –0.2 V, and VIL max =
0.2 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 812 of 1130
REJ09B0327-0400
Table 26.17 DC Characteristics (3)
Conditions: VCC = 2.7 V to 3.6 V*11, VCCB = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 3.6 V,
AVref = 2.7 V to 3.6 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–VCC × 0.2
VCCB × 0.2 —— V
Schmitt
trigger input
voltage VT+——V
CC × 0.7
VCCB × 0.7 V
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–VCC × 0.05
VCCB ×
0.05
—— V
VT–VCC × 0.3 — — VP67 to P60
(KWUL = 01) VT+——V
CC × 0.7
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —P67 to P60
(KWUL = 10) VT+——V
CC × 0.8
VT+ – VT–VCC × 0.03 — —
Schmitt
trigger input
voltage
(in level
swiching)*6
VT–VCC × 0.45 — —P67 to P60
(KWUL = 11) VT+——V
CC × 0.9
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC × 0.9 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
PA7 to PA0*7VCCB × 0.7 — VCCB +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Input pins
except (1) and
(2) above
VCC × 0.7 — VCC +0.3 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 813 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — VCC × 0.1 V
PA7 to PA0 –0.3 — VCCB × 0.2 V VCCB = 2.7 V
to 4.0 V
0.8 V VCCB = 4.0 V
to 5.5 V
–0.3 — VCC × 0.2 V VCC = 2.7 V to
3.6 V
NMI, EXTAL,
input pins except
(1) and (3)
above
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97,
and P52*4)*5 *8VCC –1.0
VCCB –1.0 —— VI
OH = –1 mA
(VCC = 2.7 V
to 3.6 V,
VCCB = 2.7 V
to 4.0 V)
P97, P52*40.5 — — V IOH = –200 µA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 5 mA
RESO ——0.4VI
OL = 1.6 mA
RES Iin— — 10.0 µA
STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Input
leakage
current
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB –0.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 814 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Ports 1 to 3 –IP5 — 150 µAInput pull-
up MOS
current Ports A*8, B
Port 6 (P6PUE =
0)
30 — 300 µA
Port 6 (P6PUE =
1) 3 — 100 µA
Vin = 0 V,
VCC = 2.7 V to
3.6 V,
VCCB = 2.7 V
to 3.6 V
Input
capacitance RES (4) Cin — — 80 pF
NMI — — 50 pF
P52, P97,
P42, P86,
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation ICC — 30 40 mA f = 10 MHzCurrent
dissipation*9Sleep mode — 20 32 mA f = 10 MHz
Standby mode*10 —1.05.0µAT
a ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 3.6 V
During A/D conversion Alref —0.51.0mAReference
power
supply
current
During A/D, D/A
conversion —2.05.0mA
Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 2.7 — 3.6 V Operating
2.0 — 3.6 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 815 of 1130
REJ09B0327-0400
4. In the H8S/2148 Group, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2148 Group, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
9. Current dissipation values are for VIH min = VCC –0.2 V, VCCB –0.2 V, and VIL max =
0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC –0.2 V, VCCB –0.2 V, and VIL max =
0.2 V.
11.For flash memory program/erase operations, the applicable ranges are VCC = 3.0 V to
3.6 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 816 of 1130
REJ09B0327-0400
Table 26.18 Permiss ible Output Currents
Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) SCL1, SCL0, SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4 (bus drive
function se lec ted)
IOL ——20mA
Ports 1, 2, 3 — — 10 mA
RESO ——3 mA
Other output pi ns — — 2 mA
Total of ports 1, 2, and 3 ∑ IOL ——80mAPermissible output
low current (total) Total of all output pins,
including the above — — 120 mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——40mA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 817 of 1130
REJ09B0327-0400
Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) SCL1, SCL0, SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4 (bus drive
function se lec ted)
IOL ——10mA
Ports 1, 2, 3 — — 2 mA
RESO ——1 mA
Other output pi ns — — 1 mA
Total of ports 1, 2, and 3 ∑ IOL ——40mAPermissible output
low current (total) Total of all output pins,
including the above ——60mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——30mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 26.18.
2. When driving a Darlington pair or LED, alwa ys ins ert a current-limiting resistor in the
output line, as show in figure s 26.1 and 26.2 .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 818 of 1130
REJ09B0327-0400
Table 26.19 Bus Drive Characteristics
Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V
Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected)
Item Symbol Min Typ Max Unit Test Conditions
VT–VCC × 0.3 — — VSchmitt trigger
input voltage VT+——V
CC × 0.7
VT+ – VT–VCC × 0.05 — —
Input high voltage VIH VCC × 0.7 — VCC +0.5 V
Input low voltage VIL –0.5 — VCC × 0.3
Output low voltage VOL ——0.8VI
OL = 16 mA,
VCC = 4.5 V to 5.5 V
——0.5 I
OL = 8 mA
——0.4 I
OL = 3 mA
Input capacitan ce Cin — — 20 pF Vin = 0 V, f = 1 MHz,
Ta = 25°C
Three-state leakage
current (off state) | ITSI | — — 1.0 µA Vin = 0.5 to VCC –0.5 V
SCL, SDA output
fall time tOf 20 + 0.1 Cb — 250 ns
Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VCCB = 2.7 V to 5.5 V,
VSS = 0 V
Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive
function selected)
Item Symbol Min Typ Max Unit Test Conditions
Output low voltage VOL ——0.8VI
OL = 16 mA,
VCCB = 4.5 V to 5.5 V
——0.5 I
OL = 8 mA
——0.4 I
OL = 3 mA
26.3.3 AC Characteristics
Clock timing, control signal timing, bus timing, and timing of on-chip supporting modules list the
following.
Figure 26.4 shows the test conditions for th e AC character istics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 819 of 1130
REJ09B0327-0400
(1) Clock Timing
Table 26.20 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and exter nal clock input (EXTAL pin) oscillation settling times.
For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock
Pulse Generator.
Table 26.20 Clock Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 50 500 62.5 500 100 500 ns Figure 26.5
Clock high pulse
width tCH 17 — 20 — 30 — ns Figure 26.5
Clock low pulse
width tCL 17 — 20 — 30 — ns
Clock rise time tCr —8 —10 —20 ns
Clock fall time tCf —8 —10 —20 ns
Oscillati on sett ling
time at reset
(crystal)
tOSC1 10 — 10 — 20 — ms Figure 26.6
Oscillati on sett ling
time in software
standby (cr ysta l)
tOSC2 8—8— 8— msFigure 26.7
External clock
output stabilization
delay time
tDEXT 500 — 500 — 500 — µs
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 820 of 1130
REJ09B0327-0400
(2) Control Signal Timing
Table 26.21 shows the control signal timing. The only external interrupts that can operate on the
subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7.
Table 26.21 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
RES setup time tRESS 200 — 200 — 300 — ns Figure 26.8
RES pulse width tRESW 20 — 20 — 20 — tcyc
NMI setup time
(NMI) tNMIS 150 — 150 — 250 — ns Figure 26.9
NMI hold time
(NMI) tNMIH 10 — 10 — 10 —
NMI pulse width
(exiting sof t war e
standby mode)
tNMIW 200 — 200 — 200 — ns
IRQ setup time
(IRQ7 to IRQ0)tIRQS 150 — 150 — 250 — ns
IRQ hold time
(IRQ7 to IRQ0)tIRQH 10 — 10 — 10 — ns
IRQ pulse width
(IRQ7, IRQ6,
IRQ2 to IRQ0)
(exiting sof t war e
standby mode)
tIRQW 200 — 200 — 200 — ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 821 of 1130
REJ09B0327-0400
(3) Bus Timing
Table 26.22 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (φ = 32.768 kHz).
Table 26.22 Bus Timing (1) (Nomal mode)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Address
delay time tAD —20 —30 —40 ns
Address
setup time tAS 0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —0.5 ×
tcyc –30 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD —20 —30 —40 ns
AS delay
time tASD —30 —45 —60 ns
RD delay
time 1 tRSD1 —30 —45 —60 ns
RD delay
time 2 tRSD2 —30 —45 —60 ns
Read data
setup time tRDS 15 — 20 — 35 — ns
Read data
hold time tRDH 0— 0— 0— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 822 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Read data
access
time 1
tACC1 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —1.0 ×
tcyc –60 ns Figure 26.10
to
figure 26.14
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –35 —1.5 ×
tcyc –50 ns
Read data
access
time 3
tACC3 —2.0 ×
tcyc –30 —2.0 ×
tcyc –40 —2.0 ×
tcyc –60 ns
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –35 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –30 —3.0 ×
tcyc –40 —3.0 ×
tcyc –60 ns
WR delay
time 1 tWRD1 —30 —45 —60 ns
WR delay
time 2 tWRD2 —30 —45 —60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –30 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD —30 —45 —60 ns
Write data
setup time tWDS 0— 0— 0— ns
Write data
hold time tWDH 10 — 15 — 20 — ns
WAIT
setup time tWTS 30 — 45 — 60 — ns
WAIT hold
time tWTH 5— 5— 10— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 823 of 1130
REJ09B0327-0400
Table 26.22 Bus Timing (2) (Advanced mode)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Address
delay time tAD —30 —45 —60 ns
Address
setup time tAS 0.5 ×
tcyc –25 —0.5 ×
tcyc –35 —0.5 ×
tcyc –50 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD —30 —45 —60 ns
AS delay
time tASD —30 —45 —60 ns
RD delay
time 1 tRSD1 —30 —45 —60 ns
RD delay
time 2 tRSD2 —30 —45 —60 ns
Read data
setup time tRDS 15 — 20 — 35 — ns
Read data
hold time tRDH 0— 0— 0— ns
Read data
access
time 1
tACC1 —1.0 ×
tcyc –40 —1.0 ×
tcyc –55 —1.0 ×
tcyc –80 ns
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –35 —1.5 ×
tcyc –50 ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 824 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Read data
access
time 3
tACC3 —2.0 ×
tcyc –40 —2.0 ×
tcyc –55 —2.0 ×
tcyc –80 ns Figure 26.10
to
figure 26.14
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –35 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –40 —3.0 ×
tcyc –55 —3.0 ×
tcyc –80 ns
WR delay
time 1 tWRD1 —30 —45 —60 ns
WR delay
time 2 tWRD2 —30 —45 —60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –30 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD —30 —45 —60 ns
Write data
setup time tWDS 0— 0— 0— ns
Write data
hold time tWDH 10 — 15 — 20 — ns
WAIT
setup time tWTS 30 — 45 — 60 — ns
WAIT hold
time tWTH 5— 5— 10— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 825 of 1130
REJ09B0327-0400
(4) Timing of On-Chip Supporting Modules
Tables 26.23 to 26.25 show the on-chip supporting module timing. The only on-chip supporting
modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external
interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and
1).
Table 26. 23 Timing of On- C hip Supporting Modules (1 )
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
I/O
ports Output data delay
time tPWD — 50 — 50 — 100 ns Figure
26.15
Input data setup
time tPRS 30 — 30 — 50 —
Input data hold
time tPRH 30 — 30 — 50 —
FRT Timer output de lay
time tFTOD — 50 — 50 — 100 ns Figure
26.16
Timer input setup
time tFTIS 30 — 30 — 50 —
Timer clock input
setup time tFTCS 30 — 30 — 50 — Figure
26.17
Single
edge tFTCWH 1.5 — 1.5 — 1.5 — tcyc
Timer
clock
pulse
width Both
edges tFTCWL 2.5 —2.5 —2.5—
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 826 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
TMR Timer output
delay time tTMOD — 50 — 50 — 100 ns Figure
26.18
Timer reset input
setup time tTMRS 30 —30 — 50 — Figure
26.20
Timer clock input
setup time tTMCS 30 — 30 — 50 — Figure
26.19
Single
edge tTMCWH 1.5 — 1.5 — 1.5 —tcyc
Timer
clock
pulse
width Both
edges tTMCWL 2.5 — 2.5 — 2.5 —
PWM,
PWMX Pulse output
delay time tPWOD — 50 — 50 — 100 ns Figure
26.21
SCI Asynchro-
nous tScyc 4— 4—4— t
cyc Figure
26.22
Input
clock
cycle Synchro-
nous 6— 6— 6—
Input clock pulse
width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc
Input clock rise
time tSCKr — 1.5 — 1.5 — 1.5 tcyc
Input clock fall
time tSCKf — 1.5 — 1.5 — 1.5
Transmit data
delay time
(synchronous)
tTXD — 50 — 50 — 100 ns Figure
26.23
Receive data set up
time (synchronous) tRXS 50 — 50 — 100 — ns
Receive data hol d
time (synchronous) tRXH 50 — 50 — 100 — ns
A/D
conver-
ter
Trigger input setup
time tTRGS 30 — 30 — 50 — ns Figure
26.24
WDT RESO output delay
time tRESD — 100 — 120 — 200 ns Figure
26.25
RESO output pulse
width tRESOW 132 — 132 — 132 — tcyc
Note: *Only supporting modules that can be used in subc lock operation
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 827 of 1130
REJ09B0327-0400
Table 26. 23 Timing of On- C hip Supporting Modules (2 )
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
HIF read
cycle CS/HA0 setup
time tHAR 10 — 10 — 10 — ns Figure
26.26
CS/HA0 hold time tHRA 10 — 10 — 10 — ns
IOR pulse width tHRPW 120 — 120 — 220 — ns
HDB delay time tHRD — 100 — 100 — 200 ns
HDB hold time t HRF 025 025040ns
HIRQ delay time tHIRQ — 120 — 120 — 200 ns
HIF writ e
cycle CS/HA0 setup
time tHAW 10 — 10 — 10 — ns
CS/HA0 hold time tHWA 10 — 10 — 10 — ns
IOW pulse width tHWPW 60 — 60 — 100 — ns
HDB
setup
time
Fast A20
gate not
used
tHDW 30 — 30 — 50 — ns
Fast A20
gate used 45 — 55 — 85 — ns
HDB hold time t HWD 15 — 15 — 25 — ns
GA20 delay time tHGA — 90 — 90 — 180 ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 828 of 1130
REJ09B0327-0400
Table 26.24 Keyboard Buffer Controller Timing
Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VCCB = 2.7 V to 5.5 V,
VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C
Ratings
Item Symbol Min Typ Max Unit Test
Conditions Notes
KCLK, KD output
fall time tKBF 20 + 0.1 Cb — 250 ns Figure 26.27
KCLK, KD input
data hold time tKBIH 150 — — ns
KCLK, KD input
data setup time tKBIS 150 — — ns
KCLK, KD output
delay time tKBOD — — 450 ns
KCLK, KD
capacitive load Cb— — 400 pF
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 829 of 1130
REJ09B0327-0400
Table 26.25 I2C Bus Timing
Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V,
φ = 5 MHz to maximum operating frequency
Ratings
Item Symbol Min Typ Max Unit Test Conditions Notes
SCL input cycle
time tSCL 12 — — tcyc Figure 26.28
SCL input high
pulse width tSCLH 3——t
cyc
SCL input low
pulse width tSCLL 5——t
cyc
SCL, SDA input
rise time tSr ——7.5
*tcyc
SCL, SDA input
fall time tSf — — 300 ns
SCL, SDA output
fall time tof 20 + 0.1 Cb — 250 ns
SCL, SDA input
sp ike pulse
elimination time
tSP ——1t
cyc
SDA input bus
free time tBUF 5——t
cyc
Start condition
input hold time tSTAH 3——t
cyc
Retransmission
start condit ion
input setup time
tSTAS 3——t
cyc
Stop condition
input setup time tSTOS 3——t
cyc
Data input setup
time tSDAS 0.5 — — tcyc
Data input hold
time tSDAH 0——ns
SCL, SDA
capacitive load Cb— — 400 pF
Note: *17.5tcyc can be set according to the clock selected for use by the I2C module. For details,
see section 16.4, Usage Notes.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 830 of 1130
REJ09B0327-0400
26.3.4 A/D Conversion Characteristics
Tables 26.26 and 26.27 list the A/D conversion characteristics.
Table 26.26 A/D Conversion Characteristics
(AN7 to AN0 Input: 134/266-St ate Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*3——6.7 ——8.4 ——13.4µs
Analog input
capacitance ——20 ——20 ——20 pF
——10
*1——10
*1——5 kΩPermissible signal-
source impedance 5*25*2
Nonlinearity error — — ±3.0 — — ±3.0 — — ±7.0 LSB
Offset error ——±3.5——±3.5——±7.5LSB
Full-scale error — — ± 3. 5 — — ±3.5 — — ±7.5 LSB
Quantization error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy——±4.0——±4.0——±8.0LSB
Notes: 1. When conver sio n time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
2. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
3. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 831 of 1130
REJ09B0327-0400
Table 26.27 A/D Conversion Characteristics
(CIN15 to CIN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 3.6 V*4, AVCC = 3.0 V to 3.6 V*4, AVref = 3.0 V to AVCC*4,
VCCB = 3.0 V to 5.5 V*4, VSS = AVSS = 0 V,
φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*3——6.7 ——8.4 ——13.4µs
Analog input
capacitance ——20 ——20 ——20 pF
——10
*1——10
*1——5 kΩPermissible signal-
source impedance 5*25*2
Nonlinearity error — — ±5.0 — — ±5.0 — — ±11.0 LSB
Offset error — — ±5.5 — — ±5. 5 — — ±11.5 LS B
Full-scale error — — ± 5. 5 — — ±5.5 — — ±11.5 LSB
Quantization error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy——±6.0——±6.0——±12.0LSB
Notes: 1. When conver sio n time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
2. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
3. In single mode and φ = maximum operating frequency.
4. When using CIN, the applicable range is VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V,
AVref = 3.0 V to 3.6 V, and VCCB = 3.0 V to 5.5 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 832 of 1130
REJ09B0327-0400
26.3.5 D/A Conversion Characteristics
Table 26.28 lists the D/A conversion characteristics.
Table 26.28 D/A Conversion Characteristics
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 888 888 888 Bits
Conversion
time With 20-pF
load
capacitance
——10 ——10 ——10 µs
Absolute
accuracy With 2-MΩ
load
resistance
— ±1.0 ±1.5 — ±1.0 ±1.5 — ±2.0 ±3.0 LSB
With 4-MΩ
load
resistance
——±1.0——±1.0——±2.0
26.3.6 Flash Memory Characteristics
Table 26.29 shows the flash memory characteristics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 833 of 1130
REJ09B0327-0400
Table 26.29 Flash Memory Characteristics (Programming/erasing operating range)
Conditions (5 V version): VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
(3 V version): VCC = 3.0 V to 3.6V, VSS = 0 V, Ta = –20 t o 75°C
Item Symbol Min Typ Max Unit Test
Condition
Programming time*1 *2 *4tP — 10 200 ms/
128 bytes
Erase time*1 *3 *6tE — 100 1200 ms/
block
Reprogramming count NWEC 100*810000*9—Times
Data retention time*10 tDRP 10 — — Years
Programming Wai t time after SWE-bit setting*1x1——µs
Wait time after PSU-bit setting*1y50——µs
z1 28 30 32 µs 1 ≤ n ≤ 6Wait time after P-bit setting*1 *4
z2 198 200 202 µs 7 ≤ n ≤ 1000
z3 8 10 12 µs Additional
writing
Wait time after P-bit clear*1α5——µs
Wait time after PSU-bit clear*1β5——µs
Wait time after PV-bit setting*1γ4——µs
Wait time after dummy write*1ε2——µs
Wait time after PV-bit clear*1η2——µs
Wait time after SWE-bit clear*1θ100 — — µs
Maximum programming
count*1 *4 *5N — — 1000 Times
Erase Wait time after SWE-bit setting*1x1——µs
Wait time after ESU-bit setting*1y 100 — — µs
Wait time after E-bit setting*1 *6z 10 — 100 ms
Wait time after E-bit clear*1α10 — — µs
Wait time after ESU-bit clear*1β10 — — µs
Wait time after EV-bit setting*1γ20 — — µs
Wait time after H'FF dummy
write*1ε2——µs
Wait time after EV-bit clear*1η4——µs
Wait time after SWE-bit clear*1θ100 — — µs
Maximum erase count*1 *6 *7N — — 120 Times
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 834 of 1130
REJ09B0327-0400
Notes: 1. Set the times according to the program /era se alg orithm s .
2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time .)
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximu m programming time (tP (max))
tP(max) = (Wait time after P-bit setting (z1) + (z3)) × 6 + Wait time after P-bit setting (z2)
× ((N) – 6)
5. Maximum programming count (N) should be set according to the actual set value of (z1,
z2, z3) to allow programming within the maximum programming time (tP(max)). The
wait time after P-bit setting (z1, z2, z3) must be changed with the value of the number
of writing times (n) as follows.
The number of times for writing n
1 ≤ n ≤ 6 z1 = 30 µs, z3 = 10 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE(max) = Waiting time after E-bit setting (z) × Maximu m eras e count (N)
7. Maximum erase count (N) should be set according to the actual setting (z) to allow
erase within the maximum erase time (tE(max)).
8. Minimum number of times for which all characteristics are guaranteed after rewriting
(Guarantee range is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should normally function up to this
value).
10.Data retention characteristic when rewriting is performed within the specification range,
including the minimum value.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 835 of 1130
REJ09B0327-0400
26.3.7 Usage Note
(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference
values for electrical characteristics shown in this manual. However, actual performance
figures, operating margins, noise margins, and other properties may vary due to differences in
the manufacturing process, on-chip ROM, layout patterns, etc.
When system ev aluation testing is car ried out using the F-ZTAT version, the same evaluation
tests should also be conducted for the mask ROM version when ch anging over to that version.
(2) On-chip power supply step-down circuit
The following products incorporate an internal power supply step-down circuit, which
automatically drops down the inter nal power supply voltage to the optimum internal voltage
level: the F-ZTAT A-mask versions of the H8S/2148, H8S/2147, and H8S/2144
(HD64F2148A, HD64F2147A, and HD64F2144A) and the mask ROM versions of the
H8S/2148, H8S/2147, H8S/2144, and H8S/2143 (HD6432148S, HD6432148SW,
HD6432147S, HD6432147SW, HD6432144S, and HD6432143S).
The voltage- stabilization capacitor (0.47 µF one or two connected in group) must be connected
between the VCL (internal power supply step-down) and VSS pins.
Figure 26.3 shows the connection of the external capacitors.
For the 5- or 4-V version whose power supply (VCC) voltage exceeds 3.6 V, do not connect the
VCL pin in a product incorporating an internal step-down circuit to the VCC power supply.
(Connect the VCC1 pin to the VCC power supply as usual.)
For the 3-V version whose power supply (VCC) voltage is 3.6 V or lower, connect both the
VCL and VCC1 pins to the system power supply.
When changing from the F-ZTAT versions not incorporating an internal step-down circuit to
the F-ZTAT A-mask versions or mask ROM versions incorporating an internal step-down
circuit, the VCL pin has the same pin location as the VCC2 pin. Therefore, note that the circuit
patterns differ between these two types of products.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 836 of 1130
REJ09B0327-0400
26.4 Electrical Characteristics of H8S/2147N F-ZTAT
26.4.1 Absolute Maximum Ratings
Table 26.30 lists th e absolute maximum ratings.
Table 26.30 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage*VCC –0.3 to +7.0 V
Input/output buffer pow er sup ply
(power supply for the port A) VCCB –0.3 to +7.0 V
Input voltage (except ports 6, 7,
and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port 6) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port A) Vin –0.3 to VCCB +0.3 V
Input voltage (CIN input selected
for port 6) Vin –0.3 V to lower of voltages VCC +0.3 and
AVCC +0.3 V
Input voltage (CIN input selected
for port A) Vin –0.3 V to lower of voltages VCCB +0.3 and
AVCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Reference supply voltage AVref –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Operating temperature (flash
memory programming/erasing) Topr Regular specifications: 0 to +75 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Note: *Power supply voltage for VCC1 and VCC2 pins .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 837 of 1130
REJ09B0327-0400
26.4.2 DC Characteristics
Table 26.31 lists the DC characteristics. Permitted o utput current values and bus drive
characteristics are shown in tables 26.32 and 26.33, respectively.
Table 26.31 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, AVCC*1 = 5.0 V ±10%,
AVref*1 = 4.5 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*11
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — VSchmitt
trigger input
voltage VT+——V
CC × 0.7
VCCB × 0.7
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–0.4 — —
VT–VCC × 0.3 — — V
VT+——V
CC × 0.7
P67 to P60
(KWUL = 01)
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —
Schmitt
trigger input
voltage
(in level
switching)*6
VT+——V
CC × 0.8
P67 to P60
(KWUL = 10)
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —
VT+——V
CC × 0.9
P67 to P60
(KWUL = 11)
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3
PA7 to PA0*7VCCB × 0.7 — VCCB +0.3
Port 7 2.0 — AVCC +0.3
Input pins except
(1) and (2)
above
2.0 — VCC +0.3
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 838 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97, and
P52*4)*5 *83.5 — — V IOH = –1 mA
P97, P52*42.5 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB –0.5 V
Ports 1 to 3 –IP50 — 300 µA Vin = 0 VInput
pull-up
MOS
current
Ports A*8, B,
Port 6
(P6PUE = 0)
60 — 500 µA
Port 6
(P6PUE = 1) 15 — 150 µA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 839 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
RES (4) Cin — — 80 pFInput
capacitance NMI — — 50 pF
P52, P97,
P42, P86
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins except
(4) above — — 15 pF
Normal operation ICC — 75 100 mA f = 20 MHzCurrent
dissipation*9Sleep mode — 60 85 mA f = 20 MHz
Standby mode*10 — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC= 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mAReference
power
supply
current
During A/D, D/A
conversion —2.05.0mA
Idle — 0.01 5.0 µA AVref= 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.5 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. In the H8S/2147N, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2147N, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 840 of 1130
REJ09B0327-0400
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. Port A characteristics depends on VCCB (or on VCC when other pins are in output mode).
9. Current dissipation values are for VIH min = VCC –0.5 V, VCCB –0.5 V, and VIL max = 0.5 V
with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC × 0.9, VCCB × 0.9, and VIL max =
0.3 V.
11.For flash memory program/erase operations, the applicable range is Ta = 0 to +75°C
(regular specifications).
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 841 of 1130
REJ09B0327-0400
Table 26.31 DC Characteristics (2)
Conditions: VCC = 3.0 V to 5.5 V*11, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 5.5 V,
AVref = 3.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*11
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–VCC × 0.2
VCCB × 0.2 —— V
Schmitt
trigger input
voltage VT+——V
CC × 0.7
VCCB × 0.7 V
P67 to
P60(KWUL =
00)*2 *6,
KIN15 to
KIN8*7 *8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+ – VT–V
CC
× 0.05
VCCB ×
0.05
—— V
VT–VCC × 0.3 — — VP67 to P60
(KWUL = 01) VT+——V
CC × 0.7
VT+ – VT–VCC × 0.05 — —
VT–VCC × 0.4 — —P67 to P60
(KWUL = 10) VT+——V
CC × 0.8
Schmitt
trigger input
voltage
(in level
swiching)*6
VT+ – VT–VCC × 0.03 — —
VT–VCC × 0.45 — —P67 to P60
(KWUL = 11) VT+——V
CC × 0.9
VT+ – VT–0.05 — —
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC × 0.9 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
PA7 to PA0*7VCCB × 0.7 — VCCB +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Input pins
except (1) and
(2) above
VCC × 0.7 — VCC +0.3 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 842 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — VCC × 0.1 V
PA7 to PA0 –0.3 — VCCB × 0.2 V VCCB = 3.0 V
to 4.0 V
0.8 V VCCB = 4.0 V
to 5.5 V
–0.3 — VCC × 0.2 V VCC = 3.0 V to
4.0 V
NMI, EXTAL,
input pins except
(1) and (3)
above 0.8 V VCC = 4.0 V to
5.5 V
Output high
voltage VOH VCC –0.5
VCCB –0.5 —— VI
OH = –200 µAAll output pins
(except P97,
and P52*4)*5 *8VCC –1.0
VCCB –1.0 —— VI
OH = –1 mA
(VCC = 3.0 V
to 4.0 V, VCCB
= 3.0 V to
4.0 V)
P97, P52*41.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*5VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 5 mA
(VCC < 4.0 V),
IOL = 10 mA
(4.0 V ≤ VCC ≤
5.5 V)
RESO ——0.4VI
OL = 1.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A*8, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V,
Vin = 0.5 to
VCCB –0.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 843 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Ports 1 to 3 –IP10 — 150 µAInput pull-
up MOS
current Ports A*8, B
Port 6
(P6PUE = 0)
30 — 250 µA
Port 6
(P6PUE = 1) 3 — 70 µA
Vin = 0 V,
VCC = 3.0 V to
3.6 V,
VCCB = 3.0 V
to 3.6 V
RES (4) Cin — — 80 pF
NMI — — 50 pF
Input
capacitance
P52, P97,
P42, P86,
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation ICC — 45 60 mA f = 10 MHzCurrent
dissipation*9Sleep mode — 35 50 mA f = 10 MHz
Standby mode*10 — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mAReference
power
supply
current
During A/D, D/A
conversion —2.05.0mA
Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 3.0 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 844 of 1130
REJ09B0327-0400
4. In the H8S/2147N, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
In the H8S/2147N, P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
6. The upper limit of the port 6 applied voltage is VCC +0.3 V when CIN input is not
selected, and the lower of VCC +0.3 V and AVCC +0 .3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
7. The upper limit of the port A applied voltage is VCCB +0.3 V when CIN input is not
selected, and the lower of VCCB +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
8. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
9. Current dissipation values are for VIH min = VCC –0.5 V, VCCB –0.5 V, and VIL max =
0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state.
10.The values are for VRAM ≤ VCC < 3.0 V, VIH min = VCC × 0.9, VCCB × 0.9, and VIL max =
0.3 V.
11.For flash memory program/erase operations, the applicable ranges are VCC = 3.0 V to
3.6 V and Ta = 0 to +75°C.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 845 of 1130
REJ09B0327-0400
Table 26.32 Permiss ible Output Currents
Conditions: VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) SCL1, SCL0, SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4 (bus drive
function se lec ted)
IOL ——20mA
Ports 1, 2, 3 — — 10 mA
RESO ——3 mA
Other output pi ns — — 2 mA
Total of ports 1, 2, and 3 ∑ IOL ——80mAPermissible output
low current (total) Total of all output pins,
including the above — — 120 mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——40mA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 846 of 1130
REJ09B0327-0400
Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) SCL1, SCL0, SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4 (bus drive
function se lec ted)
IOL ——10mA
Ports 1, 2, 3 — — 2 mA
RESO ——1 mA
Other output pi ns — — 1 mA
Total of ports 1, 2, and 3 ∑ IOL ——40mAPermissible output
low current (total) Total of all output pins,
including the above ——60mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——30mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 26.32.
2. When driving a Darlington pair or LED, alwa ys ins ert a current-limiting resistor in the
output line, as show in figure s 26.1 and 26.2 .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 847 of 1130
REJ09B0327-0400
Table 26.33 Bus Drive Characteristics
Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V
Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected)
Item Symbol Min Typ Max Unit Test Conditions
VT–VCC × 0.3 — — V VCC = 3.0 V to 5.5 VSchmitt trigger
input voltage VT+——V
CC × 0.7 VCC = 3.0 V to 5.5 V
VT+ – VT–VCC × 0.05 — — VCC = 3.0 V to 5.5 V
Input high voltage VIH VCC × 0.7 — VCC +0.5 V VCC = 3.0 V to 5.5 V
Input low voltage VIL –0.5 — VCC × 0.3 VCC = 3.0 V to 5.5 V
Output low voltage VOL ——0.8VI
OL = 16 mA,
VCC = 4.5 V to 5.5 V
——0.5 I
OL = 8 mA
——0.4 I
OL = 3 mA
Input capacitan ce Cin — — 20 pF Vin = 0 V, f = 1 MHz,
Ta = 25°C
Three-state leakage
current (off state) | ITSI | — — 1.0 µA Vin = 0.5 to VCC –0.5 V
SCL, SDA output
fall time tOf 20 + 0.1 Cb — 250 ns VCC = 3.0 V to 5.5 V
Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V
Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive
function selected)
Item Symbol Min Typ Max Unit Test Conditions
Output low voltage VOL ——0.8VI
OL = 16 mA,
VCCB = 4.5 V to 5.5 V
——0.5 I
OL = 8 mA
——0.4 I
OL = 3 mA
26.4.3 AC Characteristics
Clock timing, control signal timing, bus timing, and timing of on-chip supporting modules list the
following.
Figure 26.4 shows the test conditions for th e AC character istics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 848 of 1130
REJ09B0327-0400
(1) Clock Timing
Table 26.34 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and exter nal clock input (EXTAL pin) oscillation settling times.
For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock
Pulse Generator.
Table 26.34 Clock Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 50 500 100 500 ns Figure 26.5
Clock high pulse
width tCH 17 — 30 — ns Figure 26.5
Clock low pulse
width tCL 17 — 30 — ns
Clock rise time tCr —8 —20 ns
Clock fall time tCf —8 —20 ns
Oscillati on sett ling
time at reset
(crystal)
tOSC1 10 — 20 — ms Figure 26.6
Figure 26.7
Oscillati on sett ling
time in software
standby (cr ysta l)
tOSC2 8— 8—ms
External clock
output stabilization
delay time
tDEXT 500 — 500 — µs
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 849 of 1130
REJ09B0327-0400
(2) Control Signal Timing
Table 26.35 shows the control signal timing. The only external interrupts that can operate on the
subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7.
Table 26.35 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
RES setup time tRESS 200 — 300 — ns Figure 26.8
RES pulse width tRESW 20 — 20 — tcyc
NMI setup time
(NMI) tNMIS 150 — 250 — ns Figure 26.9
NMI hold time
(NMI) tNMIH 10 — 10 — ns
NMI pulse width
(exiting sof t war e
standby mode)
tNMIW 200 — 200 — ns
IRQ setup time
(IRQ7 to IRQ0)tIRQS 150 — 250 — ns
IRQ hold time
(IRQ7 to IRQ0)tIRQH 10 — 10 — ns
IRQ pulse width
(IRQ7, IRQ6,
IRQ2 to IRQ0)
(exiting sof t war e
standby mode)
tIRQW 200 — 200 — ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 850 of 1130
REJ09B0327-0400
(3) Bus Timing
Table 26.36 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (φ = 32.768 kHz).
Table 26.36 Bus Timing (1) (Nomal mode)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Address
delay time tAD — 20 — 40 ns
Address
setup time tAS 0.5 ×
tcyc –15 —0.5 ×
tcyc –30 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD — 20 — 40 ns
AS delay
time tASD — 30 — 60 ns
RD delay
time 1 tRSD1 — 30 — 60 ns
RD delay
time 2 tRSD2 — 30 — 60 ns
Read data
setup time tRDS 15 — 35 — ns
Read data
hold time tRDH 0— 0—ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 851 of 1130
REJ09B0327-0400
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Read data
access
time 1
tACC1 —1.0 ×
tcyc –30 —1.0 ×
tcyc –60 ns Figure 26.10
to
figure 26.14
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –50 ns
Read data
access
time 3
tACC3 —2.0 ×
tcyc –30 —2.0 ×
tcyc –60 ns
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –30 —3.0 ×
tcyc –60 ns
WR delay
time 1 tWRD1 — 30 — 60 ns
WR delay
time 2 tWRD2 — 30 — 60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD — 30 — 60 ns
Write data
setup time tWDS 0— 0—ns
Write data
hold time tWDH 10 — 20 — ns
WAIT
setup time tWTS 30 — 60 — ns
WAIT hold
time tWTH 5—10— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 852 of 1130
REJ09B0327-0400
Table 26.36 Bus Timing (2) (Advanced mode)
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Address
delay time tAD — 30 — 60 ns
Address
setup time tAS 0.5 ×
tcyc –25 —0.5 ×
tcyc –50 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD — 30 — 60 ns
AS delay
time tASD — 30 — 60 ns
RD delay
time 1 tRSD1 — 30 — 60 ns
RD delay
time 2 tRSD2 — 30 — 60 ns
Read data
setup time tRDS 15 — 35 — ns
Read data
hold time tRDH 0— 0—ns
Read data
access
time 1
tACC1 —1.0 ×
tcyc –40 —1.0 ×
tcyc –80 ns
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –50 ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 853 of 1130
REJ09B0327-0400
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Read data
access
time 3
tACC3 —2.0 ×
tcyc –40 —2.0 ×
tcyc –80 ns Figure 26.10
to
figure 26.14
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –40 —3.0 ×
tcyc –80 ns
WR delay
time 1 tWRD1 — 30 — 60 ns
WR delay
time 2 tWRD2 — 30 — 60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD — 30 — 60 ns
Write data
setup time tWDS 0— 0—ns
Write data
hold time tWDH 10 — 20 — ns
WAIT
setup time tWTS 30 — 60 — ns
WAIT hold
time tWTH 5—10— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 854 of 1130
REJ09B0327-0400
(4) Timing of On-Chip Supporting Modules
Tables 26.37 to 26.39 show the on-chip supporting module timing. The only on-chip supporting
modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external
interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and
1).
Table 26. 37 Timing of On- C hip Supporting Modules (1 )
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
I/O
ports Output data delay
time tPWD — 50 — 100 ns Figure
26.15
Input data setup
time tPRS 30 — 50 —
Input data hold
time tPRH 30 — 50 —
FRT Timer output delay
time tFTOD — 50 — 100 ns Figure
26.16
Timer input setup
time tFTIS 30 — 50 —
Timer clock input
setup time tFTCS 30 — 50 — Figure
26.17
Single
edge tFTCWH 1.5 —1.5—t
cyc
Timer
clock
pulse
width Both
edges tFTCWL 2.5 — 2.5 —
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 855 of 1130
REJ09B0327-0400
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
TMR Timer output
delay time tTMOD — 50 — 100 ns Figure
26.18
Timer reset input
setup time tTMRS 30 — 50 — Figure
26.20
Timer clock input
setup time tTMCS 30 — 50 — Figure
26.19
Single
edge tTMCWH 1.5 — 1.5 — tcyc
Timer
clock
pulse
width Both
edges tTMCWL 2.5 — 2.5 —
PWM,
PWMX Pulse output
delay time tPWOD — 50 — 100 ns Figure
26.21
SCI Asynchro-
nous tScyc 4— 4— t
cyc Figure
26.22
Input
clock
cycle Synchro-
nous 6— 6—
Input clock pulse
width tSCKW 0.4 0.6 0.4 0.6 tScyc
Input clock rise
time tSCKr — 1.5 — 1.5 tcyc
Input clock fall
time tSCKf — 1.5 — 1.5
Transmit data
delay time
(synchronous)
tTXD — 50 — 100 ns Figure
26.23
Receive data set up
time (synchronous) tRXS 50 — 100 — ns
Receive data hol d
time (synchronous) tRXH 50 — 100 — ns
A/D
conver-
ter
Trigger input setup
time tTRGS 30 — 50 — ns Figure
26.24
WDT RESO output delay
time tRESD — 100 — 200 ns Figure
26.25
RESO output pulse
width tRESOW 132 — 132 — tcyc
Note: *Only supporting modules that can be used in subc lock operation
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 856 of 1130
REJ09B0327-0400
Table 26. 37 Timing of On- C hip Supporting Modules (2 )
Condition A: VCC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
HIF read
cycle CS/HA0 setup
time tHAR 10 — 10 — ns Figure
26.26
CS/HA0 hold time tHRA 10 — 10 — ns
IOR pulse width tHRPW 120 — 220 — ns
HDB delay time tHRD — 100 — 200 ns
HDB hold time t HRF 0 25 0 40 ns
HIRQ delay time tHIRQ — 120 — 200 ns
HIF writ e
cycle CS/HA0 setup
time tHAW 10 — 10 — ns
CS/HA0 hold time tHWA 10 — 10 — ns
IOW pulse width tHWPW 60 — 100 — ns
HDB
setup
time
Fast A20
gate not
used
tHDW 30 — 50 — ns
Fast A20
gate used 45 — 85 — ns
HDB hold time t HWD 15 — 25 — ns
GA20 delay time tHGA — 90 — 180 ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 857 of 1130
REJ09B0327-0400
Table 26.38 Keyboard Buffer Controller Timing
Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum
operating frequency, Ta = –20 to +75°C
Ratings
Item Symbol Min Typ Max Unit Test
Conditions Notes
KCLK, KD output
fall time tKBF 20 + 0.1 Cb — 250 ns Figure 26.27
KCLK, KD input
data hold time tKBIH 150 — — ns
KCLK, KD input
data setup time tKBIS 150 — — ns
KCLK, KD output
delay time tKBOD — — 450 ns
KCLK, KD
capacitive load Cb— — 400 pF
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 858 of 1130
REJ09B0327-0400
Table 26.39 I2C Bus Timing
Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency
Ratings
Item Symbol Min Typ Max Unit Test Conditions Notes
SCL input cycle
time tSCL 12 — — tcyc Figure 26.28
SCL input high
pulse width tSCLH 3——t
cyc
SCL input low
pulse width tSCLL 5——t
cyc
SCL, SDA input
rise time tSr ——7.5
*tcyc
SCL, SDA input
fall time tSf — — 300 ns
SCL, SDA input
sp ike pulse
elimination time
tSP ——1t
cyc
SDA input bus
free time tBUF 5——t
cyc
Start condition
input hold time tSTAH 3——t
cyc
Retransmission
start condit ion
input setup time
tSTAS 3——t
cyc
Stop condition
input setup time tSTOS 3——t
cyc
Data input setup
time tSDAS 0.5 — — tcyc
Data input hold
time tSDAH 0——ns
SCL, SDA
capacitive load Cb— — 400 pF
Note: *17.5tcyc can be set according to the clock selected for use by the I2C module. For details,
see section 16.4, Usage Notes.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 859 of 1130
REJ09B0327-0400
26.4.4 A/D Conversion Characteristics
Tables 26.40 and 26.41 list the A/D conversion characteristics.
Table 26.40 A/D Conversion Characteristics
(AN7 to AN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 Bits
Conversion time*5— — 6.7 — — 13.4 µs
Analog input
capacitance ——20 ——20 pF
——10
*3——10
*1kΩPermissible signal-
source impedance 5*45*2
Nonlinearity error — — ±3.0 — — ±7.0 LSB
Offset error — — ±3.5 — — ±7.5 LSB
Full-scale error — — ±3.5 — — ±7.5 LSB
Quantization error — — ±0.5 — — ±0.5 LSB
Absolute accuracy — — ±4.0 — — ±8.0 LSB
Notes: 1. When 4.0 V ≤ AVCC ≤ 5.5 V
2. When 3.0 V ≤ AVCC < 4.0 V
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
5. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 860 of 1130
REJ09B0327-0400
Table 26.41 A/D Conversion Characteristics
(CIN15 to CIN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 Bits
Conversion time*5— — 6.7 — — 13.4 µs
Analog input
capacitance ——20 ——20 pF
——10
*3——10
*1kΩPermissible signal-
source impedance 5*45*2
Nonlinearity error — — ±5.0 — — ±11.0 LSB
Offset error — — ±5.5 — — ±11.5 LSB
Full-scale error — — ±5.5 — — ±11.5 LSB
Quantization error — — ±0.5 — — ±0.5 LSB
Absolute accuracy — — ±6.0 — — ±12.0 LSB
Notes: 1. When 4.0 V ≤ AVCC ≤ 5.5 V
2. When 3.0 V ≤ AVCC < 4.0 V
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
5. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 861 of 1130
REJ09B0327-0400
26.4.5 D/A Conversion Characteristics
Table 26.42 lists the D/A conversion ch aracteristics.
Table 26.42 D/A Conversion Characteristics
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Min Typ Max Min Typ Max Unit
Resolution 888 888 Bits
Conversion
time With 20-pF
load
capacitance
——10 ——10 µs
Absolute
accuracy With 2-MΩ
load
resistance
— ±1.0 ±1.5 — ±2.0 ±3.0 LSB
With 4-MΩ
load
resistance
——±1.0——±2.0
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 862 of 1130
REJ09B0327-0400
26.4.6 Flash Memory Characteristics
Table 26.43 shows the flash memory characteristics.
Table 26.43 Flash Memory Characteristics (Programming/erasing operating range)
Conditions (5 V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C
(3 V version): VCC = 3.0 V to 3.6V, VSS = 0 V, Ta = 0 to +75°C
Item Symbol Min Typ Max Unit Test
Condition
Programming time*1 *2 *4tP — 10 200 ms/
32 bytes
Erase time*1 *3 *6tE — 100 1200 ms/
block
Reprogramming count NWEC 100*810000*9—Times
Data retention time*10 tDRP 10 — — Years
Programming Wai t time after SWE-bit setting*1x10——µs
Wait time after PSU-bit setting*1y50——µs
Wait time after P-bit setting*1 *4z 150 — 200 µs
Wait time after P-bit clear*1α10 — — µs
Wait time after PSU-bit clear*1β10 — — µs
Wait time after PV-bit setting*1γ4——µs
Wait time after dummy write*1ε2——µs
Wait time after PV-bit clear*1η4——µs
Maximum programming
count*1 *4 *5N — — 1000 Times z = 200 µs
Erase Wait time after SWE-bit setting*1x10——µs
Wait time after ESU-bit setting*1y 200 — — µs
Wait time after E-bit setting*1 *6z5—10ms
Wait time after E-bit clear*1α10 — — µs
Wait time after ESU-bit clear*1β10 — — µs
Wait time after EV-bit setting*1γ20 — — µs
Wait time after dummy write*1ε2——µs
Wait time after EV-bit clear*1η5——µs
Maximum erase count*1 *6 *7N — — 120 Times z = 10 ms
Notes: 1. Set the times according to the program /era se alg orithm s .
2. Programming time per 32 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time .)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 863 of 1130
REJ09B0327-0400
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximu m programming time (tP (max))
tP(max) = wait time after P-bit setting (z) × maximum programming count (N)
5. Number of times when the wait time after P-bit setting (z) = 200 µs.
The number of writes should be set according to the actual set value of (z) to allow
programming within the maximum programming time (tP(max)).
6. Maximum erase time (tE (max))
tE(max) = wait time after E-bit setting (z) × maximum erase count (N)
7. Number of times when the wait time after E-bit setting (z ) = 10 ms.
The number of erases should be set according to the actual set value of (z) to allow
erasing within the maximum erase ti me (tE(max)).
8. Minimum number of times for which all characteristics are guaranteed after rewriting
(Guarantee range is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should normally function up to this
value).
10.Data retention characteristic when rewriting is performed within the specification range,
including the minimum value.
26.4.7 Usage Note
(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference
values for electrical characteristics shown in this manual. However, actual performance
figures, operating margins, noise margins, and other properties may vary due to differences in
the manufacturing process, on-chip ROM, layout patterns, etc.
When system ev aluation testing is car ried out using the F-ZTAT version, the same evaluation
tests should also be conducted for the mask ROM version when changing over to that version.
(2) On-chip power supply step-down circuit
The H8S/2147N F-ZTAT does not incorporate an internal power supply step-down circuit.
When changing over to F-ZTAT versions or mask ROM versions incorporating an internal
step-down circuit, the VCC2 pin has the same pin location as the VCL pin in a step-down
circuit (See figure 26.3).
Therefore, note that the circuit patterns differ between these two types of products.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 864 of 1130
REJ09B0327-0400
26.5 Electrical Characteristics of H8S/2144 F-ZTAT, H8S/2142 F-ZTAT,
and Mask ROM Version of H8S/2142
26.5.1 Absolute Maximum Ratings
Table 26.44 lists th e absolute maximum ratings.
Table 26.44 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage*VCC –0.3 to +7.0 V
Input voltage (except ports 6, 7,
and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not
selected for port 6 and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input selected
for port 6 and A) Vin –0.3 V to lower of voltages VCC +0.3 and
AVCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Reference supply voltage AVref –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Topr Regular specifications: 0 to +75 °COperating temperature (flash
memory programming/erasing) Wide-range specifications: 0 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Note: *Power supply voltage for VCC1 and VCC2 pins .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 865 of 1130
REJ09B0327-0400
26.5.2 DC Characteristics
Table 26.45 lists the DC characteristics. Permitted o utput current values and bus drive
characteristics are shown in tables 26.46 and 26.47, respectively.
Table 26.45 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, AVCC*1 = 5.0 V ±10%, AVref*1 = 4.5 V to AVCC,
VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*8 (regular specifications),
Ta = –40 to +85°C*8 (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — VSchmitt
trigger input
voltage VT+——V
CC × 0.7 V
P67 to P60*2 *5,
KIN15 to KIN8*5,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3 VT+ – VT–0.4 — — V
Input high
voltage RES, STBY,
NMI, MD1,
MD0
(2) VIH VCC –0.7 — VCC +0.3 V
EXTAL,
PA7 to PA0*5VCC × 0.7 — VCC +0.3 V
Port 7 2.0 — AVCC +0.3 V
Input pins except
(1) and (2)
above
2.0 — VCC +0.3 V
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0 V
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8 V
All output pins*4VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage 3.5 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*4VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 866 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
RES Iin— — 10.0 µA Vin = 0.5 to
VCC –0.5 V
Input
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V
Ports 1 to 3 –IP50 — 300 µA Vin = 0 VInput
pull-up
MOS
current
Ports 6, A, B 60 — 500 µA
RES (4) Cin — — 80 pFInput
capacitance NMI — — 50 pF
P52, P97,
P42, P86
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins except
(4) above — — 15 pF
Normal operation ICC — 75 100 mA f = 20 MHzCurrent
dissipation*6Sleep mode — 60 85 mA
Standby mode*7— 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC= 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref= 2.0 V
to AVCC
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 867 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Analog power supply voltage*1AVCC 4.5 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. When IICS = 0. Low-level output when the bus driv e function is selected is determined
separately.
5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is
not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
6. Current dissipation values are for VIH min = VCC –0.5 V, and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
7. The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
8. For flash memory program/erase operations, the applicable range is Ta = 0 to +75°C
(regular specifications) or Ta = 0 to +85°C (wide-range specifications).
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 868 of 1130
REJ09B0327-0400
Table 26.45 DC Characteristics (2)
Conditions: VCC = 4.0 V to 5.5 V*8, AVCC*1 = 4.0 V to 5.5 V, AVref*1 = 4.0 V to AVCC,
VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*8 (regular specifications),
Ta = –40 to +85°C*8 (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7 V VCC = 4.5 V to
5.5 V
VT+ – VT–0.4 — — V
Schmitt
trigger input
voltage
VT–0.8 — — V
P67 to P60*2 *5,
KIN1
5
to KIN8*5,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+——V
CC × 0.7 V VCC= 4.0 V to
4.5 V
VT+ – VT–0.3 — — V
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC –0.7 — VCC +0.3 V
EXTAL,
PA7 to PA0*5VCC × 0.7 — VCC +0.3 V
Port 7 2.0 — AVCC +0.3 V
Input pins
except (1) and
(2) above
2.0 — VCC +0.3 V
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0 V VCC = 4.5 V to
5.5 V
–0.3 — 0.8 V VCC = 4.0 V to
4.5 V
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8 V
All output pins*4VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage 3.5 — — V IOH = –1 mA,
VCC = 4.5 V to
5.5 V
3.0 — — V IOH = –1 mA,
VCC = 4.0 V to
4.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 869 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Output low
voltage All output pins
(except RESO)*4VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V
Ports 1 to 3 –IP50 — 300 µA
Ports 6, A, B 60 — 500 µA Vin = 0 V,
VCC = 4.5 V to
5.5 V
Ports 1 to 3 30 — 200 µA
Input
pull-up
MOS
current
Ports 6, A, B 40 — 400 µA Vin = 0 V,
VCC = 4.0 V to
4.5 V
RES (4) Cin — — 80 pFInput
capacitance NMI — — 50 pF
P52, P97, P42,
P86, PA7 to PA2 — — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation I CC — 65 85 mA f = 16 MHzCurrent
dissipation*6Sleep mode — 50 70 mA f = 16 MHz
Standby mode*7— 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 5.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 870 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
During A/D conversion Alref —0.51.0mAReference
power
supply
current
During A/D, D/A
conversion —2.05.0mA
Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.0 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. When IICS = 0. Low-level output when the bus driv e function is selected is determined
separately.
5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is
not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
6. Current dissipation values are for VIH min = VCC –0.5 V, and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
7. The values are for VRAM ≤ VCC < 4.0 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
8. For flash memory program/erase operations, the applicable ranges are VCC = 4.5 V to
5.5 V and Ta = 0 to +75°C (regular specifications) or Ta = 0 to +85°C (wide-range
specifications).
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 871 of 1130
REJ09B0327-0400
Table 26.45 DC Characteristics (3)
Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 5.5 V, AVref*1 = 2 .7 V
to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C
(Flash memory version): VCC = 3.0 V to 5.5 V*8, AVCC*1 = 3.0 V to 5.5 V, AVref = 3.0 V
to 5.5 V, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C*8
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–VCC × 0.2 — — V
VT+——V
CC × 0.7 V
Schmitt
trigger input
voltage
P67 to P60*2 *5,
KIN1
5
to KIN8*5,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3 VT+ – VT–VCC × 0.05 — — V
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC × 0.9 — VCC +0.3 V
EXTAL,
PA7 to PA0*5VCC × 0.7 — VCC +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Input pins
except (1) and
(2) above
VCC × 0.7 — VCC +0.3 V
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — VCC × 0.1 V
PA7 to PA0 –0.3 — VCC × 0.2 V VCC < 4.0 V
0.8 V VCC = 4.0 V to
5.5 V
–0.3 — VCC × 0.2 V VCC < 4.0 VNMI, EXTAL,
input pins except
(1) and (3)
above
0.8 V VCC = 4.0 V to
5.5 V
All output pins*4VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage VCC –1.0 — — V IOH = –1 mA
(VCC < 4.0 V)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 872 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Output low
voltage All output pins
(except RESO)*4VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 5 mA
(VCC < 4.0 V),
IOL = 10 mA
(4.0 V ≤ VCC ≤
5.5 V)
RESO ——0.4VI
OL = 1.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V
Ports 1 to 3 –IP10 — 150 µAInput pull-
up MOS
current Ports 6, A, B 30 — 250 µA Vin = 0 V,
VCC = 2.7 V*8
to 3.6 V
Input
capacitance RES (4) Cin — — 80 pF
NMI — — 50 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
P52, P97,
P42, P86,
PA7 to PA2
— — 20 pF
Input pins
except (4) above — — 15 pF
Normal operation ICC — 45 60 mA f = 10 MHzCurrent
dissipation*6Sleep mode — 35 50 mA
Standby mode*7— 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
o 5.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 873 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 2.7 — 5.5 V Operating
(mask ROM
version)
3.0 — 5.5 V Operating
(F-ZTAT
version)
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connection to the power supply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. When IICS = 0. Low-level output when the bus driv e function is selected is determined
separately.
5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is
not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
6. Current dissipation values are for VIH min = VCC –0.5 V, and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
7. The values are for VRAM ≤ VCC < 2.7 V (mask ROM version), and VRAM ≤ VCC < 3.0 V
(F-ZTAT version), VIH min = VCC × 0.9, and VIL max = 0.3 V.
8. For flash memory program/erase operations, the applicable ranges are VCC = 3.0 V to
3.6 V and Ta = 0 to +75°C. For the F-ZTAT versions, the test condition is VCC = 3.0 V or
higher.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 874 of 1130
REJ09B0327-0400
Table 26.46 Permiss ible Output Currents
Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) PA7 to PA4 (bus drive
function se lec ted) IOL ——20mA
Ports 1, 2, 3 — — 10 mA
RESO ——3 mA
Other output pi ns — — 2 mA
Total of ports 1, 2, and 3 ∑ IOL ——80mAPermissible output
low current (total) Total of all output pins,
including the above — — 120 mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——40mA
Conditions: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),
VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) PA7 to PA4 (bus drive
function se lec ted) IOL ——10mA
Ports 1, 2, 3 — — 2 mA
RESO ——1 mA
Other output pi ns — — 1 mA
Total of ports 1, 2, and 3 ∑ IOL ——40mAPermissible output
low current (total) Total of all output pins,
including the above ——60mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——30mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 26.46.
2. When driving a Darlington pair or LED, alwa ys ins ert a current-limiting resistor in the
output line, as show in figure s 26.1 and 26.2 .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 875 of 1130
REJ09B0327-0400
Table 26.47 Bus Drive Characteristics
Conditions: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),
VSS = 0 V
Applicable Pins: PA7 to PA4 (bus drive function selected)
Item Symbol Min Typ Max Unit Test Conditions
Output low voltage VOL ——0.8VI
OL = 16 mA,
VCC = 4.5 V to 5.5 V
——0.5 I
OL = 8 mA
——0.4 I
OL = 3 mA
26.5.3 AC Characteristics
Clock timing, control signal timing, bus timing, and timing of on-chip supporting modules list the
following.
Figure 26.4 shows the test conditions for th e AC character istics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 876 of 1130
REJ09B0327-0400
(1) Clock Timing
Table 26.48 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and exter nal clock input (EXTAL pin) oscillation settling times.
For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock
Pulse Generator.
Table 26.48 Clock Timing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition C: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version)
VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 50 500 62.5 500 100 500 ns Figure 26.5
Clock high pulse
width tCH 17 — 20 — 30 — ns Figure 26.5
Clock low pulse
width tCL 17 — 20 — 30 — ns
Clock rise time tCr —8 —10 —20 ns
Clock fall time tCf —8 —10 —20 ns
Oscillati on sett ling
time at reset
(crystal)
tOSC1 10 — 10 — 20 — ms Figure 26.6
Figure 26.7
Oscillati on sett ling
time in software
standby (cr ysta l)
tOSC2 8— 8— 8— ms
External clock
output stabilization
delay time
tDEXT 500 — 500 — 500 — µs
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 877 of 1130
REJ09B0327-0400
(2) Control Signal Timing
Table 26.49 shows the control signal timing. The only external interrupts that can operate on the
subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7.
Table 26.49 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition C: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),
VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
RES setup time tRESS 200 — 200 — 300 — ns Figure 26.8
RES pulse width tRESW 20 — 20 — 20 — tcyc
NMI setup time
(NMI) tNMIS 150 — 150 — 250 — ns Figure 26.9
NMI hold time
(NMI) tNMIH 10 — 10 — 10 — ns
NMI pulse width
(exiting sof t war e
standby mode)
tNMIW 200 — 200 — 200 — ns
IRQ setup time
(IRQ7 to IRQ0)tIRQS 150 — 150 — 250 — ns
IRQ hold time
(IRQ7 to IRQ0)tIRQH 10 — 10 — 10 — ns
IRQ pulse width
(IRQ7, IRQ6,
IRQ2 to IRQ0)
(exiting sof t war e
standby mode)
tIRQW 200 — 200 — 200 — ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 878 of 1130
REJ09B0327-0400
(3) Bus Timing
Table 26.50 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (φ = 32.768 kHz).
Table 26.50 Bus Tim ing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition C: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),
VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Address
delay time tAD —20 —30 —40 ns
Address
setup time tAS 0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —0.5 ×
tcyc –30 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD —20 —30 —40 ns
AS delay
time tASD —30 —45 —60 ns
RD delay
time 1 tRSD1 —30 —45 —60 ns
RD delay
time 2 tRSD2 —30 —45 —60 ns
Read data
setup time tRDS 15 — 20 — 35 — ns
Read data
hold time tRDH 0— 0— 0— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 879 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Read data
access
time 1
tACC1 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —1.0 ×
tcyc –60 ns Figure 26.10
to
figure 26.14
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –35 —1.5 ×
tcyc –50 ns
Read data
access
time 3
tACC3 —2.0 ×
tcyc –30 —2.0 ×
tcyc –40 —2.0 ×
tcyc –60 ns
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –35 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –30 —3.0 ×
tcyc –40 —3.0 ×
tcyc –60 ns
WR delay
time 1 tWRD1 —30 —45 —60 ns
WR delay
time 2 tWRD2 —30 —45 —60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –30 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD —30 —45 —60 ns
Write data
setup time tWDS 0— 0— 0— ns
Write data
hold time tWDH 10 — 15 — 20 — ns
WAIT
setup time tWTS 30 — 45 — 60 — ns
WAIT hold
time tWTH 5— 5— 10— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 880 of 1130
REJ09B0327-0400
(4) Timing of On-Chip Supporting Modules
Tables 26.51 shows the on-chip supporting module timing. The only on-chip supporting modules
that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI
and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1).
Table 26. 51 Timing of On-Chip Support ing Modules
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition C: VCC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),
VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
I/O
ports Output data delay
time tPWD — 50 — 50 — 100 ns Figure
26.15
Input data setup
time tPRS 30 — 30 — 50 —
Input data hold
time tPRH 30 — 30 — 50 —
FRT Timer output
delay
time
tFTOD — 50 — 50 — 100 ns Figure
26.16
Timer input setup
time tFTIS 30 — 30 — 50 —
Timer clock input
setup time tFTCS 30 — 30 — 50 — Figure
26.17
Single
edge tFTCWH 1.5 — 1.5 — 1.5 — tcyc
Timer
clock
pulse
width Both
edges tFTCWL 2.5 — 2.5 — 2.5 —
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 881 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
TMR Timer output
delay time tTMOD — 50 — 50 — 100 ns Figure
26.18
Timer reset input
setup time tTMRS 30 —30 — 50 — Figure
26.20
Timer clock input
setup time tTMCS 30 — 30 — 50 — Figure
26.19
Single
edge tTMCWH 1.5 — 1.5 — 1.5 —tcyc
Timer
clock
pulse
width Both
edges tTMCWL 2.5 — 2.5 — 2.5 —
PWMX Pulse output
delay time tPWOD — 50 — 50 — 100 ns Figure
26.21
SCI Asynchro-
nous tScyc 4— 4— 4— t
cyc Figure
26.22
Input
clock
cycle Synchro-
nous 6— 6— 6—
Input clock pulse
width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc
Input clock rise
time tSCKr — 1.5 — 1.5 — 1.5 tcyc
Input clock fall
time tSCKf — 1.5 — 1.5 — 1.5
Transmit data
delay time
(synchronous)
tTXD — 50 — 50 — 100 ns Figure
26.23
Receive data set up
time (synchronous) tRXS 50 — 50 — 100 — ns
Receive data hol d
time (synchronous) tRXH 50 — 50 — 100 — ns
A/D
conver-
ter
Trigger input setup
time tTRGS 30 — 30 — 50 — ns Figure
26.24
WDT RESO output delay
time tRESD — 100 — 120 — 200 ns Figure
26.25
RESO output pulse
width tRESOW 132 — 132 — 132 — tcyc
Note: *Only supporting modules that can be used in subc lock operation
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 882 of 1130
REJ09B0327-0400
26.5.4 A/D Conversion Characteristics
Tables 26.52 and 26.53 list the A/D conversion characteristics.
Table 26.52 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V,
φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS =
0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Condition C (mask ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVref = 2.7 V to
AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition C (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*5——6.7 ——8.4 ——13.4µs
Analog input
capacitance ——20 ——20 ——20 pF
——10
*3——10
*3——10
*1kΩPermissible signal-
source impedance 5*45*45*2
Nonlinearity error — — ±3.0 — — ±3.0 — — ±7.0 LSB
Offset error ——±3.5——±3.5——±7.5LSB
Full-scale error — — ± 3. 5 — — ±3.5 — — ±7.5 LSB
Quantization error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy——±4.0——±4.0——±8.0LSB
Notes: 1. When 4.0 V ≤ AVCC ≤ 5.5 V
2. When 2.7 V ≤ AVCC < 4.0 V (mask ROM version) or when 3.0 V ≤ AVCC < 4.0 V (F-ZTAT
version)
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
5. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 883 of 1130
REJ09B0327-0400
Table 26.53 A/D Conversion Characteristics
(CIN15 to CIN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V,
φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS =
0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Condition C (mask ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVref = 2.7 V to
AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition C (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*5——6.7 ——8.4 ——13.4µs
Analog input
capacitance ——20 ——20 ——20 pF
——10
*3——10
*3——10
*1kΩPermissible signal-
source impedance 5*45*45*2
Nonlinearity error — — ±5.0 — — ±5.0 — — ±11.0 LSB
Offset error — — ±5.5 — — ±5. 5 — — ±11.5 LS B
Full-scale error — — ± 5. 5 — — ±5.5 — — ±11.5 LSB
Quantization error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy——±6.0——±6.0——±12.0LSB
Notes: 1. When 4.0 V ≤ AVCC ≤ 5.5 V
2. When 2.7 V ≤ AVCC < 4.0 V (mask ROM version) or when 3.0 V ≤ AVCC < 4.0 V (F-ZTAT
version)
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
5. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 884 of 1130
REJ09B0327-0400
26.5.5 D/A Conversion Characteristics
Table 26.54 lists the D/A conversion characteristics.
Table 26.54 D/A Conversion Characteristics
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V,
φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS =
0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
Condition C (mask ROM version): VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, AVref = 2.7 V to
AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition C (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 888 888 888 Bits
Conversion
time With 20 pF
load
capacitance
——10 ——10 ——10 µs
Absolute
accuracy With 2 MΩ
load
resistance
— ±1.0 ±1.5 — ±1.0 ±1.5 — ±2.0 ±3.0 LSB
With 4 MΩ
load
resistance
——±1.0——±1.0——±2.0
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 885 of 1130
REJ09B0327-0400
26.5.6 Flash Memory Characteristics
Table 26.55 shows the flash memory characteristics.
Table 26.55 Flash Memory Characteristics (Programming/erasing operating range)
Conditions (5 V version): VCC = 5.0 V ±10%, VSS = 0 V, Ta = 0 to +75°C (regular specifications),
Ta = 0 to +85°C (wide-range specifications)
(3 V version): VCC = 3.0 V to 3.6V, VSS = 0 V, Ta = 0 to +75°C
Item Symbol Min Typ Max Unit Test
Condition
Programming time*1 *2 *4tP — 10 200 ms/
32 bytes
Erase time*1 *3 *6tE — 100 1200 ms/
block
Reprogramming count NWEC 100*810000*9—Times
Data retention time*10 tDRP 10 — — Years
Programming Wai t time after SWE-bit setting*1x10——µs
Wait time after PSU-bit setting*1y50——µs
Wait time after P-bit setting*1 *4z 150 — 200 µs
Wait time after P-bit clear*1α10 — — µs
Wait time after PSU-bit clear*1β10 — — µs
Wait time after PV-bit setting*1γ4——µs
Wait time after dummy write*1ε2——µs
Wait time after PV-bit clear*1η4——µs
Maximum programming
count*1 *4 *5N — — 1000 Times z = 200 µs
Erase Wait time after SWE-bit setting*1x10——µs
Wait time after ESU-bit setting*1y 200 — — µs
Wait time after E-bit setting*1 *6z5—10ms
Wait time after E-bit clear*1α10 — — µs
Wait time after ESU-bit clear*1β10 — — µs
Wait time after EV-bit setting*1γ20 — — µs
Wait time after dummy write*1ε2——µs
Wait time after EV-bit clear*1η5——µs
Maximum erase count*1 *6 *7N — — 120 Times z = 10 ms
Notes: 1. Set the times according to the program /era se alg orithm s .
2. Programming time per 32 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time .)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 886 of 1130
REJ09B0327-0400
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximu m programming time (tP (max))
tP (max) = wait time after P-bit setting (z) × maximum programming count (N)
5. Number of times when the wait time after P-bit setting (z) = 200 µs.
The number of writes should be set according to the actual set value of (z) to allow
programming within the maximum programming time (tP (max)).
6. Maximum erase time (tE (max))
tE (max) = wait time after E-bit setting (z) × maximum e rase count (N))
7. Number of times when the wait time after E-bit setting (z ) = 10 ms.
The number of erases should be set according to the actual set value of (z) to allow
erasing within the maximum erase ti me (tE (max)).
8. Minimum number of times for which all characteristics are guaranteed after rewriting
(Guarantee range is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should normally function up to this
value).
10.Data retention characteristic when rewriting is performed within the specification range,
including the minimum value.
26.5.7 Usage Note
(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference
values for electrical characteristics shown in this manual. However, actual performance
figures, operating margins, noise margins, and other properties may vary due to differences in
the manufacturing process, on-chip ROM, layout patterns, etc.
When system ev aluation testing is car ried out using the F-ZTAT version, the same evaluation
tests should also be conducted for the mask ROM version when changing over to that version.
(2) On-chip power supply step-down circuit
The H8S/2144F-ZTAT, H8S/2142F-ZTAT, and mask ROM version of H8S/2142 do not
incorporate an internal power supply step-down circuit.
When changing over to F-ZTAT versions or mask ROM versions incorporating an internal
step-down circuit, the VCC2 pin has the same pin location as the VCL pin in a step-down
circuit (See figure 26.3).
Therefore, note that the circuit patterns differ between these two types of products.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 887 of 1130
REJ09B0327-0400
26.6 Electrical Characteristics of H8S/2144 F-ZTAT (A-mask version)
and Mask ROM Versions of H8S/2144 and H8S/2143
26.6.1 Absolute Maximum Ratings
Table 26.56 lists th e absolute maximum ratings.
Table 26.56 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage*1VCC –0.3 to +7.0 V
Power supply voltage*1 (3-V version) VCC –0.3 to +4.3 V
Power supply voltage*2 (VCL pin) VCL –0.3 to +4.3 V
Input voltage (except ports 6, 7, and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input not sel ected
for port 6 and A) Vin –0.3 to VCC +0.3 V
Input voltage (CIN input selected for
port 6 and A) Vin –0.3 V to lower of voltages VCC +0 .3
and AVCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Reference supply voltage AVref –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog power supply voltage
(3 V version) AVCC –0.3 to +4.3 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Topr Regular specifications: –20 to +75 °COperating temperature (flash memory
programming/erasing) Wide-range specifications: –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: 1. Permanent damage to the chip may result if absolute maximum ratings are
exceeded.
2. Never apply more than 7.0 V to any of the pins of the 5- or 4-V version or 4.3 V to
any of the pins (except for port A) of the 3-V version.
Notes: 1. Power supply voltage for VCC1 pin.
Never exceed the maximum rating of VCL in the low-power version (3-V version)
because both the VCC1 and VCL pins are connected to the VCL power supp ly.
2. It is an operating power supply voltage pin on the chip.
Never apply power supply voltage to the VCL pin in the 5- or 4-V version.
Always connect an external capacitor between the VCL pin and ground for internal
voltage sta bil iza tion.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 888 of 1130
REJ09B0327-0400
26.6.2 DC Characteristics
Table 26.57 lists the DC ch aracteristics. Permitted output current valu es and b us drive
characteristics are shown in tables 26.58 and 26.59, respectively.
Table 26.57 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, AVCC*1 = 5.0 V ±10%, AVref*1 = 4.5 V to AVCC,
VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7 V
Schmitt
trigger input
voltage
P67 to P60*2 *5,
KIN15 to KIN8*5,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3 VT+ – VT–0.4 — — V
Input high
voltage RES, STBY,
NMI, MD1,
MD0
(2) VIH VCC –0.7 — VCC +0.3 V
EXTAL,
PA7 to PA0*5VCC × 0.7 — VCC +0.3 V
Port 7 2.0 — AVCC +0.3 V
Input pins except
(1) and (2)
above
2.0 — VCC +0.3 V
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0 V
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8 V
All output pins*4VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage 3.5 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)*4VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 889 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V
Ports 1 to 3 –IP30 — 300 µA Vin = 0 VInput
pull-up
MOS
current
Ports 6, A, B 60 — 600 µA
RES (4) Cin — — 80 pFInput
capacitance NMI — — 50 pF
P52, P97,
P42, P86
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins except
(4) above — — 15 pF
Normal operation ICC — 55 70 mA f = 20 MHzCurrent
dissipation*6Sleep mode — 36 55 mA
Standby mode*7—1.05.0µAT
a ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC= 2.0 V
to 5.5 V
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref= 2.0 V
to AVCC
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 890 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Analog power supply voltage*1AVCC 4.5 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. When IICS = 0. Low-level output when the bus driv e function is selected is determined
separately.
5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is
not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
6. Current dissipation values are for VIH min = VCC –0.2 V, and VIL max = 0.2 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
7. The values are for VRAM ≤ VCC < 4.5V, VIH min = VCC –0.2 V, and VIL max = 0.2 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 891 of 1130
REJ09B0327-0400
Table 26.57 DC Characteristics (2)
Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, AVref*1 = 4.0 V to AVCC,
VSS = AVSS*1 = 0 V, Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–1.0 — — V
VT+——V
CC × 0.7 V VCC = 4.5 V to
5.5 V
VT+ – VT–0.4 — — V
Schmitt
trigger input
voltage
VT–0.8 — — V VCC < 4.5 V
P67 to P60*2 *5,
KIN1
5
to KIN8*5,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
VT+——V
CC × 0.7 V
VT+ – VT–0.3 — — V
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC –0.7 — VCC +0.3 V
EXTAL,
PA7 to PA0*5VCC × 0.7 — VCC +0.3 V
Port 7 2.0 — AVCC +0.3 V
Input pins
except (1) and
(2) above
2.0 — VCC +0.3 V
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — 0.5 V
PA7 to PA0 –0.3 — 1.0 V VCC = 4.5 V to
5.5 V
–0.3 — 0.8 V VCC < 4.5 V
NMI, EXTAL,
input pins except
(1) and (3)
above
–0.3 — 0.8 V
All output pins*4VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage 3.5 — — V IOH = –1 mA,
VCC = 4.5 V to
5.5 V
3.0 — — V IOH = –1 mA,
VCC < 4.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 892 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Output low
voltage All output pins
(except RESO)*4VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V
Ports 1 to 3 –IP30 — 300 µA
Ports 6, A, B 60 — 600 µA Vin = 0 V,
VCC = 4.5 V to
5.5 V
Input
pull-up
MOS
current Ports 1 to 3 20 — 200 µA
Ports 6, A, B 40 — 500 µA Vin = 0 V,
VCC < 4.5 V
RES (4) Cin — — 80 pF
NMI — — 50 pF
Input
capacitance
P52, P97, P42,
P86, PA7 to PA2 — — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation I CC — 45 58 mA f = 16 MHzCurrent
dissipation*6Sleep mode — 30 46 mA f = 16 MHz
Standby mode*7—1.05.0µAT
a ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 5.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 893 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
During A/D conversion Alref —0.51.0mA
During A/D, D/A
conversion —2.05.0mA
Reference
power
supply
current Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 4.0 — 5.5 V Operating
2.0 — 5.5 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 5.5 V to AVCC and AVref pins by connectio n to the power sup ply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. When IICS = 0. Low-level output when the bus driv e function is selected is determined
separately.
5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is
not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
6. Current dissipation values are for VIH min = VCC –0.2 V, and VIL max = 0.2 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
7. The values are for VRAM ≤ VCC < 4.0 V, VIH min = VCC –0.2 V, and VIL max = 0.2 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 894 of 1130
REJ09B0327-0400
Table 26.57 DC Characteristics (3)
Conditions: VCC = 2.7 V to 3.6 V*8, AVCC*1 = 2.7 V to 3.6 V, AVref*1 = 2.7 V to 3.6 V,
VSS = AVSS*1 = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
(1) VT–VCC × 0.2 — — V
VT+——V
CC × 0.7 V
Schmitt
trigger input
voltage
P67 to P60*2 *5,
KIN1
5
to KIN8*5,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3 VT+ – VT–VCC × 0.05 — — V
Input high
voltage RES, STBY,
NMI, MD1, MD0 (2) VIH VCC × 0.9 — VCC +0.3 V
EXTAL,
PA7 to PA0*5VCC × 0.7 — VCC +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Input pins
except (1) and
(2) above
VCC × 0.7 — VCC +0.3 V
Input low
voltage RES, STBY,
MD1, MD0 (3) VIL –0.3 — VCC × 0.1 V
PA7 to PA0 –0.3 — VCC × 0.2 V
–0.3 — VCC × 0.2 VNMI, EXTAL,
input pins except
(1) and (3)
above
All output pins*4VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage VCC –1.0 — — V IOH = –1 mA
(VCC = 2.7 V
to 3.6 V
Output low
voltage All output pins
(except RESO)*4VOL ——0.4VI
OL = 1.6 mA
Ports 1 to 3 — — 1.0 V IOL = 5 mA
RESO ——0.4VI
OL = 1.6 mA
RES Iin— — 10.0 µAInput
leakage
current STBY, NMI,
MD1, MD0 ——1.0µA
Vin = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 895 of 1130
REJ09B0327-0400
Item Symbol Min Typ Max Unit Test
Conditions
Three-state
leakage
current
(off state)
Ports 1 to 6, 8,
9, A, B ITSI——1.0µAV
in = 0.5 to
VCC –0.5 V
Ports 1 to 3 –IP5 — 150 µAInput pull-
up MOS
current Ports 6, A, B 30 — 300 µA Vin = 0 V,
VCC = 2.7 V to
3.6 V
RES (4) Cin — — 80 pF
NMI — — 50 pF
Input
capacitance
P52, P97,
P42, P86,
PA7 to PA2
— — 20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Input pins
except (4) above — — 15 pF
Normal operation ICC — 30 40 mA f = 10 MHzCurrent
dissipation*6Sleep mode — 20 32 mA
Standby mode*7—1.05.0µAT
a ≤ 50°C
— — 20.0 µA 50°C < Ta
During A/D, D/A
conversion AlCC —1.22.0mAAnalog
power
supply
current Idle — 0.01 5.0 µA AVCC = 2.0 V
to 3.6 V
During A/D conversion Alref —0.51.0mAReference
power
supply
current
During A/D, D/A
conversion —2.05.0mA
Idle — 0.01 5.0 µA AVref = 2.0 V
to AVCC
Analog power supply voltage*1AVCC 2.7 — 3.6 V Operating
2.0 — 3.6 V Idle/not used
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and
D/A converter are not used.
Even if the A/D converter and D/A converter are not used, apply a value in the range
2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some
other method. En sure that AVref ≤ AVCC.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 896 of 1130
REJ09B0327-0400
4. When IICS = 0. Low-level output when the bus driv e function is selected is determined
separately.
5. The upper limit of the applied voltage on Ports 6 and A is VCC +0.3 V when CIN input is
not selected, and the lower of VCC +0.3 V and AVCC +0.3 V when CIN input is selected.
When a pin is in output mode, the output voltage is equivalent to the applied voltage.
6. Current dissipation values are for VIH min = VCC –0.2 V, and VIL max = 0.2 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
7. The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC –0.2 V, and VIL max = 0.2 V.
8. For flash memory program/erase operations, the applicable range is VCC = 3.0 V to
3.6 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 897 of 1130
REJ09B0327-0400
Table 26.58 Permiss ible Output Currents
Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40
to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) PA7 to PA4 (bus drive
function se lec ted) IOL ——20mA
Ports 1, 2, 3 — — 10 mA
RESO ——3 mA
Other output pi ns — — 2 mA
Total of ports 1, 2, and 3 ∑ IOL ——80mAPermissible output
low current (total) Total of all output pins,
including the above — — 120 mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——40mA
Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) PA7 to PA4 (bus drive
function se lec ted) IOL ——10mA
Ports 1, 2, 3 — — 2 mA
RESO ——1 mA
Other output pi ns — — 1 mA
Total of ports 1, 2, and 3 ∑ IOL ——40mAPermissible output
low current (total) Total of all output pins,
including the above ——60mA
Permissible output
high current (per pin) All output pins –IOH ——2 mA
Permissible output
high current (total) Total of all output pins ∑ –IOH ——30mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 26.58.
2. When driving a Darlington pair or LED, alwa ys ins ert a current-limiting resistor in the
output line, as show in figure s 26.1 and 26.2 .
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 898 of 1130
REJ09B0327-0400
Table 26.59 Bus Drive Characteristics
Conditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V
Applicable Pins: PA7 to PA4 (bus drive function selected)
Item Symbol Min Typ Max Unit Test Conditions
Output low voltage VOL ——0.8VI
OL = 16 mA,
VCC = 4.5 V to 5.5 V
——0.5 I
OL = 8 mA
——0.4 I
OL = 3 mA
26.6.3 AC Characteristics
Clock timing, control signal timing, bus timing, and timing of on-chip supporting modules list the
following.
Figure 26.4 shows the test conditions for th e AC character istics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 899 of 1130
REJ09B0327-0400
(1) Clock Timing
Table 26.60 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and exter nal clock input (EXTAL pin) oscillation settling times.
For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock
Pulse Generator.
Table 26.60 Clock Timing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition C: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 50 500 62.5 500 100 500 ns Figure 26.5
Clock high pulse
width tCH 17 — 20 — 30 — ns Figure 26.5
Clock low pulse
width tCL 17 — 20 — 30 — ns
Clock rise time tCr —8 —10 —20 ns
Clock fall time tCf —8 —10 —20 ns
Oscillati on sett ling
time at reset
(crystal)
tOSC1 10 — 10 — 20 — ms Figure 26.6
Figure 26.7
Oscillati on sett ling
time in software
standby (cr ysta l)
tOSC2 8— 8— 8— ms
External clock
output stabilization
delay time
tDEXT 500 — 500 — 500 — µs
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 900 of 1130
REJ09B0327-0400
(2) Control Signal Timing
Table 26.61 shows the control signal timing. The only external interrupts that can operate on the
subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7.
Table 26.61 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
RES setup time tRESS 200 — 200 — 300 — ns Figure 26.8
RES pulse width tRESW 20 — 20 — 20 — tcyc
NMI setup time
(NMI) tNMIS 150 — 150 — 250 — ns Figure 26.9
NMI hold time
(NMI) tNMIH 10 — 10 — 10 — ns
NMI pulse width
(exiting sof t war e
standby mode)
tNMIW 200 — 200 — 200 — ns
IRQ setup time
(IRQ7 to IRQ0)tIRQS 150 — 150 — 250 — ns
IRQ hold time
(IRQ7 to IRQ0)tIRQH 10 — 10 — 10 — ns
IRQ pulse width
(IRQ7, IRQ6,
IRQ2 to IRQ0)
(exiting sof t war e
standby mode)
tIRQW 200 — 200 — 200 — ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 901 of 1130
REJ09B0327-0400
(3) Bus Timing
Table 26.62 shows the bus timing. Operation in external expansion mode is not guaranteed when
operating on the subclock (φ = 32.768 kHz).
Table 26.62 Bus Tim ing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range
specifications)
Condition C: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Address
delay time tAD —20 —30 —40 ns
Address
setup time tAS 0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —0.5 ×
tcyc –30 —ns
Figure 26.10
to
figure 26.14
Address
hold time tAH 0.5 ×
tcyc –10 —0.5 ×
tcyc –15 —0.5 ×
tcyc –20 —ns
CS delay
time (IOS)tCSD —20 —30 —40 ns
AS delay
time tASD —30 —45 —60 ns
RD delay
time 1 tRSD1 —30 —45 —60 ns
RD delay
time 2 tRSD2 —30 —45 —60 ns
Read data
setup time tRDS 15 — 20 — 35 — ns
Read data
hold time tRDH 0— 0— 0— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 902 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Read data
access
time 1
tACC1 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —1.0 ×
tcyc –60 ns Figure 26.10
to
figure 26.14
Read data
access
time 2
tACC2 —1.5 ×
tcyc –25 —1.5 ×
tcyc –35 —1.5 ×
tcyc –50 ns
Read data
access
time 3
tACC3 —2.0 ×
tcyc –30 —2.0 ×
tcyc –40 —2.0 ×
tcyc –60 ns
Read data
access
time 4
tACC4 —2.5 ×
tcyc –25 —2.5 ×
tcyc –35 —2.5 ×
tcyc –50 ns
Read data
access
time 5
tACC5 —3.0 ×
tcyc –30 —3.0 ×
tcyc –40 —3.0 ×
tcyc –60 ns
WR delay
time 1 tWRD1 —30 —45 —60 ns
WR delay
time 2 tWRD2 —30 —45 —60 ns
WR pulse
width 1 tWSW1 1.0 ×
tcyc –20 —1.0 ×
tcyc –30 —1.0 ×
tcyc –40 —ns
WR pulse
width 2 tWSW2 1.5 ×
tcyc –20 —1.5 ×
tcyc –30 —1.5 ×
tcyc –40 —ns
Write data
delay time tWDD —30 —45 —60 ns
Write data
setup time tWDS 0— 0— 0— ns
Write data
hold time tWDH 10 — 15 — 20 — ns
WAIT
setup time tWTS 30 — 45 — 60 — ns
WAIT hold
time tWTH 5— 5— 10— ns
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 903 of 1130
REJ09B0327-0400
(4) Timing of On-Chip Supporting Modules
Tables 26.63 shows the on-chip supporting module timing. The only on-chip supporting modules
that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI
and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1).
Table 26. 63 Timing of On-Chip Support ing Modules
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-
range specifications)
Condition C: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating
frequency, Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
I/O
ports Output data delay
time tPWD — 50 — 50 — 100 ns Figure
26.15
Input data setup
time tPRS 30 — 30 — 50 —
Input data hold timetPRH 30 — 30 — 50 —
FRT Timer output delay
time tFTOD — 50 — 50 — 100 ns Figure
26.16
Timer input setup
time tFTIS 30 — 30 — 50 —
Timer clock input
setup time tFTCS 30 —30 —50 — Figure
26.17
Single
edge tFTCWH 1.5 —1.5 —1.5—t
cyc
Timer
clock
pulse
width Both
edges tFTCWL 2.5 — 2.5 — 2.5 —
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 904 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
TMR Timer output
delay time tTMOD — 50 — 50 — 100 ns Figure
26.18
Timer reset input
setup time tTMRS 30 —30 — 50 — Figure
26.20
Timer clock input
setup time tTMCS 30 — 30 — 50 — Figure
26.19
Single
edge tTMCWH 1.5 — 1.5 — 1.5 —tcyc
Timer
clock
pulse
width Both
edges tTMCWL 2.5 — 2.5 — 2.5 —
PWMX Pulse output
delay time tPWOD — 50 — 50 — 100 ns Figure
26.21
SCI Asynchro-
nous tScyc 4— 4—4— t
cyc Figure
26.22
Input
clock
cycle Synchro-
nous 6— 6— 6—
Input clock pulse
width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc
Input clock rise
time tSCKr — 1.5 — 1.5 — 1.5 tcyc
Input clock fall
time tSCKf — 1.5 — 1.5 — 1.5
Transmit data
delay time
(synchronous)
tTXD — 50 — 50 — 100 ns Figure
26.23
Receive data set up
time (synchronous) tRXS 50 — 50 — 100 — ns
Receive data hol d
time (synchronous) tRXH 50 — 50 — 100 — ns
A/D
conver-
ter
Trigger input setup
time tTRGS 30 — 30 — 50 — ns Figure
26.24
WDT RESO output delay
time tRESD — 100 — 120 — 200 ns Figure
26.25
RESO output pulse
width tRESOW 132 — 132 — 132 — tcyc
Note: *Only supporting modules that can be used in subc lock operation
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 905 of 1130
REJ09B0327-0400
26.6.4 A/D Conversion Characteristics
Tables 26.64 and 26.65 list the A/D conversion characteristics.
Table 26.64 A/D Conversion Characteristics
(AN7 to AN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*3——6.7 ——8.4 ——13.4µs
Analog input
capacitance ——20 ——20 ——20 pF
——10
*1——10
*1——5 kΩPermissible signal-
source impedance 5*25*2
Nonlinearity error — — ±3.0 — — ±3.0 — — ±7.0 LSB
Offset error ——±3.5——±3.5——±7.5LSB
Full-scale error — — ± 3. 5 — — ±3.5 — — ±7.5 LSB
Quantization error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy——±4.0——±4.0——±8.0LSB
Notes: 1. When conver sio n time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
2. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
3. In single mode and φ = maximum operating frequency.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 906 of 1130
REJ09B0327-0400
Table 26.65 A/D Conversion Characteristics
(CIN15 to CIN0 Input: 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 3.6 V*4, AVCC = 3.0 V to 3.6 V*4, AVref = 3.0 V to AVCC*4,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 Bits
Conversion time*3——6.7 ——8.4 ——13.4µs
Analog input
capacitance ——20 ——20 ——20 pF
——10
*1——10
*1——5 kΩPermissible signal-
source impedance 5*25*2
Nonlinearity error — — ±5.0 — — ±5.0 — — ±11.0 LSB
Offset error — — ±5.5 — — ±5. 5 — — ±11.5 LS B
Full-scale error — — ± 5. 5 — — ±5.5 — — ±11.5 LSB
Quantization error — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy——±6.0——±6.0——±12.0LSB
Notes: 1. When conver sio n time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
2. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 MHz)
3. In single mode and φ = maximum operating frequency.
4. When using CIN, the applicable range is VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, and
AVref = 3.0 V to 3.6 V.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 907 of 1130
REJ09B0327-0400
26.6.5 D/A Conversion Characteristics
Table 26.66 lists the D/A conversion ch aracteristics.
Table 26.66 D/A Conversion Characteristics
Condition A: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVref = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C (regular specifications),
Ta = –40 to +85°C (wide-range specifications)
Condition C: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 888 888 888 Bits
Conversion
time With 20-pF
load
capacitance
——10 ——10 ——10 µs
Absolute
accuracy With 2-MΩ
load
resistance
— ±1.0 ±1.5 — ±1.0 ±1.5 — ±2.0 ±3.0 LSB
With 4-MΩ
load
resistance
——±1.0——±1.0——±2.0
26.6.6 Flash Memory Characteristics
Table 26.67 shows the flash memory characteristics.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 908 of 1130
REJ09B0327-0400
Table 26.67 Flash Memory Characteristics (Programming/erasing operating range)
Conditions (5 V version): VCC = 4.0 V to 5.5 V,VSS = 0 V, Ta = –20 to +75°C (regular
specifications), Ta = –40 to +85°C (wide-range specifications)
(3 V version): VCC = 3.0 V to 3.6V, VSS = 0 V, Ta = –20 t o 75°C
Item Symbol Min Typ Max Unit Test
Condition
Programming time*1 *2 *4tP — 10 200 ms/
128 bytes
Erase time*1 *3 *6tE — 100 1200 ms/
block
Reprogramming count NWEC 100*810000*9—Times
Data retention time*10 tDRP 10 — — Years
Programming Wai t time after SWE-bit setting*1x1——µs
Wait time after PSU-bit setting*1y50——µs
z1 28 30 32 µs 1 ≤ n ≤ 6Wait time after P-bit setting*1 *4
z2 198 200 202 µs 7 ≤ n ≤ 1000
z3 8 10 12 µs Additional
writing
Wait time after P-bit clear*1α10 — — µs
Wait time after PSU-bit clear*1β10 — — µs
Wait time after PV-bit setting*1γ4——µs
Wait time after dummy write*1ε2——µs
Wait time after PV-bit clear*1η4——µs
Wait time after SWE-bit clear*1θ100 — — µs
Maximum programming
count*1 *4 *5N — — 1000 Times
Erase Wait time after SWE-bit setting*1x1——µs
Wait time after ESU-bit setting*1y 100 — — µs
Wait time after E-bit setting*1 *6z 10 — 100 ms
Wait time after E-bit clear*1α10 — — µs
Wait time after ESU-bit clear*1β10 — — µs
Wait time after EV-bit setting*1γ20 — — µs
Wait time after H'FF dummy
write*1ε2——µs
Wait time after EV-bit clear*1η4——µs
Wait time after SWE-bit clear*1θ100 — — µs
Maximum erase count*1 *6 *7N — — 120 Times
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 909 of 1130
REJ09B0327-0400
Notes: 1. Set the times according to the program /era se alg orithm s .
2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time .)
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximu m programming time (tP (max))
tP (max) = (Wait time after P-bit setting (z1) + (z3)) × 6 + Wait time after P-bit setting
(z2) × ((N) – 6)
5. Maximum programming count (N) should be set according to the actual set value of (z1,
z2, z3) to allow programming within the maximum programming time (tP (max)). The
wait time after P-bit setting (z1, z2, z3) must be changed with the value of the number
of writing times (n) as follows.
The number of times for writing n
1 ≤ n ≤ 6 z1 = 30 µs, z3 = 10 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Waiting time after E-bit setting (z) × Maximum erase count (N)
7. Maximum erase count (N) should be set according to the actual setting (z) to allow
erase within the maximum erase time (tE (max)).
8. Minimum number of times for which all characteristics are guaranteed after rewriting
(Guarantee range is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should normally function up to this
value).
10.Data retention characteristic when rewriting is performed within the specification range,
including the minimum value.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 910 of 1130
REJ09B0327-0400
26.6.7 Usage Note
(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference
values for electrical characteristics shown in this manual. However, actual performance
figures, operating margins, noise margins, and other properties may vary due to differences in
the manufacturing process, on-chip ROM, layout patterns, etc.
When system ev aluation testing is car ried out using the F-ZTAT version, the same evaluation
tests should also be conducted for the mask ROM version when changing over to that version.
(2) On-chip power supply step-down circuit
The following products incorporate an internal power supply step-down circuit, which
automatically drops down the inter nal power supply voltage to the optimum internal voltage
level: the F-ZTAT A-mask versions of the H8S/2144 (HD64F2144A) and the mask ROM
versions of the H8S/2144, and H8S/2143 (HD6432144S and HD6432143S).
The voltage- stabilization capacitor (0.47 µF one or two connected in series) must be connected
between the VCL (internal power supply step-down) and VSS pins.
Figure 26.3 shows the connection of the external capacitors.
For the 5- or 4-V version, do not connect the VCL pin in a product incorporating an internal
step-down circuit to the VCC power supply. (Connect the VCC1 pin to the VCC power supp l y as
usual.)
For the 3-V version, connect both the VCL and VCC1 pins to the system power supply.
When changing from the F-ZTAT versions not incorporating an internal step-down circuit to
the mask ROM versions incorporating an internal step-down circuit, the VCL pin has the same
pin location as the VCC2 pin.
Therefore, note that the circuit patterns differ between these two types of products.
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 911 of 1130
REJ09B0327-0400
26.7 Operational Timing
26.7.1 Test Conditions for the AC Characteristics
C
Chip output
pin
R
H
R
L
C = 30 pF: All output ports
R
L
= 2.4 kΩ
R
H
= 12 kΩ
I/O timing test levels
• Low level: 0.8 V
• High level: 2.0 V
V
CC
Figure 26.4 Output Load Circuit
26.7.2 Clock Timing
tCH
tcyc
tCf
tCL tCr
φ
Figure 26.5 System Clock Timing
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 912 of 1130
REJ09B0327-0400
t
OSC1
t
OSC1
EXTAL
V
CC
STBY
RES
φ
t
DEXT
t
DEXT
Figure 26.6 Oscillatio n Set t ling Timing
26.7.3 Control Signal Timing
φ
NMI
IRQi
(i = 0, 1, 2, 6, 7)
t
OSC2
Figure 26.7 Oscillation Setting Timing (Ex it ing Software St andby Mode)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 913 of 1130
REJ09B0327-0400
tRESW
tRESS
φ
tRESS
RES
Figure 26.8 Reset Input Timing
t
IRQS
φ
t
NMIS
t
NMIH
IRQ
Edge input
NMI
t
IRQS
t
IRQH
IRQi
(i = 7 to 0)
IRQ
Level input
t
NMIW
t
IRQW
Figure 26. 9 Interrupt Input Timi ng
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 914 of 1130
REJ09B0327-0400
26.7.4 Bus Timing
t
RSD2
φ
T
1
t
AD
t
CSD
AS*
A23 to A0,
IOS*
Note: *AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
t
ASD
RD
(read)
T
2
t
AS
t
ASD
t
ACC2
t
RSD1
t
ACC3
t
RDS
t
WRD2
t
WRD2
t
WDD
t
WSW1
t
WDH
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
t
AH
t
AH
t
AS
t
AS
t
RDH
Figure 26.10 Basic Bus Timing (Two-State Access)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 915 of 1130
REJ09B0327-0400
t
RSD2
φ
T
2
AS*
A23 to A0,
IOS*
t
ASD
RD
(read)
T
3
t
AS
t
ASD
t
ACC4
t
RSD1
t
ACC5
t
RDS
t
WRD1
t
WRD2
t
WDS
t
WSW2
t
WDH
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
T
1
t
WDD
t
AD
t
CSD
Note: *AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
t
AH
t
AH
t
AS
t
RDH
Figure 26.11 Basic Bus Timing (Three-State Access)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 916 of 1130
REJ09B0327-0400
φ
T
W
AS*
A23 to A0,
IOS*
RD
(read)
T
3
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
T
2
t
WTS
T
1
t
WTH
t
WTS
t
WTH
WAIT
Note: *AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 26.12 Basic Bus Timing (Three-State Access with One Wait State)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 917 of 1130
REJ09B0327-0400
t
RSD2
φ
T
1
AS*
A23 to A0,
IOS*
T
2
t
AH
t
ACC3
t
RDS
D15 to D0
(read)
T
2
or T
3
t
AS
T
1
t
ASD
t
ASD
t
RDH
t
AD
RD
(read)
Note: *AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 26.13 Burst ROM Access Timing (Two-State Access)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 918 of 1130
REJ09B0327-0400
t
RSD2
φ
T
1
AS*
A23 to A0,
IOS*
T
1
t
ACC1
D15 to D0
(read)
T
2
or T
3
t
RDH
t
AD
RD
(read) t
RDS
Note: *AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 26.14 Burst ROM Access Timing (One-State Access)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 919 of 1130
REJ09B0327-0400
26.7 .5 Timing o f On-Chip Supporting Modules
φ
Ports 1 to 9, A, B
(read)
T
2
T
1
t
PWD
t
PRH
t
PRS
Ports 1 to 6, 8, 9, A, B
(write)
Figure 26. 15 I/O Port Input/Out put Timing
φ
t
FTIS
t
FTOD
FTOA, FTOB
FTIA, FTIB,
FTIC, FTID
Figure 26 .16 FRT Input/O utput Timing
φ
t
FTCS
FTCI
t
FTCWH
t
FTCWL
Figure 26 . 17 FRT Clock Input Timing
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 920 of 1130
REJ09B0327-0400
φ
TMO0, TMO1
TMOX
t
TMOD
Figure 26.18 8-Bit Timer Output Timing
φ
TMCI0, TMCI1
TMIX, TMIY
t
TMCS
t
TMCS
t
TMCWH
t
TMCWL
Figure 26 . 19 8-Bit Timer Clock Input Timing
φ
TMRI0, TMRI1
TMIX, TMIY
t
TMRS
Figure 26 . 20 8-Bit Timer Reset I nput Timing
φ
PW15 to PW0,
PWX1 to PWX0
t
PWOD
Figure 26.21 PWM, PWMX Output Timing
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 921 of 1130
REJ09B0327-0400
SCK0 to SCK2
tSCKW tSCKr tSCKf
tScyc
Figure 26. 22 SCK Clock Input Timing
TxD0 to TxD2
(transmit data)
RxD0 to RxD2
(receive data)
SCK0 to SCK2
t
RXS
t
RXH
t
TXD
Figure 26 . 23 SCI Input/Output Timing (Synchronous Mode)
φ
ADTRG
t
TRGS
Figure 26.24 A/D Converter Ext ernal Trigger Input Timing
t
RESOW
t
RESD
t
RESD
φ
RESO
Figure 26.25 WDT Output Timing (RESO
RESORESO
RESO)
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 922 of 1130
REJ09B0327-0400
CS/HA0
IOR
HDB7 to HDB0 Valid data
HIRQi*
(i = 1, 3, 4, 11, 12)
t
HAR
t
HRPW
t
HRA
t
HRF
t
HIRQ
t
HRD
CS/HA0
IOW
HDB7 to HDB0
GA20
t
HAW
t
HWPW
t
HWA
t
HWD
t
HGA
t
HDW
Host interface read timing
Note: * The rising edge timing is the same as the port 4 and port B output timing.
See figure 26.15.
Host interface write timing
Figure 26.26 Host Interface Timing
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 923 of 1130
REJ09B0327-0400
1. Reception
φ
KCLK/
KD*
KCLK/
KD*
t
KBIS
t
KBIH
Transmission (b)
t
KBF
2. Transmission (a)
φ
KCLK/
KD*
T1 T2
t
KBOD
Note: φ shown here is the clock scaled by 1/N when the operating mode is active
medium-speed mode.
* KCLK: PS2AC to PS2CC
KD: PS2AD to PS2CD
Figure 26.27 Keyboard Buffer Controller Timing
Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 924 of 1130
REJ09B0327-0400
SDA0,
SDA1 V
IL
V
IH
t
BUF
P*P*
S*
t
STAH
t
SCLH
t
Sr
t
SCLL
t
SCL
t
Sf
t
of
t
SDAH
Sr*
t
SDAS
t
STAS
t
SP
t
STOS
Note: *S, P, and Sr indicate the following conditions.
S:
P:
Sr:
Start condition
Stop condition
Retransmission start condition
SCL0,
SCL1
Figure 26.28 I2C Bus Interface Input/Output Timing (O pt ion)
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 925 of 1130
REJ09B0327-0400
Appendi x A Instructi on Set
A.1 Instruction
Operation Notation
Rd General register (destination )*1
Rs General register (source)*1
Rn General register*1
ERn General register (32-bi t register)
MAC Multiply-and-accumulate register (32-bit register)*2
(EAd) Destination operand
(EAs) Source operand
EXR Extend register
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷ Division
∧Logical AND
∨Logical OR
⊕Exclusi ve log ical OR
→Transfer from left-hand operand to right-hand operand, or transition from left-
hand state to right-hand state
¬ NOT (logical complement)
( ) < > Operand contents
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
2. MAC instructions cannot be used in this LSI.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 926 of 1130
REJ09B0327-0400
Condition Code Notatio n
Symbol Meaning
Changes according operation result.
*Indeterminate (value not guaranteed).
0 Always cleared to 0.
1 Always set to 1.
— Not affected by operation result.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 927 of 1130
REJ09B0327-0400
Table A.1 Instruction Set
1. Data Transfer Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
MOV MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
#xx:8→Rd8
Rs8→Rd8
@ERs→Rd8
@(d:16,ERs)→Rd8
@(d:32,ERs)→Rd8
@ERs→Rd8,ERs32+1→ERs32
@aa:8→Rd8
@aa:16→Rd8
@aa:32→Rd8
Rs8→@ERd
Rs8→@(d:16,ERd)
Rs8→@(d:32,ERd)
ERd32-1→ERd32,Rs8→@ERd
Rs8→@aa:8
Rs8→@aa:16
Rs8→@aa:32
#xx:16→Rd16
Rs16→Rd16
@ERs→Rd16
@(d:16,ERs)→Rd16
@(d:32,ERs)→Rd16
@ERs→Rd16,ERs32+2→ERs32
@aa:16→Rd16
@aa:32→Rd16
Rs16→@ERd
Rs16→@(d:16,ERd)
Rs16→@(d:32,ERd)
ERd32-2→ERd32,Rs16→@ERd
Rs16→@aa:16
Rs16→@aa:32
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
W
W
2
4
2
2
2
2
2
2
4
8
4
8
4
8
4
8
2
2
2
2
2
4
6
2
4
6
4
6
4
6
—
—
—
—
—
—
—
—
—
——
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
2
3
5
3
2
3
4
2
3
5
3
2
3
4
2
1
2
3
5
3
3
4
2
3
5
3
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
——
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 928 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
MOV
POP
PUSH
LDM*
4
STM*
4
MOVFPE
MOVTPE
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
LDM @SP+,(ERm-ERn)
STM (ERm-ERn),@-SP
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
#xx:32→ERd32
ERs32→ERd32
@ERs→ERd32
@(d:16,ERs)→ERd32
@(d:32,ERs)→ERd32
@ERs→ERd32,ERs32+4→ERs32
@aa:16→ERd32
@aa:32→ERd32
ERs32→@ERd
ERs32→@(d:16,ERd)
ERs32→@(d:32,ERd)
ERd32-4→ERd32,ERs32→@ERd
ERs32→@aa:16
ERs32→@aa:32
@SP→Rn16,SP+2→SP
@SP→ERn32,SP+4→SP
SP-2→SP,Rn16→@SP
SP-4→SP,ERn32→@SP
(@SP→ERn32,SP+4→SP)
Repeated for each restored register.
(SP-4→SP,ERn32→@SP)
Repeated for each saved register.
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
W
L
L
L
6
2
4
4
6
10
6
10
4
4
6
8
6
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
1
4
5
7
5
5
6
4
5
7
5
5
6
3
5
3
5
7/9/11 [1]
7/9/11 [1]
[2]
[2]
2
4
2
4
4
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
Size
Cannot be used with this LSI.
—
—
—
—
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 929 of 1130
REJ09B0327-0400
2. Arithmetic Instr u ctions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
ADD
ADDX
ADDS
INC
DAA
SUB
SUBX
SUBS
DEC
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
DAA Rd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
Rd8+#xx:8→Rd8
Rd8+Rs8→Rd8
Rd16+#xx:16→Rd16
Rd16+Rs16→Rd16
ERd32+#xx:32→ERd32
ERd32+ERs32→ERd32
Rd8+#xx:8+C→Rd8
Rd8+Rs8+C→Rd8
ERd32+1→ERd32
ERd32+2→ERd32
ERd32+4→ERd32
Rd8+1→Rd8
Rd16+1→Rd16
Rd16+2→Rd16
ERd32+1→ERd32
ERd32+2→ERd32
Rd8 decimal adjust →Rd8
Rd8-Rs8→Rd8
Rd16-#xx:16→Rd16
Rd16-Rs16→Rd16
ERd32-#xx:32→ERd32
ERd32-ERs32→ERd32
Rd8-#xx:8-C→Rd8
Rd8-Rs8-C→Rd8
ERd32-1→ERd32
ERd32-2→ERd32
ERd32-4→ERd32
Rd8-1→Rd8
Rd16-1→Rd16
Rd16-2→Rd16
ERd32-1→ERd32
ERd32-2→ERd32
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
2
4
6
2
4
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
2
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
3
1
1
1
1
1
1
1
1
1
1
1
—
—
—
*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
*
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
[5]
[5]
—
—
—
[5]
[5]
—
—
—
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 930 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
NEG
EXTU
EXTS
TAS
DAS Rd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS.B Rs,Rd
MULXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
TAS @ERd
*3
Rd8 decimal adjust →Rd8
Rd8×Rs8→Rd16 (unsigned
multiplication)
Rd16×Rs16→ERd32 (unsigned
multiplication)
Rd8×Rs8→Rd16 (signed
multiplication)
Rd16×Rs16→ERd32 (signed
multiplication)
Rd16÷Rs8→Rd16
(RdH: remainder, RdL: quotient)
(unsigned division)
ERd32÷Rs16→ERd32
(Ed: remainder, Rd: quotient)
(unsigned division)
Rd16÷Rs8→Rd16
(RdH: remainder, RdL: quotient)
(signed division)
ERd32÷Rs16→ERd32
(Ed: remainder, Rd: quotient)
(signed division)
Rd8-#xx:8
Rd8-Rs8
Rd16-#xx:16
Rd16-Rs16
ERd32-#xx:32
ERd32-ERs32
0-Rd8→Rd8
0-Rd16→Rd16
0-ERd32→ERd32
0 → (<bits 15 to 8> of Rd16)
0 → (<bits 31 to 16> of ERd32)
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
(<bits 31 to 16> of ERd32)
@ERd-0 → CCR set, (1) →
(<bit 7> of @ERd)
B
B
W
B
W
B
W
B
W
B
B
W
W
L
L
B
W
L
W
L
W
L
B
2
2
2
4
4
2
2
4
4
2
2
2
2
2
2
2
2
2
2
1
12
20
13
21
12
20
13
21
1
1
2
1
3
1
1
1
1
1
1
1
1
4
——
Operation
Condition Code No. of
States*
1
Normal
Advanced
*
Size
*
4
2
4
6
————— —
————— —
——— —
——— —
[7] ———[6] —
[7] ———[6] —
[7] ———[8] —
[7] ———[8] —
—
—
— [3]
— [3]
— [4]
— [4]
—
—
—
——— 00
——— 00
——— 0
——— 0
——— 0
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 931 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
MAC
CLRMAC
LDMAC
STMAC
MAC @ERn+,@ERm+
CLRMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
STMAC MACH,ERd
STMAC MACL,ERd
Cannot be used with this LSI. [2]
Operation
Condition Code No. of
States*
1
Normal
Advanced
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 932 of 1130
REJ09B0327-0400
3. Logic Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
AND
OR
XOR
NOT
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
Rd8∧#xx:8→Rd8
Rd8∧Rs8→Rd8
Rd16∧#xx:16→Rd16
Rd16∧Rs16→Rd16
ERd32∧#xx:32→ERd32
ERd32∧ERs32→ERd32
Rd8∨#xx:8→Rd8
Rd8∨Rs8→Rd8
Rd16∨#xx:16→Rd16
Rd16∨Rs16→Rd16
ERd32∨#xx:32→ERd32
ERd32∨ERs32→ERd32
Rd8⊕#xx:8→Rd8
Rd8⊕Rs8→Rd8
Rd16⊕#xx:16→Rd16
Rd16⊕Rs16→Rd16
ERd32⊕#xx:32→ERd32
ERd32⊕ERs32→ERd32
¬ Rd8→Rd8
¬ Rd16→Rd16
¬ ERd32→ERd32
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
4
6
2
4
6
2
4
6
2
2
4
2
2
4
2
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
2
1
3
2
1
1
2
1
3
2
1
1
2
1
3
2
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 933 of 1130
REJ09B0327-0400
4. Shift Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
SHAL
SHAR
SHLL
SHLR
ROTXL
SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
Size
CMSB LSB
0
C
0
MSB LSB
0
C
MSB LSB
C
MSB LSB
CMSB LSB
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 934 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
ROTXR
ROTL
ROTR
ROTXR.B Rd
ROTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
Size
C
MSB LSB
CMSB LSB
C
MSB LSB
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 935 of 1130
REJ09B0327-0400
5. Bit-Manipulation Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
BSET
BCLR
BNOT
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
(#xx:3 of Rd8)←1
(#xx:3 of @ERd)←1
(#xx:3 of @aa:8)←1
(#xx:3 of @aa:16)←1
(#xx:3 of @aa:32)←1
(Rn8 of Rd8)←1
(Rn8 of @ERd)←1
(Rn8 of @aa:8)←1
(Rn8 of @aa:16)←1
(Rn8 of @aa:32)←1
(#xx:3 of Rd8)←0
(#xx:3 of @ERd)←0
(#xx:3 of @aa:8)←0
(#xx:3 of @aa:16)←0
(#xx:3 of @aa:32)←0
(Rn8 of Rd8)←0
(Rn8 of @ERd)←0
(Rn8 of @aa:8)←0
(Rn8 of @aa:16)←0
(Rn8 of @aa:32)←0
(#xx:3 of Rd8)← [¬ (#xx:3 of Rd8)]
(#xx:3 of @ERd)← [¬ (#xx:3
of @ERd)]
(#xx:3 of @aa:8)← [¬ (#xx:3
of @aa:8)]
(#xx:3 of @aa:16)← [¬ (#xx:3
of @aa:16)]
(#xx:3 of @aa:32)← [¬ (#xx:3
of @aa:32)]
(Rn8 of Rd8)← [¬ (Rn8 of Rd8)]
(Rn8 of @ERd)← [¬ (Rn8 of @ERd)]
(Rn8 of @aa:8)← [¬ (Rn8 of @aa:8)]
(Rn8 of @aa:16)← [¬ (Rn8
of @aa:16)]
(Rn8 of @aa:32)← [¬ (Rn8
of @aa:32)]
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
4
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 936 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
BTST
BLD
BILD
BST
BIST
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
¬ (#xx:3 of Rd8)→Z
¬ (#xx:3 of @ERd)→Z
¬ (#xx:3 of @aa:8)→Z
¬ (#xx:3 of @aa:16)→Z
¬ (#xx:3 of @aa:32)→Z
¬ (Rn8 of Rd8)→Z
¬ (Rn8 of @ERd)→Z
¬ (Rn8 of @aa:8)→Z
¬ (Rn8 of @aa:16)→Z
¬ (Rn8 of @aa:32)→Z
(#xx:3 of Rd8)→C
(#xx:3 of @ERd)→C
(#xx:3 of @aa:8)→C
(#xx:3 of @aa:16)→C
(#xx:3 of @aa:32)→C
¬ (#xx:3 of Rd8)→C
¬ (#xx:3 of @ERd)→C
¬ (#xx:3 of @aa:8)→C
¬ (#xx:3 of @aa:16)→C
¬ (#xx:3 of @aa:32)→C
C→(#xx:3 of Rd8)
C→(#xx:3 of @ERd)
C→(#xx:3 of @aa:8)
C→(#xx:3 of @aa:16)
C→(#xx:3 of @aa:32)
¬ C→(#xx:3 of Rd8)
¬ C→(#xx:3 of @ERd)
¬ C→(#xx:3 of @aa:8)
¬ C→(#xx:3 of @aa:16)
¬ C→(#xx:3 of @aa:32)
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
4
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
4
4
5
6
1
4
4
5
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 937 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
BAND
BIAND
BOR
BIOR
BXOR
BIXOR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
C∧ (#xx:3 of Rd8)→C
C∧ (#xx:3 of @ERd)→C
C∧ (#xx:3 of @aa:8)→C
C∧ (#xx:3 of @aa:16)→C
C∧ (#xx:3 of @aa:32)→C
C∧ [¬ (#xx:3 of Rd8)]→C
C∧ [¬ (#xx:3 of @ERd)]→C
C∧ [¬ (#xx:3 of @aa:8)]→C
C∧ [¬ (#xx:3 of @aa:16)]→C
C∧ [¬ (#xx:3 of @aa:32)]→C
C∨ (#xx:3 of Rd8)→C
C∨ (#xx:3 of @ERd)→C
C∨ (#xx:3 of @aa:8)→C
C∨ (#xx:3 of @aa:16)→C
C∨ (#xx:3 of @aa:32)→C
C∨ [¬ (#xx:3 of Rd8)]→C
C∨ [¬ (#xx:3 of @ERd)]→C
C∨ [¬ (#xx:3 of @aa:8)]→C
C∨ [¬ (#xx:3 of @aa:16)]→C
C∨ [¬ (#xx:3 of @aa:32)]→C
C⊕ (#xx:3 of Rd8)→C
C⊕ (#xx:3 of @ERd)→C
C⊕ (#xx:3 of @aa:8)→C
C⊕ (#xx:3 of @aa:16)→C
C⊕ (#xx:3 of @aa:32)→C
C⊕ [¬ (#xx:3 of Rd8)]→C
C⊕ [¬ (#xx:3 of @ERd)]→C
C⊕ [¬ (#xx:3 of @aa:8)]→C
C⊕ [¬ (#xx:3 of @aa:16)]→C
C⊕ [¬ (#xx:3 of @aa:32)]→C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
4
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 938 of 1130
REJ09B0327-0400
6. Branch Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
Bcc BRA d:8(BT d:8)
BRA d:16(BT d:16)
BRN d:8(BF d:8)
BRN d:16(BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8(BHS d:8)
BCC d:16(BHS d:16)
BCS d:8(BLO d:8)
BCS d:16(BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
if condition is true then
PC←PC+d
else next;
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
Always
Never
C∨Z=0
C∨Z=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V=0
N⊕V=1
Z∨(N⊕V)=0
Z∨(N⊕V)=1
Branch
Condition
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 939 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
JMP
BSR
JSR
RTS
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
PC←ERn
PC←aa:24
PC←@aa:8
PC→@-SP,PC←PC+d:8
PC→@-SP,PC←PC+d:16
PC→@-SP,PC←ERn
PC→@-SP,PC←aa:24
PC→@-SP,PC←@aa:8
PC←@SP+
—
—
—
—
—
—
—
—
—
2
2
4
4
—
—
—
—
—
—
—
—
—
2
3
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
4
3
4
3
4
4
4
5
4
5
4
5
6
5
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 940 of 1130
REJ09B0327-0400
7. System Control Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
TRAPA
RTE
SLEEP
LDC
TRAPA #xx:2
RTE
SLEEP
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
PC→@-SP,CCR→@-SP,
EXR→@-SP,<vector>→PC
EXR←@SP+,CCR←@SP+,
PC←@SP+
Transition to power-down state
#xx:8→CCR
#xx:8→EXR
Rs8→CCR
Rs8→EXR
@ERs→CCR
@ERs→EXR
@(d:16,ERs)→CCR
@(d:16,ERs)→EXR
@(d:32,ERs)→CCR
@(d:32,ERs)→EXR
@ERs→CCR,ERs32+2→ERs32
@ERs→EXR,ERs32+2→ERs32
@aa:16→CCR
@aa:16→EXR
@aa:32→CCR
@aa:32→EXR
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
2
4
2
2
4
4
6
6
10
10
4
4
6
6
8
8
1
—
—
—
—
—
—
—
—
—
7 [9]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
5 [9]
2
1
2
1
1
3
3
4
4
6
6
4
4
4
4
5
5
8 [9]
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 941 of 1130
REJ09B0327-0400
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
STC
ANDC
ORC
XORC
NOP
STC CCR,Rd
STC EXR,Rd
STC CCR,@ERd
STC EXR,@ERd
STC CCR,@(d:16,ERd)
STC EXR,@(d:16,ERd)
STC CCR,@(d:32,ERd)
STC EXR,@(d:32,ERd)
STC CCR,@-ERd
STC EXR,@-ERd
STC CCR,@aa:16
STC EXR,@aa:16
STC CCR,@aa:32
STC EXR,@aa:32
ANDC #xx:8,CCR
ANDC #xx:8,EXR
ORC #xx:8,CCR
ORC #xx:8,EXR
XORC #xx:8,CCR
XORC #xx:8,EXR
NOP
CCR→Rd8
EXR→Rd8
CCR→@ERd
EXR→@ERd
CCR→@(d:16,ERd)
EXR→@(d:16,ERd)
CCR→@(d:32,ERd)
EXR→@(d:32,ERd)
ERd32-2→ERd32,CCR→@ERd
ERd32-2→ERd32,EXR→@ERd
CCR→@aa:16
EXR→@aa:16
CCR→@aa:32
EXR→@aa:32
CCR∧#xx:8→CCR
EXR∧#xx:8→EXR
CCR∨#xx:8→CCR
EXR∨#xx:8→EXR
CCR⊕#xx:8→CCR
EXR⊕#xx:8→EXR
PC←PC+2
B
B
W
W
W
W
W
W
W
W
W
W
W
W
B
B
B
B
B
B
—
2
4
2
4
2
4
2
2
4
4
6
6
10
10
4
4
6
6
8
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
3
3
4
4
6
6
4
4
4
4
5
5
1
2
1
2
1
2
1
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code No. of
States*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 942 of 1130
REJ09B0327-0400
8. Block Transfer Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
EEPMOV EEPMOV.B
EEPMOV.W
if R4L≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L-1→R4L
Until R4L=0
else next;
if R4≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4-1→R4
Until R4=0
else next;
—
—
—
—
4+2n*2
4+2n*2
4
4
—
—
—
—
—
—
Operation
Condition Code No. of
States*1
Normal
Advanced
—
—
—
—
Size
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory.
2. n is the initial value set in R4L or R4.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
4. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
[1] 7 states when the number of saved/restored registers is 2, 9 states when 3, and 11
states when 4.
[2] Cannot be used with this LSI.
[3] Set to 1 when there is a carry from or borrow to bit 11; otherwise cleared to 0.
[4] Set to 1 when there is a carry from or borrow to bit 27; otherwise cleared to 0.
[5] If the result is zero, the previous value of the flag is retained; otherwise the fl ag is
cleared to 0.
[6] Set to 1 if the divisor is negative; otherwise cleared to 0.
[7] Set to 1 if the divisor is zero; otherwise cleared to 0.
[8] Set to 1 if the quotient is negative; otherwise cleared to 0.
[9] When EXR is valid, the number of states is increased by 1.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 943 of 1130
REJ09B0327-0400
A.2 Instruction Codes
Table A.2 Instruction Codes
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
B
B
W
W
L
L
L
L
L
B
B
B
B
W
W
L
L
B
B
B
B
B
B
B
—
—
—
—
1
0
0
ers
IMM
erd
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
ers
IMM
IMM
0erd
0IMM
0IMM
0
0
0
8
0
7
0
7
0
0
0
0
9
0
E
1
7
6
7
0
0
0
7
7
7
6
6
4
5
4
5
rd
8
9
9
A
A
B
B
B
rd
E
rd
6
9
6
A
1
6
1
6
C
E
A
A
0
8
1
8
rd
rd
rd
rd
rd
rd
rd
0
1
rd
0
0
0
0
0
6
0
7
7
6
6
6
6
0
0
76 0
76 0
IMM
IMM
IMM
IMM
abs
disp
disp
rs
1
rs
1
0
8
9
rs
rs
6
rs
6
F
4
1
3
0
1
IMM
IMM
abs
disp
disp
IMM
IMM
abs
IMM
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 944 of 1130
REJ09B0327-0400
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
Bcc —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
8
A
8
B
8
C
8
D
8
E
8
F
8
2
3
4
5
6
7
8
9
A
B
C
D
E
F
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 945 of 1130
REJ09B0327-0400
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
BCLR
BIAND
BILD
BIOR
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
0
0
0
1
0
1
0
1
0
IMM
erd
erd
IMM
erd
IMM
erd
IMM
erd
0
1
1
1
IMM
IMM
IMM
IMM
0
1
1
1
IMM
IMM
IMM
IMM
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
2
D
F
A
A
2
D
F
A
A
6
C
E
A
A
7
C
E
A
A
4
C
E
A
A
1
3
rn
1
3
1
3
1
3
1
3
rd
0
8
8
rd
0
8
8
rd
0
0
0
rd
0
0
0
rd
0
0
0
7
7
6
6
7
7
7
7
7
7
2
2
2
2
6
6
7
7
4
4
rn
rn
0
0
0
0
0
0
0
0
0
0
7
6
7
7
7
2
2
6
7
4
rn
0
0
0
0
0
7
6
7
7
7
2
2
6
7
4
rn
0
0
0
0
0
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
0
0
1
1
1
1
1
1
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 946 of 1130
REJ09B0327-0400
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
BIST
BIXOR
BLD
BNOT
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
1
0
1
0
0
0
0
0
0
IMM
erd
IMM
erd
IMM
erd
IMM
erd
erd
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
1
1
0
0
IMM
IMM
IMM
IMM
1
1
0
0
IMM
IMM
IMM
IMM
1
1
1
1
0
0
0
0
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
7
D
F
A
A
5
C
E
A
A
7
C
E
A
A
1
D
F
A
A
1
D
F
A
A
1
3
1
3
1
3
1
3
rn
1
3
rd
0
8
8
rd
0
0
0
rd
0
0
0
rd
0
8
8
rd
0
8
8
6
6
7
7
7
7
7
7
6
6
7
7
5
5
7
7
1
1
1
1
rn
rn
0
0
0
0
0
0
0
0
0
0
6
7
7
7
6
7
5
7
1
1rn
0
0
0
0
0
6
7
7
7
6
7
5
7
1
1rn
0
0
0
0
0
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 947 of 1130
REJ09B0327-0400
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BSR d:8
BSR d:16
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
BOR
BSET
BSR
BST
BTST
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
—
—
B
B
B
B
B
B
B
B
B
B
B
B
0
0
0
0
0
0
0
0
0
0
IMM
erd
IMM
erd
erd
IMM
erd
IMM
erd
erd
abs
abs
abs
disp
abs
abs
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
0
0
0
0
IMM
IMM
IMM
IMM
0
0
0
0
IMM
IMM
IMM
IMM
0
0
0
0
0
0
0
0
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
5
5
6
7
7
6
6
7
7
7
6
6
6
7
4
C
E
A
A
0
D
F
A
A
0
D
F
A
A
5
C
7
D
F
A
A
3
C
E
A
A
3
C
1
3
1
3
rn
1
3
0
1
3
1
3
rn
rd
0
0
0
rd
0
8
8
rd
0
8
8
0
rd
0
8
8
rd
0
0
0
rd
0
7
7
7
7
6
6
6
6
7
7
6
4
4
0
0
0
0
7
7
3
3
3
rn
rn
rn
0
0
0
0
0
0
0
0
0
0
0
7
7
6
6
7
4
0
0
7
3
rn
0
0
0
0
0
7
7
6
6
7
4
0
0
7
3
rn
0
0
0
0
0
abs
abs
abs
disp
abs
abs
abs
abs
abs
abs
abs
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 948 of 1130
REJ09B0327-0400
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
CLRMAC
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
DAA Rd
DAS Rd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
EEPMOV.B
EEPMOV.W
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
BTST
BXOR
CLRMAC
CMP
DAA
DAS
DEC
DIVXS
DIVXU
EEPMOV
B
B
B
B
B
B
B
B
—
B
B
W
W
L
L
B
B
B
W
W
L
L
B
W
B
W
—
—
0
0
1
IMM
erd
ers
0
0
0
0
0
erd
erd
erd
erd
erd
IMM
IMM
0 erd
0 IMM
0 IMM
0
0
7
6
6
7
7
7
6
6
A
1
7
1
7
1
0
1
1
1
1
1
1
0
0
5
5
7
7
E
A
A
5
C
E
A
A
rd
C
9
D
A
F
F
F
A
B
B
B
B
1
1
1
3
B
B
1
3
1
3
rs
2
rs
2
0
0
0
5
D
7
F
D
D
rs
rs
5
D
0
0
rd
0
0
0
rd
rd
rd
rd
rd
rd
rd
rd
0
0
rd
C
4
6
7
7
5
5
5
5
3
5
5
1
3
9
9
rn
rs
rs
8
8
0
0
0
rd
F
F
6
7
3
5
rn 0
0
6
7
3
5
rn 0
0
abs
abs
IMM
abs
abs
IMM
abs
abs
IMM
Cannot be used with this LSI.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 949 of 1130
REJ09B0327-0400
EXTS.W Rd
EXTS.L ERd
EXTU.W Rd
EXTU.L ERd
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
JMP @ERn
JMP @aa:24
JMP @@aa:8
JSR @ERn
JSR @aa:24
JSR @@aa:8
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
EXTS
EXTU
INC
JMP
JSR
LDC
W
L
W
L
B
W
W
L
L
—
—
—
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
0
0
ern
ern
0
0
0
0
erd
erd
erd
erd
ers
ers
ers
ers
ers
ers
ers
ers
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
5
5
5
5
5
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
7
7
A
B
B
B
B
9
A
B
D
E
F
7
1
3
3
1
1
1
1
1
1
1
1
1
1
D
F
5
7
0
5
D
7
F
4
0
1
4
4
4
4
4
4
4
4
4
4
rd
rd
rd
rd
rd
0
0
1
rs
rs
0
1
0
1
0
1
0
1
0
1
0
6
6
6
6
7
7
6
6
6
6
7
9
9
F
F
8
8
D
D
B
B
0
0
0
0
0
0
0
0
0
0
0
0
6
6
B
B
2
2
0
0
abs
abs
abs
abs
IMM
IMM
disp
disp
abs
abs
disp
disp
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 950 of 1130
REJ09B0327-0400
0
0
rd
abs
rs
rd
LDC @aa:32,CCR
LDC @aa:32,EXR
LDM.L @SP+, (ERn-ERn+1)
LDM.L @SP+, (ERn-ERn+2)
LDM.L @SP+, (ERn-ERn+3)
LDMAC ERs,MACH
LDMAC ERs,MACL
MAC @ERn+,@ERm+
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
LDC
LDM*3
LDMAC
MAC
MOV
W
W
L
L
L
L
L
—
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
0
0
0
0
1
1
0
1
0
0
0
ers
ers
ers
ers
erd
erd
erd
erd
ers
ers
ers
0
0
0
ern+1
ern+2
ern+3
0
0
0
0
0
F
0
6
6
7
6
2
6
6
6
6
7
6
3
6
6
7
0
6
6
7
1
1
1
1
1
rd
C
8
E
8
C
rd
A
A
8
E
8
C
rs
A
A
9
D
9
F
8
4
4
1
2
3
rs
0
2
8
A
0
rs
0
1
0
0
0
rd
rd
rd
0
rd
rd
rd
rs
rs
0
rs
rs
rs
rd
rd
rd
rd
0
6
6
6
6
6
6
6
6
B
B
D
D
D
A
A
B
2
2
7
7
7
2
A
2
IMM
abs
abs
disp
abs
disp
abs
IMM
disp
abs
abs
abs
abs
disp
disp
disp
Cannot be used with this LSI.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 951 of 1130
REJ09B0327-0400
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,Rd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16 ,ERd
MOV.L @aa:32 ,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
*1
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
MOV
MOVFPE
MOVTPE
MULXS
MULXU
W
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
B
B
B
W
B
W
0
1
1
0
1
1
ers
erd
erd
erd
erd
ers
0
0
0
erd
erd
erd
ers
ers
ers
ers
erd
erd
erd
erd
0
0
0
0
0
0
0
0
0
0
0
erd
erd
erd
erd
erd
ers
ers
ers
ers
ers
erd
0
0
erd
ers
0
0
0
0
1
1
0
1
6
6
6
6
6
7
6
6
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
D
B
B
9
F
8
D
B
B
A
F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
0
2
8
A
0
0
0
0
0
0
0
0
0
0
0
0
0
C
C
rs
rs
rd
rd
rd
rs
rs
0
rs
rs
rs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rd
6
6
6
7
6
6
6
6
6
7
6
6
6
5
5
B
9
F
8
D
B
B
9
F
8
D
B
B
0
2
A
0
2
8
A
rs
rs
rs
0
0
rd
6
6
B
B
2
A
abs
disp
abs
abs
abs
IMM
disp
abs
disp
abs
disp
abs
abs
disp
disp
Cannot be used with this LSI.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 952 of 1130
REJ09B0327-0400
NEG.B Rd
NEG.W Rd
NEG.L ERd
NOP
NOT.B Rd
NOT.W Rd
NOT.L ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
ORC #xx:8,CCR
ORC #xx:8,EXR
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
ROTL.B Rd
ROTL.B #2, Rd
ROTL.W Rd
ROTL.W #2, Rd
ROTL.L ERd
ROTL.L #2, ERd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
NEG
NOP
NOT
OR
ORC
POP
PUSH
ROTL
B
W
L
—
B
W
L
B
B
W
W
L
L
B
B
W
L
W
L
B
B
W
W
L
L
0
0
0
0
0
erd
erd
erd
erd
erd
1
1
1
0
1
1
1
C
1
7
6
7
0
0
0
6
0
6
0
1
1
1
1
1
1
7
7
7
0
7
7
7
rd
4
9
4
A
1
4
1
D
1
D
1
2
2
2
2
2
2
8
9
B
0
0
1
3
rs
4
rs
4
F
4
7
0
F
0
8
C
9
D
B
F
rd
rd
0
rd
rd
rd
rd
rd
0
1
rn
0
rn
0
rd
rd
rd
rd
IMM
IMM
6
0
6
6
4
4
D
D
ers 0
0
0
erd
ern
ern
0
7
F
IMM
IMM
IMM
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 953 of 1130
REJ09B0327-0400
ROTR.B Rd
ROTR.B #2, Rd
ROTR.W Rd
ROTR.W #2, Rd
ROTR.L ERd
ROTR.L #2, ERd
ROTXL.B Rd
ROTXL.B #2, Rd
ROTXL.W Rd
ROTXL.W #2, Rd
ROTXL.L ERd
ROTXL.L #2, ERd
ROTXR.B Rd
ROTXR.B #2, Rd
ROTXR.W Rd
ROTXR.W #2, Rd
ROTXR.L ERd
ROTXR.L #2, ERd
RTE
RTS
SHAL.B Rd
SHAL.B #2, Rd
SHAL.W Rd
SHAL.W #2, Rd
SHAL.L ERd
SHAL.L #2, ERd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
ROTR
ROTXL
ROTXR
RTE
RTS
SHAL
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
—
B
B
W
W
L
L
0
0
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
erd
erd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
1
1
1
1
1
1
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
3
3
3
6
4
0
0
0
0
0
0
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
7
7
8
C
9
D
B
F
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
0
0
rd
rd
rd
rd
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 954 of 1130
REJ09B0327-0400
SHAR.B Rd
SHAR.B #2, Rd
SHAR.W Rd
SHAR.W #2, Rd
SHAR.L ERd
SHAR.L #2, ERd
SHLL.B Rd
SHLL.B #2, Rd
SHLL.W Rd
SHLL.W #2, Rd
SHLL.L ERd
SHLL.L #2, ERd
SHLR.B Rd
SHLR.B #2, Rd
SHLR.W Rd
SHLR.W #2, Rd
SHLR.L ERd
SHLR.L #2, ERd
SLEEP
STC.B CCR,Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
SHAR
SHLL
SHLR
SLEEP
STC
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
B
B
W
W
W
W
W
W
W
W
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
8
0
1
4
4
4
4
4
4
4
4
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
0
rd
rd
0
1
0
1
0
1
0
1
erd
erd
erd
erd
erd
erd
erd
erd
1
1
1
1
0
0
1
1
6
6
6
6
7
7
6
6
9
9
F
F
8
8
D
D
0
0
0
0
0
0
0
0
6
6
B
B
A
A
0
0
disp
disp
disp
disp
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 955 of 1130
REJ09B0327-0400
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
STM.L (ERn-ERn+1), @-SP
STM.L (ERn-ERn+2), @-SP
STM.L (ERn-ERn+3), @-SP
STMAC MACH,ERd
STMAC MACL,ERd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
TAS @ERd*
2
TRAPA #x:2
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
Mnemonic Size Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte
Instruc-
tion
STC
STM*
3
STMAC
SUB
SUBS
SUBX
TAS
TRAPA
XOR
W
W
W
W
L
L
L
L
L
B
W
W
L
L
L
L
L
B
B
B
—
B
B
W
W
L
L
1
00
ers
IMM
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
erd
ers
0
0
0
0
ern
ern
ern
erd
0
0
0
0
0
0
0
0
0
1
7
1
7
1
1
1
1
B
1
0
5
D
1
7
6
7
0
1
1
1
1
1
1
1
8
9
9
A
A
B
B
B
rd
E
1
7
rd
5
9
5
A
1
4
4
4
4
1
2
3
rs
3
rs
3
0
8
9
rs
E
rs
5
rs
5
F
0
1
0
1
0
0
0
rd
rd
rd
rd
0
0
rd
rd
rd
0
6
6
6
6
6
6
6
7
6
B
B
B
B
D
D
D
B
5
8
8
A
A
F
F
F
0
0
0
0
C
abs
abs
abs
abs
IMM
IMM
IMM
IMM
IMM
IMM
Cannot be used with this LSI.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 956 of 1130
REJ09B0327-0400
XORC #xx:8,CCR
XORC #xx:8,EXR
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
XORC B
B
0
0
5
1
4
1 0 5
IMM
IMM
Notes: Bit 7 of the 4th byte of the MOV.L ERs, @ (d:32, ERd) instruction can be either 0 or 1.
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Legend:
Address Registers
32-Bit Registers
Register
Field General
Register Register
Field General
Register Register
Field General
Register
000
001
•
•
•
111
ER0
ER1
•
•
•
ER7
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0
R1
•
•
•
R7
E0
E1
•
•
•
E7
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0H
R1H
•
•
•
R7H
R0L
R1L
•
•
•
R7L
16-Bit Register 8-Bit Register
IMM:
abs:
disp:
rs, rd, rn:
ers, erd, ern, erm:
Immediate data (2, 3, 8, 16, or 32 bits)
Absolute address (8, 16, 24, or 32 bits)
Displacement (8, 16, or 32 bits)
Register field (4 bits, indicating an 8-bit or 16-bit register. rs, rd, and rn correspond to operand formats Rs, Rd, and Rn, respectively.)
Register field (3 bits, indicating an address register or 32-bit register. ers, erd, ern, and erm correspond to operand formats ERs, ERd,
ERn, and ERm, respectively.)
1.
2.
3.
The correspondence between register fields and general registers is shown in the following table.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 957 of 1130
REJ09B0327-0400
A.3 Operation Code Map
Table A.3 shows the operation code map.
Table A.3 Operation Code Map (1)
Instruction code: 1st byte 2nd byte
AH AL BH BL
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
0
NOP
BRA
MULXU
BSET
AH AL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
BRN
DIVXU
BNOT
2
BHI
MULXU
BCLR
3
BLS
DIVXU
BTST
STC
STMAC
LDC
LDMAC
4
ORC
OR
BCC
RTS
OR
BORBIOR
6
ANDC
AND
BNE
RTE
AND
5
XORC
XOR
BCS
BSR
XOR
BXOR
BIXOR
BAND
BIAND
7
LDC
BEQ
TRAPA
BST BIST
BLD BILD
8
BVC
MOV
9
BVS
A
BPL
JMP
B
BMI
EEPMOV
C
BGE
BSR
D
BLT
MOV
E
ADDX
SUBX
BGT
JSR
F
BLE
MOV.B
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
ADD
SUB
MOV
MOV
CMP
Table A.3 (3)
**
Note: * Cannot be used with this LSI.
Table
A.3 (2) Table
A.3 (2) Table
A.3 (2) Table
A.3 (2) Table
A.3 (2) Table
A.3 (2)
Table
A.3 (2) Table
A.3 (2)
Table
A.3 (2)
Table
A.3 (2)
Table
A.3 (2) Table
A.3 (2)
Table
A.3 (2) Table
A.3 (2)
Table
A.3 (2)
Table
A.3 (2)
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 958 of 1130
REJ09B0327-0400
Table A.3 Operation Code Map (2)
Instruction code: 1st byte 2nd byte
AH AL BH BL
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
6A
79
7A
0
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
MOV
SHLL
SHLR
ROTXL
ROTXR
NOT
1
LDM
BRN
ADD
ADD
2
BHI
MOV
CMP
CMP
3
STM
NOT
BLS
SUB
SUB
4
SHLL
SHLR
ROTXL
ROTXR
BCC
MOVFPE
OR
OR
5
INC
EXTU
DEC
BCS
XOR
XOR
6
MAC
BNE
AND
AND
7
INC
SHLL
SHLR
ROTXL
ROTXR
EXTU
DEC
BEQ
LDCSTC
8
SLEEP
BVC
MOV
ADDS
SHAL
SHAR
ROTL
ROTR
NEG
SUBS
9
BVS
A
CLRMAC
BPL
MOV
B
NEG
BMI
ADD
MOV
SUB
CMP
C
SHAL
SHAR
ROTL
ROTR
BGE
MOVTPE
D
INC
EXTS
DEC
BLT
E
TAS
BGT
F
INC
SHAL
SHAR
ROTL
ROTR
EXTS
DEC
BLE
BH
AH AL
**
Note: * Cannot be used with this LSI.
* *
Table
A.3 (4) Table
A.3 (4)
Table
A.3 (3)
Table
A.3 (3)
Table
A.3 (3)
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 959 of 1130
REJ09B0327-0400
Table A.3 Operation Code Map (3)
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Notes: 1. r is the register specification field.
2. aa is the absolute address specification.
AH AL BH BL CH
CL
01C05
01D05
01F06
7Cr06*
1
7Cr07*
1
7Dr06*
1
7Dr07*
1
7Eaa6*
2
7Eaa7*
2
7Faa6*
2
7Faa7*
2
0
MULXS
BSET
BSET
BSET
BSET
1
DIVXS
BNOT
BNOT
BNOT
BNOT
2
MULXS
BCLR
BCLR
BCLR
BCLR
3
DIVXS
BTST
BTST
BTST
BTST
4
OR
5
XOR
6
AND
789ABCDEF
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 960 of 1130
REJ09B0327-0400
Table A.3 Operation Code Map (4)
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
Instruction when most significant bit of FH is 0.
Instruction when most significant bit of FH is 1.
5th byte 6th byte
EH EL FH FL
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
Indicates case where MSB of HH is 0.
Indicates case where MSB of HH is 1.
Note: * aa is the absolute address specification.
5th byte 6th byte
EH EL FH FL
7th byte 8th byte
GH GL HH HL
6A10aaaa6*
6A10aaaa7*
6A18aaaa6*
6A18aaaa7*
AHALBHBLCHCLDHDLEH
EL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
6A30aaaaaaaa6
*
6A30aaaaaaaa7
*
6A38aaaaaaaa6
*
6A38aaaaaaaa7
*
AHALBHBL ... FHFLGH
GL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 961 of 1130
REJ09B0327-0400
A.4 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8S/2000 CPU. Table A.5 shows the number of instruction fetch, data
read/write, and other cycles occurring in each instruction, and table A.4 shows the number of
states required per cy cle according to the bus size. The number of states required for execution of
an instruction can be calculated from these two tables as follows:
Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed in two states with 8-bit bus width, external devices accessed in three states with one wait
state and 16-bit bus width.
1. BSET #0,@FFFFC7:8
From table A.5,
I = L = 2 and J = K = M = N = 0
From table A.4,
SI = 4 and SL = 2
Number of states = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A.5,
I = J = K = 2 and L = M = N = 0
From table A.4,
SI = SJ= SK = 4
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 962 of 1130
REJ09B0327-0400
Table A.4 Number of States per Cycle
Access Conditions
External Device
On-Chip
Supporting
Module 8-Bit Bus 16-Bit Bus
Cycle On-Chip
Memory 8-Bit
Bus 16-Bit
Bus 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI1 4 2 4 6 + 2m 2 3 + m
Branch address fetch SJ
Stack operation SK
Byte data access SL223 + m
Word data access SM4 4 6 + 2m
Internal operation SN1111111
Legend:
m: Number of wait states inserted into external device access
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 963 of 1130
REJ09B0327-0400
Table A.5 Number of Cycles per Instruction
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8,Rd 1
ADD.B Rs,Rd 1
ADD.W #xx:16,Rd 2
ADD.W Rs,Rd 1
ADD.L #xx:32,ERd 3
ADD.L ERs,ERd 1
ADDS ADDS #1/2/4,ERd 1
ADDX ADDX #xx:8,Rd 1
ADDX Rs,Rd 1
AND AND.B #xx:8,Rd 1
AND.B Rs,Rd 1
AND.W #xx:16,Rd 2
AND.W Rs,Rd 1
AND.L #xx:32,ERd 3
AND.L ERs,ERd 2
ANDC ANDC #xx:8,CCR 1
ANDC #xx:8,EXR 2
BAND BAND #xx:3,Rd 1
BAND #xx:3,@ERd 2 1
BAND #xx:3,@aa:8 2 1
BAND #xx:3,@aa:16 3 1
BAND #xx:3,@aa:32 4 1
Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 964 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc BMI d:8 2
BGE d:8 2
BLT d:8 2
BGT d:8 2
BLE d:8 2
BRA d:16 (BT d:16) 2 1
BRN d:16 (BF d:16) 2 1
BHI d:16 2 1
BLS d:16 2 1
BCC d:16 (BHS d:16) 2 1
BCS d:16 (BLO d:16) 2 1
BNE d:16 2 1
BEQ d:16 2 1
BVC d:16 2 1
BVS d:16 2 1
BPL d:16 2 1
BMI d:16 2 1
BGE d:16 2 1
BLT d:16 2 1
BGT d:16 2 1
BLE d:16 2 1
BCLR BCLR #xx:3,Rd 1
BCLR #xx:3,@ERd 2 2
BCLR #xx:3,@aa:8 2 2
BCLR #xx:3,@aa:16 3 2
BCLR #xx:3,@aa:32 4 2
BCLR Rn,Rd 1
BCLR Rn,@ERd 2 2
BCLR Rn,@aa:8 2 2
BCLR Rn,@aa:16 3 2
BCLR Rn,@aa:32 4 2
BIAND BIAND #xx:3,Rd 1
BIAND #xx:3,@ERd 2 1
BIAND #xx:3,@aa:8 2 1
BIAND #xx:3,@aa:16 3 1
BIAND #xx:3,@aa:32 4 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 965 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BILD BILD #xx:3,Rd 1
BILD #xx:3,@ERd 2 1
BILD #xx:3,@aa:8 2 1
BILD #xx :3,@aa:16 3 1
BILD #xx :3,@aa:32 4 1
BIOR BIOR #xx:8,Rd 1
BIOR #xx:8,@ERd 2 1
BIOR #xx:8,@aa:8 2 1
BIOR #xx:8,@aa:16 3 1
BIOR #xx:8,@aa:32 4 1
BIST BIST #xx:3,Rd 1
BIST #xx:3,@ERd 2 2
BIST #xx:3,@aa:8 2 2
BIST #xx:3,@ aa:16 3 2
BIST #xx:3,@ aa:32 4 2
BIXOR BIXOR #xx:3,Rd 1
BIXOR #xx:3,@ERd 2 1
BIXOR #xx:3,@aa:8 2 1
BIXOR #xx:3,@aa:16 3 1
BIXOR #xx:3,@aa:32 4 1
BLD BLD #xx:3,Rd 1
BLD #xx:3,@ERd 2 1
BLD #xx:3,@aa:8 2 1
BLD #xx:3,@aa:16 3 1
BLD #xx:3,@aa:32 4 1
BNOT BNOT #xx:3,Rd 1
BNOT #xx:3,@ER d 2 2
BNOT #xx:3,@aa:8 2 2
BNOT #xx:3,@aa:16 3 2
BNOT #xx:3,@aa:32 4 2
BNOT Rn,Rd 1
BNOT Rn,@ERd 2 2
BNOT Rn,@aa:8 2 2
BNOT Rn,@aa:16 3 2
BNOT Rn,@aa:32 4 2
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 966 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BOR BOR #xx:3,Rd 1
BOR #xx:3,@ERd 2 1
BOR #xx:3,@aa:8 2 1
BOR #xx:3,@aa:16 3 1
BOR #xx:3,@aa:32 4 1
BSET BSET #xx:3,Rd 1
BSET #xx:3, @ERd 2 2
BSET #xx:3,@aa:8 2 2
BSET #xx:3,@aa:16 3 2
BSET #xx:3,@aa:32 4 2
BSET Rn,Rd 1
BSET Rn,@ERd 2 2
BSET Rn,@aa:8 2 2
BSET Rn,@aa:16 3 2
BSET Rn,@aa:32 4 2
BSR BSR d:8 Norma l 2 1
Advanced 2 2
BSR d:16 Normal 2 1 1
Advanced 2 2 1
BST BST #xx:3,Rd 1
BST #xx:3,@ERd 2 2
BST #xx:3,@aa:8 2 2
BST #xx:3,@aa:16 3 2
BST #xx:3,@aa:32 4 2
BTST BTST #xx:3,Rd 1
BTST #xx:3,@ERd 2 1
BTST #xx:3,@ aa: 8 2 1
BTST #xx:3,@ aa: 16 3 1
BTST #xx:3,@ aa: 32 4 1
BTST Rn,Rd 1
BTST Rn,@ERd 2 1
BTST Rn,@aa:8 2 1
BTST Rn,@aa:16 3 1
BTST Rn,@aa:32 4 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 967 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BXOR BXOR #xx:3,Rd 1
BXOR #xx:3,@ERd 2 1
BXOR #xx:3,@aa:8 2 1
BXOR #xx:3,@aa:16 3 1
BXOR #xx:3,@aa:32 4 1
CLRMAC CLRMAC Cannot be used with this LSI.
CMP CMP.B #xx:8,Rd 1
CMP.B Rs,Rd 1
CMP.W #xx:16,Rd 2
CMP.W Rs,Rd 1
CMP.L #xx:32 ,E Rd 3
CMP.L ERs,ERd 1
DAA DAA Rd 1
DAS DAS Rd 1
DEC DEC.B Rd 1
DEC.W #1/2,Rd 1
DEC.L #1/2,ERd 1
DIVXS DIVXS.B Rs,Rd 2 11
DIVXS.W Rs,ERd 2 19
DIVXU DIVXU.B Rs,Rd 1 11
DIVXU.W Rs,ERd 1 19
EEPMOV EEPMOV.B 2 2n+2*2
EEPMOV.W 2 2n+2*2
EXTS EXTS.W Rd 1
EXTS.L ERd 1
EXTU EXTU.W Rd 1
EXTU.L ERd 1
INC INC.B Rd 1
INC.W #1/2,Rd 1
INC.L #1/2,E R d 1
JMP JMP @ERn 2
JMP @aa:24 2 1
JMP @@aa:8 Normal 2 1 1
Advanced 2 2 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 968 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
JSR JSR @ERn Normal 2 1
Advanced 2 2
JSR @aa:24 Norma l 2 1 1
Advanced 2 2 1
JSR @@aa:8 Normal 2 1 1
Advanced 2 2 2
LDC LDC #xx:8,CCR 1
LDC #xx:8,EXR 2
LDC Rs,CCR 1
LDC Rs,EXR 1
LDC @ERs,CCR 2 1
LDC @ERs,EXR 2 1
LDC @(d:16,ERs),CCR 3 1
LDC @(d:16,ERs),EXR 3 1
LDC @(d:32,ERs),CCR 5 1
LDC @(d:32,ERs),EXR 5 1
LDC @ERs+,CCR 2 1 1
LDC @ERs+,EXR 2 1 1
LDC @aa:16,CCR 3 1
LDC @aa:16,EXR 3 1
LDC @aa:32,CCR 4 1
LDC @aa:32,EXR 4 1
LDM*4LDM.L @SP+, ( ERn-ERn+1) 2 4 1
LDM.L @SP+, ( ERn-ERn+2) 2 6 1
LDM.L @SP+, ( ERn-ERn+3) 2 8 1
LDMAC LDMAC ERs, MACH Cannot be used with this LSI.
LDMAC ERs, MACL
MAC MAC @ERn+, @ERm+
MOV MOV.B #xx: 8,Rd 1
MOV.B Rs,Rd 1
MOV.B @ERs,Rd 1 1
MOV.B @(d:16,ERs),Rd 2 1
MOV.B @(d:32,ERs),Rd 4 1
MOV.B @ERs+,Rd 1 1 1
MOV.B @aa:8,Rd 1 1
MOV.B @aa:16,Rd 2 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 969 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.B @aa:32,Rd 3 1
MOV.B Rs,@ERd 1 1
MOV.B Rs,@(d:16,ERd) 2 1
MOV.B Rs,@(d:32,ERd) 4 1
MOV.B Rs,@-ERd 1 1 1
MOV.B Rs,@aa: 8 1 1
MOV.B Rs,@aa: 16 2 1
MOV.B Rs,@aa: 32 3 1
MOV.W #xx:16,Rd 2
MOV.W Rs,Rd 1
MOV.W @ERs ,R d 1 1
MOV.W @(d:16,ERs),Rd 2 1
MOV.W @(d:32,ERs),Rd 4 1
MOV.W @ERs+,Rd 1 1 1
MOV.W @aa:16,Rd 2 1
MOV.W @aa:32,Rd 3 1
MOV.W Rs,@ERd 1 1
MOV.W Rs,@(d:16,E R d) 2 1
MOV.W Rs,@(d:32,E R d) 4 1
MOV.W Rs,@-ERd 1 1 1
MOV.W Rs,@aa:16 2 1
MOV.W Rs,@aa:32 3 1
MOV.L #xx:32,ERd 3
MOV.L ERs,ERd 1
MOV.L @ERs,ERd 2 2
MOV.L @(d:16,ERs),ERd 3 2
MOV.L @(d:32,ERs),ERd 5 2
MOV.L @ERs+,ERd 2 2 1
MOV.L @aa:16,ERd 3 2
MOV.L @aa:32,ERd 4 2
MOV.L ERs,@ERd 2 2
MOV.L ERs,@(d:16,ERd) 3 2
MOV.L ERs,@(d:32,ERd) 5 2
MOV.L ERs,@-ERd 2 2 1
MOV.L ERs,@aa:16 3 2
MOV.L ERs,@aa:32 4 2
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 970 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOVFPE MOVFPE @:aa:16,Rd Cannot be used with this LSI.
MOVTPE MOVTPE Rs,@:aa:16
MULXS MULXS.B Rs,Rd 2 11
MULXS.W Rs,ERd 2 19
MULXU MULXU.B Rs,Rd 1 11
MULXU.W Rs,ERd 1 19
NEG NEG.B Rd 1
NEG.W Rd 1
NEG.L ERd 1
NOP NOP 1
NOT NOT.B Rd 1
NOT.W Rd 1
NOT.L ERd 1
OR OR.B #xx:8,Rd 1
OR.B Rs,Rd 1
OR.W #xx:16,Rd 2
OR.W Rs,Rd 1
OR.L #xx:32,ER d 3
OR.L ERs,ERd 2
ORC ORC #xx:8,CCR 1
ORC #xx:8,EXR 2
POP POP.W Rn 1 1 1
POP.L ERn 2 2 1
PUSH PUSH.W Rn 1 1 1
PUSH.L ERn 2 2 1
ROTL ROTL.B Rd 1
ROTL.B #2,Rd 1
ROTL.W Rd 1
ROTL.W #2,R d 1
ROTL.L ERd 1
ROTL.L #2,ERd 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 971 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ROTR ROTR.B Rd 1
ROTR.B #2,Rd 1
ROTR.W Rd 1
ROTR.W #2,Rd 1
ROTR.L ERd 1
ROTR.L #2,ERd 1
ROTXL ROTXL.B Rd 1
ROTXL.B #2,Rd 1
ROTXL.W Rd 1
ROTXL.W #2,Rd 1
ROTXL.L ERd 1
ROTXL .L #2,E R d 1
ROTXR ROTXR.B Rd 1
ROTXR.B #2,Rd 1
ROTXR.W Rd 1
ROTXR.W #2,Rd 1
ROTXR.L ERd 1
ROTXR.L #2,ERd 1
RTE RTE 2 2/3*11
RTS RTS Normal 2 1 1
Advanced 2 2 1
SHAL SHAL.B Rd 1
SHAL.B #2,Rd 1
SHAL.W Rd 1
SHAL.W #2,Rd 1
SHAL.L ERd 1
SHAL.L #2,ERd 1
SHAR SHAR.B Rd 1
SHAR.B #2,Rd 1
SHAR.W Rd 1
SHAR.W #2,Rd 1
SHAR.L ERd 1
SHAR.L #2,ERd 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 972 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SHLL SHLL.B Rd 1
SHLL.B #2,R d 1
SHLL.W Rd 1
SHLL.W #2, Rd 1
SHLL.L ERd 1
SHLL.L #2,ERd 1
SHLR SHLR.B Rd 1
SHLR.B #2,Rd 1
SHLR.W Rd 1
SHLR.W #2,R d 1
SHLR.L ERd 1
SHLR.L #2 ,ER d 1
SLEEP SLEEP 1 1
STC STC.B CCR,Rd 1
STC.B EXR,Rd 1
STC.W CCR,@ERd 2 1
STC.W EXR,@ERd 2 1
STC.W CCR,@(d:16,ERd) 3 1
STC.W EXR,@(d:16,ERd) 3 1
STC.W CCR,@(d:32,ERd) 5 1
STC.W EXR,@(d:32,ERd) 5 1
STC.W CCR,@-ERd 2 1 1
STC.W EXR,@-ERd 2 1 1
STC.W CCR,@aa:16 3 1
STC.W EXR,@aa:16 3 1
STC.W CCR,@aa:32 4 1
STC.W EXR,@aa:32 4 1
STM*4STM.L (ERn-ERn+1),@-SP 2 4 1
STM.L (ERn-ERn+2),@-SP 2 6 1
STM.L (ERn-ERn+3),@-SP 2 8 1
SUB SUB.B Rs,Rd 1
SUB.W #xx:16,Rd 2
SUB.W Rs,Rd 1
SUB.L #xx:32,ERd 3
SUB.L ERs,ERd 1
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 973 of 1130
REJ09B0327-0400
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBS SUBS #1/2/4,ERd 1
SUBX SUBX #xx:8,Rd 1
SUBX Rs,Rd 1
TAS TAS @ERd*322
TRAPA TRAPA #x:2 Normal 2 1 2/3*12
Advanced 2 2 2/3*12
XOR XOR.B #xx: 8,Rd 1
XOR.B Rs,Rd 1
XOR.W #xx:16,Rd 2
XOR.W Rs,Rd 1
XOR.L #xx:32,E R d 3
XOR.L ERs,ERd 2
XORC XORC #xx:8,CCR 1
XORC #xx:8,EXR 2
Notes: 1. 2 when EXR is invalid, 3 when valid.
2. When n bytes of data are transferred.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
4. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 974 of 1130
REJ09B0327-0400
A.5 Bus States during Instruction Execution
Table A.6 indicates the types of cycles that occu r during instruction execution by the CPU. See
table A.4 for the number of states per cycle.
How to Read the Table:
Instruction
JMP@aa:24 R:W 2nd Internal
operation,
2 state
R:W EA
12345678
End of instruction
Order of execution
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
Legend:
R:B Byte-size r ead
R:W Word-size read
W:B Byte-size write
W:W Word-size write
:M Transfer of the bus is not performed immediately after this cycle
2nd Address of 2nd word (3rd and 4th bytes)
3rd Address of 3rd word (5th and 6th bytes)
4th Address of 4th word (7th and 8th bytes)
5th Address of 5th word (9th and 10th bytes)
NEXT Start address of instruction following executing instruction
EA Effective address
VEC Vector address
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 975 of 1130
REJ09B0327-0400
Figure A.1 shows timing waveform s for the address bus and the RD, HWR, and LWR signals
during execution of th e above instruction with an 8-bit bus, using three-state access with no wait
states.
φ
Address bus
RD
HWR, LWR
R:W 2nd
Fetching 3rd byte
of instruction Fetching 4th byte
of instruction Fetching 1st byte
of branch
instruction
Fetching 2nd byte
of branch
instruction
R:W EA
High level
Internal
operation
Figure A.1 Address Bus, RD
RDRD
RD, HWR
HWRHWR
HWR, and LWR
LWRLWR
LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 976 of 1130
REJ09B0327-0400
Table A.6 Instruction Execution Cycle
Instruction123456789
ADD.B #xx:8,Rd R:W NEXT
ADD.B Rs,Rd R:W NEXT
ADD.W #xx:16,Rd R:W 2nd R:W NEXT
ADD.W Rs,Rd R:W NEXT
ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
ADD.L ERs,ERd R:W NEXT
ADDS #1/2/4,ERd R:W NEXT
ADDX #xx:8,Rd R:W NEXT
ADDX Rs,Rd R:W NEXT
AND.B #xx:8,Rd R:W NEXT
AND.B Rs,Rd R:W NEXT
AND.W #xx:16,Rd R:W 2nd R:W NEXT
AND.W Rs,Rd R:W NEXT
AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
AND.L ERs,ERd R:W 2nd R:W NEXT
ANDC #xx:8,CCR R:W NEXT
ANDC #xx:8,EXR R:W 2nd R:W NEXT
BAND #xx:3,Rd R:W NEXT
BAND #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BAND #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BAND #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BRA d:8 (BT d:8) R:W NEXT R:W EA
BRN d:8 (BF d:8) R:W NEXT R:W EA
BHI d:8 R:W NEXT R:W EA
BLS d:8 R:W NEXT R:W EA
BCC d:8 (BHS d:8) R:W NEXT R:W EA
BCS d:8 (BLO d:8) R:W NEXT R:W EA
BNE d:8 R:W NEXT R:W EA
BEQ d:8 R:W NEXT R:W EA
BVC d:8 R:W NEXT R:W EA
BVS d:8 R:W NEXT R:W EA
BPL d:8 R:W NEXT R:W EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 977 of 1130
REJ09B0327-0400
Instruction123456789
BMI d:8 R:W NEXT R:W EA
BGE d:8 R:W NEXT R:W EA
BLT d:8 R:W NEXT R:W EA
BGT d:8 R:W NEXT R:W EA
BLE d:8 R:W NEXT R:W EA
BRA d:16 (BT d:16) R:W 2nd Internal
operation,
1 state
R:W EA
BRN d:16 (BF d:16) R:W 2nd Internal
operation,
1 state
R:W EA
BHI d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BLS d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BCC d:16
(BHS d:16) R:W 2nd Internal
operation,
1 state
R:W EA
BCS d:16
(BLO d:16) R:W 2nd Internal
operation,
1 state
R:W EA
BNE d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BEQ d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BVC d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BVS d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BPL d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BMI d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BGE d:16 R:W 2nd Internal
operation,
1 state
R:W EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 978 of 1130
REJ09B0327-0400
Instruction123456789
BLT d:16 R :W 2nd Inte rn al
operation,
1 state
R:W EA
BGT d:16 R:W 2nd Inte rn al
operation,
1 state
R:W EA
BLE d:16 R:W 2nd Internal
operation,
1 state
R:W EA
BCLR #xx:3,Rd R:W NEXT
BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR#xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BCLR#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,Rd R:W NEXT
BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BIAND #xx:3,Rd R:W NEXT
BIAND #xx:3,
@ERd R:W 2nd R:B EA R:W:M
NEXT
BIAND #xx:3,
@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BIAND #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BIAND #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BILD #xx:3,Rd R:W NEXT
BILD #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B: EA R:W:M
NEXT
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 979 of 1130
REJ09B0327-0400
Instruction123456789
BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BIOR #xx:3,Rd R:W NEXT
BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BIST #xx:3,Rd R:W NEXT
BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BIXOR #xx:3,Rd R:W NEXT
BIXOR #xx:3,
@ERd R:W 2nd R:B EA R:W:M
NEXT
BIXOR #xx:3,
@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BIXOR #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BIXOR #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BLD #xx:3,Rd R:W NEXT
BLD #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BNOT #xx:3,Rd R:W NEXT
BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 980 of 1130
REJ09B0327-0400
Instruction123456789
BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BNOT #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BNOT #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BNOT Rn,Rd R:W NEXT
BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BNOT Rn,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BOR #xx:3,Rd R:W NEXT
BOR #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT
BSET #xx:3,Rd R:W NEXT
BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BSET #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,Rd R:W NEXT
BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 981 of 1130
REJ09B0327-0400
Instruction123456789
BSR
d:8 Advanced R:W NEXT R:W EA W:W:M
Stack (H) W:W
Stack (L)
BSR
d:16 Advanced R:W 2nd Internal
operation,
1 state
R:W EA W:W:M
Stack (H) W:W
Stack (L)
BST #xx:3,Rd R:W NEXT
BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BTST #xx:3,Rd R:W NEXT
BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BTST #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BTST #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BTST Rn,Rd R:W NEXT
BTST Rn,@ERd R:W 2nd R:B EA R:W:M
NEXT
BTST Rn,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BXOR #xx:3,Rd R:W NEXT
BXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BXOR #xx:3,
@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BXOR #xx:3,
@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
CLRMAC Cannot be used in this LSI
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 982 of 1130
REJ09B0327-0400
Instruction123456789
CMP.B #xx:8,Rd R:W NEXT
CMP.B Rs,Rd R:W NEXT
CMP.W #xx:16,Rd R:W 2nd R:W NEXT
CMP.W Rs,Rd R:W NEXT
CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
CMP.L ERs,ERd R:W NEXT
DAA Rd R:W NEXT
DAS Rd R:W NEXT
DEC.B Rd R:W NEXT
DEC.W #1/2,Rd R:W NEXT
DEC.L #1/2,ERd R:W NEXT
DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states
DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states
DIVXU.B Rs,Rd R:W NEXT Internal operation, 11 states
DIVXU.W Rs,ERd R:W NEXT Internal operation, 19 states
EEPMOV.B R:W 2nd R:B EAs*1R:B EAd*1R:B EAs *2W:B EAd*2R:W NEXT
EEPMOV.W R:W 2nd R:B EAs*1R:B EAd*1R:B EAs*2W:B EAd*2R:W NEXT
EXTS.W Rd R:W NEXT ← Repeated n times*2 →
EXTS.L ERd R:W NEXT
EXTU.W Rd R:W NEXT
EXTU.L ERd R:W NEXT
INC.B Rd R:W NEXT
INC.W #1/2,Rd R:W NEXT
INC.L #1/2,E R d R:W NEX T
JMP @ERn R:W NEXT R:W EA
JMP @aa:24 R:W 2nd Internal
operation,
1 state
R:W EA
JMP
@@aa:8 Advanced R:W NEXT R:W:M
aa:8 R:W aa:8 Internal
operation,
1 state
R:W EA
JSR
@ERn Advanced R:W NEXT R:W EA W:W:M
Stack (H) W:W
Stack (L)
JSR
@aa:24 Advanced R:W 2nd Internal
operation,
1 state
R:W EA W:W:M
Stack (H) W:W
Stack (L)
JSR
@@aa:8 Advanced R:W NEXT R:W:M
aa:8 R:W aa:8 W:W:M
Stack (H) W:W
Stack (L) R:W EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 983 of 1130
REJ09B0327-0400
Instruction123456789
LDC #xx:8,CCR R:W NEXT
LDC #xx:8,EXR R:W 2nd R:W NEXT
LDC Rs,CCR R:W NEXT
LDC Rs,EXR R:W NEXT
LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA
LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA
LDC@(d:16,ERs),
CCR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC@(d:16,ERs),
EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC@(d:32,ERs),
CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LDC@(d:32,ERs),
EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LDC @ERs+,CCR R:W 2nd R:W NEXT Internal
operation,
1 state
R:W EA
LDC @ERs+,EXR R:W 2nd R:W NEXT Internal
operation,
1 state
R:W EA
LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDM.L @SP+,
(ERn-ERn+1)*9R:W 2nd R:W:M
NEXT Internal
operation,
1 state
R:W:M
Stack (H)*3R:W
Stack (L)*3
LDM.L @SP+,
(ERn-ERn+2)*9R:W 2nd R:W:M
NEXT Internal
operation,
1 state
R:W:M
Stack (H)*3R:W
Stack (L)*3
LDM.L @SP+,
(ERn-ERn+3)*9R:W 2nd R:W:M
NEXT Internal
operation,
1 state
R:W:M
Stack (H)*3R:W
Stack (L)*3
LDMAC ERs,MACH Cannot be used in this LSI
LDMAC ERs,MACL
MAC @ERn+,
@ERm+
MOV.B #xx:8,Rd R:W NEXT
MOV.B Rs,Rd R:W NEXT
MOV.B @ERs,Rd R:W NEXT R:B EA
MOV.B
@(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 984 of 1130
REJ09B0327-0400
Instruction123456789
MOV.B
@(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA
MOV.B @ERs+,Rd R:W NEXT Internal
operation,
1 state
R:B EA
MOV.B @aa:8,Rd R:W NEXT R:B EA
MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA
MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.B Rs,@ERd R:W NEXT W:B EA
MOV.B Rs,
@(d:16,ERd) R:W 2nd R:W NEXT W:B EA
MOV.B Rs,
@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA
MOV.B Rs,@-ERd R:W NEXT Internal
operation,
1 state
W:B EA
MOV.B Rs,@aa:8 R:W NEXT W:B EA
MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA
MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA
MOV.W #xx:16,Rd R:W 2nd R:W NEXT
MOV.W Rs,Rd R:W NEXT
MOV.W @ERs,Rd R: W NEXT R:W EA
MOV.W
@(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA
MOV.W
@(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
MOV.W @ERs+,Rd R:W NEXT Inte rnal
operation,
1 state
R:W EA
MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA
MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.W Rs,@ERd R:W NEXT W:W EA
MOV.W Rs,
@(d:16,ERd) R:W 2nd R:W NEXT W:W EA
MOV.W Rs,
@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
MOV.W Rs,@-ERd R:W NEXT Internal
operation,
1 state
W:W EA
MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA
MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 985 of 1130
REJ09B0327-0400
Instruction123456789
MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
MOV.L ERs,ERd R:W NEXT
MOV.L @ERs,ERd R:W 2nd R:W:M
NEXT R:W:M EA R:W EA+2
MOV.L
@(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L
@(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT R:W:M EA R:W EA+2
MOV.L @ERs+,
ERd R:W 2nd R:W:M
NEXT Internal
operation,
1 state
R:W:M EA R:W EA+2
MOV.L @aa:16,
ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L @aa:32,
ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA R:W EA+2
MOV.L ERs,@ERd R:W 2nd R:W:M
NEXT W:W:M EA W:W EA+2
MOV.L ERs,
@(d:16,ERd) R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,
@(d:32,ERd) R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@-ERd R:W 2nd R:W:M
NEXT Internal
operation,
1 state
W:W:M EA W:W EA+2
MOV.L ERs,
@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,
@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2
MOVFPE
@aa:16,Rd Cannot be used in this LSI
MOVTPE
Rs,@aa:16
MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states
MULXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states
MULXU.B Rs,Rd R:W NEXT Internal operation, 11 states
MULXU.W Rs,ERd R:W NEXT Internal operation, 19 states
NEG.B Rd R:W NEXT
NEG.W Rd R:W NEXT
NEG.L ERd R:W NEXT
NOP R:W NEXT
NOT.B Rd R:W NEXT
NOT.W Rd R:W NEXT
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 986 of 1130
REJ09B0327-0400
Instruction123456789
NOT.L ERd R:W NEXT
OR.B #xx:8,Rd R:W NEXT
OR.B Rs,Rd R:W NEXT
OR.W #xx:16,Rd R:W 2nd R:W NEXT
OR.W Rs,Rd R:W NEXT
OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
OR.L ERs,ERd R:W 2nd R:W NEXT
ORC #xx:8,CCR R:W NEXT
ORC #xx:8,EXR R:W 2nd R:W NEXT
POP.W Rn R:W NEXT Internal
operation,
1 state
R:W EA
POP.L ERn R:W 2nd R:W:M
NEXT Internal
operation,
1 state
R:W:M EA R:W EA+2
PUSH.W Rn R:W NEXT Internal
operation,
1 state
W:W EA
PUSH.L ERn R:W 2nd R:W:M
NEXT Internal
operation,
1 state
W:W:M EA W:W EA+2
ROTL.B Rd R:W NEXT
ROTL.B #2,Rd R:W NEXT
ROTL.W Rd R:W NEXT
ROTL.W #2,Rd R:W NEXT
ROTL.L ERd R:W NEXT
ROTL.L #2,ERd R:W NEXT
ROTR.B Rd R:W NEXT
ROTR.B #2,Rd R:W NEXT
ROTR.W Rd R:W NEXT
ROTR.W #2,Rd R:W NEXT
ROTR.L ERd R:W NEXT
ROTR.L #2,ERd R:W NEXT
ROTXL.B Rd R:W NEXT
ROTXL.B #2,Rd R:W NEXT
ROTXL.W Rd R:W NEXT
ROTXL.W #2,Rd R:W NEXT
ROTXL.L ERd R:W NEXT
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 987 of 1130
REJ09B0327-0400
Instruction123456789
ROTXL. L #2,ERd R:W NEXT
ROTXR.B Rd R:W NEXT
ROTXR.B #2,Rd R:W NEXT
ROTXR.W Rd R:W NEXT
ROTXR.W #2,Rd R:W NEXT
ROTXR.L ERd R:W NEXT
ROTXR.L #2,ERd R:W NEXT
RTE R:W NEXT R:W
Stack
(EXR)
R:W
Stack (H) R:W
Stack (L) Internal
operation,
1 state
R:W*4
RTS Advanced R:W NEXT R:W:M
Stack (H) R:W
Stack (L) Internal
operation,
1 state
R:W*4
SHAL.B Rd R:W NEXT
SHAL.B #2,Rd R:W NEXT
SHAL.W Rd R:W NEXT
SHAL.W #2,Rd R:W NEXT
SHAL.L ERd R:W NEXT
SHAL.L #2,ERd R:W NEXT
SHAR.B Rd R:W NEXT
SHAR.B #2,Rd R:W NEXT
SHAR.W Rd R:W NEXT
SHAR.W #2,Rd R:W NEXT
SHAR.L ERd R:W NEXT
SHAR.L #2,ERd R:W NEXT
SHLL.B Rd R:W NEXT
SHLL.B #2,Rd R:W NEXT
SHLL.W Rd R:W NEXT
SHLL.W #2, Rd R:W NEXT
SHLL.L ERd R:W NEXT
SHLL.L #2,ERd R:W NEXT
SHLR.B Rd R:W NEXT
SHLR.B #2,Rd R:W NEXT
SHLR.W Rd R:W NEXT
SHLR.W #2,R d R:W NEX T
SHLR.L ERd R:W NEXT
SHLR.L #2,ERd R:W NEXT
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 988 of 1130
REJ09B0327-0400
Instruction123456789
SLEEP R:W NEXT Internal
operation
:M
STC CCR,Rd R:W NEXT
STC EXR,Rd R:W NEXT
STC CCR,@ERd R:W 2nd R:W NEXT W:W EA
STC EXR,@ERd R:W 2nd R:W NEXT W:W EA
STC CCR,
@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA
STC EXR,
@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA
STC CCR,
@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC EXR,
@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC CCR,@-ERd R:W 2nd R:W NEXT Internal
operation,
1 state
W:W EA
STC EXR,@-ERd R:W 2nd R:W NEXT Internal
operation,
1 state
W:W EA
STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STM.L
(ERn-ERn+1),
@-SP*9
R:W 2nd R:W:M
NEXT Internal
operation,
1 state
W:W:M
Stack (H)
*3
W:W
Stack (L)
*3
STM.L
(ERn-ERn+2),
@-SP*9
R:W 2nd R:W:M
NEXT Internal
operation,
1 state
W:W:M
Stack (H)
*3
W:W
Stack (L)
*3
STM.L
(ERn-ERn+3),
@-SP*9
R:W 2nd R:W:M
NEXT Internal
operation,
1 state
W:W:M
Stack (H)
*3
W:W
Stack (L)
*3
STMAC MACH ,E R d Cannot be used in this LSI
STMAC MACL,ERd
SUB.B Rs,Rd R:W NEXT
SUB.W #xx:16,Rd R:W 2nd R:W NEXT
SUB.W Rs,Rd R:W NEXT
SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
SUB.L ERs,ERd R:W NEXT
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 989 of 1130
REJ09B0327-0400
Instruction123456789
SUBS #1/2/4,ERd R:W NEXT
SUBX #xx:8,Rd R:W NEXT
SUBX Rs,Rd R:W NEXT
TAS @ERd*8R:W 2nd R:W NEXT R:B:M EA W:B EA
TRAPA
#x:2 Advanced R:W NEXT Internal
operation,
1 state
W:W
Stack (L) W:W
Stack (H) W:W
Stack
(EXR)
R:W:M
VEC R:W
VEC+2 Internal
operation,
1 state
R:W*7
XOR.B #xx8,Rd R:W NEXT
XOR.B Rs,Rd R:W NEXT
XOR.W #xx:16,Rd R:W 2nd R:W NEXT
XOR.W Rs,Rd R:W NEXT
XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
XOR.L ERs,ERd R:W 2nd R:W NEXT
XORC #xx:8,CCR R:W NEXT
XORC #xx:8,EXR R:W 2nd R:W NEXT
Reset
excep-
tion
handling
Advanced R:W:M
VEC R:W
VEC+2 Internal
operation,
1 state
R:W*5
Interrupt
excep-
tion
handling
Advanced R:W*6Internal
operation,
1 state
W:W
Stack (L) W:W
Stack (H) W:W
Stack
(EXR)
R:W:M
VEC R:W
VEC+2 Internal
operation,
1 state
R:W*7
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented
by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these
bus cycles are not executed.
3. Repeated two times to save or restore two registers, three ti mes for three registers, or
four times for four registers.
4. Start address after return.
5. Start address of the prog ram.
6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery
from sleep mode or software standby mode the read operation is replaced by an
internal operation.
7. Start address of the interrupt-handling routine.
8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
9. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 990 of 1130
REJ09B0327-0400
Appendix B Internal I/O Registers
B.1 Addresses
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
MRA SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC 16/32*
SAR
H'EC00
to
H'EFFF
MRB CHNE DISEL ——————
DAR
CRA
CRB
H'FE80HICR2—————IBFIE4IBFIE3— HIF8
H'FE84 IDR3 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
H'FE85 ODR3 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
H'FE86 STR3 DBU DBU DBU DBU C/DDBU IBF OBF
H'FE8C IDR4 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
H'FE8D ODR4 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
H'FE8E STR4 DBU DBU DBU DBU C/DDBU IBF OBF
H'FED8 KBCRH0 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS 8
H'FED9 KBCRL0 KBE KCLKO KDO — RXCR3 RXCR2 RXCR1 RXCR0
H'FEDA KBBR0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Keyboard
buffer
controller
H'FEDC KBCRH1 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS
H'FEDD KBCRL1 KBE KCLKO KDO — RXCR3 RXCR2 RXCR1 RXCR0
H'FEDE KBBR1 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
H'FEE0 KBCRH2 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS
H'FEE1 KBCRL2 KBE KCLKO KDO — RXCR3 RXCR2 RXCR1 RXCR0
H'FEE2 KBBR2 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
H'FEE4 KBCOMP IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 IrDA/
expansion
A/D
8
H'FEE6 DDCSWR SWE SW IE IF CLR3 CLR2 CLR1 CLR0 IIC0 8
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 991 of 1130
REJ09B0327-0400
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
H'FEE8 ICRA ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 8
H'FEE9 ICRB ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Interrupt
controller
H'FEEA ICRC ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
H'FEEB ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
H'FEEC ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
H'FEED ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
H'FEEE DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC 8
H'FEEF DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0
H'FEF0 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0
H'FEF1 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0
H'FEF2 DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0
H'FEF3 DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
H'FEF4ABRKCRCMF——————BIE 8
H'FEF5 BARA A23 A22 A21 A20 A19 A18 A17 A16
Interrupt
controller
H'FEF6 BARB A15 A14 A13 A12 A11 A10 A9 A8
H'FEF7BARCA7A6A5A4A3A2A1—
H'FF80 FLMCR1 FWE SWE — — EV PV E P FLASH 8
H'FF81FLMCR2FLER—————ESUPSU
H'FF82PCSR—————PWCKBPWCKA— PWM8
EBR1——————EB9/—EB8/—FLASH8
H'FF83 SYSCR2 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E HIF 8
EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FLASH 8
H'FF84 SBYCR SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 SYSTEM 8
H'FF85 LPWRCR DTON LSON NESEL EXCLE ————
H'FF86 MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
H'FF87 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
H'FF88 SMR1 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI1 8
ICCR1 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC1
H'FF89 BRR1 SCI1 8
ICSR1 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC1
H'FF8A SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI1 8
H'FF8B TDR1
H'FF8C SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT
H'FF8D RDR1
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 992 of 1130
REJ09B0327-0400
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
H'FF8ESCMR1————SDIRSINV—SMIFSCI18
ICDR1 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 IIC1 8
SARX1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
H'FF8F ICMR1 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
SAR1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
H'FF90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — FRT 16
H'FF91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'FF92 FRCH
H'FF93 FRCL
H'FF94 OCRAH
OCRBH
H'FF95 OCRAL
OCRBL
H'FF96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
H'FF97 TOCR ICRDMS OCRAMS ICRS OCRS OEA OEB OLVLA OLVLB
H'FF98 ICRAH
OCRARH
H'FF99 ICRAL
OCRARL
H'FF9A ICRBH
OCRAFH
H'FF9B ICRBL
OCRAFL
H'FF9C ICRCH
OCRDMH 00000000
H'FF9D ICRCL
OCRDML
H'FF9E ICRDH
H'FF9F ICRDL
H'FFA0 SMR2 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI2 8
DADRAH DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 PWMX
DACR TEST PWME — — OEB OEA OS CKS
H'FFA1 BRR2 SCI2 8
DADRAL DA5 DA4 DA3 DA2 DA1 DA0 CFS — PWMX
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 993 of 1130
REJ09B0327-0400
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
H'FFA2 SCR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI2 8
H'FFA3 TDR2
H'FFA4 SSR2 TDRE RDRF ORER FER PER TEND MPB MPBT
H'FFA5 RDR2
H'FFA6SCMR2————SDIRSINV—SMIF
DADRBH DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 PWMX 8
DACNTH
H'FFA7 DADRBL DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS
DACNTL — REGS
H'FFA8 TCSR0 OVF WT/IT TME RSTS RST/NMI CKS2 CKS1 CKS0 WDT0 16
TCNT0
(write)
H'FFA9 TCNT0
(read)
H'FFAA PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Ports 8
H'FFAB PAPIN
(read) PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN
PADDR
(write) PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
H'FFAC P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
H'FFAD P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
H'FFAE P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
H'FFB0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
H'FFB1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
H'FFB2 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR
H'FFB3 P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR
H'FFB4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
H'FFB5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
H'FFB6 P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR
H'FFB7 P4DR P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR
H'FFB8P5DDR—————P52DDRP51DDRP50DDR
H'FFB9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
H'FFBAP5DR—————P52DRP51DRP50DR
H'FFBB P6DR P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR
H'FFBC PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
H'FFBD PBPIN
(read) PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN
P8DDR
(write) — P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 994 of 1130
REJ09B0327-0400
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
H'FFBE P7PIN
(read) P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN Ports 8
PBDDR
(write) PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
H'FFBF P8DR — P86DR P85DR P84DR P83DR P82DR P81DR P80DR
H'FFC0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
H'FFC1 P9DR P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR
H'FFC2 IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Interrupt
controller 8
H'FFC3 STCR IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 System 8
H'FFC4 SYSCR CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME
H'FFC5 MDCR EXPE —————MDS1MDS0
H'FFC6 BCR ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — IOS1 IOS0 8
H'FFC7 WSCR RAMS RAM0 ABW AST WMS1 WMS0 WC1 WC0
Bus
controller
H'FFC8 TCR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 16
H'FFC9 TCR1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
TMR0,
TMR1
H'FFCA TCSR0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0
H'FFCB TCSR1 CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'FFCC TCORA0
H'FFCD TCORA1
H'FFCE TCORB0
H'FFCF TCORB1
H'FFD0 TCNT0
H'FFD1 TCNT1
H'FFD2 PWOERB OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 PWM 8
H'FFD3 PWOERA OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0
H'FFD4 PWDPRB OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8
H'FFD5 PWDPRA OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0
H'FFD6 PWSL PWCKE PWCKS — — RS3 RS2 RS1 RS0
H'FFD7 PWDR0
to
PWDR15
H'FFD8 SMR0 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI0 8
ICCR0 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC0
H'FFD9 BRR0 SCI0
ICSR0 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC0
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 995 of 1130
REJ09B0327-0400
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
H'FFDA SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI0 8
H'FFDB TDR0
H'FFDC SSR0 TDRE RDRF ORER FER PER TEND MPB MPBT
H'FFDD RDR0
H'FFDESCMR0————SDIRSINV—SMIF
ICDR0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 IIC0
SARX0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
H'FFDF ICMR0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
SAR0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
H'FFE0 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D 8
H'FFE1 ADDRAL AD1 AD0 ——————
H'FFE2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFE3 ADDRBL AD1 AD0 ——————
H'FFE4 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFE5 ADDRCL AD1 AD0 ——————
H'FFE6 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFE7 ADDRDL AD1 AD0 ——————
H'FFE8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'FFE9ADCRTRGS1TRGS0——————
H'FFEA TCSR1 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 WDT1 16
TCNT1
(write)
H'FFEB TCNT1
(read)
H'FFF0HICR—————IBFIE2IBFIE1FGA20EHIF8
TCRX CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMRX
TCRY CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMRY
H'FFF1 KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Interrupt
controller 8
TCSRX CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 TMRX
TCSRY CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0 TMRY
H'FFF2 KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Ports
TICRR TMRX
TCORAY TMRY
H'FFF3 KMIMRA KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Interrupt
controller 8
TICRF TMRX
TCORBY TMRY
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 996 of 1130
REJ09B0327-0400
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Bus
Width
H'FFF4 IDR1 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF 8
TCNTX TMRX
TCNTY TMRY
H'FFF5 ODR1 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 HIF
TCORC TMRX
TISR———————IS TMRY
H'FFF6 STR1 DBU DBU DBU DBU C/DDBU IBF OBF HIF
TCORAX TMRX
H'FFF7 TCORBX
H'FFF8 DADR0 D/A
H'FFF9 DADR1
H'FFFADACRDAOE1DAOE0DAE—————
H'FFFC IDR2 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF
TCONRI SIMOD1 SIMOD0 SCONE ICST HFINV VFINV HIINV VIINV Timer
connection
H'FFFD ODR2 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 HIF
TCONRO HOE VOE CLOE CBOE HOINV VOINV CLOINV CBOINV Timer
connection
H'FFFE STR2 DBU DBU DBU DBU C/DDBU IBF OBF HIF
TCONRS TMRX/Y ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0
H'FFFF SEDGR VEDG HEDG CEDG HFEDG VFEDG PREQF IHI IVI
Timer
connection
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 997 of 1130
REJ09B0327-0400
B.2 Register Selection Conditions
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
MRA
SAR
MRB
DAR
CRA
H'EC00
to
H'EFFF
CRB
RAME = 1 in SYSCR — — DT C
H'FE80 HICR2
H'FE84 IDR3
H'FE85 ODR3
H'FE86 STR3
H'FE8C IDR4
H'FE8D ODR4
H'FE8E STR4
MSTP2 = 0 MSTP2 = 0 — HIF
H'FED8 KBCRH0
H'FED9 KBCRL0
H'FEDA KBBR0
H'FEDC KBCRH1
H'FEDD KBCRL1
H'FEDE KBBR1
H'FEE0 KBCRH2
H'FEE1 KBCRL2
H'FEE2 KBBR2
MSTP2 = 0 MSTP2 = 0 — Keyboard
buffer
controller
H'FEE4 KBCOMP No conditions No conditions No conditions IrDA/
expansion
A/D
H'FEE6 DDCSWR MSTP4 = 0 MSTP4 = 0 — IIC0
H'FEE8 ICRA
H'FEE9 ICRB
H'FEEA ICRC
H'FEEB ISR
H'FEEC ISCRH
H'FEED ISCRL
No conditions No conditions No conditions Interrupt
controller
H'FEEE DTCERA
H'FEEF DTCERB
H'FEF0 DTCERC
H'FEF1 DTCERD
H'FEF2 DTCERE
No conditions — — DTC
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 998 of 1130
REJ09B0327-0400
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
H'FEF3 DTVECR No conditions — — DTC
H'FEF4 ABRKCR
H'FEF5 BARA
H'FEF6 BARB
H'FEF7 BARC
No conditions No conditions No conditions Interrupt
controller
H'FF80 FLMCR1
H'FF81 FLMCR2
FLSHE = 1 in STCR FLSHE = 1 in STCR FLSHE = 1 in STCR Flash
memory
PCSR FLSHE = 0 in STCR FLSHE = 0 in STCR — PWMH'FF82
EBR1 FL SHE = 1 in STCR FLSHE = 1 in STCR FLSHE = 1 in ST CR Flash
memory
SYSCR2 F LSHE = 0 in STCR FLSHE = 0 in ST CR — HIFH'FF83
EBR2 FL SHE = 1 in STCR FLSHE = 1 in STCR FLSHE = 1 in ST CR Flash
memory
H'FF84 SBYCR
H'FF85 LPWRCR
H'FF86 MSTPCRH
H'FF87 MSTPCRL
FLSHE = 0 in STCR FLSHE = 0 in STCR FLSHE = 0 in STCR System
SMR1 MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR SCI1H'FF88
ICCR1 MST P3 = 0, IICE = 1 in STCR MST P3 = 0, IICE = 1 in STCR — IIC1
BRR1 MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR SCI1H'FF89
ICSR1 MSTP3 = 0, IICE = 1 in STCR MSTP3 = 0, IICE = 1 in STCR — IIC1
H'FF8A SCR1
H'FF8B TDR1
H'FF8C SSR1
H'FF8D RDR1
MSTP6 = 0 MSTP6 = 0 MSTP6 = 0
SCMR1 MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR
SCI1
ICDR1 ICE = 1 in
ICCR1 ICE = 1 in
ICCR1
H'FF8E
SARX1 ICE = 0 in
ICCR1 ICE = 0 in
ICCR1
ICMR1 ICE = 1 in
ICCR1 ICE = 1 in
ICCR1
H'FF8F
SAR1
MSTP3 = 0,
IICE = 1 in STCR
ICE = 0 in
ICCR1
MSTP3 = 0,
IICE = 1 in STCR
ICE = 0 in
ICCR1
— IIC1
H'FF90 TIER
H'FF91 TCSR
H'FF92 FRCH
H'FF93 FRCL
MSTP13 = 0 MSTP13 = 0 MSTP13 = 0 FRT
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 999 of 1130
REJ09B0327-0400
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
OCRAH OCRS = 0 in
TOCR OCRS = 0 in
TOCR OCRS = 0 in
TOCR
H'FF94
OCRBH OCRS = 1 in
TOCR OCRS = 1 in
TOCR OCRS = 1 in
TOCR
OCRAL OCRS = 0 in
TOCR OCRS = 0 in
TOCR OCRS = 0 in
TOCR
H'FF95
OCRBL OCRS = 1 in
TOCR OCRS = 1 in
TOCR OCRS = 1 in
TOCR
H'FF96 TCR
H'FF97 TOCR
ICRAH ICRS = 0 in
TOCR ICRS = 0 in
TOCR ICRS = 0 in
TOCR
H'FF98
OCRARH ICRS = 1 in
TOCR ICRS = 1 in
TOCR ICRS = 1 in
TOCR
ICRAL ICRS = 0 in
TOCR ICRS = 0 in
TOCR ICRS = 0 in
TOCR
H'FF99
OCRARL ICRS = 1 in
TOCR ICRS = 1 in
TOCR ICRS = 1 in
TOCR
ICRBH ICRS = 0 in
TOCR ICRS = 0 in
TOCR ICRS = 0 in
TOCR
H'FF9A
OCRAFH ICRS = 1 in
TOCR ICRS = 1 in
TOCR ICRS = 1 in
TOCR
ICRBL ICRS = 0 in
TOCR ICRS = 0 in
TOCR ICRS = 0 in
TOCR
H'FF9B
OCRAFL ICRS = 1 in
TOCR ICRS = 1 in
TOCR ICRS = 1 in
TOCR
ICRCH ICRS = 0 in
TOCR ICRS = 0 in
TOCR ICRS = 0 in
TOCR
H'FF9C
OCRDMH ICRS = 1 in
TOCR ICRS = 1 in
TOCR ICRS = 1 in
TOCR
ICRCL ICRS = 0 in
TOCR ICRS = 0 in
TOCR ICRS = 0 in
TOCR
H'FF9D
OCRDML
MSTP13 = 0
ICRS = 1 in
TOCR
MSTP13 = 0
ICRS = 1 in
TOCR
MSTP13 = 0
ICRS = 1 in
TOCR
H'FF9E ICRDH
H'FF9F ICRDL
FRT
SMR2 MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR SCI2
DADRAH REGS = 0
in DACNT/
DADRB
REGS = 0
in DACNT/
DADRB
REGS = 0
in DACNT/
DADRB
H'FFA0
DACR
MSTP11 = 0,
IICE = 1 in STCR
REGS = 1
in DACNT/
DADRB
MSTP11 = 0,
IICE = 1 in STCR
REGS = 1
in DACNT/
DADRB
MSTP11 = 0,
IICE = 1 in STCR
REGS = 1
in DACNT/
DADRB
PWMX
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1000 of 1130
REJ09B0327-0400
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
BRR2 MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR SCI2H'FFA1
DADRAL MSTP11 = 0,
IICE = 1 in STCR REGS = 0
in DACNT/
DADRB
MSTP11 = 0,
IICE = 1 in STCR REGS = 0
in DACNT/
DADRB
MSTP11 = 0,
IICE = 1 in STCR REGS = 0
in DACNT/
DADRB
PWMX
H'FFA2 SCR2
H'FFA3 TDR2
H'FFA4 SSR2
H'FFA5 RDR2
MSTP5 = 0 MSTP5 = 0 MSTP5 = 0
SCMR2 MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR MSTP5 = 0, IICE = 0 in STCR
SCI2
DADRBH REGS = 0
in DACNT/
DADRB
REGS = 0
in DACNT/
DADRB
REGS = 0
in DACNT/
DADRB
H'FFA6
DACNTH REGS = 1
in DACNT/
DADRB
REGS = 1
in DACNT/
DADRB
REGS = 1
in DACNT/
DADRB
PWMX
DADRBL REGS = 0
in DACNT/
DADRB
REGS = 0
in DACNT/
DADRB
REGS = 0
in DACNT/
DADRB
H'FFA7
DACNTL
MSTP11 = 0,
IICE = 1 in STCR
REGS = 1
in DACNT/
DADRB
MSTP11 = 0,
IICE = 1 in STCR
REGS = 1
in DACNT/
DADRB
MSTP11 = 0,
IICE = 1 in STCR
REGS = 1
in DACNT/
DADRB
PWMX
TCSR0H'FFA8
TCNT0
(write)
H'FFA9 TCNT0
(read)
No conditions No conditions No conditions WDT0
H'FFAA PAODR0
PAPIN
(read)
H'FFAB
PADDR
(write)
H'FFAC P1PCR
H'FFAD P2PCR
H'FFAE P3PCR
H'FFB0 P1DDR
H'FFB1 P2DDR
H'FFB2 P1DR
H'FFB3 P2DR
H'FFB4 P3DDR
H'FFB5 P4DDR
H'FFB6 P3DR
H'FFB7 P4DR
No conditions No conditions No conditions Ports
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1001 of 1130
REJ09B0327-0400
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
H'FFB8 P5DDR
H'FFB9 P6DDR
H'FFBA P5DR
H'FFBB P6DR
H'FFBC PBODR
P8DDR
(write)
H'FFBD
PBPIN
(read)
P7PIN
(read)
H'FFBE
PBDDR
(write)
H'FFBF P8DR
H'FFC0 P9DDR
H'FFC1 P9DR
No conditions No conditions No conditions Ports
H'FFC2 IER No conditions No conditions No conditions Interrupt
controller
H'FFC3 STCR
H'FFC4 SYSCR
H'FFC5 MDCR
System
H'FFC6 BCR
H'FFC7 WSCR
No conditions No conditions No conditions
Bus
controller
H'FFC8 TCR0
H'FFC9 TCR1
H'FFCA TCSR0
H'FFCB TCSR1
H'FFCC TCORA0
H'FFCD TCORA1
H'FFCE TCORB0
H'FFCF TCORB1
H'FFD0 TCNT0
H'FFD1 TCNT1
MSTP12 = 0 MSTP12 = 0 MSTP12 = 0 TMR0,
TMR1
H'FFD2 PWOERB
H'FFD3 PWOERA
H'FFD4 PWDPRB
H'FFD5 PWDPRA
No conditions No conditions — PWM
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1002 of 1130
REJ09B0327-0400
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
H'FFD6 PWSL
H'FFD7 PWDR0 to
PWDR15
MSTP11 = 0 MSTP11 = 0 — PWM
SMR0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR SCI0H'FFD8
ICCR0 MST P4 = 0, IICE = 1 in STCR MST P4 = 0, IICE = 1 in STCR — IIC0
BRR0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR SCI0H'FFD9
ICSR0 MSTP4 = 0, IICE = 1 in STCR MSTP4 = 0, IICE = 1 in STCR — IIC0
H'FFDA SCR0
H'FFDB TDR0
H'FFDC SSR0
H'FFDD RDR0
MSTP7 = 0 MSTP7 = 0 MSTP7 = 0
SCMR0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR
SCI0
ICDR0 ICE = 1 in
ICCR0 ICE = 1 in
ICCR0
H'FFDE
SARX0 ICE = 0 in
ICCR0 ICE = 0 in
ICCR0
ICMR0 ICE = 1 in
ICCR0 ICE = 1 in
ICCR0
H'FFDF
SAR0
MSTP4 = 0,
IICE = 1 in STCR
ICE = 0 in
ICCR0
MSTP4 = 0,
IICE = 1 in STCR
ICE = 0 in
ICCR0
— IIC0
H'FFE0 ADDRAH
H'FFE1 ADDRAL
H'FFE2 ADDRBH
H'FFE3 ADDRBL
H'FFE4 ADDRCH
H'FFE5 ADDRCL
H'FFE6 ADDRDH
H'FFE7 ADDRDL
H'FFE8 ADCSR
H'FFE9 ADCR
MSTP9 = 0 MSTP9 = 0 MSTP9 = 0 A/D
TCSR1H'FFEA
TCNT1
(write)
H'FFEB TCNT1
(read)
No conditions No conditions No conditions WDT1
HICR MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0 , HIE = 1 in SYSCR — HIF
TCRX TMRX/Y = 0
in TCONRS ——TMRX
H'FFF0
TCRY
MSTP8 = 0,
HIE = 0 in SYSCR
TMRX/Y = 1
in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1003 of 1130
REJ09B0327-0400
Lower
Address Register
Name H8S/2148 Group Register
Selection Conditions H8S/2147N Register Selection
Conditions H8S/2144 Group Register
Selection Conditions Module
Name
KMIMR MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR Interrupt
controller
TCSRX TMRX/Y = 0
in TCONRS ——TMRX
H'FFF1
TCSRY
MSTP8 = 0,
HIE = 0 in SYSCR
TMRX/Y = 1
in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY
KMPCR MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR Ports
TICRR TMRX/Y = 0
in TCONRS ——TMRX
H'FFF2
TCORAY
MSTP8 = 0,
HIE = 0 in SYSCR
TMRX/Y = 1
in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY
KMIMRA MSTP2 = 0, HIE = 1 in SYSCR M STP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR Interrupt
controller
TICRF TMRX/Y = 0
in TCONRS ——TMRX
H'FFF3
TCORBY
MSTP8 = 0,
HIE = 0 in SYSCR
TMRX/Y = 1
in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY
IDR1 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR HIF
TCNTX TMRX/Y = 0
in TCONRS —
—
TMRX
H'FFF4
TCNTY
MSTP8 = 0,
HIE = 0 in SYSCR
TMRX/Y = 1
in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY
ODR1 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR HIF
TCORC TMRX/Y = 0
in TCONRS —
—
TMRX
H'FFF5
TISR
MSTP8 = 0,
HIE = 0 in SYSCR
TMRX/Y = 1
in TCONRS MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRY
STR1 M STP2 = 0, HIE = 1 in SYSCR M STP2 = 0, HIE = 1 in SYSCR HIFH'FFF6
TCORAX
H'FFF7 TCORBX
MSTP8 = 0,
HIE = 0 in SYSCR TMRX/Y = 0
in TCONRS —
—
TMRX
H'FFF8 DADR0
H'FFF9 DADR1
H'FFFA DACR
MSTP10 = 0 MSTP10 = 0 MSTP10 = 0 D/A
IDR2 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR HIFH'FFFC
TCONRI MSTP8 = 0, HIE = 0 in SYSCR — Timer
connection
ODR2 MSTP2 = 0, HIE = 1 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR HIFH'FFFD
TCONRO MSTP8 = 0, HIE = 0 in SYSCR — Timer
connection
STR2 M STP2 = 0, HIE = 1 in SYSCR M STP2 = 0, HIE = 1 in SYSCR HIFH'FFFE
TCONRS
H'FFFF SEDGR
MSTP8 = 0, HIE = 0 in SYSCR —
—
Timer
connection
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1004 of 1130
REJ09B0327-0400
B.3 Functions
DACR—D/A Control Register H'FFFA D/A Converter
Register
name Address to which the
register is mapped Name of
on-chip
supporting
module
Register
acronym
Bit
numbers
Initial bit
values Names of the
bits. Dashes
(—) indicate
reserved bits.
Full name
of bit
Descriptions
of bit settings
Read only
Write only
Read and write
R
W
R/W
Possible types of access
Bit
Initial value
Read/Write
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
D/A enabled
DAOE1
0
1
Conversion resultDAE
*
0
1
0
1
*
DAOE0
0
1
0
1
Channel 0 and 1 D/A conversion disabled
Channel 0 D/A conversion enabled
Channel 1 D/A conversion disabled
Channel 0 and 1 D/A conversion enabled
Channel 0 D/A conversion disabled
Channel 1 D/A conversion enabled
Channel 0 and 1 D/A conversion enabled
Channel 0 and 1 D/A conversion enabled
D/A output enable 0
0 Analog output DA0 disabled
1 Channel 0 D/A conversion enabled.
Analog output DA0 enabled
D/A output enable 1
0 Analog output DA1 disabled
1 Channel 1 D/A conversion enabled.
Analog output DA1 enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1005 of 1130
REJ09B0327-0400
MRA—DTC Mode Register A H'EC00–H'EFFF DTC
7
SM1
Undefined
—
6
SM0
Undefined
—
5
DM1
Undefined
—
4
DM0
Undefined
—
3
MD1
Undefined
—
0
Sz
Undefined
—
2
MD0
Undefined
—
1
DTS
Undefined
—
Bit
Initial value
Read/Write
DTC data transfer size
0 Byte-size transfer
1 Word-size transfer
DTC transfer mode select
0 Destination side is repeat
area or block area
1 Source side is repeat area
or block area
DTC mode
0 Normal mode
Repeat mode
0
1
1 Block transfer mode0 —1
Destination address mode
0 DAR is fixed
DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
—
0
1
DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1
Source address mode
0 SAR is fixed
SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
—
0
1
SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1006 of 1130
REJ09B0327-0400
MRB—DTC Mode Register B H'EC00–H'EFFF DTC
7
CHNE
Undefined
—
6
DISEL
Undefined
—
5
—
Undefined
—
4
—
Undefined
—
3
—
Undefined
—
0
—
Undefined
—
2
—
Undefined
—
1
—
Undefined
—
Bit
Initial value
Read/Write
DTC interrupt select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After a data transfer ends, the CPU interrupt is
enabled
DTC chain transfer enable
0 End of DTC data transfer
1 DTC chain transfer
SAR—DTC Source Address Register H'EC00–H'EFFF DTC
23
Unde-
fined
—
Bit
Initial value
Read/Write
22
Unde-
fined
—
21
Unde-
fined
—
20
Unde-
fined
—
19
Unde-
fined
—
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
- - -
- - -
- - -
- - -
Specifies DTC transfer data source address
DAR—DTC Destination Address Register H'EC00–H'EFFF DTC
23
Unde-
fined
—
Bit
Initial value
Read/Write
22
Unde-
fined
—
21
Unde-
fined
—
20
Unde-
fined
—
19
Unde-
fined
—
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
- - -
- - -
- - -
- - -
Specifies DTC transfer data destination address
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1007 of 1130
REJ09B0327-0400
CRA—DTC Transfer Count Register A H'EC00–H'EFFF DTC
15
Unde-
fined
—
Bit
Initial value
Read/Write
14
Unde-
fined
—
13
Unde-
fined
—
12
Unde-
fined
—
11
Unde-
fined
—
10
Unde-
fined
—
9
Unde-
fined
—
8
Unde-
fined
—
7
Unde-
fined
—
6
Unde-
fined
—
5
Unde-
fined
—
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
CRAH CRAL
Specifies the number of DTC data transfers
CRB—DTC Transfer Count Register B H'EC00–H'EFFF DTC
15
Unde-
fined
—
Bit
Initial value
Read/Write
14
Unde-
fined
—
13
Unde-
fined
—
12
Unde-
fined
—
11
Unde-
fined
—
10
Unde-
fined
—
9
Unde-
fined
—
8
Unde-
fined
—
7
Unde-
fined
—
6
Unde-
fined
—
5
Unde-
fined
—
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
Specifies the number of DTC block data transfers
HICR2—Host Interface Control Register 2 H'FE80 HIF
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
—
0
—
—
2
IBFIE4
0
R/W
—
1
IBFIE3
0
R/W
—
Bit
Initial value
Slave R/W
Host R/W
Input data register full interrupt enable
—
—
IBFIE4
0
1
0
IBFIE3 Description
—
—
1Input data register (IDR3) receive complete interrupt is disabled
Input data register (IDR4) receive complete interrupt is disabled
Input data register (IDR4) receive complete interrupt is enabled
Input data register (IDR3) receive complete interrupt is enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1008 of 1130
REJ09B0327-0400
IDR3—Input Da ta Register 3 H'FE84 HIF
IDR4—Input Da ta Register 4 H'FE8C HIF
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
Bit
Initial value
Slave R/W
Host R/W
Stores host data bus contents at rise of IOW when CS is low
ODR3—Output Data Register 3 H'FE85 HIF
ODR4—Output Data Register 4 H'FE8D HIF
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
Bit
Initial value
Slave R/W
Host R/W
ODR contents are output to the host data bus
when HA0 is low, CS is low, and IOR is low
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1009 of 1130
REJ09B0327-0400
STR3—Status Register 3 H'FE86 HIF
STR4—Status Register 4 H'FE8E HIF
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R/(W)
R
2
DBU
0
R/W
R
1
IBF
0
R
R
Bit
Initial value
Slave R/W
Host R/W
Output buffer full
0 [Clearing condition]
When the host processor
reads ODR or the slave
writes 0 in the OBF bit
1 [Setting condition]
When the slave processor
writes to ODR
User-defined bits
Input buffer full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR
Command/data
0 Contents of input data register (IDR) are data
1 Contents of input data register (IDR) are a command
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1010 of 1130
REJ09B0327-0400
KBCRH0—Keyboard Control Register H0 H'FED8 Keyboard Buffer Controller
KBCRH1—Keyboard Control Register H1 H'FEDC Keyboard Buffer Controller
KBCRH2—Keyboard Control Register H2 H'FEE0 Keyboard Buffer Controller
KBIOE KBF PER KBSKCLKI KDI KBFSEL KBIE
Bit
Initial value
Read/Write
76543210
01110000
R/W R/(W)*R/(W)*RR R R/W R/W
Keyboard stop
0 0 stop bit received
1 1 stop bit received
Note: * Only 0 can be written, to clear the flag.
Parity error
0 [Clearing condition]
Read PER when PER =1,
then write 0 in PER
1 [Setting condition]
When an odd parity error occurs
Keyboard buffer register full
0 [Clearing condition]
Read KBF when KBF =1, then write 0 in KBF
1
Keyboard interrupt enable
0 Interrupt requests are disabled
1 Interrupt requests are enabled
Keyboard buffer register full select
0 KBF bit is used as KCLK fall interrupt flag
1 KBF bit is used as keyboard buffer full flag
Keyboard data in
0 KD I/O pin is low
1 KD I/O pin is high
Keyboard clock in
0 KCLK I/O pin is low
1 KCLK I/O pin is high
Keyboard in/out enable
0 The keyboard buffer controller is non-operational (KCLK and KD signal pins
have port functions)
1 The keyboard buffer controller is enabled for transmission and reception
(KCLK and KD signal pins are in the bus drive state)
[Setting conditions]
• When data has been received normally while
KBFSEL = 1, and has been transferred to
KBBR (keyboard buffer register full flag)
• When a KCLK falling edge has been detected
while KBFSEL = 0 (KCLK interrupt flag)
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1011 of 1130
REJ09B0327-0400
KBCRL0—Keyboard Control Register L0 H'FED9 Keyboard Buffer Controller
KBCRL1—Keyboard Control Register L1 H'FEDD Keyboard Buffer Controller
KBCRL2—Keyboard Control Register L2 H'FEE1 Keyboard Buffer Controller
KBE RXCR2 RXCR1 RXCR0KCLKO KDO — RXCR3
Bit
Initial value
Read/Write
76543210
01110000
R/W R R RR/W R/W — R
Receive counter
RXCR2 RXCR1
0
1
0
1
0
1
0
1
0
1
—
RXCR0
0
1
0
1
0
1
0
1
0
1
0
1
—
RXCR3
0
1
Receive data contents
—
Start bit
KB0
KB1
KB2
KB3
KB4
KB5
KB6
KB7
Parity bit
—
—
Keyboard data out
0Keyboard buffer controller data I/O pin is low
1 Keyboard buffer controller data I/O pin is high
Keyboard clock out
0Keyboard buffer controller clock I/O pin is low
1 Keyboard buffer controller clock I/O pin is high
Keyboard enable
0Loading of receive data into KBBR is disabled
1 Loading of receive data into KBBR is enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1012 of 1130
REJ09B0327-0400
KBBR0—Keyboard Data Buffer Register 0 H'FEDA Keyboard Buffer Controller
KBBR1—Keyboard Data Buffer Register 1 H'FEDE Keyboard Buffer Controller
KBBR2—Keyboard Data Buffer Register 2 H'FEE2 K eyboard Buffer Controller
KB7 KB2 KB1 KB0KB6 KB5 KB4 KB3
Bit
Initial value
Read/Write
76543210
00000000
RRRRRRRR
Stores receive data
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1013 of 1130
REJ09B0327-0400
KBCOMP—Keyboard Compara tor Control Register H'FEE4 IrDA/Expansion A/D
7
IrE
0
R/W
6
IrCKS2
0
R/W
5
IrCKS1
0
R/W
4
IrCKS0
0
R/W
3
KBADE
0
R/W
0
KBCH0
0
R/W
2
KBCH2
0
R/W
1
KBCH1
0
R/W
Bit
Initial value
Read/Write
AN6
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
AN7
CIN8
CIN9
CIN10
CIN11
CIN12
CIN13
CIN14
CIN15
Keyboard comparator control
Bit 3
KBADE
0
1
A/D converter
channel 6 input A/D converter
channel 7 input
Bit 2
KBCH2
—
0
1
Bit 1
KBCH1
—
0
1
0
1
Bit 0
KBCH0
—
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B × 3/16 (3/16 of the bit rate)
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
IrDA Clock select 2 to 0
IrDA enable
0The TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2
1 The TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1014 of 1130
REJ09B0327-0400
DDCSWR—DDC Switch Reg ister H'FEE6 IIC0
7
SWE
0
R/W
6
SW
0
R/W
5
IE
0
R/W
4
IF
0
R/(W)*1
3
CLR3
1
W*2
0
CLR0
1
W*2
2
CLR2
1
W*2
1
CLR1
1
W*2
Bit
Initial value
Read/Write
DDC mode switch interrupt flag
0 No interrupt is requested when automatic format switching
is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
1 An interrupt is requested when automatic format switching
is executed
[Setting condition]
When a falling edge is detected on the SCL
pin when SWE = 1
DDC mode switch interrupt enable bit
0 Interrupt when automatic format switching is executed is disabled
1 Interrupt when automatic format switching is executed is enabled
DDC mode switch
0 IIC channel 0 is used with the I
2
C bus format
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
1 IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
DDC mode switch enable
0 Automatic switching of IIC channel 0 from formatless mode to I
2
C bus format is disabled
1 Automatic switching of IIC channel 0 from formatless mode to I
2
C bus format is enabled
IIC clear bits
Bit 3
CLR3
0
1
Description
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
Bit 2
CLR2
0
1
—
Bit 1
CLR1
—
0
1
—
Bit 0
CLR0
—
0
1
0
1
—
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1015 of 1130
REJ09B0327-0400
ICRA—Interrupt Control Register A H'FEE8 Interrupt Controller
ICRB—Interrupt Control Register B H'FEE9 Interrupt Controller
ICRC—Interrupt Control Register C H'FEEA Interrupt Controller
7
ICR7
0
R/W
6
ICR6
0
R/W
5
ICR5
0
R/W
4
ICR4
0
R/W
3
ICR3
0
R/W
0
ICR0
0
R/W
2
ICR2
0
R/W
1
ICR1
0
R/W
Bit
Initial value
Read/Write
Interrupt control level
0 Corresponding interrupt source is control level 0 (non-priority)
1 Corresponding interrupt source is control level 1 (priority)
Correspondence between Interrupt Sources and ICR Settings
Register Bits
76543210
ICRA IRQ0 IRQ1 IRQ2
IRQ3 IRQ4
IRQ5 IRQ6
IRQ7 DTC Watchdog
timer 0 Watchdog
timer 1
ICRB A/D
converter Free-
running
timer
— — 8-bit timer
channel 0 8-bit timer
channel 1 8-bit timer
channels
X, Y
HIF,
keyboard
buffer
controller
ICRC SCI
channel 0 SCI
channel 1 SCI
channel 2 IIC
channel 0
(option)
IIC
channel 1
(option)
———
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1016 of 1130
REJ09B0327-0400
ISR—IRQ Status Register H'FEEB Interrupt Contro ller
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
0
IRQ0F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
Bit
Initial value
Read/Write
IRQ7 to IRQ0 flags
0 [Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high*
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)*
1 [Setting conditions]
• When IRQn input goes low when low-level detection is set
(IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in IRQn input while falling edge detection is
set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input while rising edge detection is
set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge
detection is set (IRQnSCB = IRQnSCA = 1)
Note: * Only 0 can be written, to clear the flag.
Notes: n = 7 to 0
* When a product, in which a DTC is incorporated, is used in the
following settings, the corresponding flag bit is not automatically
cleared even when exception handling, which is a clear condition, is
executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source),
IRQ4F flag is not automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source),
IRQ5F flag is not automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source),
IRQ6F flag is not automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt souce),
IRQ7F flag is not automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts are used
with the above combinations, clear the interrupt flag by software in the
interrupt handling routine of the corresponding IRQ.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1017 of 1130
REJ09B0327-0400
ISCRH—IRQ Sense Control Register H H 'FEEC Interrupt Controller
ISCRL—IRQ Sense Control Register L H'FEED Interrupt Controller
15
IRQ7SCB
0
R/W
14
IRQ7SCA
0
R/W
13
IRQ6SCB
0
R/W
12
IRQ6SCA
0
R/W
11
IRQ5SCB
0
R/W
8
IRQ4SCA
0
R/W
10
IRQ5SCA
0
R/W
9
IRQ4SCB
0
R/W
Bit
Initial value
Read/Write
ISCRH
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
3
IRQ1SCB
0
R/W
0
IRQ0SCA
0
R/W
2
IRQ1SCA
0
R/W
1
IRQ0SCB
0
R/W
Bit
Initial value
Read/Write
ISCRL
IRQ7 to IRQ4 sense control A and B
IRQ3 to IRQ0 sense control A and B
Description
ISCRH bits 7 to 0
ISCRL bits 7 to 0
IRQ7SCB to
IRQ0SCB IRQ7SCA to
IRQ0SCA
0
1
0
1
0
1
Interrupt request generated at IRQ7 to IRQ0
input at low level
Interrupt request generated at falling edge
of IRQ7 to IRQ0 input
Interrupt request generated at rising edge
of IRQ7 to IRQ0 input
Interrupt request generated at both falling
and rising edges of IRQ7 to IRQ0 input
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1018 of 1130
REJ09B0327-0400
DTCER—DTC Enable Register H'FEEE to H'FEF2 DTC
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
Bit
Initial value
Read/Write
DTC activation enable
0 DTC activation by interrupt is disabled
[Clearing conditions]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
1 DTC activation by interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers
have not ended
DTVECR—DTC Vector Register H'FEF3 DTC
7
SWDTE
0
R/(W)*
6
DTVEC6
0
R/W
5
DTVEC5
0
R/W
4
DTVEC4
0
R/W
3
DTVEC3
0
R/W
0
DTVEC0
0
R/W
2
DTVEC2
0
R/W
1
DTVEC1
0
R/W
Bit
Initial value
Read/Write
Note: *
Sets vector number for DTC software activation
DTC software activation enable
0 DTC software activation is disabled
[Clearing condition]
When the DISEL bit is 0 and the specified number of transfers have
not ended
1 DTC software activation is enabled
[Holding conditions]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
• During software-activated deta transfer
A value of 1 can always be written to the SWDTE bit, but 0 can only be written
after 1 is read.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1019 of 1130
REJ09B0327-0400
ABRKCR—Address Break Control Register H'FEF4 Interrupt Co ntroller
7
CMF
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
BIE
0
R/W
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
Break interrupt enable
0 Address break disabled
1 Address break enabled
Condition match flag
0 [Clearing condition]
When address break interrupt exception handling is executed
1 [Setting condition]
When address set by BARA to BARC is prefetched while BIE = 1
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1020 of 1130
REJ09B0327-0400
BARA—Break Address Register A H'FEF5 Interrupt Controller
BARB—Break Address Regist er B H'FEF 6 Interrupt Controller
BARC—Break Address Register C H'FEF7 Interrupt Controller
7
A23
0
R/W
6
A22
0
R/W
5
A21
0
R/W
4
A20
0
R/W
3
A19
0
R/W
0
A16
0
R/W
2
A18
0
R/W
1
A17
0
R/W
Bit
BARA
Initial value
Read/Write
7
A15
0
R/W
6
A14
0
R/W
5
A13
0
R/W
4
A12
0
R/W
3
A11
0
R/W
0
A8
0
R/W
2
A10
0
R/W
1
A9
0
R/W
Bit
BARB
Initial value
Read/Write
7
A7
0
R/W
6
A6
0
R/W
5
A5
0
R/W
4
A4
0
R/W
3
A3
0
R/W
0
—
0
—
2
A2
0
R/W
1
A1
0
R/W
Bit
BARC
Initial value
Read/Write
Specifies address (bits 23 to 16) at which address break is to be generated
Specifies address (bits 15 to 8) at which address break is to be generated
Specifies address (bits 7 to 1) at which address break is to be generated
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1021 of 1130
REJ09B0327-0400
FLMCR1—Flash Memory Control Register 1 H 'FF80 Flash Memory
7
FWE
1
R
6
SWE
0
R/W
5
—
0
—
4
—
0
—
3
EV
0
R/W
0
P
0
R/W
2
PV
0
R/W
1
E
0
R/W
Bit
Initial value
Read/Write
Program
0 Program mode cleared
1 Transition to program mode
[Setting condition]
When SWE = 1, and PSU = 1
Erase
0 Erase mode cleared
1 Transition to erase mode
[Setting condition]
When SWE = 1, and ESU = 1
Program-verify
0 Program-verify mode cleared
1 Transition to program-verify mode
[Setting condition]
When SWE = 1
Erase-verify
0 Erase-verify mode cleared
1 Transition to erase-verify mode
[Setting condition]
When SWE = 1
Software write enable
0 Writes disabled
1 Writes enabled
Reserved bit
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1022 of 1130
REJ09B0327-0400
FLMCR2—Flash Memory Control Register 2 H 'FF81 Flash Memory
7
FLER
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
PSU
0
R/W
2
—
0
—
1
ESU
0
R/W
Bit
Initial value
Read/Write
Program setup
0 Program setup cleared
1 Program setup
[Setting condition]
When SWE = 1
Erase setup
0 Erase setup cleared
1 Erase setup
[Setting condition]
When SWE = 1
Flash memory error
0 Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 22.8.3 or 23.8.3, Error Protection
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1023 of 1130
REJ09B0327-0400
PCSR—Peripheral Clock Select Register H'FF82 P WM
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
—
0
—
2
PWCKB
0
R/W
1
PWCKA
0
R/W
Bit
Initial value
Read/Write
PWM clock select
PWSL PCSR
Bit 7
PWCKE
0
1
Bit 6
PWCKS
—
0
1
Bit 2
PWCKB
—
—
0
1
Bit 1
PWCKA
—
—
0
1
0
1
Clock input is disabled
φ (system clock) is selected
φ/2 is selected
φ/4 is selected
φ/8 is selected
φ/16 is selected
Description
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1024 of 1130
REJ09B0327-0400
SYSCR2—System Contro l Reg ister 2 H'FF8 3 HIF
7
KWUL1
0
R/W
6
KWUL0
0
R/W
5
P6PUE
0
R/W
4
—
0
—
3
SDE
0
R/W
0
HI12E
0
R/W
2
CS4E
0
R/W
1
CS3E
0
R/W
Bit
Initial value
Read/Write
Host interface enable
0 Host interface functions
are disabled
1 Host interface functions
are enabled
Shutdown enable
0 Host interface pin shutdown function disabled
1 Host interface pin shutdown function enabled
CS4 enable
0 Host interface pin channel 4
functions disabled
1 Host interface pin channel 4
functions enabled
CS3 enable
0 Host interface pin channel 3
functions disabled
1 Host interface pin channel 3
functions enabled
Port 6 input pull-up extra
0 Standard current specification is selected for port 6 MOS
input pull-up function
1Current-limit specification is selected for port 6 MOS input
pull-up function
Key wakeup level 1 and 0
0 Standard input level is selected as port 6 input level
Input level 1 is selected as port 6 input level
Input level 2 is selected as port 6 input level
Input level 3 is selected as port 6 input level
0
1
10
1
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1025 of 1130
REJ09B0327-0400
EBR1—Erase Block Register 1 H'FF82 Flash Memory
EBR2—Erase Block Register 2 H'FF83 Flash Memory
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
EB8/—*
2
0
R/W*
1
*
2
2
—
0
—
1
EB9/—*
2
0
R/W*
1
*
2
Bit
EBR1
Initial value
Read/Write
7
EB7
0
R/W*
1
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit
EBR2
Initial value
Read/Write
Block (Size)
128-kbyte versions 64-kbyte versions
Erase Blocks
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (8 kbytes)
EB7 (8 kbytes)
EB8 (32 kbytes)
EB9 (32 kbytes)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (8 kbytes)
EB7 (8 kbytes)
—
—
Addresses
H'(00)0000 to H'(00)03FF
H'(00)0400 to H'(00)07FF
H'(00)0800 to H'(00)0BFF
H'(00)0C00 to H'(00)0FFF
H'(00)1000 to H'(00)7FFF
H'(00)8000 to H'(00)BFFF
H'(00)C000 to H'(00)DFFF
H'00E000 to H'00FFFF
H'010000 to H'017FFF
H'018000 to H'01FFFF
Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.
2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they must not be set to 1.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1026 of 1130
REJ09B0327-0400
SBYCR—Standby Control Register H'F F84 Sy ste m
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
Read/Write
0
1
0
1
0
1
0
1
0
1
—
Bus master is in high-speed mode
Medium-speed clock = φ/2
Medium-speed clock = φ/4
Medium-speed clock = φ/8
Medium-speed clock = φ/16
Medium-speed clock = φ/32
—
0
1
System clock select 2 to 0
0
1
0
1
0
1
0
1
0
1
0
1
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states*
0
1
Standby timer select 2 to 0
Software standby
0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode
or medium-speed mode
Transition to subsleep mode on execution of SLEEP instruction in subactive mode
1 Transition to software standby mode, subactive mode, or watch mode after execution
of SLEEP instruction in high-speed mode or medium-speed mode
Transition to watch mode or high-speed mode after execution of SLEEP instruction in
subactive mode
Note: * This setting must not be used in the flash memory version.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1027 of 1130
REJ09B0327-0400
LPWRCR—Low-Power Control Register H'FF85 System
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
EXCLE
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
Subclock input enable
0 Subclock input from EXCL pin is disabled
1 Subclock input from EXCL pin is enabled
Noise elimination sampling frequency select
0 Sampling at φ divided by 32
1 Sampling at φ divided by 4
Low-speed on flag
0 • When a SLEEP instruction is executed in high-speed mode or
medium-speed mode, a transition is made to sleep mode, software
standby mode, or watch mode*
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode, or directly to high-speed mode
• After watch mode is cleared, a transition is made to high-speed mode
1 • When a SLEEP instruction is executed in high-speed mode a
transition is made to watch mode or subactive mode*
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode or watch mode
• After watch mode is cleared, a transition is made to subactive mode
Direct-transfer on flag
0 • When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode*
• When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode
1 • When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or software standby mode
• When a SLEEP instruction is executed in subactive mode, a transition is made directly
to high-speed mode, or a transition is made to subsleep mode
Note: * When a transition is made to watch mode or subactive mode,
high-speed mode must be set.
Note: * When a transition is made to watch mode or subactive mode, high-speed mode
must be set.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1028 of 1130
REJ09B0327-0400
MSTPCRH—Module Stop Cont rol Register H H'FF86 System
MSTPCRL—Module Stop Control Register L H'FF87 System
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
Module stop
0 Module stop mode is cleared
1 Module stop mode is set
MSTP15
MSTP14*
MSTP13
MSTP12
MSTP11
MSTP10
MSTP9
MSTP8
MSTP7
MSTP6
MSTP5
MSTP4*
MSTP3*
MSTP2*
MSTP1*
MSTP0*
—
Data transfer controller (DTC)
16-bit free-running timer (FRT)
8-bit timers (TMR0, TMR1)
8-bit PWM timer (PWM), 14-bit PWM timer (PWMX)
D/A converter
A/D converter
8-bit timers (TMRX, TMRY), timer connection
Serial communication interface 0 (SCI0)
Serial communication interface 1 (SCI1)
Serial communication interface 2 (SCI2)
I
2
C bus interface (IIC) channel 0 (option)
I
2
C bus interface (IIC) channel 1 (option)
Host interface (HIF), keyboard buffer controller (PS2)
—
—
MSTPCRH
MSTPCRL
Register Bit Module
The correspondence between MSTPCR bits and on-chip supporting modules is shown below.
Notes: Do not set bit 15 to 1. Bits 1 and 0 can be read and written but do not affect operation.
* Must be set to 1 in the H8S/2144 Group.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1029 of 1130
REJ09B0327-0400
SMR1—Serial Mode Register 1 H'FF88 SCI1
SMR2—Serial Mode Register 2 H'FFA0 SCI2
SMR0—Serial Mode Register 0 H'FFD8 SCI0
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Clock select 1 and 0
0φ clock
φ/4 clock
φ/16 clock
φ/64 clock
0
1
10
1
Stop bit length
0 1 stop bit
2 stop bits1
Multiprocessor mode
0 Multiprocessor function disabled
1 Multiprocessor format selected
Parity mode
0 Even parity
Odd parity1
Parity enable
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled1
Character length
0 8-bit data
7-bit data*
1
Note: * When 7-bit data is selected, the MSB (bit 7)
of TDR is not transmitted. Also, LSB-first/
MSB-first selection is not available.
Communication mode
0 Asynchronous mode
Synchronous mode1
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1030 of 1130
REJ09B0327-0400
ICCR1—I2C Bu s Control Register 1 H'FF88 IIC1
ICCR0—I2C Bu s Control Register 0 H'FFD8 IIC0
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Bit
Initial value
Read/Write
Start condition/stop condition
prohibit
0Writing 0 issues a start or
stop condition, in combination
with the BBSY flag
1 Reading always returns a
value of 1; writing is ignored
I
2
C bus interface interrupt request flag
0Waiting for transfer, or transfer in
progress
1 Interrupt requested
Note: For the clearing and setting
conditions, see section 16.2.5,
I
2
C Bus Control Register (ICCR).
Bus busy
0Bus is free
[Clearing condition]
When a stop condition is detected
1 Bus is busy
[Setting condition]
When a start condition is detected
Acknowledge bit judgement selection
0The value of the acknowledge bit is ignored,
and continuous transfer is performed
1 If the acknowledge bit is 1, continuous
transfer is interrupted
Master/slave select (MST), transmit/receive select (TRS)
0Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
0
1
10
1
I
2
C bus interface interrupt
enable
0Interrupts disabled
1 Interrupts enabled
Note: For details, see section 16.2.5, I
2
C Bus Control
Register (ICCR).
I
2
C bus interface enable
0I
2
C bus interface module disabled, with
SCL and SDA signal pins set to port
function
SAR and SARX can be accessed
1I
2
C bus interface module enabled for
transfer operations (pins SCL and SDA
are driving the bus)
ICMR and ICDR can be accessed
Note: * Only 0 can be written, to clear the flag.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1031 of 1130
REJ09B0327-0400
BRR1—Bit Rate Register 1 H'FF89 SCI1
BRR2—Bit Rate Register 2 H'FFA1 SCI2
BRR0—Bit Rate Register 0 H'FFD9 SCI0
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
Sets the serial transmit/receive bit rate
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1032 of 1130
REJ09B0327-0400
ICSR1—I2C Bus Status Register 1 H'FF89 IIC1
ICSR0—I2C Bus Status Register 0 H'FFD 9 IIC0
7
ESTP
0
R/(W)*
1
6
STOP
0
R/(W)*
1
5
IRTR
0
R/(W)*
1
4
AASX
0
R/(W)*
1
3
AL
0
R/(W)*
1
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
1
ADZ
0
R/(W)*
1
Bit
Initial value
Read/Write
Acknowledge bit
0Receive mode: 0 is output at
acknowledge output timing
Transmit mode: indicates that
the receiving device has
acknowledged the data (signal is 0)
1 Receive mode: 1 is output at
acknowledge output timing
Transmit mode: indicates that
the receiving device has not
acknowledged the data (signal is 1)
Notes:
General call address recognition flag*2
0General call address not recognized
1 General call address recognized
Slave address recognition flag*2
0Slave address or general call address
not recognized
1 Slave address or general call address
recognized
Arbitration lost*2
0Bus arbitration won
1 Arbitration lost
Second slave address recognition flag*2
0Second slave address not recognized
1 Second slave address recognized
I
2
C bus interface continuous transmission/reception interrupt request flag*2
0 Waiting for transfer, or transfer in progress
1 Continuous transfer state
Normal stop condition detection flag*2
0No normal stop condition
1In I
2
C bus format slave mode: Normal stop condition detected
In other modes: No meaning
Error stop condition detection flag*2
0No error stop condition
1In I
2
C bus format slave mode: Error stop condition detected
In other modes: No meaning
1. Only 0 can be written, to clear the flag.
2. For the clearing and setting conditions, see section 16.2.6, I
2
C Bus Status Register (ICSR).
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1033 of 1130
REJ09B0327-0400
SCR1—Serial Control Register 1 H'FF8A SCI1
SCR2—Serial Control Register 2 H'FFA2 SCI2
SCR0—Serial Control Register 0 H'FFDA SCI0
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit
Initial value
Read/Write
Clock enable 1 and 0
0Asynchronous
mode
Synchronous
mode
0
Asynchronous
mode
1
Synchronous
mode
1 Asynchronous
mode
0
Synchronous
mode
Asynchronous
mode
1
Synchronous
mode
Internal clock/SCK pin
functions as I/O port
Internal clock/SCK pin
functions as serial clock output
Internal clock/SCK pin
functions as clock output
Internal clock/SCK pin
functions as serial clock output
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
Transmit end interrupt enable
0Transmit-end interrupt (TEI) request disabled
1 Transmit-end interrupt (TEI) request enabled
Multiprocessor interrupt enable
0Multiprocessor interrupts disabled (normal reception mode)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1 Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive-error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
Receive enable
0Reception disabled
1 Reception enabled
Transmit enable
0Transmission disabled
1 Transmission enabled
Receive interrupt enable
0Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request disabled
1 Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request enabled
Transmit interrupt enable
0Transmit-data-empty interrupt
(TXI) request disabled
1 Transmit-data-empty interrupt
(TXI) request enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1034 of 1130
REJ09B0327-0400
RDR1—Receive Data Register 1 H'FF8D SCI1
RDR2—Receive Data Register 2 H'FFA5 SCI2
RDR0—Receive Data Register 0 H'FFDD SCI0
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Initial value
Read/Write
Stores serial receive data
TDR1—Transmit Data Reg ister 1 H'FF8B SCI1
TDR2—Transmit Data Register 2 H'FFA3 SCI2
TDR0—Transmit Data Reg ister 0 H'FFDB SCI0
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
Stores serial transmit data
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1035 of 1130
REJ09B0327-0400
SSR1—Serial Stat us Register 1 H'FF8C SCI1
SSR2—Serial Stat us Register 2 H'FFA4 SCI2
SSR0—Serial Stat us Register 0 H'FFDC SCI0
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Bit
Initial value
Read/Write
Multiprocessor bit transfer
0Data with a 0 multi-processor
bit is transmitted
1 Data with a 1 multi-processor
bit is transmitted
Note: * Only 0 can be written, to clear the flag.
Multiprocessor bit
0[Clearing condition]
When data with a 0 multiprocessor
bit is received
1 [Setting condition]
When data with a 1 multiprocessor
bit is received
Transmit end
0[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Parity error
0[Clearing condition]
When 0 is written in PER after reading PER = 1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Framing error
0[Clearing condition]
When 0 is written in FER after reading FER = 1
1 [Setting condition]
When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0
Overrun error
0[Clearing condition]
When 0 is written in ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1
Receive data register full
0[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Transmit data register empty
0[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1036 of 1130
REJ09B0327-0400
SCMR1—Serial Interface Mode Register 1 H'FF8E SCI1
SCMR2—Serial Interface Mode Register 2 H'FFA6 SCI2
SCMR0—Serial Interface Mode Register 0 H'FFDE SCI0
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit
Initial value
Read/Write
Serial communication
interface mode select
0 Normal SCI mode
1 Setting prohibited
Data invert
0 TDR contents are transmitted without modification
Receive data is stored in RDR without modification
1 TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Data transfer direction
0 TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
1 TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1037 of 1130
REJ09B0327-0400
ICDR1—I2C Bu s Data Regi ster 1 H'F F8E IIC1
ICDR0—I2C Bus Data Register 0 H'FFDE IIC0
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
Bit
Initial value
Read/Write
7
ICDRR7
—
R
6
ICDRR6
—
R
5
ICDRR5
—
R
4
ICDRR4
—
R
3
ICDRR3
—
R
0
ICDRR0
—
R
2
ICDRR2
—
R
1
ICDRR1
—
R
Bit
Initial value
Read/Write
ICDRR
ICDRS
7
ICDRS7
—
—
6
ICDRS6
—
—
5
ICDRS5
—
—
4
ICDRS4
—
—
3
ICDRS3
—
—
0
ICDRS0
—
—
2
ICDRS2
—
—
1
ICDRS1
—
—
Bit
Initial value
Read/Write
ICDRT
7
ICDRT7
—
W
6
ICDRT6
—
W
5
ICDRT5
—
W
4
ICDRT4
—
W
3
ICDRT3
—
W
0
ICDRT0
—
W
2
ICDRT2
—
W
1
ICDRT1
—
W
Bit
Initial value
Read/Write
TDRE, RDRF (internal flags)
—
RDRF
0
—
—
TDRE
0
—
Bit
Initial value
Read/Write
Note: For details, see section 16.2.1, I2C Bus Data Register (ICDR).
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1038 of 1130
REJ09B0327-0400
SARX1—Second Slave Address Register 1 H 'FF8 E IIC1
SAR1—Slave Addr ess Regist e r 1 H'FF8F IIC1
SARX0—Second Slave Address Register 0 H 'FFDE IIC0
SAR0—Slave Addr ess Regist e r 0 H'FFDF IIC0
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Bit
Initial value
Read/Write
SAR
SARX
Slave address Format select
Second slave address
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Bit
Initial value
Read/Write
Note: *
Format select
DDCSWR
Bit 6
SW
SAR
Bit 0
FS
SARX
Bit 0
FSX Operating Mode
I
2
C bus format
• SAR and SARX slave addresses recognized
000
I
2
C bus format
• SAR slave address recognized
• SARX slave address ignored
I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
Synchronous serial format
• SAR and SARX slave addresses ignored
Formatless mode (start/stop conditions not
detected)
• Acknowledge bit used
Formatless mode*
(start/stop conditions not detected)
• No acknowledge bit
1
10
1
100
1
10
1
Do not set this mode when automatic switching to the I
2
C bus format is
performed by means of the DDCSWR setting.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1039 of 1130
REJ09B0327-0400
ICMR1—I2C Bus Mode Re gister 1 H'FF8F IIC1
ICMR0—I2C B us Mode Register 0 H'FFDF IIC0
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
Bit
Initial value
Read/Write
Bit counter
BC2 BC1
0
1
0
1
0
1
BC0
0
1
0
1
0
1
0
1
Note: * Do not set this bit to 1 when the I
2
C bus format is used.
Synchronous
serial format
8
1
2
3
4
5
6
7
I
2
C bus
format
9
2
3
4
5
6
7
8
Serial clock select
CKS2 CKS1
0
1
0
1
0
1
0
1
0
1
0
1
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IICX
0
1
Clock
φ/28
φ/40
φ/48
φ/64
φ/80
φ/100
φ/112
φ/128
φ/56
φ/80
φ/96
φ/128
φ/160
φ/200
φ/224
φ/256
Wait insertion bit
0Data and acknowledge bits transferred consecutively
1 Wait inserted between data and acknowledge bits
MSB-first/LSB-first select*
0MSB-first
1 LSB-first
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1040 of 1130
REJ09B0327-0400
TIER—Timer Interrupt Enable Register H'FF90 FRT
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
R/W
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
Bit
Initial value
Read/Write
Input capture interrupt A enable
0 Input capture interrupt request A (ICIA) is disabled
1 Input capture interrupt request A (ICIA) is enabled
Input capture interrupt B enable
0 Input capture interrupt request B (ICIB) is disabled
1 Input capture interrupt request B (ICIB) is enabled
Input capture interrupt C enable
0 Input capture interrupt request C (ICIC) is disabled
1 Input capture interrupt request C (ICIC) is enabled
Input capture interrupt D enable
0 Input capture interrupt request D (ICID) is disabled
1 Input capture interrupt request D (ICID) is enabled
Output compare interrupt A enable
0 Output compare interrupt request A
(OCIA) is disabled
1 Output compare interrupt request A
(OCIA) is enabled
Output compare interrupt B enable
0 Output compare interrupt
request B (OCIB) is disabled
1 Output compare interrupt
request B (OCIB) is enabled
Timer overflow interrupt enable
0 Timer overflow interrupt
request (FOVI) is disabled
1 Timer overflow interrupt
request (FOVI) is enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1041 of 1130
REJ09B0327-0400
TCSR—Timer Control/Status Register H'FF91 FRT
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
R/(W)*
4
ICFD
0
R/(W)*
3
OCFA
0
R/(W)*
0
CCLRA
0
R/W
2
OCFB
0
R/(W)*
1
OVF
0
R/(W)*
Bit
Initial value
Read/Write
Input capture flag A
Note: * Only 0 can be written in bits 7 to 1, to clear the flags.
0[Clearing condition]
Read ICFA when ICFA = 1, then write 0 in ICFA
1 [Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRA
Input capture flag B
0[Clearing condition]
Read ICFB when ICFB = 1, then write 0 in ICFB
1 [Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRB
Input capture flag C
0[Clearing condition]
Read ICFC when ICFC = 1, then write 0 in ICFC
1 [Setting condition]
When an input capture signal is received
Input capture flag D
0[Clearing condition]
Read ICFD when ICFD = 1, then write 0 in ICFD
1 [Setting condition]
When an input capture signal is received
Counter clear A
0FRC clearing is
disabled
1 FRC is cleared at
compare match A
Timer overflow flag
0[Clearing condition]
Read OVF when OVF = 1,
then write 0 in OVF
1 [Setting condition]
When FRC changes from
H'FFFF to H'0000
Output compare flag B
0[Clearing condition]
Read OCFB when OCFB = 1, then write 0 in OCFB
1 [Setting condition]
When FRC = OCRB
Output compare flag A
0[Clearing condition]
Read OCFA when OCFA = 1, then write 0 in OCFA
1 [Setting condition]
When FRC = OCRA
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1042 of 1130
REJ09B0327-0400
FRC—Free-Running Counter H'FF92 FRT
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
8
0
R/W
10
0
R/W
9
0
R/W
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
OCRA/OCRB—Output Compare Register A/B H'FF94 F RT
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
8
1
R/W
10
1
R/W
9
1
R/W
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Constantly compared with FRC value; OCF is set when OCR = FRC
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1043 of 1130
REJ09B0327-0400
TCR—Timer Control Register H'FF96 FRT
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Input edge select A
0Capture on the falling edge of FTIA
Capture on the rising edge of FTIA1
Input edge select B
0Capture on the falling edge of FTIB
Capture on the rising edge of FTIB 1
Input edge select C
0Capture on the falling edge of FTIC
Capture on the rising edge of FTIC1
Input edge select D
0Capture on the falling edge of FTID
Capture on the rising edge of FTID1
Buffer enable A
0ICRC is not used as a buffer register for
input capture A
ICRC is used as a buffer register for input
capture A
1
Buffer enable B
0ICRD is not used as a buffer
register for input capture B
1
Clock select
0φ/2 internal clock source 0
1φ/8 internal clock source
φ/32 internal clock source
External clock source
(rising edge)
0
1
1
ICRD is used as a buffer
register for input capture B
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1044 of 1130
REJ09B0327-0400
TOCR—Timer Output Compare Contro l Register H'FF97 FRT
7
ICRDMS
0
R/W
6
OCRAMS
0
R/W
5
ICRS
0
R/W
4
OCRS
0
R/W
3
OEA
0
R/W
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
Bit
Initial value
Read/Write
Output level B
0 0 output at compare-
match B
1 1 output at compare-
match B
Output level A
0 0 output at compare-
match A
1 1 output at compare-
match A
Output enable B
0Output compare B output disabled
1Output compare B output enabled
Output enable A
0 Output compare A output disabled
1 Output compare A output enabled
Output compare register select
0 OCRA register selected
1 OCRB register selected
Input capture register select
0ICRA, ICRB, and ICRC registers selected
1OCRAR, OCRAF, and OCRDM registers selected
Output compare A mode select
0 OCRA set to normal operating mode
1 OCRA set to operating mode using OCRAR and OCRAF
Input capture D mode select
0 ICRD set to normal operating mode
1 ICRD set to operating mode using OCRDM
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1045 of 1130
REJ09B0327-0400
OCRAR—Output Compare Register AR H'FF98 FRT
OCRAF—Output Compare Register AF H'FF9A FRT
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
8
1
R/W
10
1
R/W
9
1
R/W
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Used for OCRA operation when OCRAMS = 1 in TOCR
(For details, see section 11.2.4, Output Compare Registers
AR and AF (OCRAR, OCRAF).)
OCRDM—Output Compare Register DM H'FF9C FRT
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
8
0
R
10
0
R
9
0
R
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Used for ICRD operation when ICRDMS = 1 in TOCR
(For details, see section 11.2.5, Output Compare Register
DM (OCRDM).)
ICRA—Input Capture Reg ister A H'FF9 8 FRT
ICRB—Input Capture Reg ister B H'FF9A FRT
ICRC—Input Capture Reg ister C H'FF9 C FRT
ICRD—Input Capture Reg ister D H'FF9 E F RT
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
8
0
R
10
0
R
9
0
R
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Stores FRC value when input capture signal is input
(ICRC and ICRD can be used for buffer operation.
For details, see section 11.2.3, Input Capture Registers
A to D (ICRA to ICRD).)
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1046 of 1130
REJ09B0327-0400
DADRAH—PWM (D/A) Data Register AH H'FFA0 PWMX
DADRAL—PWM (D/A) Data Register AL H'FFA1 PWMX
DADRBH—PWM (D/A) Data Register BH H'FFA6 PWMX
DADRBL—PWM (D/A) Data Register BL H'FFA7 PWMX
15
13
DA13
1
R/W
14
12
DA12
1
R/W
13
11
DA11
1
R/W
12
10
DA10
1
R/W
11
9
DA9
1
R/W
8
6
DA6
1
R/W
10
8
DA8
1
R/W
9
7
DA7
1
R/W
Bit (CPU)
Bit (data)
DADRA
Initial value
Read/Write
7
5
DA5
1
R/W
6
4
DA4
1
R/W
5
3
DA3
1
R/W
4
2
DA2
1
R/W
3
1
DA1
1
R/W
0
—
—
1
—
2
0
DA0
1
R/W
1
—
CFS
1
R/W
DADRH DADRL
DA13
1
R/W
DA12
1
R/W
DA11
1
R/W
DA10
1
R/W
DA9
1
R/W
DA6
1
R/W
DA8
1
R/W
DA7
1
R/W
DADRB
Initial value
Read/Write
DA5
1
R/W
DA4
1
R/W
DA3
1
R/W
DA2
1
R/W
DA1
1
R/W
REGS
1
R/W
DA0
1
R/W
CFS
1
R/W
Register select (DADRB only)
0 DADRA and DADRB can be accessed
1 DACR and DACNT can be accessed
Carrier frequency select
0 Base cycle = resolution (T) × 64 DADR range
is H'0401 to H'FFFD
1 Base cycle = resolution (T) × 256 DADR range
is H'0103 to H'FFFF
D/A conversion data
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1047 of 1130
REJ09B0327-0400
DACR—PWM (D/A) Control Register H'FFA0 PWMX
7
TEST
0
R/W
6
PWME
0
R/W
5
—
1
—
4
—
1
—
3
OEB
0
R/W
0
CKS
0
R/W
2
OEA
0
R/W
1
OS
0
R/W
Bit
Initial value
Read/Write
Clock select
0 Operates at resolution (T) =
system clock cycle time (t
cyc
)
1 Operates at resolution (T) =
system clock cycle time (t
cyc
) × 2
Output select
0 Direct PWM output
1 Inverted PWM output
Output enable A
0 PWM (D/A) channel A output
(PWX0 output pin) disabled
1 PWM (D/A) channel A output
(PWX0 output pin) enabled
Output enable B
0 PWM (D/A) channel B output
(PWX1 output pin) disabled
1 PWM (D/A) channel B output
(PWX1 output pin) enabled
PWM enable
0 DACNT operates as a 14-bit up-counter
1 DACNT halts at H'0003
Test mode
0 PWM (D/A) in user state: normal operation
1 PWM (D/A) in test state: correct conversion results unobtainable
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1048 of 1130
REJ09B0327-0400
DACNTH—PWM (D/A) Counter H H'FFA6 PWMX
DACNTL—PWM (D/A) Counter L H'FFA7 PWMX
15
7
0
R/W
14
6
0
R/W
13
5
0
R/W
12
4
0
R/W
11
3
0
R/W
8
0
0
R/W
10
2
0
R/W
9
1
0
R/W
Bit (CPU)
Bit (counter)
Initial value
Read/Write
7
8
0
R/W
6
9
0
R/W
5
10
0
R/W
4
11
0
R/W
3
12
0
R/W
0
—
REGS
1
R/W
2
13
0
R/W
1
—
—
1
—
DACNTH DACNTL
Up-counter
Register select
0 DADRA and DADRB can be accessed
1 DACR and DACNT can be accessed
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1049 of 1130
REJ09B0327-0400
TCSR0—Timer Co nt rol/Status Register 0 H'F F A8 WDT0
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
RSTS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Clock select 2 to 0
CKS2
0
1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
CKS1
0
1
0
1
CKS0
0
1
0
1
0
1
0
1
Note: * Only 0 can be written, to clear the flag.
Note: * When OVF is polled and the interval timer interrupt is disabled,
OVF = 1 must be read at least twice.
Clock
Reset or NMI
0 NMI interrupt requested
1 Internal reset requested
Timer enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Reserved bit
Timer mode select
0
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1
Watchdog timer mode: Generates a reset or NMI interrupt when
TCNT overflows
Overflow flag
0 [Clearing conditions]
•
Write 0 in the TME bit
•
Read TCSR when OVF = 1*, then write 0 in OVF
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.)
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1050 of 1130
REJ09B0327-0400
TCNT0—Timer Counter 0 H'FFA8 (W), H'FFA9 (R) WDT0
TCNT1—Timer C ounter 1 H'FFEA (W) , H'FF EB (R) W DT1
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
Up-counter
PAODR—Port A Output Data Register H'FFAA Port A
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
0
PA0ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
Bit
Initial value
Read/Write
Output data for port A pins
PAPIN—Port A Input Data Register H'FFAB (R) Port A
7
PA7PIN
—*
R
6
PA6PIN
—*
R
5
PA5PIN
—*
R
4
PA4PIN
—*
R
3
PA3PIN
—*
R
0
PA0PIN
—*
R
2
PA2PIN
—*
R
1
PA1PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by state of pins PA7 to PA0.
Port A pin states
PADDR—Port A Data Direction Register H'FFAB (W) Port A
7
PA7DDR
0
W
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
0
PA0DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port A pins
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1051 of 1130
REJ09B0327-0400
P1PCR—Port 1 MOS Pull-Up Control Register H'FFAC P ort 1
7
P17PCR
0
R/W
6
P16PCR
0
R/W
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
0
P10PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
Bit
Initial value
Read/Write
Control of port 1 built-in MOS input pull-ups
P2PCR—Port 2 MOS Pull-Up Control Register H'FFAD P ort 2
7
P27PCR
0
R/W
6
P26PCR
0
R/W
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
0
P20PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
Bit
Initial value
Read/Write
Control of port 2 built-in MOS input pull-ups
P3PCR—Port 3 MOS Pull-Up Control Register H'FFAE Port 3
7
P37PCR
0
R/W
6
P36PCR
0
R/W
5
P35PCR
0
R/W
4
P34PCR
0
R/W
3
P33PCR
0
R/W
0
P30PCR
0
R/W
2
P32PCR
0
R/W
1
P31PCR
0
R/W
Bit
Initial value
Read/Write
Control of port 3 built-in MOS input pull-ups
P1DDR—Port 1 Data Direction Register H'FFB0 Port 1
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
0
P10DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 1 pins
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1052 of 1130
REJ09B0327-0400
P2DDR—Port 2 Data Direction Register H'FFB1 Port 2
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
4
P24DDR
0
W
3
P23DDR
0
W
0
P20DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 2 pins
P1DR—Port 1 Data Register H'FFB2 Port 1
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
0
P10DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 1 pins
P2DR—Port 2 Data Register H'FFB3 Port 2
7
P27DR
0
R/W
6
P26DR
0
R/W
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
0
P20DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 2 pins
P3DDR—Port 3 Data Direction Register H'FFB4 Port 3
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
0
P30DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 3 pins
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1053 of 1130
REJ09B0327-0400
P4DDR—Port 4 Data Direction Register H'FFB5 Port 4
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
3
P43DDR
0
W
0
P40DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 4 pins
P3DR—Port 3 Data Register H'FFB6 Port 3
7
P37DR
0
R/W
6
P36DR
0
R/W
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
0
P30DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 3 pins
P4DR—Port 4 Data Register H'FFB7 Port 4
7
P47DR
0
R/W
6
P46DR
0
R/W
5
P45DR
0
R/W
4
P44DR
0
R/W
3
P43DR
0
R/W
0
P40DR
0
R/W
2
P42DR
0
R/W
1
P41DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 4 pins
P5DDR—Port 5 Data Direction Register H'FFB8 Port 5
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P50DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
Bit
Initial value
Read/Write
Specification of input or
output for port 5 pins
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1054 of 1130
REJ09B0327-0400
P6DDR—Port 6 Data Direction Register H'FFB9 Port 6
7
P67DDR
0
W
6
P66DDR
0
W
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
0
P60DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 6 pins
P5DR—Port 5 Data Register H'FFBA Port 5
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P50DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 5 pins
P6DR—Port 6 Data Register H'FFBB Po rt 6
7
P67DR
0
R/W
6
P66DR
0
R/W
5
P65DR
0
R/W
4
P64DR
0
R/W
3
P63DR
0
R/W
0
P60DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 6 pins
PBODR—Port B Output Data Register H'FFBC Port B
7
PB7ODR
0
R/W
6
PB6ODR
0
R/W
5
PB5ODR
0
R/W
4
PB4ODR
0
R/W
3
PB3ODR
0
R/W
0
PB0ODR
0
R/W
2
PB2ODR
0
R/W
1
PB1ODR
0
R/W
Bit
Initial value
Read/Write
Output data for port B pins
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1055 of 1130
REJ09B0327-0400
P8DDR—Port 8 Data Direction Register H'FFBD (W) Port 8
7
—
1
—
6
P86DDR
0
W
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
0
P80DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 8 pins
PBPIN—Port B Input Data Register H 'F F BD (R ) Port B
7
PB7PIN
—*
R
6
PB6PIN
—*
R
5
PB5PIN
—*
R
4
PB4PIN
—*
R
3
PB3PIN
—*
R
0
PB0PIN
—*
R
2
PB2PIN
—*
R
1
PB1PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by state of pins PB7 to PB0.
Port B pin states
PBDDR—Port B Data Direction Register H'FFBE (W) P ort B
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
0
PB0DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port B pins
P7PIN—Port 7 Input Data Register H'FFBE ( R ) Port 7
7
P77PIN
—*
R
6
P76PIN
—*
R
5
P75PIN
—*
R
4
P74PIN
—*
R
3
P73PIN
—*
R
0
P70PIN
—*
R
2
P72PIN
—*
R
1
P71PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by state of pins P77 to P70.
Port 7 pin states
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1056 of 1130
REJ09B0327-0400
P8DR—Port 8 Data Register H'FFBF Port 8
7
—
1
—
6
P86DR
0
R/W
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
0
P80DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 8 pins
P9DDR—Port 9 Data Direction Register H'FFC0 Port 9
7
P97DDR
0
W
0
W
6
P96DDR
1
W
0
W
5
P95DDR
0
W
0
W
4
P94DDR
0
W
0
W
3
P93DDR
0
W
0
W
0
P90DDR
0
W
0
W
2
P92DDR
0
W
0
W
1
P91DDR
0
W
0
W
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
Specification of input or output for port 9 pins
P9DR—Port 9 Data Register H'FFC1 Port 9
7
P97DR
0
R/W
6
P96DR
—*
R
5
P95DR
0
R/W
4
P94DR
0
R/W
3
P93DR
0
R/W
0
P90DR
0
R/W
2
P92DR
0
R/W
1
P91DR
0
R/W
Bit
Initial value
Read/Write
Note: * Determined by state of pin P96.
Output data for port 9 pins
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1057 of 1130
REJ09B0327-0400
IER—IRQ E na ble Register H'FF C 2 Interrupt Controller
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
Bit
Initial value
Read/Write
IRQ7 to IRQ0 enable
0 IRQn interrupt disabled
1 IRQn interrupt enabled
(n = 7 to 0)
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1058 of 1130
REJ09B0327-0400
STCR—Serial Timer Control Register H'FFC3 System
7
IICS
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
Bit
Initial value
Read/Write
Notes: 1.
2.
Internal Clock Source
Select*
1
Reserved bit
Flash memory control register enable
0 Flash memory control register not selected
1 Flash memory control register selected
I
2
C master enable
0 CPU access to SCI0, SCI1, and SCI2 control
registers is enabled
1 CPU access to I
2
C bus interface data, PWMX and
control registers is enabled
0 PA7 to PA4 are normal I/O pins
1 PA7 to PA4 are I/O pins with bus driving capability
I
2
C transfer select 1 and 0*
2
I
2
C extra buffer select
Used for 8-bit timer input clock selection. For details, see section 12.2.4, Timer
Control Register (TCR).
Used for I
2
C bus interface transfer clock selection. For details, see section 16.2.4,
I
2
C Bus Mode Register (ICMR).
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1059 of 1130
REJ09B0327-0400
SYSCR—System Control Register H'FFC4 System
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
RAM Enable
0On-chip RAM is disabled
1 On-chip RAM is enabled
Host interface enable
0Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to 8-bit timer (channel
X and Y) data registers and control
registers, and timer connection
control registers
1 Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to host interface data
registers and control registers, and
keyboard controller and MOS input
pull-up control registers
NMI edge select
0Falling edge
1 Rising edge
External reset
0Reset generated by watchdog timer overflow
1 Reset generated by an external reset
Interrupt control mode select
INTM1
Interrupt control mode 0
Interrupt control mode 1
INTM0 Description
00
1
CS2 enable
0CS2 pin function halted
(CS2 fixed high internally)
0
CS2E FGA20E
1
1CS2 pin function selected for P81/CS2 pin0
CS2 pin function selected for P90/ECS2 pin1
Description
SYSCR
Bit 7 HICR
Bit 0
IOS enable
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,
the address range is from H'(FF)F000 to H'(FF)F7FF.
0The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
1 The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)*
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1060 of 1130
REJ09B0327-0400
MDCR—Mode Control Register H'FFC5 System
7
EXPE
—*
R/W*
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
—
0
—
1
MDS1
—*
R
Bit
Initial value
Read/Write
Expanded mode enable
0 Single-chip mode selected
1 Expanded mode selected
Note: * Determined by the MD1 and MD0 pins.
Mode select 1 and 0
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1061 of 1130
REJ09B0327-0400
BCR—Bus Control Reg ister H'FFC6 Bus Controller
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
IOS0
1
R/W
2
—
1
R/W
1
IOS1
1
R/W
Bit
Initial value
Read/Write
IOS select
IOS1 Address for which AS/IOS pin
output goes low when IOSE = 1
0 Low in access to address
H'(FF)F000 to H'(FF)F03F
IOS0
0
Low in access to address
H'(FF)F000 to H'(FF)F0FF
1
1 Low in access to address
H'(FF)F000 to H'(FF)F3FF
0
Low in access to address
H'(FF)F000 to H'(FF)FE4F
1
Burst cycle select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst cycle select 1
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Burst ROM enable
0 Basic bus interface
1 Burst ROM interface
Idle cycle insert 0
0 Idle cycle not inserted in case of successive
external read and external write cycles
1 Idle cycle inserted in case of successive
external read and external write cycles
Reserved bit
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1062 of 1130
REJ09B0327-0400
WSCR—Wait State Control Register H'FFC7 Bus Controller
7
RAMS
0
R/W
6
RAM0
0
R/W
5
ABW
1
R/W
4
AST
1
R/W
3
WMS1
0
R/W
0
WC0
1
R/W
2
WMS0
0
R/W
1
WC1
1
R/W
Bit
Initial value
Read/Write
Reserved bits
Wait count 1 and 0
0 No program wait
states are inserted
0
1 program wait state
is inserted in external
memory space
accesses
1
1 2 program wait states
are inserted in external
memory space
accesses
0
3 program wait states
are inserted in external
memory space
accesses
1
Wait mode select 1 and 0
0 Program wait mode
0Wait disabled mode1
1 Pin wait mode0 Pin auto-wait mode1
Access state control
0 External memory space is designated as 2-state
access space
Wait state insertion in external memory space
accesses is disabled
1 External memory space is designated as 3-state
access space
Wait state insertion in external memory space
accesses is enabled
Bus width control
0 External memory space designated as 16-bit access space
1 External memory space designated as 8-bit access space
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1063 of 1130
REJ09B0327-0400
TCR0—Timer Control Register 0 H'FFC8 TMR0
TCR1—Timer Control Register 1 H'FFC9 TMR1
TCRX—Timer Control Register X H'FFF0 TMRX
TCRY—Timer Control Register Y H'FFF0 TMRY
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Clock select 2 to 0
Channel Bit 2 Bit 1 Bit 0
CKS2
0
1
X
Y
All
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
CKS1 CKS0 Description
Clock input disabled
Internal clock: counting at falling edge of φ/8
Internal clock: counting at falling edge of φ/2
Internal clock: counting at falling edge of φ/64
Internal clock: counting at falling edge of φ/32
Internal clock: counting at falling edge of φ/1024
Internal clock: counting at falling edge of φ/256
Counting at TCNT1 overflow signal*2
Clock input disabled
Internal clock: counting at falling edge of φ/8
Internal clock: counting at falling edge of φ/2
Internal clock: counting at falling edge of φ/64
Internal clock: counting at falling edge of φ/128
Internal clock: counting at falling edge of φ/1024
Internal clock: counting at falling edge of φ/2048
Count at TCNT0 compare match A*2
Clock input disabled
Internal clock: counting on φ
Internal clock: counting at falling edge of φ/2
Internal clock: counting at falling edge of φ/4
Clock input disabled
Clock input disabled
Internal clock: counting at falling edge of φ/4
Internal clock: counting at falling edge of φ/256
Internal clock: counting at falling edge of φ/2048
Clock input disabled
External clock: counting at rising edge
External clock: counting at falling edge
External clock: counting at both rising and falling
edges
*
1
*
1
*
1
*
1
*
1
*
1
Notes: 1.
2.
Selected by ICKS1 and ICKS0 in STCR. For details, see section 12.2.4,
Timer Control Register (TCR).
If the clock input of channel 0 is the TCNT1 overflow signal and that of
channel 1 is the TCNT0 compare match signal, no incrementing clock is
generated. Do not use this setting.
Counter clear 1 and 0
0Clear is disabled
Cleared on compare
match A
0
1
1 Cleared on compare
match B
0
Cleared on rising edge
of external reset input
1
Timer overflow interrupt enable
0OVF interrupt request (OVI) is disabled
1 OVF interrupt request (OVI) is enabled
Compare match interrupt enable A
0CMFA interrupt request (CMIA) is disabled
1 CMFA interrupt request (CMIA) is enabled
Compare Match Interrupt Enable B
0CMFB interrupt request (CMIB) is disabled
1 CMFB interrupt request (CMIB) is enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1064 of 1130
REJ09B0327-0400
TCSR0—Timer Co nt rol/Status Register 0 H'FF C A TMR0
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSR0
Output select 1 and 0
0 No change at compare match A
00 output at compare match A1
1 1 output at compare match A0 Output inverted at compare
match A (toggle output)
1
Note:
Output select 3 and 2
0 No change at compare match B
00 output at compare match B1
1 1 output at compare match B0 Output inverted at compare
match B (toggle output)
1
A/D trigger enable
0 A/D converter start requests by compare match A
are disabled
1 A/D converter start requests by compare match A
are enabled
Timer overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Compare match flag A
0 [Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
1 [Setting condition]
When TCNT = TCORA
Compare match flag B
0 [Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
1 [Setting condition]
When TCNT = TCORB
* Only 0 can be written in bits 7 to 5, to clear the flags.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1065 of 1130
REJ09B0327-0400
TCSR1—Timer Co nt rol/Status Register 1 H'FF C B TMR1
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSR1
Output select 1 and 0
0 No change at compare match A
00 output at compare match A1
1 1 output at compare match A0 Output inverted at compare
match A (toggle output)
1
Output select 3 and 2
0 No change at compare match B
00 output at compare match B1
1 1 output at compare match B0 Output inverted at compare
match B (toggle output)
1
Timer overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Compare match flag A
0 [Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
1 [Setting condition]
When TCNT = TCORA
Compare match flag B
0 [Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
1 [Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written in bits 7 to 5, to clear the flags.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1066 of 1130
REJ09B0327-0400
TCORA0—Time Constant Register A0 H'FFCC TMR0
TCORA1—Time Constant Register A1 H'FFCD TMR1
TCORB0—Time Constant Register B0 H'FFCE TMR0
TCORB1—Time Constant Register B1 H'FFCF TMR1
TCORAY—Time Constant Register AY H'FFF2 TMRY
TCORBY—Time Constant Register BY H'FFF3 TMRY
TCORC—Time Constant Register C H'FFF5 TMRX
TCORAX—Time Constant Register AX H'FFF6 TMRX
TCORBX—Time Constant Register BX H'FFF7 TMRX
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
15
1
R/W
Bit
Initial value
Read/Write
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORA0
TCORB0 TCORA1
TCORB1
Compare match flag (CMF) is set when TCOR and TCNT values match
Compare match flag (CMF) is set when TCOR and TCNT values match
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
Compare match C signal is generated when sum of TCORC and TICR
contents match TCNT value
TCORAX, TCORAY
TCORBX, TCORBY
TCORC
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1067 of 1130
REJ09B0327-0400
TCNT0—Timer Counter 0 H'FFD0 TMR0
TCNT1—Timer Counter 1 H'FFD1 TMR1
TCNTX—Timer Counter X H'FFF4 TMRX
TCNTY—Timer Counter Y H'FFF4 TMRY
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
Up-counter
15
0
R/W
Bit
Initial value
Read/Write
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
TCNT0 TCNT1
Up-counter
TCNTX, TCNTY
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1068 of 1130
REJ09B0327-0400
PWOERA—PWM Output Enable Register A H'FFD3 PWM
PWOERB—PWM Output Enable Register B H'FFD2 PWM
7
OE7
0
R/W
6
OE6
0
R/W
5
OE5
0
R/W
4
OE4
0
R/W
3
OE3
0
R/W
0
OE0
0
R/W
2
OE2
0
R/W
1
OE1
0
R/W
Bit
PWOERA
Initial value
Read/Write
7
OE15
0
R/W
6
OE14
0
R/W
5
OE13
0
R/W
4
OE12
0
R/W
3
OE11
0
R/W
Switching between PWM output and port output
0
OE8
0
R/W
2
OE10
0
R/W
1
OE9
0
R/W
Bit
PWOERB
Initial value
Read/Write
0
1
0
1
0
1
Port input
Port input
Port output or PWM 256/256 output
PWM output (0 to 255/256 output)
DDR OE Description
PWDPRA—PWM Data Polarity Reg ister A H'FFD5 PWM
PWDPRB—PWM Data Polarity Register B H'FFD4 PWM
7
OS7
0
R/W
6
OS6
0
R/W
5
OS5
0
R/W
4
OS4
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
PWDPRA
Initial value
Read/Write
7
OS15
0
R/W
6
OS14
0
R/W
5
OS13
0
R/W
4
OS12
0
R/W
3
OS11
0
R/W
0
OS8
0
R/W
2
OS10
0
R/W
1
OS9
0
R/W
Bit
PWDPRB
Initial value
Read/Write
PWM output polarity control
0 PWM direct output (PWDR value corresponds to high width of output)
1 PWM inverted output (PWDR value corresponds to low width of output)
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1069 of 1130
REJ09B0327-0400
PWSL—PWM Register Select H'FFD6 PWM
7
PWCKE
0
R/W
6
PWCKS
0
R/W
5
—
1
—
4
—
0
—
3
RS3
0
R/W
0
RS0
0
R/W
2
RS2
0
R/W
1
RS1
0
R/W
Bit
Initial value
Read/Write
0
1
PWDR0 selected
PWDR1 selected
PWDR2 selected
PWDR3 selected
PWDR4 selected
PWDR5 selected
PWDR6 selected
PWDR7 selected
PWDR8 selected
PWDR9 selected
PWDR10 selected
PWDR11 selected
PWDR12 selected
PWDR13 selected
PWDR14 selected
PWDR15 selected
Register Select
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PWM clock enable, PWM clock select
Clock input disabled
φ (system clock) selected
φ/2 selected
φ/4 selected
φ/8 selected
φ/16 selected
PWSL PCSR
Bit 2
PWCKB
—
—
0
1
Bit 1
PWCKA
—
—
0
1
0
1
Bit 7
PWCKE
0
1
Bit 6
PWCKS
—
0
1
Description
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1070 of 1130
REJ09B0327-0400
PWDR0 to PWDR15—PWM Data Registers H'FFD7 PWM
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
Specifies duty factor of basic output pulse and number of additional pulses
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
ADDRAH—A/D Data Register AH H'FFE0 A/D Conv erter
ADDRAL—A/D Data Register AL H'FFE1 A/D Converter
ADDRBH—A/D Data Register BH H'FFE2 A/D Converter
ADDRBL—A/D Data Register BL H'FFE3 A/D Converter
ADDRCH—A/D Data Register CH H'FFE4 A/D Conv erter
ADDRCL—A/D Data Register CL H'FFE5 A/D Converter
ADDRDH—A/D Data Register DH H'FFE6 A/D Conv erter
ADDRDL—A/D Data Register DL H'FFE7 A/D Converter
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
Bit
Initial value
Read/Write
ADDRH
Stores A/D data
Correspondence between analog input channels and ADDR registers
ADDRL
ADDRA
ADDRB
ADDRC
ADDRD
Group 0
AN0
AN1
AN2
AN3
Group 1
AN4
AN5
AN6 or CIN0 to CIN7
AN7 or CIN8 to CIN15
Analog Input Channel A/D Data Register
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1071 of 1130
REJ09B0327-0400
ADCSR—A/D Control/Sta tus Reg ister H'FFE8 A/D Converter
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
*
Bit
Initial value
Read/Write
Channel select
0
1
0
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6 or CIN0 to 7
AN7 or CIN8 to 15
Description
AN0
AN0, AN1
AN0, AN1, AN2
AN0, AN1, AN2, AN3
AN4
AN4, AN5
AN4, AN5, AN6 or CIN0 to 7
AN4, AN5, AN6 or CIN0 to 7,
AN7 or CIN8 to 15
Group
selection
CH1 CH0 Single mode Scan modeCH2
0
1
Note: * Only 0 can be written, to clear the flag.
Channel
selection
Clock select
0Conversion time = 266 states (max.)
1 Conversion time = 134 states (max.)
Scan mode
0Single mode
1 Scan mode
A/D interrupt enable
0A/D conversion end interrupt (ADI) request disabled
1 A/D conversion end interrupt (ADI) request enabled
A/D end flag
0[Clearing conditions]
• When 0 is written in the to ADF flag after reading ADF = 1
• When the DTC is activated by an ADI interrupt, and ADDR is read
1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
A/D start
0A/D conversion stopped
1 • Single mode: A/D conversion is started. Cleared to 0 automatically
when conversion on the specified channel ends
• Scan mode: A/D conversion is started. Conversion continues
sequentially on the selected channels until ADST is cleared to
0 by software, a reset, or a transition to standby mode or module
stop mode
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1072 of 1130
REJ09B0327-0400
ADCR—A/D Control Register H'FFE9 A/D Converter
7
TRGS1
0
R/W
6
TRGS0
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
Timer trigger select
0 Start of A/D conversion by external trigger is disabled
Start of A/D conversion by external trigger is disabled
Start of A/D conversion by external trigger (8-bit timer) is enabled
Start of A/D conversion by external trigger pin is enabled
0
1
10
1
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1073 of 1130
REJ09B0327-0400
TCSR1—Timer Co nt rol/Status Register 1 H'F F EA WDT1
7
OVF
0
R/(W)*
1
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Clock select 2 to 0
PSS
0
1
ClockCKS2
0
1
0
1
CKS1
0
1
0
1
0
1
0
1
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes: 1.
2.
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Reset or NMI
0NMI interrupt requested
1 Internal reset requested
Prescaler select
*
2
0TCNT counts on a ø-based prescaler (PSM) scaled clock
1 TCNT counts on a øSUB-based prescaler (PSS) scaled clock
Timer enable
0TCNT is initialized to H'00 and halted
1 TCNT counts
Timer mode select
0Interval timer mode: Interval timer interrupt request (WOVI)
sent to CPU when TCNT overflows
1 Watchdog timer mode: Reset or NMI interrupt request sent
to CPU when TCNT overflows
Only 0 can be written, to clear the flag.
For operation control when a transition is made to power-down mode, see section 25.2.3, Timer Control/Status Register (TCSR).
Note: * When OVF is polled and the interval timer interrupt is disabled,
OVF = 1 must be read at least twice.
Overflow flag
0 [Clearing conditions]
•
Write 0 in the TME bit
•
Read TCSR when OVF = 1*, then write 0 in OVF
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.)
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1074 of 1130
REJ09B0327-0400
HICR—Host Interface Control Register H'FFF0 HIF
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
FGA20E
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
Bit
Initial value
Slave R/W
Host R/W
Fast gate A20 enable
0 Fast gate A20 function
disabled
1 Fast gate A20 function
enabled
Input data register full interrupt enable 1
0 Input data register (IDR1)
receive complete interrupt is
disabled
1 Input data register (IDR1)
receive complete interrupt is
enabled
Input data register full interrupt enable 2
0 Input data register (IDR2) receive complete
interrupt is disabled
1 Input data register (IDR2) receive complete
interrupt is enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1075 of 1130
REJ09B0327-0400
TCSRX—Timer Control/Status Register X H'FFF1 TMRX
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ICF
0
R/(W)*
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSRX
Output select 1 and 0
0 No change at compare match A
00 output at compare match A1
1 1 output at compare match A0Output inverted at compare
match A (toggle output)
1
Note:
Output select 3 and 2
0 No change at compare match B
00 output at compare match B1
1 1 output at compare match B0 Output inverted at compare
match B (toggle output)
1
Input capture flag
0 [Clearing condition]
When 0 is written in ICF after reading ICF = 1
1 [Setting condition]
When a rising edge followed by a falling edge is
detected in the external reset signal after the
ICST bit in TCONRI has been set to 1
Timer overflow flag
0 [Clearing condition]
When 0 is written in OVF after reading OVF = 1
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Compare match flag A
0 [Clearing conditions]
• When 0 is written in CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt
1 [Setting condition]
When TCNT = TCORA
Compare match flag B
0 [Clearing conditions]
• When 0 is written in CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt
1 [Setting condition]
When TCNT = TCORB
* Only 0 can be written in bits 7 to 4, to clear the flags.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1076 of 1130
REJ09B0327-0400
TCSRY—Timer Control/Status Register Y H'FFF1 TMRY
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ICIE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
Read/Write
TCSRY
Output select 1 and 0
0 No change at compare match A
00 output at compare match A1
1 1 output at compare match A0Output inverted at compare
match A (toggle output)
1
Note:
Output select 3 and 2
0 No change at compare match B
00 output at compare match B1
1 1 output at compare match B0 Output inverted at compare
match B (toggle output)
1
Input capture interrupt enable
0Interrupt request by ICF (ICIX) is disabled
1Interrupt request by ICF (ICIX) is enabled
Timer overflow flag
0 [Clearing condition]
When 0 is written in OVF after reading OVF = 1
1 [Setting condition]
When TCNT overflows from H'FF to H'00
Compare match flag A
0 [Clearing conditions]
• When 0 is written in CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt
1 [Setting condition]
When TCNT = TCORA
Compare match flag B
0 [Clearing conditions]
• When 0 is written in CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt
1 [Setting condition]
When TCNT = TCORB
* Only 0 can be written in bits 7 to 5, to clear the flags.
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1077 of 1130
REJ09B0327-0400
KMIMR—Keyboard Matrix Interrupt Mask Register H'FFF1 Interrupt Controller
KMIMRA—Keyboard Matrix Interrupt Mask Register A H'FFF3 Interrupt Controller
7
KMIMR7
1
R/W
6
KMIMR6
0
R/W
5
KMIMR5
1
R/W
4
KMIMR4
1
R/W
3
KMIMR3
1
R/W
0
KMIMR0
1
R/W
2
KMIMR2
1
R/W
1
KMIMR1
1
R/W
Bit
Initial value
Read/Write
KMIMR
7
KMIMR15
1
R/W
6
KMIMR14
1
R/W
5
KMIMR13
1
R/W
4
KMIMR12
1
R/W
3
KMIMR11
1
R/W
0
KMIMR8
1
R/W
2
KMIMR10
1
R/W
1
KMIMR9
1
R/W
Bit
Initial value
Read/Write
KMIMRA
Keyboard matrix interrupt mask
0 Key-sense input interrupt requests enabled
1 Key-sense input interrupt requests disabled
Keyboard matrix interrupt mask
0 Key-sense input interrupt requests enabled
1 Key-sense input interrupt requests disabled
TICRR—Input Capture Register R H'FFF2 TMRX
TICRF—Input Capture Register F H'FFF3 TMRX
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Initial value
Read/Write
Stores TCNT value at fall of external reset input
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1078 of 1130
REJ09B0327-0400
KMPCR—Port 6 MOS Pull-Up Control Register H'FFF2 Port 6
7
KM7PCR
0
R/W
6
KM6PCR
0
R/W
5
KM5PCR
0
R/W
4
KM4PCR
0
R/W
3
KM3PCR
0
R/W
0
KM0PCR
0
R/W
2
KM2PCR
0
R/W
1
KM1PCR
0
R/W
Bit
Initial value
Read/Write
Control of port 6 built-in MOS input pull-ups
Note: KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY.
When selecting KMPCR, set the HIE bit to 1 in SYSCR.
IDR1—Input Data Reg ister 1 H'FFF4 HIF
IDR2—Input Data Reg ister 2 H'FFFC HIF
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
Bit
Initial value
Slave R/W
Host R/W
Stores host data bus contents at rise of IOW when CS is low
ODR1—Output Data Register 1 H'FFF5 HIF
ODR2—Output Data Register 2 H'FFFD HIF
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
Bit
Initial value
Slave R/W
Host R/W
ODR contents are output to the host data bus
when HA0 is low, CS is low, and IOR is low
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1079 of 1130
REJ09B0327-0400
TISR—Timer Input Select Register H'FFF5 TMRY
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IS
0
R/W
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
Input select
0
1
IVG signal is selected (H8S/2148 Group)
External clock/reset input is disabled (H8S/2144 Group,
H8S/2147N)
VSYNCI/TMIY (TMCIY/TMRIY) is selected
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1080 of 1130
REJ09B0327-0400
STR1—Status Register 1 H'FFF6 HIF
STR2—Status Register 2 H'FFFE HIF
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R/(W)
R
2
DBU
0
R/W
R
1
IBF
0
R
R
Bit
Initial value
Slave R/W
Host R/W
Output buffer full
0 [Clearing condition]
When the host processor
reads ODR
1 [Setting condition]
When the slave processor
writes to ODR
User-defined bits
Input buffer full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR
Command/data
0 Contents of input data register (IDR) are data
1 Contents of input data register (IDR) are a command
DADR0—D/A Data Register 0 H'FFF8 D/A Converter
DADR1—D/A Data Register 1 H'FFF9 D/A Converter
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
Stores data for D/A conversion
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1081 of 1130
REJ09B0327-0400
DACR—D/A Control Register H'FFFA D/A Converter
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Bit
Initial value
Read/Write
D/A enabled
DAOE1
0Conversion resultDAE
*
0
1
0
1
*1
01
DAOE0
0
1Channel 0 and 1 D/A conversion disabled
Channel 0 D/A conversion enabled
Channel 1 D/A conversion disabled
Channel 0 and 1 D/A conversion enabled
Channel 0 D/A conversion disabled
Channel 1 D/A conversion enabled
Channel 0 and 1 D/A conversion enabled
Channel 0 and 1 D/A conversion enabled
Legend: *: Don’t care
D/A output enable 0
0 Analog output DA0 disabled
1 D/A conversion is enabled on channel 0.
Analog output DA0 is enabled
D/A output enable 1
0 Analog output DA1 disabled
1 D/A conversion is enabled on channel 1.
Analog output DA1 is enabled
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1082 of 1130
REJ09B0327-0400
TCONRI—Timer Connection Register I H'FFFC Timer Connection
Bit
Initial value
Read/Write
7
SIMOD1
0
R/W
6
SIMOD0
0
R/W
5
SCONE
0
R/W
4
ICST
0
R/W
3
HFINV
0
R/W
0
VIINV
0
R/W
2
VFINV
0
R/W
1
HIINV
0
R/W
Input synchronization mode select 1 and 0
0
1
No signal
S-on-G mode
Composite mode
Separate mode
0
1
0
1
SIMOD1 Mode HFBACKI input
CSYNCI input
HSYNCI input
HSYNCI input
IHI signal VFBACKI input
PDC input
PDC input
VSYNCI input
IVI signalSIMOD0
Synchronization signal connection enable
0
1
FTIA
input
Normal
connection
SCONE FTIA FTIB FTIC FTID TMCI1 TMRI1
Mode FTIB
input FTIC
input TMCI1
input TMRI1
input
FTID
input
IVI
signal
Synchronization
signal connec-
tion mode
TMO1
signal VFBACKI
input IHI
signal IVI
inverse
signal
IHI
signal
Input synchronization
signal inversion
0The VSYNCI pin state
is used directly as
the VSYNCI input
1 The VSYNCI pin state
is inverted before use
as the VSYNCI input
Input synchronization signal inversion
0The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1 The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
Input synchronization signal inversion
0The VFBACKI pin state is used directly as the VFBACKI input
1 The VFBACKI pin state is inverted before use as the VFBACKI input
Input capture start bit
0The TICRR and TICRF input capture functions are stopped
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
1 The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Input synchronization signal inversion
0The HFBACKI pin state is used directly as the HFBACKI input
1 The HFBACKI pin state is inverted before use as the HFBACKI input
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1083 of 1130
REJ09B0327-0400
TCONRO—Timer Connection Register O H 'FFFD Timer Connection
Bit
Initial value
Read/Write
7
HOE
0
R/W
6
VOE
0
R/W
5
CLOE
0
R/W
4
CBOE
0
R/W
3
HOINV
0
R/W
0
CBOINV
0
R/W
2
VOINV
0
R/W
1
CLOINV
0
R/W
Output synchronization
signal inversion
0The CBLANK signal is
used directly as the
CBLANK output
1 The CBLANK signal is
inverted before use as
the CBLANK output
Output synchronization signal inversion
0The CLO signal (CL1, CL2, CL3,
or CL4 signal) is used directly as
the CLAMPO output
1 The CLO signal (CL1, CL2, CL3,
or CL4 signal) is inverted before
use as the CLAMPO output
Output synchronization signal inversion
0The IVO signal is used directly as
the VSYNCO output
1 The IVO signal is inverted before
use as the VSYNCO output
Output synchronization signal inversion
0The IHO signal is used directly as the HSYNCO output
1 The IHO signal is inverted before use as the HSYNCO output
Output enable
0The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin
1 In mode 1 (expanded mode with on-chip ROM disabled):
The P27/A15/PW15/CBLANK pin functions as the A15 pin
In modes 2 and 3 (expanded modes with on-chip ROM enabled):
The P27/A15/PW15/CBLANK pin functions as the CBLANK pin
Output enable
0The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin
1 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
Output enable
0The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/KIN1/CIN1 pin
1 The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin
Output enable
0The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/HIRQ1 pin
1 The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1084 of 1130
REJ09B0327-0400
TCONRS—Timer Connection Register S H'FFFE Timer Connection
7
TMRX/Y
0
R/W
6
ISGENE
0
R/W
5
HOMOD1
0
R/W
4
HOMOD0
0
R/W
3
VOMOD1
0
R/W
0
CLMOD0
0
R/W
2
VOMOD0
0
R/W
1
CLMOD1
0
R/W
Bit
Initial value
Read/Write
Clamp waveform mode select 1 and 0
CLMOD1CLMOD0
0
1
0
1
0
1
0
1
0
1
0
1
Description
The CL1 signal is selected
The CL2 signal is selected
The CL3 signal is selected
The CL4 signal is selected
ISGENE
0
1
Vertical synchronization output mode select 1 and 0
VOMOD1 VOMOD0
0
1
0
1
0
1
0
1
0
1
0
1
Description
ISGENE
0
1
Horizontal synchronization output mode select 1 and 0
HOMOD1 HOMOD0
0
1
0
1
0
1
0
1
0
1
0
1
Description
The IHI signal (without 2fH modification) is selected
The IHI signal (with 2fH modification) is selected
The CL1 signal is selected
The IHG signal is selected
ISGENE
0
1
The IVI signal (without fall modification
or IHI synchronization) is selected
The IVI signal (without fall modification,
with IHI synchronization) is selected
The IVI signal (with fall modification,
without IHI synchronization) is selected
The IVI signal (with fall modification and
IHI synchronization) is selected
The IVG signal is selected
Internal synchronization signal select
TMRX/TMRY access select
0The TMRX registers are accessed at addresses H'FFF0 to H'FFF5
1 The TMRY registers are accessed at addresses H'FFF0 to H'FFF5
Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1085 of 1130
REJ09B0327-0400
SEDGR—Edge Sense Register H'FFFF Timer Connection
Bit
Initial value
Read/Write
7
VEDG
0
R/(W)
6
HEDG
0
R/(W)
5
CEDG
0
R/(W)
4
HFEDG
0
R/(W)
3
VFEDG
0
R/(W)
0
IVI
—
*2
R
2
PREQF
0
R/(W)
1
IHI
—*
2
R
*
1
*
1
*
1
*
1
*
1
*
1
IVI signal level
0The IVI signal is low
1 The IVI signal is high
Notes: 1.
2.
IHI signal level
0The IHI signal is low
1 The IHI signal is high
Pre-equalization flag
0[Clearing condition]
When 0 is written in PREQF after
reading PREQF = 1
1 [Setting condition]
When an IHI signal 2fH modification
condition is detected
VFBACKI edge
0[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
1 [Setting condition]
When a rising edge is detected on the VFBACKI pin
HFBACKI edge
0[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
1 [Setting condition]
When a rising edge is detected on the HFBACKI pin
CSYNCI edge
0[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
1 [Setting condition]
When a rising edge is detected on the CSYNCI pin
HSYNCI edge
0[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
1 [Setting condition]
When a rising edge is detected on the HSYNCI pin
VSYNCI edge
0[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
1 [Setting condition]
When a rising edge is detected on the VSYNCI pin
Only 0 can be written, to clear the flags.
The initial value is undefined since it depends on the pin states.
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1086 of 1130
REJ09B0327-0400
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
R
QD
D
P1nPCR
C
Reset
R
QD
P1nDR
C
Reset
WP1P
R
Q
P1nDDR
C
Reset
WP1D
WP1
Internal data bus
Internal address bus
8-bit PWM
PWM output enable
PWM output
P1n
*
RP1P
RP1
Mode 2, 3
Mode 1
Hardware
standby Mode 1
EXPE
WP1P: Write to P1PCR
WP1D: Write to P1DDR
WP1: Write to port 1
RP1P: Read P1PCR
RP1: Read port 1
Notes: n = 0 to 7
* Set priority
Legend:
Figure C.1 Port 1 Block Diagram
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1087 of 1130
REJ09B0327-0400
C.2 Port 2 Block Diagrams
R
QD
D
P2nPCR
C
Reset
R
QD
P2nDR
C
Reset
WP2P
R
Q
P2nDDR
C
Reset
WP2D
WP2
8-bit PWM
PWM output enable
PWM output
P2n
*
RP2P
RP2
Mode 2, 3
EXPE
WP2P: Write to P2PCR
WP2D: Write to P2DDR
WP2: Write to port 2
RP2P: Read P2PCR
RP2: Read port 2
Notes: n = 0 to 3
* Set priority
Internal data bus
Internal address bus
Hardware
standby Mode 1
Mode 1
Legend:
Figure C.2 Port 2 Block Diagram (Pins P20 to P23)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1088 of 1130
REJ09B0327-0400
R
QD
D
P2nPCR
C
Reset
R
QD
P2nDR
C
Reset
WP2P
R
Q
P2nDDR
C
Reset
WP2D
WP2
8-bit PWM
PWM output enable
PWM output
P2n
*
RP2P
RP2
Mode 2, 3
EXPE
IOSE
WP2P: Write to P2PCR
WP2D: Write to P2DDR
WP2: Write to port 2
RP2P: Read P2PCR
RP2: Read port 2
Notes: n = 4 to 6
* Set priority
Internal data bus
Internal address bus
Hardware
standby Mode 1
Mode 1
Legend:
Figure C.3 Port 2 Block Diagram (Pins P24 to P26)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1089 of 1130
REJ09B0327-0400
R
QD
D
P27PCR
C
Reset
R
QD
P27DR
C
Reset
WP2P
R
Q
P27DDR
C
Reset
WP2D
Mode 2, 3 WP2
8-bit PWM
PWM output enable
PWM output
Timer connection
CBLANK
CBLANK output
enable
P27
*
RP2P
RP2
Mode 2, 3
EXPE
IOSE
Mode 1
WP2P: Write to P2PCR
WP2D: Write to P2DDR
WP2: Write to port 2
RP2P: Read P2PCR
RP2: Read port 2
Note: * Set priority
Legend:
Internal data bus
Internal address bus
Hardware
standby Mode 1
Figure C.4 Port 2 Block Diagram (Pin P27)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1090 of 1130
REJ09B0327-0400
C.3 Port 3 Block Diagram
R
QD
D
P3nPCR
C
Reset
R
QD
P3nDR
C
Reset
WP3P
R
Q
P3nDDR
C
Reset
WP3D
WP3
CS
IOW
P3n
RP3P
RP3
Mode 2, 3
Mode 1
Hardware
standby
External
address write
EXPE
HI12E
WP3P: Write to P3PCR
WP3D: Write to P3DDR
WP3: Write to port 3
RP3P: Read P3PCR
RP3: Read port 3
Note: n = 0 to 7
Legend:
External address read
Internal data bus
Host interface data bus
CS
IOR
Figure C.5 Port 3 Block Diagram
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1091 of 1130
REJ09B0327-0400
C.4 Port 4 Block Diagrams
D
R
QD
P40DR
C
Reset
R
Q
P40DDR
C
Reset
Hardware standby
WP4D
WP4
SCI2
TxD2/IrTxD
Transmit enable
8-bit timer 0
Counter clock input
P40
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Internal data bus
Legend:
Figure C.6 Port 4 Block Diagram (Pin P40)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1092 of 1130
REJ09B0327-0400
D
R
QD
P41DR
C
Reset
R
Q
P41DDR
C
Reset
WP4D
WP4
8-bit timer 0
8-bit timer output
Output enable
SCI2
Receive enable
RxD2/IrRxD
P41
Hardware standby
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Internal data bus
Legend:
Figure C.7 Port 4 Block Diagram (Pin P41)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1093 of 1130
REJ09B0327-0400
D
R
QD
P42DR
C
Reset
R
Q
P42DDR
C
Reset
WP4D
*
1
*
2
WP4
SCI2
Input enable
Clock output
SDA1 output
SDA1 input
Transmit enable
Output enable
Clock output
IIC1
8-bit timer 0
Reset input
P42
Hardware standby
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Notes: 1. Output enable signal
2. Open drain control signal
Internal data bus
Legend:
Figure C.8 Port 4 Block Diagram (Pin P42)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1094 of 1130
REJ09B0327-0400
D
R
QD
P43DR
C
Reset
R
Q
P43DDR
C
Reset
Hardware standby
WP4D
WP4
Host interface
RESOBF2
(resets HIRQ11)
Timer connection
HSYNCI input
8-bit timer 1
Counter clock input
P43
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Internal data bus
Legend:
Figure C.9 Port 4 Block Diagram (Pin P43)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1095 of 1130
REJ09B0327-0400
D
R
QD
P44DR
C
R
Q
P44DR
C
Reset
WP4D
WP4 TMO1 output
Output enable
8-bit timer 1
P44
Hardware standby
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Reset Host interface
RESOBF1
(resets HIRQ1)
Timer connection
HSYNCO output
Output enable
Internal data bus
Legend:
Figure C.10 Port 4 Block Diagram (Pin P44)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1096 of 1130
REJ09B0327-0400
D
R
QD
P45DR
C
Reset
R
Q
P45DDR
C
Reset
WP4D
WP4
Host interface
RESOBF1
(resets HIRQ12)
Timer connection
CSYNCI input
8-bit timer 1
Timer reset input
P45
Hardware standby
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Internal data bus
Legend:
Figure C.11 Port 4 Block Diagram (Pin P45)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1097 of 1130
REJ09B0327-0400
D
R
QD
P4nDR
C
Reset
R
Q
P4nDDR
C
Reset
WP4D
WP4
14-bit PWM
PWX0, PWX1 output
Output enable
P4n
Hardware standby
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Note: n = 6 or 7
Internal data bus
Legend:
Figure C.12 Port 4 Block Diagram (Pins P46, P47)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1098 of 1130
REJ09B0327-0400
C.5 Port 5 Block Diagrams
D
R
QD
P50DR
C
Reset
R
Q
P50DDR
C
Reset
WP5D
WP5
SCI0
Serial transmit data
Output enable
P50
RP5
WP5D: Write to P5DDR
WP5: Write to port 5
RP5: Read port 5
Internal data bus
Hardware standby
Legend:
Figure C.13 Port 5 Block Diagram (Pin P50)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1099 of 1130
REJ09B0327-0400
D
R
QD
P51DR
C
Reset
R
Q
P51DDR
C
Reset
Hardware standby
WP5D
WP5
SCI0
Input enable
Serial receive
data
P51
RP5
WP5D: Write to P5DDR
WP5: Write to port 5
RP5: Read port 5
Internal data bus
Legend:
Figure C.14 Port 5 Block Diagram (Pin P51)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1100 of 1130
REJ09B0327-0400
D
R
QD
P52DR
C
Reset
R
Q
P52DDR
C
Reset
WP5D
*
1
*
2
WP5
SCI0
Input enable
Clock output
SCL0 output
SCL0 input
Transmit enable
Output enable
Clock input
IIC0
P52
Hardware standby
RP5
WP5D: Write to P5DDR
WP5: Write to port 5
RP5: Read port 5
Notes: 1. Output enable signal
2. Open drain control signal
Legend:
Internal data bus
Figure C.15 Port 5 Block Diagram (Pin P52)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1101 of 1130
REJ09B0327-0400
C.6 Port 6 Block Diagrams
R
QD
D
KMPCR
C
Reset
R
QD
P6nDR
C
Reset
WP6P
R
Q
P6nDDR
C
Reset
WP6D
WP6 16-bit FRT
FTCI input
FTIA input
FTIB input
FTID input
A/D converter
Analog input
Timer connection
8-bit timers Y, X
Key-sense interrupt input
KMIMR0, 2, 3, 5
HFBACKI input, TMIX input,
VSYNCI input, TMIY input,
VFBACKI input
P6n
RP6P
RP6
WP6P: Write to P6PCR
WP6D: Write to P6DDR
WP6: Write to port 6
RP6P: Read P6PCR
RP6: Read port 6
Note: n = 0, 2, 3, 5
Legend:
Hardware
standby
Internal data bus
Figure C.16 Port 6 Block Diagram (Pins P60, P62, P63, P65)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1102 of 1130
REJ09B0327-0400
R
QD
D
KMPCR
C
Reset
R
QD
P61DR
C
Reset
WP6P
R
Q
P61DDR
C
Reset
WP6D
WP6
16-bit FRT
FTOA output
Output enable
Timer connection
VSYNCO output
Output enable
A/D converter
Analog input
Key-sense interrupt input
KMIMR1
P61
RP6P
RP6
WP6P: Write to P6PCR
WP6D: Write to P6DDR
WP6: Write to port 6
RP6P: Read P6PCR
RP6: Read port 6
Hardware
standby
Internal data bus
Legend:
Figure C.17 Port 6 Block Diagram (Pin P61)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1103 of 1130
REJ09B0327-0400
R
QD
D
KMPCR
C
Reset
R
QD
P64DR
C
Reset
WP6P
R
Q
P64DDR
C
Reset
WP6D
WP6
Timer connection
CLAMPO output
Output enable
A/D converter
Analog input
16-bit FRT
FTIC input
Key-sense interrupt input
KMIMR4
P64
RP6P
RP6
WP6P: Write to P6PCR
WP6D: Write to P6DDR
WP6: Write to port 6
RP6P: Read P6PCR
RP6: Read port 6
Hardware
standby
Internal data bus
Legend:
Figure C.18 Port 6 Block Diagram (Pin P64)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1104 of 1130
REJ09B0327-0400
R
QD
D
KMPCR
C
Reset
R
QD
P66DR
C
Reset
WP6P
R
Q
P66DDR
C
Reset
WP6D
WP6
16-bit FRT
FTOB output
Output enable
A/D converter
Analog input
IRQ6 input
KMIMR6
Other
key-sense interrupt inputs IRQ6 enable
P66
RP6P
RP6
WP6P: Write to P6PCR
WP6D: Write to P6DDR
WP6: Write to port 6
RP6P: Read P6PCR
RP6: Read port 6
Hardware
standby
Internal data bus
Legend:
Figure C.19 Port 6 Block Diagram (Pin P66)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1105 of 1130
REJ09B0327-0400
R
QD
D
KMPCR
C
Reset
R
QD
P67DR
C
Reset
WP6P
R
Q
P67DDR
C
Reset
WP6D
WP6
8-bit timer X
TMOX output
Output enable
A/D converter
Analog input
IRQ7 input
KMIMR7
Other
key-sense interrupt inputs IRQ7 enable
P67
RP6P
RP6
WP6P: Write to P6PCR
WP6D: Write to P6DDR
WP6: Write to port 6
RP6P: Read P6PCR
RP6: Read port 6
Hardware
standby
Internal data bus
Legend:
Figure C.20 Port 6 Block Diagram (Pin P67)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1106 of 1130
REJ09B0327-0400
C.7 Port 7 Block Diagrams
A/D converter
Analog input
P7n
RP7: Read port 7
Note: n = 0 to 5
RP7
Internal data bus
Legend:
Figure C.21 Port 7 Block Diagram (Pins P70 to P75)
A/D converter
Analog input
D/A converter
Output enable
Analog output
P7n
RP7: Read port 7
Note: n = 6 or 7
RP7
Internal data bus
Legend:
Figure C.22 Port 7 Block Diagram (Pins P76, P77)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1107 of 1130
REJ09B0327-0400
C.8 Port 8 Block Diagrams
D
R
QD
P80DR
C
Reset
R
Q
P80DDR
C
Reset
HI12E
Hardware standby
EXPE
Mode 2, 3
WP8D
WP8
HIF
HA0 input
P80
RP8
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Internal data bus
Legend:
Figure C.23 Port 8 Block Diagram (Pin P80)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1108 of 1130
REJ09B0327-0400
D
R
QD
P81DR
C
Reset
R
Q
P81DDR
C
Reset
WP8D
Mode 2, 3
Hardware standby
EXPE
CS2E
HI12E
WP8
HIF
CS2 input
HIF
GA20 output
Output enable
P81
RP8
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Internal data bus
Legend:
Figure C.24 Port 8 Block Diagram (Pin P81)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1109 of 1130
REJ09B0327-0400
D
R
QD
P8nDR
C
Reset
R
Q
P8nDDR
C
Reset
WP8D
WP8
Mode 2, 3
EXPE
HI12E
P8n
Hardware standby
RP8
HIF
HIFSD input
(P82 only)
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Note: n = 2, 3
Internal data bus
Legend:
Figure C.25 Port 8 Block Diagram (Pins P82, P83)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1110 of 1130
REJ09B0327-0400
D
R
QD
P84DR
C
Reset
R
Q
P84DDR
C
Reset
WP8D
WP8
SCI1
TxD1
Transmit enable
IRQ3 input
IRQ3 enable
P84
RP8
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Internal data bus
Hardware standby
Legend:
Figure C.26 Port 8 Block Diagram (Pin P84)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1111 of 1130
REJ09B0327-0400
D
R
QD
P85DR
C
Reset
R
Q
P85DDR
C
Reset
Hardware standby
WP8D
WP8
SCI1
Input enable
Serial receive data
IRQ4 input
IRQ4 enable
P85
RP8
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Internal data bus
Legend:
Figure C.27 Port 8 Block Diagram (Pin P85)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1112 of 1130
REJ09B0327-0400
D
R
QD
P86DR
C
Reset
R
Q
P86DDR
C
Reset
WP8D
*
1
Hardware standby
*
2WP8
SCI1
Input enable
Clock output
SCL1 output
SCL1 input
IRQ5 input
IRQ5 enable
Transmit enable
Output enable
Clock input
IIC1
P86
RP8
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Notes: 1. Output enable signal
2. Open drain control signal
Internal data bus
Legend:
Figure C.28 Port 8 Block Diagram (Pin P86)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1113 of 1130
REJ09B0327-0400
C.9 Port 9 Block Diagrams
D
R
QD
P90DR
C
Reset
R
Q
P90DDR
C
Reset
WP9D
Mode 2, 3
EXPE
EXPE
ABW
GA20
HI12E
CS2E
WP9
HIF
ECS2 input
A/D converter
External trigger
input
Bus controller
LWR output
P90
RP9
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
IRQ2 input
IRQ2 enable
Internal data bus
Hardware standby
Legend:
Figure C.29 Port 9 Block Diagram (Pin P90)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1114 of 1130
REJ09B0327-0400
D
R
QD
P9nDR
C
Reset
R
Q
P9nDDR
C
Reset
WP9D
WP9
IRQ1 input
IRQ0 input
IRQ1 enable
IRQ0 enable
P9n
RP9
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Note: n = 1 or 2
Internal data bus
Hardware standby
Legend:
Figure C.30 Port 9 Block Diagram (Pins P91, P92)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1115 of 1130
REJ09B0327-0400
D
R
QD
P9nDR
C
Reset
R
Q
P9nDDR
C
Reset
WP9D
Mode 2, 3
EXPE
EXPE
HI12E
WP9
Mode 2, 3
EXPE
HI12E
Bus controller
RD output
HWR output
AS/IOS output
HIF
IOR input
IOW input
CS1 input
P9n
RP9
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Note: n = 3 to 5
Internal data bus
Hardware standby
Legend:
Figure C.31 Port 9 Block Diagram (Pins P93 to P95)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1116 of 1130
REJ09B0327-0400
D
RS
Q
P96DDR
C
Reset
Mode 1
WP9D
Subclock input
ø output
Subclock input
enable
P96
WP9D: Write to P9DDR
RP9: Read port 9
RP9
Internal data bus
Hardware
standby
Legend:
Figure C.32 Port 9 Block Diagram (Pin P96)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1117 of 1130
REJ09B0327-0400
D
R
QD
P97DR
C
Reset
R
Q
P97DDR
C
Reset
WP9D
EXPE
WP9
IIC0
SDA0 input
SDA0 output
Transmit enable
Bus controller
Input enable
WAIT input
P97
Hardware standby
RP9
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Notes: 1. Output enable signal
2. Open drain control signal
*
1
*
2
Internal data bus
Legend:
Figure C.33 Port 9 Block Diagram (Pin P97)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1118 of 1130
REJ09B0327-0400
C.10 Port A Block Diagrams
D
R
QD
PAnODR
C
Reset
R
Q
PAnDDR
C
Reset
Mode 2
EXPE
IOSE WPAD
WPA
RPAO
RPA
A/D converter
Analog input
Key-sense
interrupt input
KMIMR n+8
PAn
WPAD: Write to PADDR
WPA: Write to PAODR
RPAO: Read PAODR
RPA: Read port A
Note: n = 0 or 1
Hardware
standby
Internal data bus
Internal address bus
Legend:
Figure C.34 Port A Block Diagram (Pins PA0, PA1)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1119 of 1130
REJ09B0327-0400
D
R
QD
PAnODR
C
Reset
R
Q
PAnDDR
C
Reset
WPAD
WPA
RPAO
RPA
A/D converter
Analog input
Key-sense
interrupt input
KMIMR n+8
PAn
WPAD: Write to PADDR
WPA: Write to PAODR
RPAO: Read PAODR
RPA: Read port A
Notes: n = 2 or 3
1. Output enable signal
2. Open-drain control signal
*1
*2
Keyboard buffer
controller
Output enable
Output
Input
Hardware
standby
Internal data bus
Internal address bus
Mode 2
EXPE
IOSE
Legend:
Figure C.35 Port A Block Diagram (Pins PA2, PA3)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1120 of 1130
REJ09B0327-0400
D
R
QD
PAnODR
C
Reset
R
Q
PAnDDR
C
Reset
IICS
WPAD
WPA
RPAO
RPA
A/D converter
Input
Analog input
Key-sense
interrupt input
KMIMR n+8
PAn
WPAD: Write to PADDR
WPA: Write to PAODR
RPAO: Read PAODR
RPA: Read port A
Notes: n = 4 to 7
1. Output enable signal
2. Open-drain control signal
*
1
*
2
Keyboard buffer
controller
Output enable
Output
Hardware
standby
Internal data bus
Internal address bus
Mode 2
EXPE
IOSE
Legend:
Figure C.36 Port A Block Diagram (Pins PA4 to PA7)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1121 of 1130
REJ09B0327-0400
C.11 Port B Block Diagram
D
R
QD
PBnODR
C
Reset
(D0, D1)
(D0, D1)
R
Q
PBnDDR
C
Reset
EXPE
External
address write
ABW
WPBD
WPB
External address
read
RPBO
RPB
PBn
WPBD: Write to PBDDR
WPB: Write to PBODR
RPBO: Read PBODR
RPB: Read port B
Note: n = 0, 1
Internal data bus
Host interface
RESOBF3, 4
(Reset HIRQ3,
HIRQ4)
Hardware standby
Legend:
Figure C.37 Port B Block Diagram (Pins PB0 and PB1)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1122 of 1130
REJ09B0327-0400
D
R
QD
PBnODR
C
Reset
(D2, D3)
(D2, D3)
R
Q
PBnDDR
C
Reset
EXPE
External
address write
ABW
WPBD
WPB
HIF
CS3 input
CS4 input
External address
read
RPBO
RPB
PBn
Mode 2, 3
EXPE
CS input enable
HI12E
WPBD:
WPB:
RPBO:
RPB:
Note: n = 2, 3
Legend: Write to PBDDR
Write to PBODR
Read PBODR
Read port B
Internal data bus
Hardware
standby
Figure C.38 Port B Block Diagram (Pins PB2 and PB3)
Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1123 of 1130
REJ09B0327-0400
D
R
QD
PBnODR
C
Reset
(D7 to D4)
(D7 to D4)
R
Q
PBnDDR
C
Reset
EXPE
External
address write
Hardware
standby
ABW
WPBD
WPB
External address
read
RPBO
RPB
PBn
Internal data bus
WPBD:
WPB:
RPBO:
RPB:
Note: n = 4 to 7
Write to PBDDR
Write to PBODR
Read PBODR
Read port B
Legend:
Figure C.39 Port B Block Diagram (Pins PB4 to PB7)
Appendix D Pin States
Rev. 4.00 Sep 27, 2006 page 1124 of 1130
REJ09B0327-0400
Appendix D Pin States
D.1 Port States in Each Processing State
Table D.1 I/O Port States in Each Processing State
Port Name
Pin Name MCU Operating
Mode Reset
Hardware
Standby
Mode
Software
Standby
Mode Watch
Mode Sleep
Mode
Sub-
sleep
Mode Subactive
Mode
Program
Execution
State
1LT
keep*keep*keep*keep*A7 to A0 A7 to A0Port 1
A7 to A0 2, 3 (EXPE = 1) T Address
output/
input port
Address
output/
input port
2, 3 (EXPE = 0) I/O port I/O port
1LTkeep*keep*keep*keep*A15 to A8 A15 to A8Port 2
A15 to A8 2, 3 (EXPE = 1) T Address
output/
input port
Address
output/
input port
2, 3 (EXPE = 0) I/O port I/O port
1 T T T T T T D15 to D8 D15 to D8
2, 3 (EXPE = 1)
Port 3
D15 to D8
2, 3 (EXPE = 0) keep keep keep keep I/O port I/O port
Port 4 1 T T keep keep keep keep I/O port I/O port
2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
Port 5 1 T T keep keep keep keep I/O port I/O port
2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
Port 6 1 T T keep keep keep keep I/O port I/O port
2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
Port 7 1 T T T T T T Input port Input port
2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
Port 8 1 T T keep keep keep keep I/O port I/O port
2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
1 T T T/keep T/keep T/keep T/keepPort 97
WAIT 2, 3 (EXPE = 1)
WAIT/
I/O port
WAIT/
I/O port
2, 3 (EXPE = 0) keep keep keep keep I/O port I/O port
Appendix D Pin States
Rev. 4.00 Sep 27, 2006 page 1125 of 1130
REJ09B0327-0400
Port Name
Pin Name MCU Operating
Mode Reset
Hardware
Standby
Mode
Software
Standby
Mode Watch
Mode Sleep
Mode
Sub-
sleep
Mode Subactive
Mode
Program
Execution
State
1 Clock
output T EXCL
input EXCL
input EXCL input
2, 3 (EXPE = 1) T
Port 96
φ
EXCL
2, 3 (EXPE = 0)
[DDR = 1]
H
[DDR = 0]
T
[DDR = 1]
clock
output
[DDR = 0]
T
Clock output/
EXCL input/
input port
1HTHHHH
2, 3 (EXPE = 1) T
AS, HWR,
RD
AS, HWR,
RD
Port 95 to 93
AS, HWR,
RD 2, 3 (EXPE = 0) keep keep keep keep I/O port I/O port
Port 92 to 91 1 T T keep keep keep keep I/O por t I/O por t
2, 3 (EXPE = 1)
2, 3 (EXPE = 0)
1 T T H/keep H/keep H/keep H/keep
2, 3 (EXPE = 1)
LWR/
I/O port
LWR/
I/O port
Port 90
LWR
2, 3 (EXPE = 0) keep keep keep keep I/O port I/O port
1TTkeep*keep*keep*keep*I/O port I/O port
2, 3 (EXPE = 1) A23 to A16/
I/O port A23 to A16/
I/O port
Port A
A23 to A16
2, 3 (EXPE = 0) I/O port I/O port
1 T T T/keep T/keep T/keep T/keepPort B
D7 to D0 2, 3 (EXPE = 1)
D7 to D0/
I/O port D7 to D0/
I/O port
2, 3 (EXPE = 0) keep keep keep keep I/O port I/O port
Legend:
H: High
L: Low
T: High-impedance state
keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, MOS input pull-
ups remain on ).
Output ports maintain their previous state.
Depending on the pins, the on-chip supporting modules may be initialized and the I/O port
function determined by DDR and DR used.
DDR: Data direction register
Note: *In the case of address output, the last address accessed is retained.
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Rev. 4.00 Sep 27, 2006 page 1126 of 1130
REJ09B0327-0400
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
E.1 Timing of Transition to Hardware Standby Mode
(1) To retain RAM co ntents with the RAME bit set to 1 in SYSCR, driv e the RES signal low 10
system clock cycles before the STBY signal goes low, as shown in figure E.1. RES must
remain lo w until STBY signal goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
RES
t
2
≥ 0 nst
1
≥ 10 t
cyc
Figure E.1 Timing o f Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained, RES does not have to be driven low as in (1).
E.2 Timing of Recovery from Hardware Standby Mode
Drive the RES signal low at least 100 ns before STBY goes high to execute a reset.
STBY
RES
t
OSC1
t ≥ 100 ns
Figure E.2 Timing of Recovery from Hardwa re St andby Mode
Appendix F Product Code Lineup
Rev. 4.00 Sep 27, 2006 page 1127 of 1130
REJ09B0327-0400
Appendix F Product Code Lineup
Table F.1 H8S/2148 Group and H8S/2144 Group Product Code Lineup
Product Type Product Code Mark Code
Package
(Package
Code) Notes
H8S/2148
Group H8S/2148 Mask-ROM
version HD6432148S HD6432148S(V)(***)FA 100-pin QFP
(FP-100B)
Standard product
(5-V version, 4-V version,
3-V version) HD6432148S(V)(***)TE 100-pin TQFP
(TFP-100B)
HD6432148SW HD6432148S(V)W(***)FA 100-pin QFP
(FP-100B)
Version with on-chip
I2C bus interface
(5-V version, 4-V version,
3-V version) HD6432148S(V)W(***)TE 100-pin TQFP
(TFP-100B)
F-ZTAT
version Standard product
(5-V version/4-V version) HD64F2148 HD64F2148FA20 100-pin QFP
(FP-100B)
HD64F2148TE 20 100-pin TQFP
(TFP-100B)
Low-voltage version
(3-V version) HD64F2148V HD64F2148VFA10 100-pin QFP
(FP-100B)
HD64F2148V TE10 100-pin TQFP
(TFP-100B)
H8S/2147 Mask-ROM
version HD6432147S HD6432147S(V)(***)FA 100-pin QFP
(FP-100B)
Standard product
(5-V version, 4-V version,
3-V version) HD6432147S(V)(***)TE 100-pin TQFP
(TFP-100B)
HD6432147SW HD6432147S(V)W(***)FA 100-pin QFP
(FP-100B)
Version with on-chip
I2C bus interface
(5-V version, 4-V version,
3-V version) HD6432147S(V)W(***)TE 100-pin TQFP
(TFP-100B)
H8S/2148A Standard product
(5-V version/4-V version) HD64F2148A HD64F2148AFA20 100-pin QFP
(FP-100B)
H8S/2148
Group
A-mask
version
F-ZTAT
version
A-mask
version HD64F2148ATE20 100-pin TQFP
(TFP-100B)
Low-voltage version
(3-V version) HD64F2148AV HD64F2148AVFA10 100-pin QFP
(FP-100B)
HD64F2148AVTE 10 100-pin TQFP
(TFP-100B)
H8S/2147A Standard product
(5-V version/4-V version) HD64F2147A HD64F2147AFA20 100-pin QFP
(FP-100B)
F-ZTAT
version
A-mask
version HD64F2147A TE20 100-pin TQFP
(TFP-100B)
Low-voltage version
(3-V version) HD64F2147AV HD64F2147AVFA10 100-pin QFP
(FP-100B)
HD64F2147AVTE 10 100-pin TQFP
(TFP-100B)
Appendix F Product Code Lineup
Rev. 4.00 Sep 27, 2006 page 1128 of 1130
REJ09B0327-0400
Product Type Product Code Mark Code
Package
(Package
Code) Notes
H8S/2147N H8S/2147N F-ZTAT
version Standard product
(5-V version) HD64F2147N HD64F2147NFA20 100-pin QFP
(FP-100B)
HD64F2147N TE20 100-pin TQFP
(TFP-100B)
Low-voltage version
(3-V version) HD64F2147NV HD64F2147NVFA10 100-pin QFP
(FP-100B)
HD64F2147NVTE1 0 100-pin TQFP
(TFP-100B)
H8S/2144
Group H8S/2144 Mask-ROM
version HD6432144S HD6432144S(V)(***)FA 100-pin QFP
(FP-100B)
Standard product
(5-V version, 4-V version,
3-V version) HD6432144S(V)(***)TE 100-pin TQFP
(TFP-100B)
F-ZTAT
version Standard product
(5-V version/4-V version) HD64F2144 HD64F2144FA20 100-pin QFP
(FP-100B)
HD64F2144TE20 100-pin TQFP
(TFP-100B)
Low-voltage version
(3-V version) HD64F2144V HD64F2144VFA10 100-pin QFP
(FP-100B)
HD64F2144VTE10 100-pin TQFP
(TFP-100B)
H8S/2143 Mask-ROM
version HD6432143S HD6432143S(V)(***)FA 100-pin QFP
(FP-100B)
Standard product
(5-V version, 4-V version,
3-V version) HD6432143S(V)(***)TE 100-pin TQFP
(TFP-100B)
H8S/2142 Mask-ROM
version HD6432142 HD6432142(***)FA 100-pin QFP
(FP-100B)
Standard product
(5-V version, 4-V version,
3-V version) HD6432142(***)TE 100-pin TQFP
(TFP-100B)
F-ZTAT
version Standard product
(5-V version/4-V version) HD64F2142R HD64F2142RFA20 100-pin QFP
(FP-100B)
HD64F2142R TE20 100-pin TQFP
(TFP-100B)
Low-voltage version
(3-V version) HD64F2142RV HD64F2142RVFA10 100-pin QFP
(FP-100B)
HD64F2142RVTE1 0 100-pin TQFP
(TFP-100B)
H8S/2144A Standard product
(5-V version/4-V version) HD64F2144A HD64F2144AFA20 100-pin QFP
(FP-100B)
F-ZTAT
version
A-mask
version HD64F2144ATE20 100-pin TQFP
(TFP-100B)
H8S/2144
Group
A-mask
version
Low-voltage version
(3-V version) HD64F2144AV HD64F2144AVFA10 100-pin QFP
(FP-100B)
HD64F2144AVTE10 100-pin TQFP
(TFP-100B)
Note: (***) is the ROM code.
The F-ZTAT version of the H8S/2148 has an on-chip I2C bus interface as standard.
The F-ZTAT 5 V/4 V version supports the operating ranges of the 5 V version and the 4 V version.
The operating range of the F-ZTAT low-voltage version will be dec ided later.
The above table includes products under developm ent. Info rm ation on the status of indivi dual products
can be obtained from Renesas sales offices.
Appendix G Package Dimensions
Rev. 4.00 Sep 27, 2006 page 1129 of 1130
REJ09B0327-0400
Appendix G Package Dimensions
The package dimension that is shown in the Renesas Semiconductor Package Data Book has
priority.
NOTE
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
*2
*3p
E
D
E
D
F
100
125
26
76
75 51
50
xMy
Z
Z
D
H
E
H
b
Terminal cross section
p
1
1
c
b
c
b
2
1
1
Detail F
c
AA
L
L
A
1.0
1.0
0.08
0.10
0.5
8°0°
0.250.12
0.15
0.20
0.00
0.270.220.17
0.220.170.12
3.05
16.316.015.7
L
1
Z
E
Z
D
y
x
c
b
1
b
p
A
H
D
A
2
E
D
A
1
c
1
e
e
L
H
E
0.70.50.3
MaxNomMin
Dimension in Millimeters
Symbol
Reference
14
2.70
16.316.015.7
1.0
14
θ
θ
P-QFP100-14x14-0.50 1.2g
MASS[Typ.]
FP-100B/FP-100BVPRQP0100KA-A
RENESAS CodeJEITA Package Code Previous Code
Figure G.1 Package Dimensions (FP-100B)
Appendix G Package Dimensions
Rev. 4.00 Sep 27, 2006 page 1130 of 1130
REJ09B0327-0400
NOTE
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
1.00
1.00
0.08
0.10
0.5
8°0°
15.8 16.0 16.2
0.15
0.20
1.20
0.200.100.00
0.270.220.17
0.220.170.12
L
1
Z
E
Z
D
y
x
c
b
1
b
p
A
H
D
A
2
E
D
A
1
c
1
e
e
L
H
E
0.60.50.4
MaxNomMin
Dimension in Millimeters
Symbol
Reference
14
1.00
16.216.015.8
1.0
14
Index mark
*1
*2
*3p
E
D
E
D
100
1
F
xMy
26
25
76
75
50
51
Z
Z
H
E
H
D
b
2
1
1
Detail F
c
L
AA
A
L
Terminal cross section
p
1
1
b
c
b
c
θ
θ
P-TQFP100-14x14-0.50 0.5g
MASS[Typ.]
TFP-100B/TFP-100BVPTQP0100KA-A
RENESAS CodeJEITA Package Code Previous Code
Figure G.2 Package Dimensions (TFP-100B)
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8S/2148 Group, H8S/2144 Group,
H8S/2148FZTAT™, H8S/2147N F-ZTAT™,
H8S/2144F-ZTAT™, H8S/2142F-ZTAT™
Publication Date: 1st Edition, November 1999
Rev.4.00, September 27, 2006
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Dep artme nt
Global Strategic Communication Div.
Renesas Soluti ons Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
Colophon 6.0
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
H8S/2148 Group, H8S/2144 Group,
H8S/2148F-ZTAT™, H8S/2147N F-ZTAT™,
H8S/2144F-ZTAT™, H8S/2142F-ZTAT™
REJ09B0327-0400
Hardware Manual
