MB85RS1MTPNF-G-JNE1 - FUJITSU

FUJITSU SEMICONDUCTOR

DATA SHEET

2016.10

Memory FRAM

1M (128 K × 8) Bit SPI

MB85RS1MT

■DESCRIPTION

MB85RS1MT is a FRAM (Ferroelect ric Random Access Memory) chip in a configuration of 131,072

words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the

nonvolatile memory cells.

MB85RS1MT adopts the Serial Peripheral Interface (SPI).

The MB85RS1MT is able to retain data without using a back-up battery, as is needed for SRAM.

The memory cells used in the MB85RS1MT can be used for 1013 read/write operations, which is a significant

improvement ove r the number of read and write operations supported by Flash memory and E2PROM.

MB85RS1MT does not take long time to write data like Flash memories or E2PROM, and MB85RS1MT takes

no wait time.

■FEATURES

• Bit configuration : 131,072 words × 8 bit s

• Serial Peripheral Interface : SPI (Serial Peripheral Interface)

Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)

• Operating frequency : 1.8 V to 2.7 V, 25 MHz (Max)

2.7 V to 3.6 V, 30 MHz (Max)

For FSTRD command 2.7 V to 3.6 V, 40 MHz (Ma x)

• High endurance : 1013 times / byte

• Data retention : 10 years (+85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C)

• Operating power supply voltage : 1.8 V to 3.6 V

• Low power consumption : Operating power supply current 9.5 mA (M ax@30 MHz)

Standby current 120 μA (Max)

Sleep current 10 μA (Max)

• Operation ambient temperature range : -40 °C to +85 °C

• Package : 8-pin plastic SOP (FPT-8P-M02)

8-pin plastic WLP (WLP-8P-M01)

8-pin plastic DIP (DIP -8P-M03)

RoHS compliant

DS501-00022-6v0-E

MB85RS1MT

2DS501-00022-6v0-E

■PIN ASSIGNMENT

VSS SI

VDD

SCK

HOLD

VDD

SCK

HOLD

ࠉࠉ

,1'(;

(

VSS SI

(TOP VIEW)

(FPT-8P-M02)

(BOTTOM VIEW)

(WLP-8P-M01)

(TOP VIEW)

(DIP-8P-M03)

VSS

VDD

SCK

HOLD

MB85RS1MT

DS501-00022-6v0-E 3

■PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name Functional description

1E CS

Chip Select pin

This is an input pin to make chips select. When CS is “H” level, device is in deselect

(standby) statu s an d SO be co m es High- Z . Inp ut s fro m othe r pin s ar e ign or e d for this

time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before

inputting op-code. The Chip Select pin is pulled up internally to the VDD pin.

2B WP

Write Protect pin

This is a pin to control writing to a st atus register. The writing of status register (see “■

STATUS REGISTER”) is protected in related with WP and WPEN. See “■ WRITING

PROTECT” for detail.

2D HOLD

Hold pin

This pin is used to interrupt serial input/output without making chips deselect. When

HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become

do not care. While the hold operation, CS has to be retained “L” level.

3C SCK Serial Clock pin

This is a clock input pin to input/ou tput serial d ata. SI is loaded synchronously t o a rising

edge, SO is output synchronously to a falling e dge.

3A SI Serial Data Input pin

This is an input pin of serial data. This inputs op-code, address, an d writing data.

1C SO Serial Data Output pin

This is an output pin of seri al data. Reading data of FRAM memory cell array and status

3E VDD Supply Voltage pin

1A VSS Ground pin

MB85RS1MT

4DS501-00022-6v0-E

■BLOCK DIAGRAM

SCK

SI Serial-Parallel Converter

FRAM Cell Array

131,072 ✕ 8

Column Decoder/Sense Amp/

Write Amp

FRAM

Status Register

Data Register

Parallel-Serial Converter

Control Circuit

Address Counter

Row Decoder

HOLD

MB85RS1MT

DS501-00022-6v0-E 5

■SPI MODE

MB85RS1MT corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .

SCK

76543210

MSBLSB

SPI Mode 0

SPI Mode 3

MB85RS1MT

6DS501-00022-6v0-E

■SERIAL PERIPHERAL INTERFACE (S PI)

MB85RS1MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller

equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus

connected to use.

SCK

SS1

HOLD1

MOSI

MISO

SS2

HOLD2

SCK

CS HOLD

SISO SCK

CS HOLD

SISO

MB85RS1MT MB85RS1MT

SCK

CS HOLD

SISO

MB85RS1MT

SPI

Microcontroller

MOSI : Master Out Slave I n

MISO : Master In Slave Out

SS : Slave Select

System Configuration with SPI Port

System Configuration without SPI Port

Microcontroller

MB85RS1MT

DS501-00022-6v0-E 7

■STATUS REGISTER

■OP-CODE

MB85RS1MT accepts 9 kinds of command specified in op-code. Op-code is a code composed of 8 bits

shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting

op-code, the command are not performed.

Bit No. Bit Name Function

7 WPEN

Status Register Write Protect

This is a bit composed of nonvolatile memories (FRAM). WPEN protects

writing to a status register (refer to “■ WRITING PROTECT”) relating with

WP input. Wr iting wit h t he WRSR comman d and read ing wit h the RDSR

command are possible.

6 to 4 ⎯

Not Used Bits

These are bits composed of nonvolatile memories, writing with the WRSR

command is possible. The se bit s ar e no t u sed b ut th ey ar e r ea d with th e

RDSR command.

3 BP1 Block Protect

This is a bit composed of nonvolatile memory. This defines size of write

protect block for the WRITE command (refer to “■ BLOCK PROTECT”).

Writing with th e WRSR comma nd and r ea ding with t he RDSR comman d

are possible.

2 BP0

1WEL

Write Enable Latch

This indicates FRAM Array and status registe r are writable. The WREN

command is for setting, and the WRDI command is for resettin g. With the

RDSR command, reading is possible but writing is not possible with the

WRSR command. WEL is reset after the following operations.

After power ON.

After WRDI command recognition.

The rising edge of CS after WRSR command recognition.

The rising edge of CS after WRITE command recognition.

0 0 This is a bit fixed to “0”.

Name Description Op-code

WREN Set Write Enable Latch 0000 0110B

WRDI Reset Write Enable Latch 0000 0100B

RDSR Read Status Register 0000 0101B

WRSR Write Status Register 0000 0001B

READ Read Memory Code 0000 0011B

WRITE Write Memory Code 0000 0010B

RDID Read Device ID 1001 1111B

FSTRD Fast Read Memory Code 0000 1011B

SLEEP Sleep Mode 1011 1001B

MB85RS1MT

8DS501-00022-6v0-E

■COMMAND

• WREN

The WREN command sets WEL ( Write Enable Latch ) . WEL has to be set with the WREN comma nd before

writing operation (WRSR command and WRITE command) . WREN command is applicable to “Up to

25 MHz (1.8 V to 2.7 V) and 30 MHz (2.7 V to 3.6 V) op eration”.

• WRDI

The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE

command) are not perfor med when WEL is reset. WRDI command is applicable to “Up to 25 MHz (1.8 V to

2.7 V) and 30 MHz (2.7 V to 3.6 V) operation”.

SCK

00000110

High-Z

76543210

InvalidInvalid

SCK

00000100

High-Z

76543210

InvalidInvalid

MB85RS1MT

DS501-00022-6v0-E 9

• RDSR

The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input

to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the

RDSR command, rep eated reading of status register is enabled by sending SCK cont inuously before ri sing

of CS. RDSR command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 30 MHz (2.7 V to 3.6 V) operation”.

• WRSR

The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR

op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR

command. A SI value corresp ondent to bit 1 is ignored. Bi t 0 of t he status registe r is fixed to “0” and ca nnot

be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before perfor ming

WRSR command, and do not change the WP signal level until the end of command sequence. WRSR

command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 30 MHz (2.7 V to 3.6 V) operation”.

SCK

00000101

High-Z

76543210

Invalid

MSB

76543210

Data Out

LSB

Invalid

SCK

00000001

76543210

Data In

MSB

76543210

High-Z LSB

76543210

Instruction

MB85RS1MT

10 DS501-00022-6v0-E

• READ

The READ command read s FRAM memory cell array d ata. Arbitrary 24 b its address and op-code of READ

are input to SI. The 7-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output

synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ

command is completed, but keeps on reading with automatic address increment which is enabled by con-

tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant

address, it rolls over to the starting address, and reading cycle keeps on infinitely. READ command is

applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 30 MHz (2.7 V to 3.6 V) operation”.

• WRITE

The WRITE comma nd writes data to FRAM memor y cell array. WRITE op- code, arbitrary 24 bits of ad dress

and 8 bits of writing data are inpu t to SI. The 7-bit up per addr ess bit is inva lid. When 8 bit s of writ ing data is

input, data is wr itte n to FRAM memory cell array. Risen CS will terminate the WR ITE command, but if you

continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with

automatic address increment. When it reaches the most significant address, it rolls over to the starting

address, and writing cycle can be continued infinitely. WRITE command is applicable to “Up to 25 MHz (1.8

V to 2.7 V) and 30 MHz (2. 7 V to 3.6 V) operation”.

SCK

SI Invalid

MSB LSB MSB Data Out LSB

High-Z

Invalid

450123 26276 7 8 9 10 11 12 13 14 15 38 3928 29 30 31 32 33 34 35 36 37

00000011X 32

XXXXXX16 54

SO 76 3

54 210

24-bit Address

OP-CODE

SCK Data In

MSB

24-bit Address

OP-CODE

LSB MSB LSB

High-Z

10 110123456789 14 15 26 31 3212 13 27 28 29 30 33 34 35 36 37 38 39

0000001 30XXXXX 210

XX16 54 32107654

MB85RS1MT

DS501-00022-6v0-E 11

• FSTRD

The FSTRD command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of FSTRD

are input to SI followed by 8 bits dummy. The 7-bit upper address bit is invalid. Then, 8-cycle clock is input

to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When

CS is risen, th e FSTRD command is completed, but keeps on reading w ith automatic address increment

which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches

the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. FSTRD

command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 40 MHz (2.7 V to 3.6 V) operation”.

• RDID

The RDID command rea ds fi xed De vice ID. Af t er per f orming RDID op-cod e t o SI, 3 2-cycle clock is in put t o

SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output

is in order of Manufacturer ID (8bit)/C ontinuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).

In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen. RDID

command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 30 MHz (2.7 V to 3.6 V) operation”.

SCK

SI Invalid

MSB LSB MSB Data Out LSB

High-Z

Invalid

450123 29306 7 8 9 10 11 12 13 1415 46 4731 32 38 39 40 41 42 43 44 45

00001011X

16 210X XX

SO 7

XXXXXX

0543

24-bit Address 8-bit Dummy

OP-CODE

SCK

MSB

76543210

Data OutData Out

High-Z

LSB

111098333231393837363534

Invalid

30282931

10011111

201364578

bit

76543210Hex

Manufacturer ID 0000010 004

HFujitsu

Continuation code 011111117F

Proprietary use Density Hex

Product ID (1st Byte)0010011127

HDensity: 00111B = 1 Mbit

Proprietary use Hex

Product ID (2nd Byte)0000001103

MB85RS1MT

12 DS501-00022-6v0-E

• SLEEP

The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP

mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when

at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command,

this SLEEP command is canceled.

After the SLEEP mode transition, SCK and SI inputs are ignored and SO changes to a Hi-Z state.

Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 μs) time from the

falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it

is prohibited to bring down CS to L level again during tREC period.

■BLOCK PROTECT

Writing protect bl ock for WRITE comma nd is configured by th e value of BP0 and BP1 in th e status regist er.

BP1 BP0 Protected Blo ck

00None

0 1 18000H to 1FFFFH (upper 1/4)

1 0 10000H to 1FFFFH (upper 1/2)

1 1 00000H to 1FFFFH (all)

Enter Sleep Mode

SCK

SI Invalid Invalid

Hi-Z

Sleep Mode Entry

67012345

11011100

REC

Exit Sleep Mode

Sleep Mode Exit

From this time

Command input enable

MB85RS1MT

DS501-00022-6v0-E 13

■WRITING PROTECT

Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,

WPEN, WP as shown in the table.

■HOLD OPERATION

Hold status is retained with out abort ing a command if HOLD is “L” level while CS is “L” level. The timing for

starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is

transited to th e hold conditio n as shown in the diagram below. In case th e HOLD pin transited to “L” level

when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case

the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”

level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.

And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a

command is aborted. In case the command is aborted before its recognition, WEL holds the value before

transition to hold status.

WEL WPEN WP Protected Blocks Unprotected Blocks Status Register

0 X X Protected Protected Protected

1 0 X Protected Unprotected Unprotected

1 1 0 Protected Unprotected Protected

1 1 1 Protected Unprotected Unprotected

SCK

Hold Condition

HOLD

Hold Condition

MB85RS1MT

14 DS501-00022-6v0-E

■ABSOLUTE MAXIMUM RATINGS

*: These parameters are based on the condition that VSS is 0 V.

WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without

limitation, voltage, current or temperature) in excess of absolute maximum ratings.

Do not exceed any of these ratings.

■RECOMMENDED OPERATING CONDITIONS

*1: These parameters are based on the condition t hat VSS is 0 V.

*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the

package surface temperature.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated under these conditions.

Any use of semiconductor devices will be under their recommended operating condition.

Operation under any conditions other than these conditions may adversely affect reliability of

device and could res ult in de vice failu re.

No warranty is made with respect to any use, operating conditions or combinations not represented

on this data sheet. If you are considering application under any conditions other than listed herein,

please contact sales representatives beforehand.

Parameter Symbol Rating Unit

Min Max

Power supply voltage* VDD − 0.5 + 4.0 V

Input voltage* VIN − 0.5 VDD + 0.5 V

Output voltage* VOUT − 0.5 VDD + 0.5 V

Operation ambient temperature TA − 40 + 85 °C

Storage temperature Tstg − 55 + 125 °C

Parameter Symbol Value Unit

Min Typ Max

Power supply voltage*1 VDD 1.8 3.3 3.6 V

Operation ambient temperature*2 TA − 40 ⎯ + 85 °C

MB85RS1MT

DS501-00022-6v0-E 15

■ELECTRICAL CHARACTERISTICS

1. DC Characteristics (within recomme nd e d operatin g co nd itio ns )

*1 : Applicable pin : CS, WP, HOLD, SCK, SI

*2 : Applicable pin : SO

Parameter Symbol Condition Value Unit

Min Typ Max

Input leakage current*1|ILI|

0 ≤ CS< VDD ⎯⎯200

μA

CS = VDD ⎯⎯ 1

WP, HOLD, SCK

SI = 0 V to VDD ⎯⎯ 1

Output leakage current*2|ILO|SO = 0 V to VDD ⎯⎯ 1μA

Operating power supply current IDD

SCK = 1 MHz ⎯0.77 ⎯mA

SCK = 10 MHz ⎯2.3 ⎯mA

SCK = 25 MHz ⎯4.85 ⎯mA

SCK = 30 MHz ⎯5.7 9.5 mA

Standby current ISB SCK = SI = CS = VDD ⎯25 120 μA

Sleep current IZZ CS = VDD

All inputs VSS or VDD ⎯⎯10 μA

Input high voltage VIH VDD = 1.8 V to 3.6 V VDD × 0.7 ⎯VDD + 0.5 V

Input low voltage VIL VDD = 1.8 V to 3.6 V − 0.5 ⎯VDD × 0.3 V

Output high voltage VOH IOH = − 2 mA VDD − 0.5 ⎯⎯V

Output low voltage VOL IOL = 2 mA ⎯⎯0.4 V

Pull up resistance for CS RP⎯18 33 80 kΩ

MB85RS1MT

16 DS501-00022-6v0-E

2. AC Characteristics

*1 : All commands except FSTRD are applicable to “Up to 25 MHz operation” in VDD = 1.8 V to 2.7 V.

*2 : All commands except FSTRD are applicable to “Up to 30 MHz operation” in VDD = 2.7 V to 3.6 V.

AC Test Condition

Power supply voltage : 1.8 V to 3.6 V

Operation am b i en t tem p er a tur e : − 40 °C to + 85 °C

Input voltage magnit ude : VDD × 0.7 ≤ VIH ≤ VDD

0 ≤ VIL ≤ VDD × 0.3

Input rising time : 5 ns

Input falling time : 5 ns

Input judge level : VDD/2

Output judge level : VDD/2

Parameter Symbol

Value

Unit

Up to 25 MHz operation*1

(VDD = 1.8 V to 2.7 V) Up to 30 MHz operation*2

(VDD = 2.7 V to 3.6 V)

Min Max Min Max

SCK clock frequency

(All commands except

FSTRD command) fCK 025030MHz

SCK clock frequency

(for FSTRD command) fCK 025040MHz

Clock high time tCH 15 ⎯11 ⎯ns

Clock low time tCL 15 ⎯11 ⎯ns

Chip select set up time tCSU 10 ⎯10 ⎯ns

Chip select hold time tCSH 10 ⎯10 ⎯ns

Output disable time tOD ⎯12 ⎯12 ns

Output data valid time tODV ⎯18 ⎯9ns

Output hold time tOH 0⎯0⎯ns

Deselect time tD40 ⎯40 ⎯ns

Data in rising time tR⎯50 ⎯50 ns

Data falling time tF⎯50 ⎯50 ns

Data set up time tSU 5⎯5⎯ns

Data hold time tH5⎯5⎯ns

HOLD set uptime tHS 10 ⎯10 ⎯ns

HOLD hold time tHH 10 ⎯10 ⎯ns

HOLD output floating time tHZ ⎯20 ⎯20 ns

HOLD output active time tLZ ⎯20 ⎯20 ns

SLEEP recovery time tREC ⎯400 ⎯400 μs

MB85RS1MT

DS501-00022-6v0-E 17

AC Load Equivalent Circuit

3. Pin Capacitance

Parameter Symbol Condition Value Unit

Min Max

Output capacitance COVDD = VIN = VOUT = 0 V,

f = 1 MHz, TA = +25 °C

⎯6pF

Input capacit ance CI⎯8pF

30 pF

Output

3.3 V

1.2 k

0.95 k

MB85RS1MT

18 DS501-00022-6v0-E

■TIMING DIAGRAM

• Serial Data Timing

• Hold Timing

SCK

Valid in

SOHigh-Z

: H or L

CSU

ODV

CSH

High-Z

SCK

tHStHStHHtHH tHH tHH

tHZ tLZ tHZ tLZ

tHStHS

HOLD

High-ZHigh-Z

MB85RS1MT

DS501-00022-6v0-E 19

■POWER ON/OFF SEQUENCE

If the device does not operate within the specified conditions of read cycle, write cycle or power on/off

sequence, memory data can not be guaranteed.

■FRAM CHARACTERISTICS

*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates

with destructive readout mechanism.

*2 : Minimum va lues define retention time of the first reading/writing data right afte r shipment, and these value s

are calculated by qualification results.

■NOTE ON USE

We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.

Parameter Symbol Value Unit

Min Max

CS level hold time at power OFF tpd 400 ⎯ns

CS level hold time at power ON tpu 250 ⎯μs

Power supply rising time tr 0.05 ⎯ms/V

Power supply falling time tf 0.1 ⎯ms/V

Item Min Max Unit Parameter

Read/Write Endurance*11013 ⎯Tim es/ by te Operation Ambient Temper at ur e TA = + 85 °C

Data Retention*2

10 ⎯

Years

Operation Amb ie nt Tem p er at ur e T A = + 85 °C

95 ⎯Operation Amb ie nt Tem p er at ur e T A = + 55 °C

≥ 200 ⎯Operation Amb ie nt Tem p er at ur e T A = + 35 °C

GND

CS >V

× 0.8 ∗

tpd tputr

(Max)

1.0 V

(Min)

CS : don't care CS >V

× 0.8 ∗

CSCS

GND

(Max)

1.0 V

(Min)

* : CS (M a x) < VDD + 0.5 V

MB85RS1MT

20 DS501-00022-6v0-E

■ESD AND LATCH-UP

• Current method of Latch-Up Resistance Test

Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.

Confirm the latch up does not occur under IIN = ± 300 mA.

In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be

increased to the level that meets the specific requirement.

Test DUT Value

ESD HBM (Human Body Model)

JESD22-A114 compliant

MB85RS1MTPNF-G-JNE1

≥ |2000 V|

ESD MM (Machine Model)

JESD22-A115 compliant ≥ |200 V|

ESD CDM (Charged Device Model)

JESD22-C101 compliant ≥ |1000 V|

Latch-Up (I-test)

JESD78 compliant ⎯

Latch-Up (V supply overvoltage test)

JESD78 compliant ⎯

Latch-Up (C ur re nt Method)

Proprietary method ⎯

Latch-Up (C -V Me th od )

Proprietary method ≥ |200 V|

VDD

VSS

DUT

Test terminal

Protection Resistance

VDD

(Max.Rating)

Reference

terminal

MB85RS1MT

DS501-00022-6v0-E 21

• C-V method of Latch-Up Resistance Test

Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is

considered as one cycle. Repeat this process 5 times. However, if the lat ch-up condition occurs before

completing 5times, this test must be stopped immed iately.

■REFLOW CONDITIONS AND FLOOR LIFE

[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)

■Current status on Contained Restricted Substances

This product complies with the r egulation s of REACH Regulat ions , EU Ro HS Directiv e and China RoHS . 　

VDD

VSS

DUT

200pF

Test

terminal

Protection Resistance

VDD

(Max.Rating)

Reference

terminal

MB85RS1MT

22 DS501-00022-6v0-E

■ORDERING IN FORMATION

*1 : Please contact ou r sales office about mi nimum shipping quantity.

*2 : Will be available in January, 2017.

Part number Package Shipping form Minimum shipping

quantity

MB85RS1MTPNF-G-JNE1 8-pin plastic SOP

(FPT-8P-M02) Tube ⎯ *1

MB85RS1MTPNF-G-JNERE1 8-pin plastic SOP

(FPT-8P-M02) Embossed Carrier tape 1500

MB85RS1MTPW-G-APEWE1 8-pin plastic WLP

(WLP-8P-M01) Embossed Carrier tape 1500

MB85RS1MTPH-G-JNE1*2 8-pin plastic DIP

(DIP-8P-M03) Tube ⎯ *1

MB85RS1MT

DS501-00022-6v0-E 23

■PACKAGE DIMENSION

(Continued)

8-pin plastic SOP Lead pitch 1.27 mm

Package width ×

package length 3.9 mm × 5.05 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.75 mm MAX

We ight 0.06 g

8-pin plastic SOP

(FPT-8P-M02)

(

FPT-8P-M02

)

1.27(.050)

3.90±0.30 6.00±0.20

.199

–.008

+.010

–0.20

+0.25

5.05

0.13(.005)

(.154±.012) (.236±.008)

0.10(.004)

0.44±0.08

(.017±.003)

–0.07

+0.03

0.22

.009

+.001

–.003

0.40(.016) "A" 0~8

0.25(.010)

(Mounting height)

Details of "A" part

1.55±0.20

(.061±.008)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.15±0.10

(.006±.004)

(Stand off)

0.10(.004)

2002-2012 FUJITSUSEMICONDUCT OR LIMITED F08004S-c-5-10

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) 1 : These dimensions include resin protrusion.

Note 2) 2 : These dimensions do not include resin protrusion.

Note 3) Pins width and pins thickness include plating thickness.

Note 4) Pins width do not include tie bar cutting remainder.

MB85RS1MT

24 DS501-00022-6v0-E

(Continued)

8-pin plastic WLP Lead pitch 0.5 mm

Package width ×

package length 2.28 mm × 3.092 mm

Sealing method Print

Mounting height 0.33 mm Max.

Weight TBD

8-pin plastic WLP

( WLP- 08P-M01 )

2015 FUJITSU SEMICONDUCTOR LIMITED

Dimensions in mm.

Note: The values in parentheses are reference values.

3.092±0.03

2.28±0.03



0.08±0.02

0.25±0.02

0.05

ࠉࠉ

2)127&+

1.2

0.946

0.11

0.74

ڧ,1'(;

0.8

ȍs

P 0.5

( WLP- 08P-M01 )

Lead shape Soldering ball

MB85RS1MT

DS501-00022-6v0-E 25

(Continued)

8-pin plastic DIP Lead pitch 2.54 mm

Sealing method

Plastic mold

8-pin plastic DIP

(DIP-8P-M03)

2006-2010 FUJITSUSEMICONDUCTOR LIMITED D08008S-c-1-4

0.25±0.05

(.010±.002)

15° MAX

.370 –.012

+.016

–0.30

+0.40

9.40

(.250±.010)

6.35±0.25

INDEX

0.50(.020)

MIN

TYP.

2.54(.100)

(.018±.003)

0.46±0.08

3.00(.118)MIN

4.36(.172)MAX

1.52

.060 –0

+.012

–0

+0.30

–0

–00.99+0.30

+.012

.039

.035

0.89+.014

+0.35

–.012

–0.30

TYP.

7.62(.300)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Weight

0.46 g

MB85RS1MT

26 DS501-00022-6v0-E

■MARKING

RS1MT

E11150

300

[MB85RS1MTPNF-G-JNE1]

[MB85RS1MTPNF-G-JNERE1]

[FPT-8P-M02]

[WLP-8P-M01]

[MB85RS1MTPW-G-APE1]

[MB85RS1MTPW-G-APEWE1]

MB85RS1MT

DS501-00022-6v0-E 27

[DIP-8P-M03]

[MB85RS1MTPH-G-JNE1]

RS1MT

E11600

300

MB85RS1MT

28 DS501-00022-6v0-E

■PACKING INFORMATION

1. Tube

1.1 Tube Dimensions

• Tube/stopper shape

Tube cross-sections and Maximum quantity

Package form Package code Maximum quantity

pcs/

tube pcs/inner

box pcs/outer

box

SOP, 8, plastic (2)

t = 0.5

Transparent polyethylene terephthalate

FPT-8P-M02 95 7600 30400

(Dimensions in mm)

(treated to ant i sta ti c)

Tube length: 520 mm

(treated to antistatic)

Stopper

Tube

Transparent polyethylene terephthalate

4.4

6.4

7.4

1.8

C2006 FUJITSU LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-1

2.6

F08008-SET1-PET:FJ99L-0022-E0008-1-K-3

MB85RS1MT

DS501-00022-6v0-E 29

1.2 Tube Dry pack packing specifications

*1:For a product of witch part number is suffixed with “E1”, a “ ” marks is display to the moisture barrier

bag and the inner boxes.

*2:The space in the outer box will be filled with empty inner boxes, or cushions, etc.

*3:Please refer to an attached sheet about the indication label.

Note: The packing specifications ma y not be applied when the product is delivered via a distributor .

Tube

Dry pack

Inner box

Outer box

For SOP

Stopper

Aluminum Iaminated bag

Index mark

Desiccant

Label I

*1*3

Heat seal

Aluminum Iaminated bag

(tubes inside)

Cushioning material

Inner box

Label I

*1*3

Cushioning material

Humidity indicator

Outer box

Label II-A

Label II-B

Use adhesive tapes.

GPb

MB85RS1MT

30 DS501-00022-6v0-E

1.3 Product labe l indi ca t ors

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)

[C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)]

Label II-A: La bel on Outer box [D Label] (100mm × 100mm)

Label II-B: Outer boxes prod uct indicate

Note: Depending on shipment state, “Label II -A” and “Label II-B” on the external boxes might not be printed.

(Customer part number or FJ part number)

(FJ control number bar code)

XX/XX XXXX-XXX XXX

XXXX-XXX XXX

(Lot Number and quantity)

(Package count)

(Customer part number or FJ part number

bar code)

(Part number and quantity)

(FJ control number)

QC PASS

XXXXXXXXXXXXXX

XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx

(3N)1 XXXXXXXXXXXXXX XXX

(Quantity)

(3N)2 XXXXXXXXXX

XXX pcs

XXXXXX

XXXXXXXXXXXXXX

(Customer part number or FJ part number)

XXXXXXXXXXXXXX

(Comment)

XXXXXXXXXXXXXX

(FJ control number )

XXXXXXXXXX

(LEAD FREE mark)

C-3 Label

Supplemental Label

Perforated line

XXXXXXXXXXXXX (Customer Name)

(CUST.)

XXX (FJ control number)

XXXXXXXXXXXXXX

(Part number)

(FJ control number + Product quantity)

(FJ control number + Product quantity

bar code)

(Part number + Product quantity bar code)

XXXXXXXXX (Delivery Address)

(DELIVERY POINT)

XXXXXXXXXXXXXX

(TRANS.NO.) (FJ control number)

XXXXXXXXXXXXXX

(PART NO.) (Customer part number or

FJ part number)

XXX/XXX

(Q’TY/TOTAL Q’TY) XX

(UNIT)

(CUSTOMER'S

REMARKS)

XXXXXXXXXXXXXXXXXXXX

(PACKAGE COUNT)

XXX/XXX

(PART NAME) XXXXXXXXXXXXXX (Part number)

(3N)3 XXXXXXXXXXXXXX XXX

(Part number + Product quantity)

(3N)4 XXXXXXXXXXXXXX XXX

(FJ control number)

(FJ control number bar code)

(3N)5 XXXXXXXXXX

D Label

XXXXXXXXXXXXXX (Part number)

(Lot Number)

XXXX-XXX

(Count) (Quantity)

X XXX

XXX

MB85RS1MT

DS501-00022-6v0-E 31

1.4 Dimensions for Containers

(1) Dimensions for in ner box

(2) Dimensions for outer box

LWH

540 125 75

(Dimensions in mm)

LWH

565 270 180

(Dimensions in mm)

MB85RS1MT

32 DS501-00022-6v0-E

2. Emboss Tape (FPT-8P-M02)

2.1 Tape Dimensions

PKG code Reel No Maximum storage capacity

pcs/reel pcs/inner box pcs/outer box

FPT-8P-M02 3 1500 1500 10500

(Dimensions in mm)

Material : Conductive polystyrene

Heat proof temperature : No heat resistance.

Package should not be baked

by using tape and reel.

C2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1

8±0.1

6.4±0.1

3.9±0.2

4±0.1

5.5±0.05

5.5±0.1

2.1±0.1

0.4

1.75±0.1

0.3±0.05

2±0.05

+0.1

–0

ø1.5

+0.1

–0

ø1.5

+0.3

–0.1

BA A

SEC.A-A

SEC.B-B

MB85RS1MT

DS501-00022-6v0-E 33

2.2 IC orientation

2.3 Reel dimensions

Dimensions in mm

Reel No 123456789101112131415

Tape width

Symbol 8 12 16 24 32 44 56121624

A 254 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 330 ± 2

B100 100 150 100 150 100 100 ± 2

C 13 ± 0.2 13

D 21 ± 0.8 20.5

E 2 ± 0.5

W1 8.4 12.4 16.4 24.4 32.4 44.4 56.4 12.4 16.4 24.4

less than

14.4

less than 18.4 less than 22.4 less than 30.4 less than 38.4 less than 50.4

less than

62.4 less than

18.4 less than

22.4 less than

30.4

7.9 ~ 10.9 11.9 ~ 15.4 15.9 ~ 19.4 23.9 ~ 27 .4 31.9 ~ 35.4 43.9 ~ 47.4 55.9 ~

59.4 12.4 ~

14.4 16.4 ~

18.4 24.4 ~

26.4

r1.0

(User Direction of Feed) (User Direction of Feed)

• ER type Index mark

(Reel side)

∗

: Hub unit width dimensions

Reel cutout dimensions

W2 r

-0

+0.5

-0.2

-0

+0.1

-0

MB85RS1MT

34 DS501-00022-6v0-E

2.4 Taping (φ330mm Reel) Dry Pack Packing Specifications

*1:For a product of witch part number is suffixed with “E1”, a “ ” marks is display to the moisture barrier

bag and the inner boxes.

*2:The size of the outer box may be changed depending on the quantity of inner boxes.

*3:The space in the outer box will be filled with empty inner boxes, or cushions, etc.

*4:Please refer to an attached sheet about the indication label.

Note: The packing specifications ma y not be applied when the product is delivered via a distributor .

Embossed

tapes

Dry pack

Inner box

Outer box

Outside diameter: 330mm reel

Heat seal

Label I

*1, *4

Label II-B

Label II-A

Label I

*1, *4

Label I

*1, *4

Taping

Use adhesive tapes.

Outer box

*2, *3

Inner box

Label I

*1, *4

Desiccant

Humidity indicator

Aluminum laminated bag

GPb

MB85RS1MT

DS501-00022-6v0-E 35

2.5 Product labe l indi ca t ors

Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)

[C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)]

Label II-A: La bel on Outer box [D Label] (100mm × 100mm)

Label II-B: Outer boxes prod uct indicate

Note: Depending on shipment state, “Label II -A” and “Label II-B” on the external boxes might not be printed.

(Customer part number or FJ part number)

(FJ control number bar code)

XX/XX XXXX-XXX XXX

XXXX-XXX XXX

(Lot Number and quantity)

(Package count)

(Customer part number or FJ part number

bar code)

(Part number and quantity)

(FJ control number)

QC PASS

XXXXXXXXXXXXXX

XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx

(3N)1 XXXXXXXXXXXXXX XXX

(Quantity)

(3N)2 XXXXXXXXXX

XXX pcs

XXXXXX

XXXXXXXXXXXXXX

(Customer part number or FJ part number)

XXXXXXXXXXXXXX

(Comment)

XXXXXXXXXXXXXX

(FJ control number )

XXXXXXXXXX

(LEAD FREE mark)

C-3 Label

Supplemental Label

Perforated line

XXXXXXXXXXXXX (Customer Name)

(CUST.)

XXX (FJ control number)

XXXXXXXXXXXXXX

(Part number)

(FJ control number + Product quantity)

(FJ control number + Product quantity

bar code)

(Part number + Product quantity bar code)

XXXXXXXXX (Delivery Address)

(DELIVERY POINT)

XXXXXXXXXXXXXX

(TRANS.NO.) (FJ control number)

XXXXXXXXXXXXXX

(PART NO.) (Customer part number or

FJ part number)

XXX/XXX

(Q’TY/TOTAL Q’TY) XX

(UNIT)

(CUSTOMER'S

REMARKS)

XXXXXXXXXXXXXXXXXXXX

(PACKAGE COUNT)

XXX/XXX

(PART NAME) XXXXXXXXXXXXXX (Part number)

(3N)3 XXXXXXXXXXXXXX XXX

(Part number + Product quantity)

(3N)4 XXXXXXXXXXXXXX XXX

(FJ control number)

(FJ control number bar code)

(3N)5 XXXXXXXXXX

D Label

XXXXXXXXXXXXXX (Part number)

(Lot Number)

XXXX-XXX

(Count) (Quantity)

X XXX

XXX

MB85RS1MT

36 DS501-00022-6v0-E

2.6 Dimensions for Containers

(1) Dimensions for in ner box

(2) Dimensions for outer box

Tape width L W H

12, 16

365 345

24, 32 50

44 65

56 75

(Dimensions in mm)

LWH

415 400 315

(Dimensions in mm)

MB85RS1MT

DS501-00022-6v0-E 37

■MAJOR CHANGES IN THIS EDITION

A change on a page is indicated by a vertical line drawn on the left side of that page.

Page Section Change Results

1, 2, 22, 25, 27 DIP, 8pin Added DIP package.

1■ FEATURES Added Data retention under 85 °C.

19 ■ FRAM CHARACTERISTICS Added Data retention under 85 °C.

MB85RS1MT

38 DS501-00022-6v0-E

MEMO

MB85RS1MT

DS501-00022-6v0-E 39

MEMO

MB85RS1MT

FUJITSU SEMICONDUCTOR LIMITED

Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,

Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan

http://jp.fujitsu.com/fsl/en/

FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves

the right to make changes to the information contained in this document without notice. Please contact your FUJITSU

SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.

Information contained in this document, such as descriptions of function and application circuit examples is presented solely for

reference to examples of operations and uses of FUJITSU SEMICOND UCTOR device. FUJITSU SEMICONDUCTOR disclaims

any and all warranties of any kind, whether express or implied, rela ted to such information, including, without limitation, quality,

accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the

FUJITSU SEMICONDUCTOR device based on such information, you must assume any responsibility or liability arising out of or

in connection with such information or any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liab ility for any

damages whatsoever arising out of or in connection with such information or any use thereof.

Nothing contained in this document shall be constr ued as granting or conferring any right under any patents, copyr ights, or any other

intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express or implied.

FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringe ment of any intellectual property rights or other

rights of third parties resulting from or in connection with the information contained herein or use thereof.

The products described in this document are designed, developed and manufactured as contemplated for general use including

without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and

manufactured as con templated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safet y is secured,

could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear

facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and

military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater

and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages

arising out of or in connection with above-mentioned uses of the products.

Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and

safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your

facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal

operating conditions.

The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control

Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring

compliance with such laws and regulations relating to export or re-export of the products and technical information de scribed herein.

All company names, brand names and trademarks herein are property of their respective owners.

Edited: System Memory Business Division