DS646F3 3
CS42438
5.8 Recommended Power-Up Sequence ............................................................................................. 37
5.8.1 Hardware Mode ..................................................................................................................... 37
5.8.2 Software Mode ...................................................................................................................... 38
5.9 Reset and Power-Up ...................................................................................................................... 38
5.10 Power Supply, Grounding, and PCB Layout ................................................................................ 38
6. REGISTER QUICK REFERENCE ........................................................................................................ 39
7. REGISTER DESCRIPTION .................................................................................................................. 41
7.1 Memory Address Pointer (MAP) ..................................................................................................... 41
7.1.1 Increment (INCR) .................................................................................................................. 41
7.1.2 Memory Address Pointer (MAP[6:0]) .. ......... .......... .......... ......... .......... .......... ......... .......... ...... 41
7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 41
7.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 41
7.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 41
7.3 Power Control (Address 02h) ......................................................................................................... 42
7.3.1 Power Down ADC Pairs (PDN_ADCX) ........... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42
7.3.2 Power Down DAC Pairs (PDN_DACX) ....... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42
7.3.3 Power Down (PDN) ............ ... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ...................... 42
7.4 Functional Mode (Address 03h) .............. .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 43
7.4.1 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 43
7.5 Miscellaneous Control (Address 04h) ................ ................ ................ ................. ................ ............ 43
7.5.1 Freeze Controls (FREEZE) ................................................................................................... 43
7.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 43
7.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 44
7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 44
7.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) ......................................................... 44
7.6.3 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 44
7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 44
7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 44
7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) ......................................................................... 45
7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) ......................................................................... 45
7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) ......................................................................... 45
7.7 Transition Control (Address 06h) . ... ... ... .......................................................................................... 45
7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 45
7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 46
7.7.3 Auto-Mute (AMUTE) .............................................................................................................. 46
7.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 47
7.8 DAC Channel Mute (Address 07h) ................................................................................................. 47
7.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 47
7.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 47
7.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 47
7.10 DAC Channel Invert (Address 10h) .............................................................................................. 48
7.10.1 Invert Signal Polarity (INV_AOUTX) .... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ... ... ... ... 48
7.11 AINX Volume Control (Address 11h-16h) .. ...................................................................................48
7.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 48
7.12 ADC Channel Invert (Address 17h) .............................................................................................. 49
7.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 49
7.13 Status (Address 19h) (Read Only) ............... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 49
7.13.1 CLOCK ERROR (CLK ERROR) ............. ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ................ 49
7.13.2 ADC Overflow (ADCX_OVFL) .......... ...... ... .......................................................................... 49
7.14 Status Mask (Address 1Ah) .......................................................................................................... 49
8. EXTERNAL FILTERS ........................................................................................................................... 50
8.1 ADC Input Filter .............................................................................................................................. 50
8.1.1 Passive Input Filter ............................................................................................................. 51
8.1.2 Passive Input Filter w/Attenuation ......................................................................................... 52