MITSUBISHI <CONTROL / DRIVER IC> M56694FP/GP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER DESCRIPTION The M56694 is a semiconductor integrated circuit that has a built- PIN CONFIGURATION (TOP VIEW) in, 32-bit shift register and a latch of CMOS structure with serial input and serial/parallel output, and a 32-bit totem-pole-type Operating temperature: -20 - 75C 23 HVO22 24 HVO21 25 HVO20 26 HVO19 27 HVO18 28 HVO17 29 HVO16 30 HVO15 19 HVO26 18 HVO27 38 M56694FP 39 17 HVO28 16 HVO29 41 15 HVO30 42 14 HVO31 43 13 HVO32 44 12 PGND 5 4 3 FUNCTION 2 Vacuum Fluorescent Display ANODE DRIVER 1 40 PGND VH SIN BLK LAT APPLICATION 20 HVO25 37 VDD 9 SOUT 10 VH 11 Driver section supply voltage: VH=120V 21 HVO24 36 8 Latch circuit included for each stage 22 HVO23 35 7 Cascade connections possible through serial output 34 6 Serial input-serial/parallel output HVO11 HVO10 HVO 9 HVO 8 HVO 7 HVO 6 HVO 5 HVO 4 HVO 3 HVO 2 HVO 1 CLK LGND N.C FEATURES 31 HVO14 Employed are Bi-CMOS and high pressure proof DMOS processing technology. 32 HVO13 33 HVO12 parallel output driver of high pressure proof DMOS structure. The M56694 comprises a 32-bit D type flip-flop with 32 latches connected to its output. Outline 44P6N-A (FP) In accordance with truth table 1, inputting data to SIN and clock pulse to CLK allows SIN signal to be put into the internal shift register when the clock changes from "H" to "L", and simultaneously shift register data to be shifted sequentially. 25 HVO22 26 HVO21 27 HVO20 28 HVO19 29 HVO18 30 HVO17 31 HVO16 22 HVO23 40 21 HVO24 41 20 HVO25 42 19 HVO26 M56694GP 43 18 HVO27 PGND 12 11 10 9 13 HVO32 8 14 HVO31 48 7 15 HVO30 47 6 16 HVO29 46 5 17 HVO28 45 4 44 3 the latch. 23 N.C 39 VH SIN BLK LAT CLK LGND VDD SOUT VH to be output if BLK input is turned to "H", irrespective of data from 24 N.C 38 2 data from the latch to be output if BLK input is turned to "L", and "L" 37 1 retained if LAT input is turned to "L". Driver output HVOn allows N.C HVO11 HVO10 HVO 9 HVO 8 HVO 7 N.C HVO 6 HVO 5 HVO 4 HVO 3 HVO 2 HVO 1 PGND pass data through if LAT input is turned to "H", and data to be 32 HVO15 In accordance with truth table 2, parallel output allows the latch to 33 HVO14 in the series. 34 HVO13 36 N.C M56694 SIN when more than one M56694 is used to expand bits 35 HVO12 Serial output SOUT is used by connecting to the next stage Outline 48P6D-A (GP) N.C: no connection MITSUBISHI <CONTROL / DRIVER IC> M56694FP/GP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER BLOCK DIAGRAM (Note : Pin No. in paretheses are of M56694GP) HVO 1 (1) 44 HVO 2 (48) HVO 3 43 (47) HVO30 42 HVO31 15 (15) HVO32 14 (14) 13 (13) Output protect circuit VDD 2 11 9 1 (9) VH (3)(11) PGND 12 (2)(12) 4 BLK (5) Q Q Q Q Q Q L D L D L D L D L D L D 5 LAT 7 (6) LGND (8) 3 SIN D Q D Q D Q D Q D Q D Q T T T T T T (4) 8 6 CLK 10 SOUT (10) N.C (23)(24)(36) (37)(43) (7) TRUTH TABLE Truth table 1. Shift register section CLK Shift register operation DATA is shifted. H or L No changes. Truth table 2. Latch and driver sections Dn LAT BLK HVOn X X H Output all "L" H H L H L H L L X L L Latch's data output. Dn=nth bit DFF retention data HVOn=nth bit driver output L="L" level H="H" level X="L" level or "H" level MITSUBISHI <CONTROL / DRIVER IC> M56694FP/GP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER PIN FUNCTION DESCRIPTION Pin name VDD LGND VH PGND CLK SIN SOUT LAT BLK HVO1 - 32 Function Logic stage supply voltage Logic stage ground Output stage supply voltage Output stage ground Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be shifted in order by High to Low change of the clock. Serial data input Serial data output Latch input. When the LATCH is set to "H", the data in the shift resister will enter the each latch circuit. When the LATCH input is set to "L", the data will be held. Enable input for output control. When the BLK input is set to "L", data in the latch circuit will appear at outputs. When the BLK input is set to "H", all outputs will be set to "L". Output driver (push-pull) ABSOLUTE MAXIMUM RATINGS (Ta=25C, unless otherwise noted) Symbol VDD VH VI VO VHVO Pd Tstg Parameter Logic stage supply voltage Output stage supply voltage Logic inputs voltage Logic outputs voltage Output voltage Power dissipation range Storage temperature range Conditions Data output High supply voltage output pin Ta 25C Ratings -0.3 - 7 -0.3 - 120 -0.3 - VDD+0.3 -0.3 - VDD+0.3 -0.3 - VH 940 -55 - 150 Unit V V V V V mW C Ratings 4.5 - 5.5 10 - 110 -20 - 75 Unit V V C RECOMMENDED OPERATING CONDITIONS Symbol VDD VH Topr Parameter Supply voltage Supply voltage Operating temperature Conditions ELECTRICAL CHARACTERISTICS (VDD=5V, VH=110V and Ta=25C, unless otherwise noted) Parameter Symbol IDD Supply current 1 IH Supply current 2 IIH "H" input current IIL "L" input current VHVOH VHVOL VOH VOL IHVOH IHVOL VTH VTL Driver output voltage Logic output voltage "H" output current "L" output current Output protect operating voltage Test conditions No load Output all "L", no load Output all "H", no load Input pin VIH=5V SIN, LAT, CLK VIL = 0V BLK IHVOH = -0.5mA IHVOL = 0.5mA IOH = -0.1mA IOL = +0.1mA High supply voltage output pin High supply voltage output pin Min. Limits Typ. 1 0 2 0 0 100 4.5 -20 106 0.7 4.95 0.04 -1 1 3.4 3.1 Max. 2 50 4 2 -2 -100 2 0.4 -3 3 Unit mA A mA A A A V V mA mA V V MITSUBISHI <CONTROL / DRIVER IC> M56694FP/GP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER SWITCHING CHARACTERISTICS (VDD=5V, VH=110V and Ta=25C, unless otherwise noted) Parameter Symbol fCLK t PLH(SO) t PHL(SO) t PLH(OUT) t PHL(OUT) t rout t fout Test conditions Clock frequency Min. Limits Typ. Max. Duty = 45 - 55% CL = 15pF Logic output propagation time Driver output propagation time 8 300 300 2 1 2.5 120 100 1 0.16 1.3 0.35 RO = 220K CO = 50pF Driver output rise and fall time 2 TEST CIRCUIT input VDD VH SOUT PG DUT CL (1) Pulse generator characteristics tr20ns tf20ns (2) Capacitance CL includes connection floating capacitance and probe input capacitance. : RO=220K : CO=50pF HVOn 50 CO RO TIMING WAVEFORM 1/fmax CLK 50% 50% SIN 50% 50% 50% tsu th trso tfso SOUT 90% 50% 10% 90% 50% 10% tPHL(SO) tPLH(SO) BLK 50% 50% trOUT HVOn 10% tPLH(OUT) tfOUT 90% 50% 90% 50% tPHL(OUT) 10% Unit MHz ns ns s s s s MITSUBISHI <CONTROL / DRIVER IC> M56694FP/GP Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER TYPICAL CHARACTERISTICS Thermal derating Driver output VON-IOH 10 Ta=+75C 0.5 0 8 "H" output current IOH(mA) Power dissipation Pd(W) 1.0 0.94 Ta=+25C Ta=-20C 6 4 2 0 0 25 50 75 0 100 2 Duty cycle vs Permissible output current 1 - 13 16 8 7 24 6 5 32 4 3 7 6 4 24 3 32 2 1 100 Duty cycle (%) Note * Ta=25C * Repeated frequency >100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit. 16 5 1 80 9 8 2 0 1 - 8 9 Output current IOH(mA) Output current IOH(mA) 9 60 10 10 14 40 8 Duty cycle vs Permissible output current 10 20 6 "H" output voltage VON(V) Temperature Ta(C) 0 4 0 0 20 40 60 80 100 Duty cycle (%) Note * Ta=75C * Repeated frequency >100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit. Note 1. VDD=5V and VH=110V, unless otherwise noted 2. Thermal derating characteristics represent those of an individual IC unit. 3. Allowable duty cycle output current characteristics represent that when a standard substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)