MJE13009 - Motorola / Freescale Semiconductor

3–676 Motorola Bipolar Power Transistor Device Data





 

 

  !  

The MJE13009 is designed for high–voltage, high–speed power switching inductive

circuits where fall time is critical. They are particularly suited for 115 and 220 V

switchmode applications such as Switching Regulators, Inverters, Motor Controls,

Solenoid/Relay drivers and Deflection circuits.

SPECIFICATION FEATURES:

•VCEO(sus) 400 V and 300 V

•Reverse Bias SOA with Inductive Loads @ TC = 100

•Inductive Switching Matrix 3 to 12 Amp, 25 and 100

...tc @ 8 A, 100

C is 120 ns (Typ).

•700 V Blocking Capability

•SOA and Switching Applications Information.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Rating

ÎÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

Value

ÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Voltage

ÎÎÎÎÎÎÎ

VCEO(sus)

ÎÎÎÎÎÎÎÎ

400

ÎÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Voltage

ÎÎÎÎÎÎÎ

VCEV

ÎÎÎÎÎÎÎÎ

700

ÎÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter Base Voltage

ÎÎÎÎÎÎÎ

VEBO

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Current — Continuous

— Peak (1)

ÎÎÎÎÎÎÎ

ICM

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

Adc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Base Current — Continuous

— Peak (1)

ÎÎÎÎÎÎÎ

IBM

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

Adc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter Current — Continuous

— Peak (1)

ÎÎÎÎÎÎÎ

IEM

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

Adc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Total Power Dissipation @ TA = 25

Derate above 25

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

Watts

mW/

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Total Power Dissipation @ TC = 25

Derate above 25

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

100

800

ÎÎÎÎ

Watts

mW/

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating and Storage Junction Temperature Range

ÎÎÎÎÎÎÎ

TJ, Tstg

ÎÎÎÎÎÎÎÎ

–65 to +150

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

THERMAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

Max

ÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Thermal Resistance, Junction to Ambient

ÎÎÎÎÎÎÎ

RθJA

ÎÎÎÎÎÎÎÎ

62.5

ÎÎÎÎ

C/W

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Thermal Resistance, Junction to Case

ÎÎÎÎÎÎÎ

RθJC

ÎÎÎÎÎÎÎÎ

1.25

ÎÎÎÎ

C/W

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Lead Temperature for Soldering Purposes:

1/8″ from Case for 5 Seconds

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

275

ÎÎÎÎ

(1) Pulse Test: Pulse Width = 5 ms, Duty Cycle

10%.

Designer’s Data for “W orst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Designer’s and SWITCHMODE are trademarks of Motorola, Inc.



SEMICONDUCTOR TECHNICAL DATA Order this document

by MJE13009/D

 Motorola, Inc. 1995



12 AMPERE

NPN SILICON

POWER TRANSISTOR

400 VOLTS

100 WATTS

*Motorola Preferred Device



CASE 221A–06

TO–220AB

REV 2

MJE13009

3–677

Motorola Bipolar Power Transistor Device Data

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (TC = 25

C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

*OFF CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Sustaining Voltage

(IC = 10 mA, IB = 0)

ÎÎÎÎ

VCEO(sus)

ÎÎÎÎ

400

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Cutoff Current

(VCEV = Rated Value, VBE(off) = 1.5 Vdc)

(VCEV = Rated Value, VBE(off) = 1.5 Vdc, TC = 100

ÎÎÎÎ

ICEV

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter Cutoff Current

(VEB = 9 Vdc, IC = 0)

ÎÎÎÎ

IEBO

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SECOND BREAKDOWN

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Second Breakdown Collector Current with base forward biased

Clamped Inductive SOA with Base Reverse Biased

ÎÎÎÎ

IS/b

—

ÎÎÎÎÎÎÎÎÎÎÎÎ

See Figure 1

See Figure 2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clamped Inductive SOA with Base Reverse Biased

ÎÎÎÎ

S/b

—

ÎÎÎÎÎÎÎÎÎÎÎÎ

See Figure 2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

*ON CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Gain

(IC = 5 Adc, VCE = 5 Vdc)

(IC = 8 Adc, VCE = 5 Vdc)

ÎÎÎÎ

hFE

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Saturation Voltage

(IC = 5 Adc, IB = 1 Adc)

(IC = 8 Adc, IB = 1.6 Adc)

(IC = 12 Adc, IB = 3 Adc)

(IC = 8 Adc, IB = 1.6 Adc, TC = 100

ÎÎÎÎ

VCE(sat)

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

1.5

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Base–Emitter Saturation Voltage

(IC = 5 Adc, IB = 1 Adc)

(IC = 8 Adc, IB = 1.6 Adc)

(IC = 8 Adc, IB = 1.6 Adc, TC = 100

ÎÎÎÎ

VBE(sat)

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

1.2

1.6

1.5

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DYNAMIC CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Current–Gain — Bandwidth Product

(IC = 500 mAdc, VCE = 10 Vdc, f = 1 MHz)

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)

ÎÎÎÎ

Cob

ÎÎÎÎ

—

ÎÎÎÎ

180

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Resistive Load (Table 1)

ÎÎÎÎÎÎÎÎ

Delay Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

(VCC = 125 Vdc, IC = 8 A,

IB1 = IB2 = 1.6 A, tp = 25 µs,

Duty Cycle

1%)

ÎÎÎÎ

—

ÎÎÎÎ

0.06

ÎÎÎÎ

0.1

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎ

Rise Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

(VCC = 125 Vdc, IC = 8 A,

IB1 = IB2 = 1.6 A, tp = 25 µs,

Duty Cycle

1%)

ÎÎÎÎ

—

ÎÎÎÎ

0.45

ÎÎÎÎ

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎ

Storage Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

IB1 = IB2 = 1.6 A, tp = 25 µs,

Duty Cycle

1%)

ÎÎÎÎ

—

ÎÎÎÎ

1.3

ÎÎÎÎ

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎ

Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

1%)

ÎÎÎÎ

—

ÎÎÎÎ

0.2

ÎÎÎÎ

0.7

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Inductive Load, Clamped (Table 1, Figure 13)

ÎÎÎÎÎÎÎÎ

Voltage Storage Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

C = 8 A, Vclamp = 300 Vdc,

IB1 = 1.6 A, VBE(off) = 5 Vdc, TC = 100

ÎÎÎÎ

tsv

ÎÎÎÎ

—

ÎÎÎÎ

0.92

ÎÎÎÎ

2.3

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎ

Crossover Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

(IC = 8 A, Vclamp = 300 Vdc,

IB1 = 1.6 A, VBE(off) = 5 Vdc, TC = 100

ÎÎÎÎ

—

ÎÎÎÎ

0.12

ÎÎÎÎ

0.7

ÎÎÎ

µs

*Pulse Test: Pulse Width = 300 µs, Duty Cycle = 2%.

MJE13009

3–678 Motorola Bipolar Power Transistor Device Data

IC, COLLECTOR CURRENT (AMP)

100

1 ms

100

7VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

0.02

0.5

0.1

0.05

30 50 70 100

Figure 1. Forward Bias Safe Operating Area Figure 2. Reverse Bias Switching Safe

Operating Area

0.2

0.01 300 5005 20

0800

100 300

≤

100

IB1 = 2.5 A

500 700

VBE(off) = 9 V

VCEV, COLLECTOR–EMITTER CLAMP VOLTAGE (VOLTS)

200 400 600

5 V

TC = 25

3 V 1.5 V

IC, COLLECTOR (AMP)

200

THERMAL LIMIT

BONDING WIRE LIMIT

SECOND BREAKDOWN LIMIT

CURVES APPLY BELOW RATED VCEO

The Safe Operating Area figures shown in Figures 1 and 2 are specified ratings for these devices under the test conditions shown.

Figure 3. Forward Bias Power Derating

TC, CASE TEMPERATURE (

040 120 160

0.6

POWER DERATING FACTOR

SECOND BREAKDOWN

DERATING

0.8

0.4

0.2

60 100 14080

THERMAL

DERATING

There are two limitations on the power handling ability of a

transistor: average junction temperature and second break-

down. Safe operating area curves indicate IC – VCE limits of

the transistor that must be observed for reliable operation;

i.e., the transistor must not be subjected to greater dissipa-

tion than the curves indicate.

The data of Figure 1 is based on TC = 25

C; TJ(pk) is

variable depending on power level. Second breakdown pulse

limits are valid for duty cycles to 10% but must be derated

when TC ≥ 25

C. Second breakdown limitations do not der-

ate the same as thermal limitations. Allowable current at the

voltages shown on Figure 1 may be found at any case tem-

perature by using the appropriate curve on Figure 3.

TJ(pk) may be calculated from the data in Figure 4. At high

case temperatures, thermal limitations will reduce the power

that can be handled to values less than the limitations im-

posed by second breakdown. Use of reverse biased safe op-

erating area data (Figure 2) is discussed in the applications

information section.

t, TIME (ms)

0.01

0.7

0.2

0.1

0.05

0.02

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.05 1 2 5 10 20 50 100 200 500

JC(t) = r(t) R

JC = 1.25

C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) – TC = P(pk) Z

JC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1/t2

D = 0.5

0.02

SINGLE PULSE

0.1

0.1 0.50.2 1.0 k

0.5

0.3

0.07

0.03

0.02

Figure 4. Typical Thermal Response [ZθJC(t)]

0.01

0.05

0.2

MJE13009

3–679

Motorola Bipolar Power Transistor Device Data

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMP)IC, COLLECTOR CURRENT (AMP)

1.2

1.4

0.8

0.4

Figure 5. DC Current Gain

IC, COLLECTOR CURRENT (AMP)

0.5 1 5 7

Figure 6. Collector Saturation Region

0.05 IB, BASE CURRENT (AMP)

0.30.07

1.2

0.4

hFE, DC CURRENT GAIN

0.1 0.2 0.5 5

Figure 7. Base–Emitter Saturation Voltage Figure 8. Collector–Emitter Saturation Voltage

Figure 9. Collector Cutoff Region

0.8

0.1

VBE, BASE–EMITTER VOLTAGE (VOLTS)

TJ = 25

0.7 3

Figure 10. Capacitance

VR, REVERSE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Cib

Cob

0.1

, COLLECTOR CURRENT ( A)

–0.4 –0.2

100

500

1.6

0.6

IC = 1 A

50.2 2

0.3 1 70.7 100.2 0.5 32 5

600

400

200

200100510.5

V, VOLTAGE (VOLTS)

+0.6

3 A

0.7 1 2

0.5

0.7

0.4

0.2

0.6

0.3

VCE = 5 V

TJ = 150

– 55

0.3

+0.4+0.2

100

10K

800

10 50

REVERSE FORWARD

VCE = 250 V

10 20

5 A 8 A 12 A

TJ = –55

IC/IB = 3

C150

0.3 1 70.7 100.2 0.5 32 5 20

0.1

IC/IB = 3 TJ = 150

– 55

TJ = 150

125

100

0.2 2 20

TJ = 25

MJE13009

3–680 Motorola Bipolar Power Transistor Device Data

REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING RESISTIVE

SWITCHING

OUTPUT WAVEFORMS

TEST CIRCUITS

CIRCUIT

VALUES

TEST WAVEFORMS

NOTE

PW and VCC Adjusted for Desired IC

RB Adjusted for Desired IB1

5 V

DUTY CYCLE

≤

10%

tr, tf

≤

10 ns 68 1 k

0.001

0.02

1N4933

270

+5 V

1 k 2N2905

1/2 W 100

–VBE(off)

MJE200

D.U.T.

1N4933

1N4933 33

2N2222

1 k

MJE210

VCC

+5 V

MR826*

Vclamp

*SELECTED FOR

≥

1 kV

VCE

5.1 k

+125 V

SCOPE

–4.0 V

RBTUT

t1 ADJUSTED TO

OBTAIN IC

≈

Lcoil (ICM)

VCC

≈

Lcoil (ICM)

Vclamp

+10 V 25

–8 V

Coil Data:

Ferroxcube Core #6656

Full Bobbin (~16 Turns) #16

GAP for 200 µH/20 A

Lcoil = 200 µHVCC = 20 V

Vclamp = 300 Vdc

VCC = 125 V

RC = 15

Ω

D1 = 1N5820 or Equiv.

RB =

Ω

Test Equipment

Scope–Tektronics

475 or Equivalent

tr, tf < 10 ns

Duty Cycle = 1.0%

RB and RC adjusted

for desired IB and IC

VCE

TIME

ICM

VCEM

tf CLAMPED

tf UNCLAMPED

≈

Vclamp

Table 1. Test Conditions for Dynamic Performance

APPLICATIONS INFORMATION FOR SWITCHMODE SPECIFICATIONS

INTRODUCTION

The primary considerations when selecting a power tran-

sistor for SWITCHMODE applications are voltage and cur-

rent ratings, switching speed, and energy handling capability.

In this section, these specifications will be discussed and re-

lated to the circuit examples illustrated in Table 2.(1)

VOLTAGE REQUIREMENTS

Both blocking voltage and sustaining voltage are important

in SWITCHMODE applications.

Circuits B and C in Table 2 illustrate applications that re-

quire high blocking voltage capability. In both circuits the

switching transistor is subjected to voltages substantially

higher than VCC after the device is completely off (see load

line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking ca-

pability at this point depends on the base to emitter condi-

tions and the device junction temperature. Since the highest

device capability occurs when the base to emitter junction is

reverse biased (VCEV), this is the recommended and speci-

fied use condition. Maximum ICEV at rated VCEV is specified

at a relatively low reverse bias (1.5 Volts) both at 25°C and

100

C. Increasing the reverse bias will give some improve-

ment in device blocking capability.

The sustaining or active region voltage requirements in

switching applications occur during turn–on and turn–off. If

the load contains a significant capacitive component, high

current and voltage can exist simultaneously during turn–on

and the pulsed forward bias SOA curves (Figure 1) are the

proper design limits.

For inductive loads, high voltage and current must be sus-

tained simultaneously during turn–of f, in most cases, with the

base to emitter junction reverse biased. Under these condi-

tions the collector voltage must be held to a safe level at or

below a specific value of collector current. This can be ac-

complished by several means such as active clamping, RC

snubbing, load line shaping, etc. The safe level for these de-

vices is specified as a Reverse Bias Safe Operating Area

(Figure 2) which represents voltage–current conditions that

can be sustained during reverse biased turn–off. This rating

is verified under clamped conditions so that the device is

never subjected to an avalanche mode.

(1) For detailed information on specific switching applications, see

Motorola Application Notes AN–719, AN–767.

MJE13009

3–681

Motorola Bipolar Power Transistor Device Data

VOLTAGE REQUIREMENTS (continued)

In the four application examples (Table 2) load lines are

shown in relation to the pulsed forward and reverse biased

SOA curves.

In circuits A and D, inductive reactance is clamped by the

diodes shown. In circuits B and C the voltage is clamped by

the output rectifiers, however, the voltage induced in the pri-

mary leakage inductance is not clamped by these diodes and

could be large enough to destroy the device. A snubber net-

work or an additional clamp may be required to keep the

turn–off load line within the Reverse Bias SOA curve.

Load lines that fall within the pulsed forward biased SOA

curve during turn–on and within the reverse bias SOA curve

during turn–off are considered safe, with the following as-

sumptions:

(1) The device thermal limitations are not exceeded.

(2) The turn–on time does not exceed 10 µs (see standard

pulsed forward SOA curves in Figure 1).

(3) The base drive conditions are within the specified limits

shown on the Reverse Bias SOA curve (Figure 2).

CURRENT REQUIREMENTS

An efficient switching transistor must operate at the re-

quired current level with good fall time, high energy handling

capability and low saturation voltage. On this data sheet,

these parameters have been specified at 8 amperes which

represents typical design conditions for these devices. The

current drive requirements are usually dictated by the

VCE(sat) specification because the maximum saturation volt-

age is specified at a forced gain condition which must be du-

plicated or exceeded in the application to control the

saturation voltage.

SWITCHING REQUIREMENTS

In many switching applications, a major portion of the tran-

sistor power dissipation occurs during the fall time ( tfi). For

this reason considerable effort is usually devoted to reducing

the fall time. The recommended way to accomplish this is to

reverse bias the base–emitter junction during turn–off. The

reverse biased switching characteristics for inductive loads

are discussed in Figure 11 and Table 3 and resistive loads in

Figures 13 and 14. Usually the inductive load component will

be the dominant factor in SWITCHMODE applications and

the inductive switching data will more closely represent the

device performance in actual application. The inductive

switching characteristics are derived from the same circuit

used to specify the reverse biased SOA curves, (See Table

1) providing correlation between test procedures and actual

use conditions.

Figure 11. Turn–On Time

IC, COLLECTOR CURRENT (AMP)

td @ VBE(off) = 5 V

100

700

500

IC, COLLECTOR CURRENT (AMP)

0.7 31 20.2

VCC = 125 V

IC/IB = 5

TJ = 25

0.5

200

300

t, TIME (ns)

0.3

Figure 12. Turn–Off Time

200

100

700 VCC = 125 V

IC/IB = 5

TJ = 25

300

500

t, TIME (ns)

75 10 20 0.7 1 20.2 0.50.3 75 10 20

Figure 13. Inductive Switching Measurements

TIME

Figure 14. Typical Inductive Switching Waveforms

(at 300 V and 12 A with IB1 = 2.4 A and VBE(off) = 5 V)

TIME 20 ns/DIV

VCE

CURRENT 2 A/DIV

VOLTAGE 50 V/DIV

Vclamp

IB90% IB1

10%

VCEM 10%

ICM 2%

Vclamp

90% VCEM 90% IC

tsv trv tfi tti

RESISTIVE SWITCHING PERFORMANCE

MJE13009

3–682 Motorola Bipolar Power Transistor Device Data

CIRCUIT LOAD LINE DIAGRAMS TIME DIAGRAMS

SERIES SWITCHING

REGULATOR

RINGING CHOKE

INVERTER

PUSH–PULL

INVERTER/CONVERTER

SOLENOID DRIVER

VCC VO

VCC

SOLENOID

Collector CurrentCollector CurrentCollector CurrentCollector Current

24 A

12 A

TC = 100

TURN–ON

TURN–OFF

VCC 400 V 700 V

COLLECTOR VOLTAGE

350 V

TURN–ON (FORWARD BIAS) SOA

ton

≤

10 ms

DUTY CYCLE

≤

10%

PD = 4000 W

TURN–OFF (REVERSE BIAS) SOA

1.5 V

≤

VBE(off)

≤

9.0 V

DUTY CYCLE

≤

10%

VCE

VCC

TIME t

24 A

TC = 100

12 A TURN–OFF

TURN–ON

VCC 400 V 1

VCC + N(Vo)

350 V

PD = 4000 W 2

TURN–ON (FORWARD BIAS) SOA

TURN–ON ton

≤

10 ms

TURN–ON DUTY CYCLE

≤

10%

TURN–OFF (REVERSE BIAS) SOA

TURN–OFF 1.5 V

≤

VBE(off)

≤

9.0 V

TURN–OFF DUTY CYCLE

≤

10%

700 V 1

COLLECTOR VOLTAGE

24 A

12 A

TC = 100

TURN–OFF

TURN–ON

VCC 400 V 1700 V 1

2 VCC

350 V

PD = 4000 W 2

TURN–ON (FORWARD BIAS) SOA

TURN–ON ton

≤

10 ms

TURN–ON DUTY CYCLE

≤

10%

TURN–OFF (REVERSE BIAS) SOA

TURN–OFF 1.5 V

≤

VBE(off)

≤

9.0 V

TURN–OFF DUTY CYCLE

≤

10%

24 A

12 A

TC = 100

TURN–OFF

TURN–ON

VCC 400 V 1700 V 1

COLLECTOR VOLTAGE

TURN–OFF (REVERSE BIAS) SOA

TURN–OFF 1.5 V

≤

VBE(off)

≤

9.0 V

TURN–OFF DUTY CYCLE

≤

10%

350 V

PD = 4000 W 2

TURN–ON (FORWARD BIAS) SOA

TURN–ON ton

≤

10 ms

TURN–ON DUTY CYCLE

≤

10%

VCE

VCC

VCC+

N(Vo)

LEAKAGE SPIKE

TIME

toff

ton

VCE

ton toff

VCC

2 VCC

VCE

ton toff t

VCC

Table 2. Applications Examples of Switching Circuits

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Motorola Bipolar Power Transistor Device Data

Table 3. Typical Inductive Switching Performance

ÎÎÎÎ

AMP

ÎÎÎ

ÎÎÎÎ

tsv

ÎÎÎÎ

trv

ÎÎÎÎ

tfi

ÎÎÎÎ

tti

ÎÎÎÎ

ÎÎÎ

100

ÎÎÎÎ

770

1000

ÎÎÎÎ

100

230

ÎÎÎÎ

150

160

ÎÎÎÎ

200

ÎÎÎÎ

240

320

ÎÎÎÎ

ÎÎÎ

100

ÎÎÎÎ

630

820

ÎÎÎÎ

100

ÎÎÎÎ

100

180

ÎÎÎÎ

ÎÎÎ

100

ÎÎÎÎ

720

920

ÎÎÎÎ

120

ÎÎÎÎ

ÎÎÎ

100

ÎÎÎÎ

640

800

ÎÎÎÎ

NOTE: All Data recorded In the Inductive Switching Circuit In Table 1.

SWITCHING TIME NOTES

In resistive switching circuits, rise, fall, and storage times

have been defined and apply to both current and voltage

waveforms since they are in phase. However, for inductive

loads which are common to SWITCHMODE power supplies

and hammer drivers, current and voltage waveforms are not

in phase. Therefore, separate measurements must be made

on each waveform to determine the total switching time. For

this reason, the following new terms have been defined.

tsv = Voltage Storage Time, 90% IB1 to 10% VCEM

trv = Voltage Rise Time, 10–90% VCEM

tfi = Current Fall Time, 90–10% ICM

tti = Current Tail, 10–2% ICM

tc = Crossover Time, 10% VCEM to 10% ICM

An enlarged portion of the turn–off waveforms is shown in

Figure 13 to aid in the visual identity of these terms.

For the designer, there is minimal switching loss during

storage time and the predominant switching power losses

occur during the crossover interval and can be obtained us-

ing the standard equation from AN–222:

PSWT = 1/2 VCCIC(tc) f

Typical inductive switching waveforms are shown in Fig-

ure 14. In general, trv + t fi

]

tc. However, at lower test cur-

rents this relationship may not be valid.

As is common with most switching transistors, resistive

switching is specified at 25

C and has become a benchmark

for designers. However, for designers of high frequency con-

verter circuits, the user oriented specifications which make

this a “SWITCHMODE” transistor are the inductive switching

speeds (tc and tsv) which are guaranteed at 100

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3–684 Motorola Bipolar Power Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A–06

TO–220AB

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.570 0.620 14.48 15.75

B0.380 0.405 9.66 10.28

C0.160 0.190 4.07 4.82

D0.025 0.035 0.64 0.88

F0.142 0.147 3.61 3.73

G0.095 0.105 2.42 2.66

H0.110 0.155 2.80 3.93

J0.018 0.025 0.46 0.64

K0.500 0.562 12.70 14.27

L0.045 0.060 1.15 1.52

N0.190 0.210 4.83 5.33

Q0.100 0.120 2.54 3.04

R0.080 0.110 2.04 2.79

S0.045 0.055 1.15 1.39

T0.235 0.255 5.97 6.47

U0.000 0.050 0.00 1.27

V0.045 ––– 1.15 –––

Z––– 0.080 ––– 2.04

1 2 3

SEATING

PLANE

–T–

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Motorola Bipolar Power Transistor Device Data

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