ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIALTO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853210 is a low skew, high performance ICS dual 1-to-5 Differential-to-2.5V/3.3V LVPECL/ECL HiPerClockSTM Fa n o u t B u f f e r a n d a m e m b e r o f t h e HiPerClockSTMfamily of High Performance Clock Solutions from IDT. The ICS853210 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS853210 ideal for those clock distribution applications demanding well defined perfor mance and repeatability. * Two differential 2.5V/3.3V LVPECL / ECL bank outputs * Two differential clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLKx input * Output skew: 13ps (typical) * Part-to-part skew: 85ps (typical) * Propagation delay: 485ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages VBB nQB1 QB1 nQB0 QB0 27 14 nQB2 nQA1 28 13 QB3 QA1 29 12 nQB3 nQA0 30 11 QB4 QA0 31 10 nQB4 VCCO 32 9 VCCO ICS853210 1 2 3 4 5 6 7 8 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View QB3 nQB3 QB4 nQB4 IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER QB2 QA2 VEE QB2 nQB2 VCCO 15 nPCLKB QB1 nQB1 16 26 PCLKB Pullup/Pulldown QB0 nQB0 25 VBB QA4 nQA4 VCCO nQA2 nPCLKA QA3 nQA3 Pulldown nQA4 24 23 22 21 20 19 18 17 QA2 nQA2 PCLKB nPCLKB QA4 QA3 QA1 nQA1 PCLKA Pullup/Pulldown QA0 nQA0 nc Pulldown VCC PCLKA nPCLKA PIN ASSIGNMENT nQA3 BLOCK DIAGRAM 1 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Type 2 nc Unused 3 PCLKA Input 4 nPCLKA Input 5 VBB Output 6 PCLKB Input 7 nPCLKB Input 8 VEE Power 9, 25, 32 VCCO Power Description Positive supply pin. No connect. Pulldown Non-inver ting differential clock input. Pullup/ Clock input. VCC/2 default when left floating. Pulldown Bias voltage. Pulldown Non-inver ting differential clock input. Pullup/ Clock input. VCC/2 default when left floating. Pulldown Negative supply pin. Output supply pins. 10, 11 nQB4, QB4 Output Differential output pair. LVPECL interface levels. 12, 13 nQB3, QB3 Output Differential output pair. LVPECL interface levels. 14, 15 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 17, 18 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 19, 20 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 21, 22 nQA4, QA4 Output Differential output pair. LVPECL interface levels. 23, 24 nQA3, QA3 Output Differential output pair. LVPECL interface levels. 26, 27 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 28, 29 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 30, 31 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units RPULLDOWN Input Pulldown Resistor 75 k RVCC/2 Pullup/Pulldown Resistors 50 k TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs PCLKA or PCLKB 0 nPCLKA or nPCLKB 1 1 0 0 1 Outputs QA0:QA4, nQA0:nQA4, QB0:QB4 nQB0:nQB4 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting HIGH LOW Differential to Differential Non Inver ting Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 2 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Negative Supply Voltage, VEE 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to -4.6V (ECL mode, V = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Supply Voltage, VCC CC Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA VBB Sink/Source, IBB 0.5mA the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40C to +85C Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA 47.9C/W (0 lfpm) (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.8 V 80 mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Min -40C Typ Max Min 25C Typ Max Min 85C Typ Max Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VIH Input High Voltage(Single-Ended) 2.075 2.36 2.075 2.36 2.075 2.36 V VIL Input Low Voltage(Single-Ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference; NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 PCLK0, PCLK1 Input Low Current nPCLK0, nPCLK1 150 1200 150 1200 150 1200 mV 3.3 1.2 3.3 1.2 3. 3 V 150 A Symbol Parameter VOH VOL VCMR IIH IIL 1.2 800 150 800 800 15 0 Units -10 -10 -10 A -150 -150 -150 A Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol Parameter VOH -40C 25C 85C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565 V VOL Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V VIH Input High Voltage(Single-Ended) 1.275 1.56 1.275 1.56 1.275 -0.83 V VIL Input Low Voltage(Single-Ended) 0.63 0.965 0.63 0.965 0.63 0.965 V VPP 150 1200 150 1200 150 1200 mV 2.5 1.2 2.5 1.2 2.5 V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 150 A IIL Input Low Current VCMR PCLK0, PCLK1 800 1.2 80 0 150 -10 800 150 -10 -10 A -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. A TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V Symbol Parameter VOH -40C 25C 85C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V VBB Output Voltage Reference; NOTE 2 -1.44 -1.32 -1.44 -1.32 -1.44 VPP 150 1200 150 1200 150 0 VEE+1.2V 0 VEE+1.2V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 IIL Input Low Current VCMR PCLK0, PCLK1 VEE+1.2V 800 150 -10 800 800 150 -10 -10 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. -150 IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER -150 4 -150 V -1.32 V 1200 mV 0 V 150 A A A ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V Symbol VCC = 2.375 -40C Parameter fMAX Output Frequency tP LH tsk(o) Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, @ 2.5V High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR/tF Output Rise/Fall Time tP HL OR Min Typ 415 400 115 3.8V; VEE = 0V 25C Max Min Typ 470 520 430 470 54 0 425 13 85C Min Typ 485 54 5 435 515 585 ps 490 55 0 445 515 585 ps 25 13 25 13 25 ps 85 160 85 160 85 160 ps 188 260 19 0 250 190 235 ps >3 130 Max Units Max >3 20% to 80% TO >3 145 GHz All parameters tested 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC VCC, VCCO Qx SCOPE nPCLKA, nPCLKB PCLKA, PCLKB LVPECL V Cross Points PP V CMR nQx VEE VEE -0.375V to -1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nPCLKA, nPCLKB 80% 80% PCLKA, PCLKB VSW I N G Clock Outputs nQA0:nQA4, nQB0:nQB4, 20% 20% tR QA0:QA4, QB0:QB4, tF tPD OUTPUT RISE/FALL TIME IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER PROPAGATION DELAY 6 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 1A shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC(or VDD) CLK_IN PCLK VBB nPCLK FIGURE 1A. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1B shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1B. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 7 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 2A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 2B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK CLK R5 100 Zo = 50 Ohm nCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 2C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PCL K/n PC LK R2 1K FIGURE 2D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 2E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TERMINATION FOR 3.3V LVPECL OUTPUTS transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V Zo = 50 125 FOUT FIN 125 Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 3A. LVPECL OUTPUT TERMINATION IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 84 FIGURE 3B. LVPECL OUTPUT TERMINATION 9 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V VCCO=2.5V 2.5V 2.5V VCCO=2.5V Zo = 50 Ohm R1 250 R3 250 + Zo = 50 Ohm Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 10 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853210. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853210 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW * Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW Total Power_MAX (3.465V, with all outputs switching) = 304mW + 309.4mW = 613.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.613W * 42.1C/W = 110.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 32-PIN LQFP FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 11 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CCO * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.935V (VCCO_MAX - VOH_MAX) = 0.935V * For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.67V (VCCO_MAX - VOL_MAX) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = L L [(2V - 0.935V)/50] * 0.935V = 19.92mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = L L [(2V - 1.67V)/50] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 12 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853210 is: 437 Pin compatible with MC100EP210 and MC100LVEP210 IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 0 -- 7 ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS853210AY ICS853210AY 32 Lead LQFP tray -40C to 85C ICS853210AYT ICS853210AY 32 Lead LQFP 1000 tape & reel -40C to 85C ICS853210AYLF ICS853210AYL 32 Lead "Lead-Free" LQFP tray -40C to 85C ICS853210AYLFT ICS853210AYL 32 Lead "Lead-Free" LQFP 1000 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER REVISION HISTORY SHEET Rev Table A T8 Page 1 9 15 Description of Change Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free par t number, marking, and note. IDT TM / ICSTM 1-TO-5, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 16 Date 10/23/06 ICS853210 REV A OCTOBER 23, 2006 ICS853210 LOW SKEW, DUAL, 1-TO-5, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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