Application Note AN2077/D Rev. 1.2, 11/2001 Motorola RISC Microprocessor Design Checklist Gary Milliorn CPD Applications This application note describes the generally recommended connections for new designs based on Motorola processors which implement the PowerPC architecture, as well as integrated embedded processors, and system controller logic for them. These devices include: * MPC603, MPC603e, MPC603ev * MPC740, MPC745, MPC750, MPC755 * MPC7400, MPC7410 * MPC7440, MPC7450 * MPC8240, MPC8241, MPC8245 * MPC107 The design checklist may also be applicable to bus- or footprint-compatible processors which may be introduced. It may also serve as a useful guide to debugging a newly-designed system, by highlighting those areas of a design which merit special attention during initial system startup. The design checklist covers the following topics: Topic Page Section 1.1, "Introduction" 2 Section 1.2, "Connections" 2 Section 1.3, "L2 Cache Pipelined/Late-Write SRAM Connections" 14 Section 1.4, "L3 Cache DDR SRAM Connections" 15 Section 1.5, "L3 Cache Pipelined/Late-Write SRAM Connections" 15 Section 1.6, "Power" 16 Section 1.7, "Clocks" 17 Section 1.8, "References" 17 Section 1.9, "Revision History" 17 To locate any published errata or updates for this document, refer to the website at http://www.motorola.com/semiconductors. Introduction 1.1 Introduction The Motorola processors that implement the PowerPC architecture, and the PCI bridge/memory controllers which operate with them, are all fairly easy to design to, as long as some simple rules are followed regarding connections and pullups. For reference purposes, many designers may refer to the application notes and example/reference designs available on the Motorola website. 1.2 Connections This section summarizes the connections and special conditions (such as pullups or pulldowns required) which may be needed for Motorola embedded/networking processors and corresponding system/memory controller logic (internal or external). Table 1 lists connections for the MPC603, MPC75x, MPC7400/MPC7410, MPC7450, and MPC824x microprocessors/microcontrollers, while Table 2 lists connections for the MPC8240, MPC8245 and MPC107 microcontrollers/system controllers. To keep the table compact, the cacheless variants (MPC740, MPC745 and MPC7440) are not listed in Table 1; instead, refer to the cache versions (MPC750, MPC755 and MPC7450) and ignore references to the L2 interface. The older MPC604 and MPC106 devices are also not listed; the MPC603 and MPC107 entries are very similar and can be used instead. In the tables, if a connection to a specific signal is not named, it may be one of the following terms: * xx-yy OVDD A pullup resistor to the OVDD power supply, with a value between xx and yy ohms. The choice of value may be selected by the designer, based upon system requirements such as noise immunity and the ability to share pullups. * xx-yy GND A pulldown resistor to the ground power connection, with a value between xx and yy ohms. Again, the value may be specified by the designer. * "open" The signal may/should be left unconnected. * "as needed" The connection is determined principally by the system. It generally connects to the system controller logic, whether from Motorola or one of several third-parties who make such logic. Lastly, some of the signals have a "critical" designation: " May cause complete failure; board will likely not operate if the signal is not properly connected. This designator indicates signals which can cause system failure if not properly handled. If a new design is not running cycles (i.e., logic analyzer traces cannot be captured), the indicated signals should be checked first to narrow down possible problem sources. If these critical signals are not in the correct state, whether due to design or manufacturing error, the part may be improperly configured into a test mode and will not operate as desired. As an example, consider transfer start (TS). On an MPC107-based design, if a pullup is not present, TS may float low. Each device will wait for the (false) cycle to complete. A simple pullup insures that all devices sees an idle bus. Pullups or pulldowns may also be added to other signals without harm; it is not an error if a design has more pullups than might be minimally required. On several Motorola reference designs, pullups are added to some non-critical signals (GBL, TBST) in order to help logic analyzers present a more coherent picture of bus activity. 2 Motorola RISC Microprocessor Design Checklist MOTOROLA BVSEL BR " BG # # # # # # # # ARTRY AVDD # # APE # # # # # # # BMODE[0:1] " MPC603 # MPC750 AP[0:3] AP[1:4] AP[0] " " ABB " ABB/AMON0 AACK Critical " A[4:35] A[0:3] A[0:31] Signal MPC755 # # # # # # # # # MPC74X0 # # # # # # # # # MPC745X # # # # # # # # # # # # MPC824X Address parity may be pulled up if unused to minimize sleep-mode power consumption; otherwise, pullups may be omitted. 1K-5K OVDD open as needed 1K-10K OVDD 100-1K GND GND, HRESET, OVDD 100-1K OVDD as needed as needed filtered VDD 1K-5K OVDD If MPC7450 is operated in 32-bit address mode, AP0 is unused and should be pulled down to ground. 1K GND as needed Connect BVSEL to: MPC755/7400/7410 MPC745X GND 1.8V OVDD 1.8V OVDD HRESET 2.5V OVDD 2.5V OVDD OVDD 3.3V OVDD 2.5V OVDD or as described in the hardware specification. Pullup needed to insure initial startup. Selects bus mode, address-bus-driven mode, and processor ID. Pullup recommended for initial startup, or pulldown for permanently parked address bus. Must be connected to core voltage (VDD), not I/O (OVDD) through a 10 ohm resistor, with (2) 2.2uF ceramic caps on the AVDD pin. Trace lengths should be short, but do not need to be thick (~15mW typical). Avoid routing near noisy traces. Pullup needed to insure initial startup. Open-drain output; pullup only if needed. ABB is an output-only pin on the MPC74xx family. A pullup may be used where MPC75x/MPC74x0 footprint compatibility is needed. open Not needed for MPC10x-based systems. as needed 1K-5K OVDD Pullup needed to insure initial startup. 1K-5K OVDD Extended address (MSBs). When not used (as with 32-bit logic), connect to pulldowns. Address bus may be pulled up to minimize sleep-mode power consumption; otherwise, pullups may be omitted. 74x0 in address bus drive mode (see EMODE) does not need pullups in either case. Notes When used with 32-bit system bus logic (e.g. MPC107), connect CPU A(4:35) to device A(0:32). 100-1K GND if not used to corresponding address pins as needed as needed if used Connection Table 1. Processor Connections Critical DTI[0:2] DTI[0:3] DRTRY # # # DPE " # # DP[0:7] DRDY # # D[0:63] or DH[0:31] DL[0:31] # # # DBWO # " # # # DBDIS DBG # # DBB DBB/DMON0 # # # # # # # # CSE[0:1] CLK_OUT CKSTP_OUT CKSTP_IN MPC603 # MPC750 " " CI CHK Signal MPC755 # # # # # # # # # # # # MPC74X0 # # # # # # # # # # # MPC745X # # # # # # # # MPC824X open open 100-1K GND tie to HRESET 1-5K OVDD as needed open open open as needed 1K-5K OVDD as needed as needed 1K-5K OVDD open 100-1K GND 1K-5K OVDD as needed 1K-10K OVDD as needed to testpoint 1K-5K OVDD open CI may be pulled up to minimize sleep-mode power consumption; otherwise, pullup may be omitted. 1K-5K OVDD MPX bus mode signals only; pulldowns insure strict ordering when in 60X bus mode. Tie DRTRY to HRESET to set NO-DRTRY mode. NO-DRTRY mode improves performance by eliminating an idle bus clock cycle after data transfers. DRTRY must not be tied to ground to enable NO-DRTRY mode. MPX bus mode output only. Open-drain output; pullup only if needed. Pullups are not needed if parity is unused. Connect only to other CPUs, local-bus I/O and bridge devices. Memory is typically on an independent data bus (MDH/MDL). For 32-bit bus mode, if supported, DL(0:31) may be left open with no pullups required. Rarely used signal; must be pulled up. Can be shared with other pullups. Rarely used signal; must be pulled up. Can be shared with other pullups. Pullup recommended for initial startup, or pulldown for permanently parked data bus. DBB is an output-only pin on the MPC74xx family. A pullup may be used where MPC75x/MPC74x0 footprint compatibility is needed. Not needed for MPC10x-based systems. Output-only debug status; rarely used, connect to logic analyzer or float. CLK_OUT is useful only for debugging, it cannot be used as a clock source. CKSTP_OUT is an open-drain output. If CKSTP_IN is not pulled up, the CPU will halt immediately. The CKSTP_IN pullup may be shared with others if not used. Connect to HRESET to trigger a post-reset self-test. Usually not needed. Notes 1K-5K OVDD if not used 1K-5K OVDD as needed HRESET if used Connection Table 1. Processor Connections (Continued) MPC603 MPC750 " " # # # # # # # # L2CLK_OUTA L2CLK_OUTB L2DATA[0:63] L2DP[0:7] # # # # # SRAM A[18] # SRAM DP[0:7] SRAM D[0:63] SRAM CLK SRAM SE1 filtered VDD SRAM A[17] # SRAM A[16:0] open Use a strong pullup to keep noise from coupling to this pin. Do not share with other input-only pullups since asserting L1_TSTCLK during HRESET may be needed to correct errata on some devices. Pullup may be shared with others if INT not used. HRST_CTRL should be tied to HRST_CPU. A longer interval is acceptable, and may be needed for other devices such as the MPC10X. MPX bus mode output only. GBL should be strongly pulled up. Connect/pulldown to ground. Connect as follows: GND MPX bus mode with address bus drive mode. HRESET MPX bus mode OVDD 60X bus mode Notes open open open open open open open L2DP data bits can be rearranged to make routing better. L2 data bits can be rearranged to make routing better. Traces must be point-to-point and equal length, equal to other SRAM trace lengths. For differential mode route using a split-T configuration. Directly drives SRAM SE1 pin. SE2 is typically tied high and SE3 tied low. Must be connected to core voltage (VDD), not I/O (OVDD), through a 10 ohm resistor, with two 2.2uF ceramic caps on the AVDD pin. Trace lengths should be short and noise-free, but do not need to be thick (~15mW typical). L2ASPARE may be used for larger SRAM L2ADDR17 can be used for larger SRAM The L2ADDR bus is little-endian, connect to similarly named SRAM address pins. 100 - 1K GND Unlike other parts the MPC745X L1_TSTCLK must be connected to ground, or L3 will not work. 100 - 1K OVDD 1K-5K OVDD # # # as needed assert >= 255 bus clocks as needed as needed + 200-500 OVDD # # # # # 1K-5K OVDD if not used 0-100 GND as needed if used Connection Table 1. Processor Connections (Continued) # # # L2CE # # # # # # # L2AVDD L2ASPARE L2ADDR17 L2ADDR[16:0] L1_TSTCLK INT # HRST_CTRL # " # # # HRESET HRST_CPU " GBL # # # # Critical HIT # MPC755 # # MPC74X0 # MPC745X # EXT_QUAL EMODE Signal MPC824X L3DATA[0:63] L3_CNTL1 L3_CNTL0 L3_CLK[0:1] L3ADDR[17:0] L3VSEL L2ZZ L2WE L2_TSTCLK L2VSEL L2SYNC_IN L2SYNC_OUT Signal MPC603 # MPC750 # # # # # MPC755 # # # MPC74X0 # # # # # MPC745X # # # # # # # MPC824X Critical open open DDRSRAM: B1 PBSRAM: SE1 DDRSRAM: B2 PBSRAM: SGW open open DDRSRAM: CK PBSRAM: K SRAM D[0:63] open open open SRAM A[17:0] GND, HRESET, OVDD SRAM ZZ SRAM SGW to HRESET L3DATA[0:31] data bits may be rearranged to make routing more optimal, as may L3DATA[32:63]. Preserve the association between L3_ECHO_CLK[0:1] and L3DATA[0:31], and L3_ECHO_CLK[2:3] and L3DATA[32:63]. Function depends on SRAM type used. Function depends on SRAM type used. One clock per SRAM device. The L3ADDR bus is little-endian, connect to similarly named SRAM address pins. MPC745X GND 1.8V OVDD HRESET 2.5V OVDD OVDD 2.5V OVDD or as described in the hardware specification. Connect L3VSEL to: Directly drives SRAM ZZ pin. Directly drives SRAM SGW (global write) pin. SBW(AD) and SW are typically grounded. May also connect to pullup or pulldown. 100-1K OVDD Factory test pin only (has nothing to do with L2 interface). MPC755/7400/7410 GND 1.8V L2OVDD HRESET 2.5V L2OVDD OVDD 3.3V L2OVDD or as described in the hardware specification. Connect L2VSEL to: GND, HRESET, OVDD Notes Connect L2SYNC_IN to L2SYNC_OUT with a trace length equal to that of the L2CLK_OUTA. If L2 is not used, the feedback loop is still required. if not used feedback if used Connection Table 1. Processor Connections (Continued) Critical " " " " " MPC755 MPC603 # # # # # # # QREQ RSRV SCK # # QACK # # # # # # # For PBSRAM, connect L3_ECHO_CLK2 to L3_ECHO_CLK3, and match the trace length of L3_CLK1. Only pullups and pulldowns should be used. Jumpers to OVDD and GND, or digital logic, may be used only if debug mode is NEVER enabled. Pullups and pulldowns, jumpers to OVDD and GND, or digital logic may be used. PLL_EXT is essentially the MSB of a 5-bit PLL encoding, or PLL_CFG[-1]. An alternate numbering scheme is to relabel the set {PLL_EXT, PLL_CFG[0:3]} as {PLL_CFG[0:4]} in that order. as needed as needed 1K-3K OVDD as needed as needed 1K GND; or merge with HRESET logic open open open 100-1K GND open Pullups and pulldowns, jumpers to OVDD and GND, or digital logic may be used. as needed SCK is open drain. RSRV is a little-used output-only pin. Output typically used only with MPC10X and/or COP interface. COP emulators require QACK asserted to single-step. 603 devices require QACK asserted during HRESET to prevent reduced-bus mode. Application-dependant. Performance monitor signal can be connected to any signal to measure. Clock input traces should match those for other PCI devices. Connect to PCICLK if PCI clock tree is not used. Never connect anything to a NC pin unless it is defined on an upwardly compatible footprint (for upgrade purposes). For example, L2ADDR17 is NC on some BGA360 footprints; it is acceptable to connect this NC pad to an SRAM address line. Pullup may be shared with others if MCP not used. as needed 1K-5K OVDD open open as needed # # # # 1K-5K OVDD as needed # # # # # PMON_OUT # # # # to event # # # open DDRSRAM: CQ PBSRAM: loop For PBSRAM, connect L3_ECHO_CLK0 to L3_ECHO_CLK1, and match the trace length of L3_CLK0. L3DP[0:3] and L3DP[4:7] data bits can be rearranged to make routing more optimal. Notes 100-1K OVDD Use a strong pullup to keep noise from coupling to this pin. open DDRSRAM: CQ PBSRAM: loop # # # # # open if not used SRAM DP[0:7] if used Connection Table 1. Processor Connections (Continued) PMON_IN PLL_EXT PLL_CFG[0:4] PLL_CFG[0:3] PCI_SYNC_IN # # # MCP NC # # LSSD_MODE # MPC750 L3_ECHO_ CLK[2:3] # MPC74X0 # # MPC745X L3_ECHO_ CLK[0:1] L3DP[0:7] Signal MPC824X # # TBST TEST[0:5] TEST6 " " # TS " # # # # # # # # " TRST TMS TLBISYNC TEST0 " # # # TDO TEA # # TDI " # # TCK # # # TBEN TC[0:1] # # TA # " # # # SRESET SYSCLK Critical " # MPC603 # MPC750 SMI SHD[0:1] SDA Signal MPC755 # # # # # # # # # # # # # # MPC74X0 # # # # # # # # # # # # # # MPC745X # # # # # # # # # # # # # # # # # # # # # # # # # # MPC824X open 1K-5K OVDD 0-100 GND TMS has a weak (>=20K) internal pullup. TLBISYNC selects 32-bit bus mode on 60X devices; assert during HRESET if needed. TLBISYNC must be pulled up on the MPC750. TLBISYNC on the MPC7400 is not supported, so pull it up. Use a strong pulldown to keep noise from coupling to this pin. 100-1K OVDD Use a strong pullup to keep noise from coupling to this pin. 1K-5K OVDD Pullup needed for initial startup. actively drive with HRESET, logically While TRST has a weak (>=20K) internal pullup, do not leave it floating OR'ed with COP TRST, if any or pulled up. TRST must be asserted to initialize the boundary scan chain. If COP is not used, a pulldown is sufficient. If COP is used, use discrete logic to merge the COP TRST source and the target system HRESET. as needed assert during HRESET if needed Pullup needed for initial startup. TDO has a weak (>=20K) internal pullup to OVD. TDI has a weak (>=20K) internal pullup to OVD. TCK has a weak (>=20K) internal pullup to OVDD. TC outputs indicate data vs. instruction cycles for 603 only. Often used for logic analyzer headers (compare with WT for 75x/745x processors and TT[0] for 74x0 processors). Pullup needed for initial startup. May be pulled down to disable TBU/TBL/DEC registers (rarely useful). Pullup needed for initial startup. Clock input traces should match those for other PowerPC-bus devices. SRESET need not be asserted during power-up reset. Pullup may be shared with others if SMI not used. In 60X mode, SHD pins are ignored; pullup in all cases. SDA is open drain. Notes 100-1K OVDD Use a strong pullup to keep noise from coupling to this pin. open open open open 1K-5K OVDD 1K-5K OVDD 1K-5K OVDD as needed as needed as needed as needed 1K-5K OVDD as needed 1K-5K OVDD as needed as needed 1K-5K OVDD open if not used 1K-5K OVDD 1K-3K OVDD if used Connection Table 1. Processor Connections (Continued) MPC603 # # # # MPC750 # # # # MPC755 # # # # MPC74X0 # # # # # # MPC745X Critical " " CKE C/BE[3:0] AVDD2 AVDD AD[31:0] Signal MPC107 # # # # MPC8240 # # # # # # # # # # MPC8245 Critical VOLTDET definition varies by device; may be connected to GND, OVDD, or VDD (core) depending on device and mask revision. open 1K-5K OVDD as needed as needed WT may be pulled up to minimize sleep-mode power consumption; otherwise, pullup may be omitted. WT distinguishes instruction vs. data reads, for debugging on MPC7xxx series. TT bus may be pulled up to minimize sleep-mode power consumption; otherwise, pullups may be omitted. TT0 indicates instruction vs. data information for debugging on MPC74x0. as needed Notes TSIZ bus may be pulled up to minimize sleep-mode power consumption; otherwise, pullups may be omitted. if not used as needed if used Connection Table 1. Processor Connections (Continued) SDRAM CKE as needed 1K-5K LVDD filtered VDD open 1K-5K LVDD 1K-5K LVDD as needed 1K-5K LVDD filtered VDD if not used if used Connection Notes Standard SDRAM control signal. If low-power is not a concern, CKE can be wired to `1' at the SDRAM device and the CKE can be left open. Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). Connect to core voltage (VDD not OVDD) through a 10 ohm resistor, with (2) 2.2uF ceramic capacitors. Trace lengths should be short, but do not need to be thick (~15mW typical). Connect to core voltage (VDD not OVDD) through a 10 ohm resistor, with (2) 2.2uF ceramic capacitors. Trace lengths should be short, but do not need to be thick (~15mW typical). Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If the PCI port is not used, the bus must be pulled up or the PCI bus parked. Table 2. Memory/PCI/System Controller Connections Table 2 lists only the memory/PCI/system controller signals of the devices, not the 60X bus signals (if any). For example, the MPC107 does not have an entry for the TS signal, since TS should already have been properly connected as described in Table 1, when the (required) PowerPC CPU is connected. WT VOLTDET TT[0:4] TSIZ[0:2] Signal MPC824X Critical " GNT[4:0] FRAME FOE DQM[0:7] DEVSEL CTS1 CS[0:7] CPU_CLK[0:2] Signal MPC107 # # # # # # # MPC8240 # # # # # # # # # # # # # MPC8245 as needed as needed 1K-5K LVDD as needed GNT0: 1K-5K LVDD, others open 1K-5K LVDD open open 1K-5K LVDD as needed 1K-5K LVDD SDRAM DQ[0:7] 1K-5K OVDD RS232 receiver open open as needed SDRAM CS if not used if used Connection If the arbiter is disabled, GNT0 becomes "REQ" and should be pulled up on a PCI motherboard or private PCI bus. Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). FOE is not needed if non-writable devices (PROM) is used for the boot code (or if the boot code is on PCI). Each DQM must be associated with corresponding MDH/MDL byte lanes: DQM0$-%MDH[0:7] DQM1$-%MDH[8:15] DQM2$-%MDH[16:23] DQM3$-%MDH[24:31] DQM4$-%MDL[0:7] DQM5$-%MDH[8:15] DQM6$-%MDH[16:23] DQM7$-%MDH[24:31] If an 8-bit SDRAM device is attached to MDH[0:7], then DQM0 should be connected to the DQM pin, and so forth. Any parity SDRAM devices can use any DQM[0:7] signal (it will have to share). Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). RS232 signal: Clear to send. Standard SDRAM control signal. Each CS[0:7] pin must control one 64-bit (or 32-bit) array of memory. Each SODIMM or DIMM will have one or two arrays of memory on it with one, two or four usable chip-selects. Standard wiring is: SODIMM (64 only): One CS[0:7] to CS0, second CS[0:7] to CS1. DIMM (as 64-bits): One CS[0:7] to CS0 and CS2, second CS[0:7] to CS1 and CS3. DIMM (as 32-bits): One CS[0:7] to CS0, second CS[0:7] to CS2, third CS[0:7] to CS1, fourth CS[0:7] to CS3. CPU_CLK signals must have trace length added to match any delay on the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback path. Refer to the MPC107 Design Guide (AN1849) for details. Notes Table 2. Memory/PCI/System Controller Connections (Continued) Critical " " MPC107 PCI_CLK[0:4] PAR PAR(0:7) OSC_IN # # # # # # # # # # # # # # MIV # # MDH[0:31] MDL[0:31] # # # # # MAA[0:2] # # # # # # # # LOCK LAVDD IRQ(0:4) # as needed as needed 1K-5K LVDD open 1K-5K LVDD open 1K-5K OVDD PCI clock source as needed open open 1K-5K LVDD open or AVDD 1K-5K LVDD to logic analyzer as needed to logic analyzer as needed 1K-5K LVDD filtered VDD as needed 1K-5K LVDD 1K-5K LVDD open GND one of AD[31:0] as needed 1K-5K LVDD # # IRDY # if not used if used Connection PCI clocks to target PCI devices should have equal lengths. If not used, disable clock drivers in the CDCR register. PAR should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). All flash, SDRAM/DRAM, and I/O devices connect to PAR[0:7], not to the DH/DL processor data bus (if visible). For Flash and I/O, PAR[0:7] is used for addressing, not flash or I/O parity. OSC_IN recommended only for embedded host systems, not for PCI agent cards due to clock skew. MIV assists logic analyzers in recovering addressing information. All flash, SDRAM/DRAM, and PortX I/O devices connect to MDH/MDL, not to the DH/DL processor data bus (if any). MAA assists logic analyzers in recovering addressing information Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). Internally connected to AVDD (pin C17). Connect to core voltage (VDD not OVDD) through a 10 ohm resistor, with (2) 2.2uF ceramic capacitors. Trace lengths should be short, but do not need to be thick (~15mW typical). INT[0:4] should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). In agent mode, INTA typically connects to a central interrupt controller. In host mode, INTA may be used to assert interrupts to other devices, such as a second processor. IDSEL should be connected to GND for host systems and to one address line of AD[31:0] for agent systems. If the PCI port is not used, it should be grounded. Notes Table 2. Memory/PCI/System Controller Connections (Continued) as needed # MPC8240 INTA IDSEL Signal MPC8245 Critical " MPC107 # RCS[2:3] # # # # # # SDBA0 SDBA1 SDCAS # # # SDA SDMA12/ SDBA1 # # SCK # # # # # open open SDRAM A12 and/or SDBA1 open open open open open SDRAM CKE 1K-3K OVDD 1K-3K OVDD RS232 driver # RTS1 open to LF oscillator # RFC (RTC) # 1K-5K LVDD REQ[4:0] as needed 1K-10K LVDD open # as needed open to boot ROM or 100-1K pulldown open # # open 1K-5K LVDD open if not used to logic analyzer as needed 1K-5K LVDD PCI_SYNC_IN 3.3V PCICLK, local clock source or PCI_SYNC_OUT if used Connection Standard SDRAM address signal. Connects to SDBA1 or A12, depending on SDRAM size. For modules, connect to both A12 and SDBA1 pins. Standard SDRAM control signal. Standard SDRAM address signal. Standard SDRAM address signal. SDA is open drain. SCK is open drain. RS232 Request-To-Send output Refresh clock is independent of all other clocks. If the arbiter is enabled, REQ[4:0] should be pulled up on a PCI motherboard or private PCI bus. If PCI is not used, ground REQ0 (which becomes GNT) to park the PCI bus and maintain valid PCI state. Local ROM or PortX chip select. Local ROM or PortX chip select. RCS0 is used for reset startup code. A pulldown on RCS0 selects PCI boot mode. PMAA assists logic analyzers in recovering addressing information Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). PCI feedback path should have a trace length to PCI_SYNC_IN of equal lengths to other PCI device clocks. PCI_SYNC_IN is the primary clock input for the chip, (OSC_IN is just a clock buffer). If the buffer is not used, the PCI clock "CLK" connects to PCI_SYNC_IN with the same consideration any other PCI clock gets: max of 2.0 ns skew on a motherboard, max 2.5" trace length on a plug-in card. If PCI_SYNC_IN is connected to a PCI backplane, the clock source must be 3.3V or restricted (pin is not 5V PCI compatible). Notes Table 2. Memory/PCI/System Controller Connections (Continued) as needed # # # RCS1 # # # # # # # # # # # # # MPC8240 # RCS0 PMAA[0:2] PERR PCI_SYNC_ OUT PCI_SYNC_IN Signal MPC8245 Critical " " " " # SDMA[11:0] WE TRIG_OUT TRIG_IN TRDY SUSPEND # # # # # # # # # # # # # open open TRIG_IN or CKSTP_IN as needed 1K-5K OVDD 1K-5K LVDD TRIG_OUT as needed 1K-5K LVDD 1K-5K OVDD 1K-5K LVDD as needed 1K-5K LVDD STOP # open RS232 driver # SOUT1 open RS232 receiver # SIN1 # 1K-5K LVDD # as needed 1K-5K LVDD SERR # # SDRAM_ SYNC_IN open # # SDRAS # # SDRAM_ SYNC_OUT open SDRAM CLK # open SDRAM A14 # open open SDRAM A[13:12] SDRAM A[11:0] if not used # # if used Connection WE is not needed if non-writable devices (PROM) is used for the boot code (or if the boot code is on PCI). TRIG_OUT is usually connected to TRIG_IN, CKSTP_IN, or a logic analyzer. TRIG_IN is usually connected to TRIG_OUT, or a logic analyzer. Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). SUSPEND requires a pullup. Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). RS232 Transmitted data. RS232 Received data. Should be pulled up on a PCI motherboard or private PCI bus, but not on a plug-in peripheral card. If PCI is not used, pull up (or park the PCI bus). Standard SDRAM control signal. SDRAM feedback path should have a trace length at least equal to that of SDRAM_CLK to SDRAM clock pin path lengths. Additional delay can be added to increase hold time for SDRAM modules (usually required). Connects to SDRAM_SYNC_OUT usually, except when zero-delay buffers are inserted between feedback path. Standard SDRAM clock signal. Clocks to the SDRAM should have equal-length traces, and generally match the trace length of the SDRAM. Standard SDRAM address signal. Standard SDRAM address signal. Standard SDRAM address signal. Notes Table 2. Memory/PCI/System Controller Connections (Continued) SDRAM CKE # # # # SDRAM_ SYNC_OUT SDRAM_ SYNC_IN SDRAM_CLK # [0:3] SDMA14 # # MPC107 SDMA[13:12] # MPC8240 Signal MPC8245 L2 Cache Pipelined/Late-Write SRAM Connections 1.3 L2 Cache Pipelined/Late-Write SRAM Connections The MPC750, MPC755 and MPC74X0 processors support a "backside" L2 cache on a private cache bus. For some devices this bus can act as a private memory area. The L2 interface uses standard synchronous pipelined-burst or late-write SRAM devices in a non-pipelined manner. The connections are shown in Table 3. Table 3. L2 Cache SRAM Connections SRAM Signal A[16:0] Connection Notes L2ADDR[16:0] Connect buses; order is not important since burst mode is not used. A17 L2ADDR17 If present and/or needed. For forward compatibility, tie to a weak (1K-5K pulldown) since LA17 = CE3 on some SRAM devices. A18 L2ASPARE If present and/or needed. ADV L2OVDD Deasserted since burst mode not used. ADSC GND Asserted to continually accept addresses. ADSP L2OVDD Deasserted since burst mode not used. L2DATA[0:63] Connect buses; order is not important since byte access modes are not used. DP bits may be intermixed with DQ bits if and only if parity-capable SRAMs are always used; otherwise, connect DP only to DP. L2DP[0:7] Connect buses; order is not important since byte access modes are not used. DP bits may be intermixed with DQ bits if and only if parity-capable SRAMs are always used; otherwise, connect DP only to DP. G OE GND Since the L2 is chip-select-controlled, it is normally in output mode unless being written to. OE may tied low. CK K L2CLK_OUTA L2CLK_OUTB For single-ended clocks, tie one clock to each of two SRAMs without sharing. Keep trace lengths matching other L2 traces. For differential clocks, tie "A" to the active high clocks and "B" to the active low clocks. Route the clocks in a "Y" manner so the stubs have the same, minimal, length. GND or VCC GND is for PowerPC bursts order; however, burst mode is not used so may be tied high or low. GND or L2OVDD Byte write modes are not used. L2WE Write cause global writes. SW L2OVDD Byte write modes are not used. SE1 L2CE Connect SRAM chip select. SE2 L2OVDD Second chip-select not used. SE3 GND Third chip-select not used. L2ZZ or GND Optional; not all SRAMs have ZZ. DQ[0:63] DP[0:7] LBO SB[A:D] SGW ZZ In addition, the L2SYNC_OUT pin should be connected to the L2SYNC_IN pin using a trace length equal to the ones used on the L2CLK_OUT[A:B] traces. 14 Motorola RISC Microprocessor Design Checklist MOTOROLA L3 Cache DDR SRAM Connections 1.4 L3 Cache DDR SRAM Connections The MPC745x processors support a "backside" L3 cache on a private cache bus. The L3 interface supports double-data rate SRAM (DDRSRAM) devices of the MSUG2 and PCDDR types. The connections are shown in Table 4. Table 4. L3 Cache DDRSRAM Connections SRAM Signal A[17:0] Connection L3ADDR[17:0] Connect buses; order is not important since burst mode is not used. B1 L3CNTL0 Signal operates as load address strobe. B2 L3CNTL1 Signal operates as read/write enable. B3 GND Signal operates as single/double rate selection (double-rate selected). CK K L3_CLK0 or L3_CLK1 Connect one clock to each of the SRAMs without sharing. Keep trace lengths matching other L3_ECHO_CLK feedback traces. CK K GVDD/2 Connect to a resistor divider or power supply set to the L3 cache power supply. Two 250 resistors are sufficient current. CQ1 L3ECHO_CLK0 or L3ECHO_CLK2 L3ECHO_CLK0 is paired with DQ[0:15] and L3DP[0:1]. L3ECHO_CLK2 is paired with DQ[32:47] and L3DP[4:5]. CQ2 L3ECHO_CLK1 or L3ECHO_CLK3 L3ECHO_CLK1 is paired with DQ[16:31] and L3DP[2:3]. L3ECHO_CLK3 is paired with DQ[48:63] and L3DP[6:7]. CQ1 CQ2 No connection. NC DQ[0:15] DQP[0:1] L3DATA[0:15] L3DP[0:1] DQ[16:31] DQP[2:3] L3DATA[16:31] L3DP[2:3] DQ[32:47] DQP[4:5] L3DATA[32:47] L3DP[4:5] DQ[48:63] DQP[6:7] L3DATA[48:63] L3DP[6:7] Connect buses; order is not important since byte access modes are not used. DQ bits may be reordered. DQP bits may be reordered. DQ and DQP bits may be intermixed within this pairing only, if and only if parity-capable SRAMs are always used, otherwise connect only DQ to DQ and DQP to DQP. Connect buses; order is not important since byte access modes are not used. DQ bits may be reordered. DQP bits may be reordered. DQ and DQP bits may be intermixed within this pairing only, if and only if parity-capable SRAMs are always used, otherwise connect only DQ to DQ and DQP to DQP. G OE GND The L3 is chip-select-controlled, so it is normally in output mode unless being written to. G may tied low. LBO GND Selects linear burst order. GVDD/2 Connect to a resistor divider or power supply set to the L3 cache power supply. Two 250 resistors are sufficient current. ZQ 1.5 Notes L3 Cache Pipelined/Late-Write SRAM Connections The MPC745x processors also support pipelined burst SRAM (PBSRAM) or late-write SRAM (LWSRAM) devices in a non-pipelined manner. Refer to the processor connection table for non-SRAM-specific connections (such as L3_ECHO_CLK). The PB/LWSRAM connections are shown in Table 5. MOTOROLA Motorola RISC Microprocessor Design Checklist 15 Power Table 5. L3 Cache PBSRAM/LWSRAM Connections SRAM Signal A[17:0] Connection L3ADDR[17:0] Connect buses; order is not important since burst mode is not used. GVDD Deasserted since burst mode not used. ADSC GND Asserted to continually accept addresses. ADSP GVDD Deasserted since burst mode not used. CK K L3_CLK0 or L3_CLK1 Connect one clock to each of the SRAMs without sharing. Keep trace lengths matching other L3_ECHO_CLK feedback traces. CK K GVDD/2 Connect to a resistor divider or power supply set to the L3 cache power supply. Two 250 resistors are sufficient current. ADV DQ[0:31] DQP[0:3] L3DATA[0:31] L3DP[0:3] DQ[32:63] DQP[4:7] L3DATA[32:63] L3DP[4:7] Connect buses; order is not important since byte access modes are not used. DQ bits may be reordered. DQP bits may be reordered. DQ and DQP bits may be intermixed within this pairing only, if and only if parity-capable SRAMs are always used, otherwise connect only DQ to DQ and DQP to DQP. G OE GND The L3 is chip-select-controlled, so it is normally in output mode unless being written to. G may tied low. LBO GND Selects linear burst order. GVDD Byte write modes are not used. SE1 L3CNTL0 Signal operates as SRAM chip select. SE2 GVDD Second active-high chip-select not used. SE3 GND Third active-low chip-select not used. SGW L3CNTL1 Signal operates as global write enable. SW GVDD Byte write modes are not used. ZZ GND Optional; not all SRAMs have ZZ. SBW[A:D] 1.6 Notes Power Motorola processor specifications state restrictions on the amount of time any power pin can be at a non-standard voltage in relation to another power pin. Typically these event occur during power-up and power-down. When the restrictions are not met, if the amount of time exceeds approximately 50 mS, damage to the part may occur. If the power supply can sequence all the I/O voltage (OVDD), L2 I/O voltage (L2OVDD), and core voltage (VDD) within the specification limits, or stabilize within 50 mS, then no further design work is needed. Otherwise, power supply sequencing assistance is needed. The easiest way is to apply a diode voltage sourcing network as shown in the hardware specifications, but other means such as MOSFETs configured as a linear regulator would be suitable as well. The diode solution supplies just under the targeted operating voltage, but within the differential allowances in the hardware specification. Each device has slightly different allowances, so refer to the hardware specifications for particular examples of diode networks for each device. Note that the diode network is needed for each non-compliant power supply. However, it is not needed between all power supplies, only between those which are too slow. Thus, if OVDD (typically 3.3V) is stable first and last, the others can be derived from it alone. 16 Motorola RISC Microprocessor Design Checklist MOTOROLA Clocks 1.7 Clocks All clocks should be carefully routed to be of equal lengths within similar domains (processor system bus, cache bus, memory bus, or PCI bus). Devices with integrated clock drivers make this relatively easy; see the corresponding hardware specifications, or the MPC107 Design Guide for further details. 1.8 References The reference materials shown in Table may be useful to the designer. To locate the documents, go to http://www.motorola.com/ and search for the document title. Table 6. Reference Material Description 1.9 Document MPC107 Design Guide AN1849/D MPC603eTM Hardware Specifications (PID6) MPC603EEC/D R2 MPC603e Hardware Specifications (PID7t) MPC603E7TEC/D R3 MPC750A Hardware Specification MPC750EC/D MPC7400 Hardware Specifications MPC7400EC/D MPC7410 Hardware Specifications MPC7410EC/D MPC7450 Hardware Specification MPC7450EC/D MPC107 Hardware Specification MPC107EC/D MPC8240 Integrated Processor Hardware Specifications MPC8240EC/D MPC8245 Integrated Processor Hardware Specifications MPC8240EC/D Revision History Table 7 provides a revision history of this document. Table 7. Document History Revision Number MOTOROLA Changes Rev 1.1 Added MPC7450 Support. Rev 1.2 Corrected AP0 data; changed OVDD pullup recommendations, Motorola processor references. Motorola RISC Microprocessor Design Checklist 17 Revision History 18 Motorola RISC Microprocessor Design Checklist MOTOROLA Revision History MOTOROLA Motorola RISC Microprocessor Design Checklist 19 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Information in this document is provided solely to enable system and software implementers to use Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. 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