September 1983
Revised February 1999
MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
© 1999 Fairchild Semicond uctor Corpor ation DS005341.prf www.f airchildsemi.com
MM74HC540 • MM74HC541
Inverting Octa l 3-STATE Buffer • Octal 3-STATE Buffer
General Descript ion
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
cir c ui try, i.e., high no i se i m m un i ty, and lo w power co nsu mp -
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate ope r a t es a s a t w o- i n put N OR s u c h th at i f e i t he r G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC 541 offers a pinout having in puts and outpu ts on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
■Typical propagation delay: 12 ns
■3-STATE outputs for connection to system buses
■Wide power supply range: 2–6V
■Low quiescent current: 80 µA maximum (74HC Series)
■Output current: 6 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appen ding the suffix lett er “X” to the orde ring code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540 Top View
MM74HC541
Order Number Package Number Package Description
MM74HC540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HC540 • MM74HC541
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those va lues beyond which dam-
age to the device may occur.
Note 2: Unless otherwise spec if ied all voltages are refere nc ed to ground.
Note 3: Power Dissipati on temperat ure derat ing — plas tic “N” p ackage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V ±10% t he worst case ou tput voltages (V OH, an d VOL) occur for HC at 4.5V. Thus the 4 .5V values shou ld be used wh en
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3. 85V.) T he worst ca se leakage cur-
rent (IIN, ICC, and IOZ) occur for CMO S at the highe r voltage and so the 6.0 V valu es s hould be used.
Supply Voltage (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (ICD)±20 mA
DC Output Current, per pin (IOUT)±35 mA
DC VCC or GND Current,
per pin (ICC)±70 mA
Storage Temperature Range (TSTG)−65°C to +150°C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operating Temperature Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf) VCC
= 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
IOZ Maximum 3-STATE VIN = VIH or VIL, G = VIH 6.0V ±0.5 ±5±10 µA
Output Leakage VOUT = VCC or GND
Current
ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA
Supply Current IOUT = 0 µA
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MM74HC540 • MM74HC541
AC Electrical Characteri s tics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
AC Electrical Characteri s tics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 5: CPD determ ines the no load dy namic power con s um ption, PD = CPD VCC2f + ICC VCC, and the no load dynam ic cu rrent consumpt ion,
IS = CPD VCC f + ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL, tPLH Maximum Propagation CL = 45 pF 12 18 ns
Delay (540)
tPHL, tPLH Maximum Propagation CL = 45 pF 14 20 ns
Delay (541)
tPZH, tPZL Maximum Output Enable RL = 1 kΩ17 28 ns
Time CL = 45 pF
tPHZ, tPLZ Maximum Output Disable RL = 1 kΩ15 25 ns
Time CL = 5 pF
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 55 100 126 149 ns
Delay (540) CL = 150 pF 2.0V 83 150 190 224 ns
CL = 50 pF 4.5V 12 20 25 30 ns
CL = 150 pF 4.5V 22 30 38 45 ns
CL = 50 pF 6.0V 11 17 21 25 ns
CL = 150 pF 6.0V 18 26 32 38 ns
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 58 115 145 171 ns
Delay (541) CL = 150 pF 2.0V 83 165 208 246 ns
CL = 50 pF 4.5V 14 23 29 34 ns
CL = 150 pF 4.5V 17 33 42 49 ns
CL = 50 pF 6.0V 11 20 25 29 ns
CL = 150 pF 6.0V 14 28 35 42 ns
tPZH, tPZL Maximum Output Enable RL = 1 kΩ
Time CL = 50 pF 2.0V 75 150 189 224 ns
CL = 150 pF 2.0V 100 200 252 298 ns
CL = 50 pF 4.5V 15 30 38 45 ns
CL = 150 pF 4.5V 30 40 50 60 ns
CL = 50 pF 6.0V 13 26 32 38 ns
CL = 150 pF 6.0V 17 34 43 51 ns
tPHZ, tPLZ Maximum Output Disable RL = 1 k Ω2.0V 75 150 189 224 ns
Time CL = 50 pF 4.5V 15 30 38 45 ns
6.0V 13 26 32 38 ns
tTHL, tTLH Maximum Output Rise CL = 50 pF 2.0V 25 60 75 90 ns
and Fall Time 4.5V 7 12 15 18 ns
6.0V 6 10 13 15 ns
CPD Power Dissipation G = VIH 10 pF
Capacitance (Note 5) G = VIL 50 pF
CIN Maximum Input 5 10 10 10 pF
Capacitance
COUT Maximum Output Capacit an ce 15 20 20 20 pF
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MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and F airchild reserves the right at any tim e without notice to change said circuitry and specifications.
MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A criti cal comp onent in any comp onent of a l ife suppor t
device or system whose failure to perform can be rea-
sonably expected to cau se the failure of the li fe support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
