HM6G168H-45, HMG6G168H-55, HM6168H-70, HMG6G16G8SHP-45, HM6G16GSHP-55, HM6168HP-70 4096-word x 4-bit High Speed Static CMOS RAM MFEATURES @ High Speed: Fast Access Time 45/55/70 ns (max.) @ Single +5V Supply and High Density 20 Pin Package @ Low Power Standby and Low Power Operation; 100LW typ. (Standby), 200mW typ. (Operation) Completely Static Memory No Clock or Timing Strobe Required @ Equal Access and Cycle Times Directly TTL Compatible All Inputs and Outputs HM6168H-45/55/70 MBFUNCTIONAL BLOCK DIAGRAM {DG-20) Ao A HM6168HP-45/55/70 Az Row Memory Array As Decoder 128 x 128 Ac As Ae 1/01 Column 1/0 1/02 Input Column Decoder Data 1/03 Control (DP-20i 1/04 Ar As As Aro An PIN ARRANGEMENT yo WE Te] 19] As E on HMABSOLUTE MAXIMUM RATINGS aT [7 a Item Symbol Rating Unit a fs] Lie] A= Voltage on Any Pin Relative to GND | Vin 3.5* to +7.0 Vv [| fas] vex Power Dissipation Pr 1.0 Ww av [7] 14] WO Operating Temperature Tope 0 to +70 Ol an [ie] 5 Storage Temperature (Ceramic) Toe 65 to +150 Cc cs [3 12] 1/0 Storage Temperature (Plastic) Tae 55 to +125 c cn [10 Dk Temperature under Bias Tries 10 to +85 c (Top View) * Pulse Width 20ns, DC=0.5V 128 @ HITACHIHM6168H-45, HM6168H-55, HM6168H-70, HM6168HP-45, HM6168HP-55, HM6168HP-70 TRUTH TABLE cs WE Mode Voc Current 1/O Pin Reference Cycle H x Not selected Ign, I5p1 High Z L #H Read lec Dout Read Cycle 1, 2 L L Write Tec Din Write Cycle 1, 2 = RECOMMENDED DC OPERATING CONDITIONS (72=0 to + 70C) Item Symbol min typ max Unit Suoply Volta Vee 4.5 5.0 5.5 Vv U: 3. Pel ee GND 0 0 0 Vv V. 2.2 - 6.0 v Input Voltage TH Vin ~0.5* - 0.8 Vv * _3.0V (Pulse width 20ns) = DC AND OPERATING CHARACTERISTICS (Vcec=5V +10%, GND=0V, Ta =0 to + 70C) Item Symbol Test Conditions Imin|typ |max | Unit Imput Leakage Current Yor) ) Vec=5.5V, Vin= GND to Voc }]- 12.0) vA Output Leakage Current \In9 | | CS=Vy3z, Viyo=GND to Voc ~|- 120] yA Operating Power Supply Current lec CS=V yz, [7;9=0mMA 140 | 90 | mA Standby Power Supply Current Isp CS=Vipy {15 | 25 | mA Standby Power Supply Current(1) Tsp1 | CS=Veog0.2V, Vin S0.2V or Vine Veg0.2V, |0.02 | 2.0 | mA Output Low Voltage Vor |Jor=8mA -|- |04) V Output High Voltage Vou | lonw=-4mA 2.4] - v Note: Typical limits are at Veg=5.0V, Ta=25C and specified loading. CAPACITANCE (Ta=25C, f= 1MHz) Item Symbol | Test Conditions | min | max | Unit Input Capacitance Cy Vin=0V - 6 pF Input/Output Capacitance | Cyo Vio =0V - 8 pF AC CHARACTERISTICS (Vcc=5V 10%, Ta=0 to + 70C, unless otherwise noted.) @ AC TEST CONDITION @ input pulse levels: GND to 3.0V Input rise and fall times: 5ns Input and Output timing reference levels: 1.5V Output load: See Figure 3v Sv J 4809 J 4800 [ 2852 _ Dour Dout == 30pF* 2559 pe Sere TIT 71 Output Load (A) Output Load (B) * Including scope and jig. (for ty, trz, twz, tow) @ HITACHI 129HM6168H-45, HM6168H-55, HM6168H-70, HM6168HP-45, HM6168HP-55, HM6168HP-70 @ READ CYCLE HM6168H/P-45 | HM6168H/P-55 HM6168H/P-70 Item Symbol ~ 7 - Unit min max min max min max Read Cycle Time tre 45 - 55 _ 70 - ns Address Access Time tAA - 45 - 35 - 70 ns Chip Select Access Time tacs - 45 - 55 - 1) ns Output Hold from Address Change tou 5 - 5 ~ 5 - ns Chip Selection to Output in Low Z* trz 20 - 20 - 20 - ns Chip Deselection to Output in High Z* tyz 0 20 0 20 0 20 ns Chip Selection to Power Up Time tpu 0 - 0 - 0 - ns Chip Deselection to Power Down Time tpp - 30 - 30 - 30 ns * Transition is measured +500mV for high impedance voltage with Load (B). This parameter is sampled and not 100% tested. @ TIMING WAVEFORM OF READ CYCLE NO. 14) (2) tac sts *K X we OO Ca TIMING WAVEFORM OF READ CYCLE NO. 2): @) Dout Data Valid Vcc supply current Notes) 1. WE is High for Read Cycle. _. 2. Device is continuously selected, CS=Vy,. __ 3. Address Valid prior to or coincident with CS transition Low. 130 @ HITACHIHM6168H-45, HM6168H-55, HM6168H-70, HM6168HP-45, HM6168HP-55, HM6168HP-70 @ WRITE CYCLE HM6 168H/P-45 HM6168H/P-55 HM6168H/P-70 Item Symbol 7 . Unit min max min max min max Write Cycle Time twe 45 = 55 70 = ns Chip Selection to End of Write tcw 40 - 50 ~ 60 - ns Address Valid to End of Write taw 40 ~ 30 - 60 - ns Address Setup Time tas 0 - 0 - 0 ~_ ns Write Pulse Width twp 35 - 45 ~ 55 - ns Write Recovery Time twr 0 - 0 - 0 - ns Data Valid to End of Write tow 20 _ 25 - 30 - ns Data Hold Time toy 0 - 0 = 0 = ns Write Enabled to Output in High Z* twz 0 15 0 20 0 25 ns Output Active from End of Write* tow 0 - 0 - 0 - ns * Thansition is measured +500mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested, TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Controlled) Address Bout TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Controlled) Notes) an wn > Whe we Address High Impedance Dout A write occurs during the overlap of a low cS and a low WE, (twp) . twr is measured from the earlier of CS or WE going high to the end of write cycle. - During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. . If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffer buffers remain in a high impedance state, . If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. - Dout is the same phase of Write data of this write cycle. @ HITACHI 131