Publication Number S71GL-N_00 Revision 06 Issue Date January 13, 2010
S71GL-N Based MCPs
S71GL-N Based MCPs Cover Sheet
Stacked Multi-Chip Product (MCP)
Flash Memory and RAM
64/32 Megabit (4/2 M x 16-bit) CMOS 3.0 Volt-Only
Page Mode Flash Memory and
32/16/8/4 Megabit (2M/1M/512k/256k x 16-bit) Pseudo Static RAM
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
2 S71GL-N Based MCPs S71GL-N_00_06 January 13, 2010
Data Sheet (Advance Information)
Notice On Data Sheet Designations
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product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
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Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
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“This document states the current technical specifications regarding the Spansion product(s)
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Combination
Some data sheets contain a combination of products with different designations (Advance Information,
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When a product has been in production for a period of time such that no changes or only nominal changes
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“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
Publication Number S71GL-N_00 Revision 06 Issue Date January 13, 2010
Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt
High performance
– 90 ns access time (90 ns Flash, 70 ns pSRAM/SRAM)
– 25 ns page read times
Packages
– 7 x 9 x 1.2 mm 56 ball FBGA
Operating Temperature
– –25°C to +85°C
General Description
The S71GL-N product series consists of S29GL-N Flash memory with pSRAM combinations defined as:
For detailed specifications, please refer to the individual data sheets.
S71GL-N Based MCPs
Stacked Multi-Chip Product (MCP)
Flash Memory and RAM
64/32 Megabit (4/2 M x 16-bit) CMOS 3.0 Volt-Only
Page Mode Flash Memory and
32/16/8/4 Megabit (2M/1M/512k/256k x 16-bit) Pseudo Static RAM
Data Sheet (Advance Information)
Flash Memory Density
32 Mb 64 Mb
pSRAM Density
4 Mb S71GL032N40
8 Mb S71GL032N80
16 Mb S71GL032NA0 S71GL064NA0
32 Mb S71GL064NB0
Document Publication Identification Number (PID)
S29GL-N S29GL-N_00
4 Mb pSRAM Type 9 pSRAM_33
8 Mb pSRAM Type 9 pSRAM_34
16 Mb pSRAM Type 9/10 pSRAM_40
32 Mb pSRAM Type 8 pSRAM_31
32 Mb pSRAM Type 9 SPH032D970R1R
4 S71GL-N Based MCPs S71GL-N_00_06 January 13, 2010
Data Sheet (Advance Information)
1. Product Selector Guide
Note
Please see the valid combinations table for the model# description.
Device-Model# (Note) Flash Access time
(ns)
(p)SRAM
density
(p)SRAM Access time
(ns) (p)SRAM type Package
S71GL032N40-0K
90
4 Mb
70
pSRAM 9
TLC056
S71GL032N40-0P
S71GL032N80-0K 8 Mb
S71GL032N80-0P
S71GL032NA0-0B
16 Mb
pSRAM 10
S71GL032NA0-0F pSRAM 10
S71GL032NA0-0K pSRAM 9
S71GL032NA0-0P
S71GL064NA0-0B pSRAM 10
TSC056
S71GL064NA0-0F pSRAM 10
S71GL064NB0-0K
32 Mb
pSRAM 9
S71GL064NB0-0P
S71GL064NB0-0U pSRAM 8
S71GL064NB0-0Z
January 13, 2010 S71GL-N_00_06 S71GL-N Based MCPs 5
Data Sheet (Advance Information)
2. MCP Block Diagram
VSS
RESET#
Flash
IO15-IO0
VCCf
DQ15 to DQ0
RY/BY#
WP#/ACC
VCC
VCC
CE1#f
Flash-only Address
Shared Address
OE#
WE#
VCCS
VCC
CE1#s
UB#
LB#
CE#
UB#
LB#
pSRAM
CE2s
6 S71GL-N Based MCPs S71GL-N_00_06 January 13, 2010
Data Sheet (Advance Information)
3. Connection Diagram
Note
May be shared depending on density.
3.1 Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
MCP Flash-only Addresses Shared Addresses
S71GL032NA0 A20 A19-A0
S71GL032N80 A20-A19 A18-A0
S71GL032N40 A20-A18 A17-A0
S71GL064NB0 A21 A20-A0
S71GL064NA0 A21-A20 A19-A0
C3
UB#
D3
A18
E3
A17
F3
DQ1
G3
DQ9
H3
DQ10
DQ2
B3
LB#
C5
CE2s
A20
G5
DQ4
H5
VCCs
RFU
B5
WE#
C6
A19
D6
A9
E6
A10
F6
DQ6
G6
DQ13
H6
DQ12
DQ5
B6
A8
C4
RST#f
RY/BY#
G4
DQ3
H4
VCCf
DQ11
B4
WP/ACC
C7
A12
D7
A13
E7
A14
F7
RFU
G7
DQ15
H7
DQ7
DQ14
B7
A11
C8
A15
D8
A21
E8
RFU
F8
A16
G8
RFU
VSS
C2
A6
D2
A5
E2
A4
F2
VSS
G2
OE#
H2
DQ0CE1#s
DQ8
B2
A7
C1
A3
D1
A2
E1
A1
F1
A0
G1
CE1#f
F5F4
B1 B8
A3 A5 A6A4 A7A2
RAM only
Shared
(Note 1)
Flash only
Legend
Reserved for
Future Use
56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
January 13, 2010 S71GL-N_00_06 S71GL-N Based MCPs 7
Data Sheet (Advance Information)
4. Pin Description
Pin Description
A21–A0 22 Address Inputs (Common and Flash only) (A20-A0 for the S71GL032N)
DQ15–DQ0 16 Data Inputs/Outputs (Common)
CE1#f Chip Enable (Flash)
CE1#s Chip Enable 1 (pSRAM/SRAM)
CE2s Chip Enable 2 (pSRAM/SRAM)
OE# Output Enable (Common)
WE# Write Enable (Common)
RY/BY# Ready/Busy Output (Flash 1)
UB# Upper Byte Control (pSRAM/SRAM)
LB# Lower Byte Control (pSRAM/SRAM)
RESET# Hardware Reset Pin, Active Low (Flash)
WP#/ACC Hardware Write Protect/Acceleration Pin (Flash)
VCCfFlash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage
supply tolerances)
VCCS pSRAM/SRAM Power Supply
VSS Device Ground (Common)
NC
Not Connected. No device internal signal is connected to the package connector nor is there any
future plan to use the connector for a signal. The connection may safely be used for routing space for
a signal on a Printed Circuit Board (PCB).
8 S71GL-N Based MCPs S71GL-N_00_06 January 13, 2010
Data Sheet (Advance Information)
5. Ordering Information
The order number is formed by a valid combinations of the following:
Note
1. Type 0 is standard. Specify other options as required.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
S71GL 064 N A0 BF W 0 Z 0
PACKING TYPE
0=Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER
See the Valid Combinations table.
PACKAGE MODIFIER
0 = 7 x 9 mm, 1.2 mm height, 56 balls
TEMPERATURE RANGE
W = Wireless (-25°C to +85°C)
PACKAGE TYPE
BF = Fine-pitch BGA Lead (Pb)-free package
BH = Fine-pitch BGA Lead (PB)-free, Low-Halogen package
pSRAM / SRAM DENSITY
B0 = 32 Mb pSRAM
A0 = 16 Mb pSRAM
40 = 4 Mb pSRAM
80 = 8 Mb pSRAM
PROCESS TECHNOLOGY
N = 110 nm, MirrorBit® Technology
FLASH DENSITY
064 = 64Mb
032 = 32Mb
PRODUCT FAMILY
S71GL Multi-chip Product (MCP)
3.0-volt Page Mode Flash Memory and RAM
Table 5.1 Valid Combinations
S71GL064N Valid Combinations Speed Options (ns)/Boot
Sector Option
(p)SRAM Type/
Access Time
(ns)
Package
Marking
Base Ordering
Part Number
Package &
Temperature
Package Modifier/Model
Number Packing Type
S71GL032N40
BFW, BHW
0K
0, 2, 3 (1)
90 / Bottom Boot Sector pSRAM 9 / 70
TLC056
0P 90 / Top Boot Sector
S71GL032N80 0K 90 / Bottom Boot Sector pSRAM 9 / 70
0P 90 / Top Boot Sector
S71GL032NA0 BHW 0B 90 / Bottom Boot Sector pSRAM 10 / 70
0F 90 / Top Boot Sector
S71GL032NA0 BHW 0K 90 / Bottom Boot Sector pSRAM 9 / 70
0P 90 / Top Boot Sector
S71GL064NA0 BHW 0B 90 / Bottom Boot Sector pSRAM 10 / 70
TSC056
0F 90 / Top Boot Sector
S71GL064NB0
BFW, BHW
0K 90 / Bottom Boot Sector pSRAM 9 / 70
S71GL064NB0 0P 90 / Top Boot Sector
S71GL064NB0 0U 90 / Bottom Boot Sector pSRAM 8 / 70
S71GL064NB0 0Z 90 / Top Boot Sector
January 13, 2010 S71GL-N_00_06 S71GL-N Based MCPs 9
Data Sheet (Advance Information)
6. Physical Dimensions
6.1 TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package
3348 \ 16-038.22a
PACKAGE TLC 056
JEDEC N/A
D x E 9.00 mm x 7.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.20 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 9.00 BSC. BODY SIZE
E 7.00 BSC. BODY SIZE
D1 5.60 BSC. MATRIX FOOTPRINT
E1 5.60 BSC. MATRIX FOOTPRINT
MD 8 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
n 56 BALL COUNT
φb 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
E1
7
SE
A
D1
eD
DCEFGH
8
7
6
4
3
2
1
eE
5
B
PIN A1
CORNER
7
SD
BOTTOM VIEW
C
0.08
0.20 C
A
E
B
C
0.15
(2X)
C
D
C
0.15
(2X)
INDEX MARK
10
6
b
TOP VIEW
SIDE VIEW
CORNER
56X
A1
A2
A
0.15 M
M
C
C
AB
0.08
PIN A1
10 S71GL-N Based MCPs S71GL-N_00_06 January 13, 2010
Data Sheet (Advance Information)
6.2 TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package
3427 \ 16-038.22
PACKAGE TSC 056
JEDEC N/A
D x E 9.00 mm x 7.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 9.00 BSC. BODY SIZE
E 7.00 BSC. BODY SIZE
D1 5.60 BSC. MATRIX FOOTPRINT
E1 5.60 BSC. MATRIX FOOTPRINT
MD 8 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
n 56 BALL COUNT
φb 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
E1
7
SE
A
D1
eD
DCEFGH
8
7
6
4
3
2
1
eE
5
B
PIN A1
CORNER
7
SD
BOTTOM VIEW
C
0.08
0.20 C
A
E
B
C
0.15
(2X)
C
D
C
0.15
(2X)
INDEX MARK
10
6
b
TOP VIEW
SIDE VIEW
CORNER
56X
A1
A2
A
0.15 M
M
C
C
AB
0.08
PIN A1
January 13, 2010 S71GL-N_00_06 S71GL-N Based MCPs 11
Data Sheet (Advance Information)
7. Revision History
Section Description
Revision 01 (May 14, 2007)
Initial release.
Revision 02 (June 19, 2007)
Global Editorial changes to valid combinations table
Revision 03 (March 25, 2008)
Ordering Information Added Low-Halogen option to package type.
Revision 04 (October 31, 2008)
General Description Added pSRAM Type 8, 90 nm
Product Selector Guide Added pSRAM Type 8, 90 nm
Changed S71GL064Nxx-xx package to TSC056
Ordering Information Changed S71GL064Nxx-xx package to TSC056
Physical Dimensions Added TSC056
Revision 05 (January 20, 2009)
Global Added OPNs S71GL032NA0BHW0B/0F and S71GL064NA0BHW0B/0F
General Description Added pSRAM Type 10
Revision 06 (January 13, 2010)
General Description Updated Table with current pSRAM offerrings
Global Removed pSRAM Type 7 MCPs
Added 32 Mb and 64 Mb pSRAM Type 9 MCPs
12 S71GL-N Based MCPs S71GL-N_00_06 January 13, 2010
Data Sheet (Advance Information)
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2007-2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
