Burr-BrownAudio
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
Stereo Audio DAC with USB Interface,
Single-Ended Headphone Output and S/PDIF Output
Check for Samples: PCM2704C,PCM2705C,PCM2706C,PCM2707C
1FEATURES
23456• On-Chip USB Interface: – Up to Eight Human Interface Device (HID)
Interfaces (Model and Setting Dependent)
– No Dedicated Device Driver Needed – Suspend Flag
– Full-Speed Transceivers – S/PDIF Out with SCMS
– Fully Compliant with USB 2.0 Specification – External ROM Interface (PCM2704C/6C)
– USB 1.1 Descriptors with USB Audio
Class Support – Serial Programming Interface
(PCM2705C/7C)
– Certified by USB-IF – I2S™ Interface (Selectable on
– Partially Programmable Descriptors PCM2706C/7C)
– Adaptive Isochronous Transfer for • Packages:
Playback – 28-Pin SSOP (PCM2704C/5C)
– Bus-Powered or Self-Powered Operation – 32-Pin TQFP (PCM2706C/7C)
• Sampling Rates: 32 kHz, 44.1 kHz, 48 kHz
• On-Chip Clock Generator with Single 12-MHz APPLICATIONS
Clock Source • USB Headphones
• Single Power Supply: • USB Audio Speaker
– Bus-Powered: 5 V, Typical (VBUS)• USB CRT/LCD Monitor
– Self-Powered: 3.3 V, Typical • USB Audio Interface Box
• 16-Bit Delta-Sigma Stereo DAC • USB-Featured Consumer Audio Product
– Analog Performance at 5 V (Bus-Powered),
3.3 V (Self-Powered): DESCRIPTION
– THD+N: 0.006% RL> 10 kΩ, Self- The PCM2704C/5C/6C/7C are TI's single-chip USB
Powered stereo audio digital-to-analog converters (DACs) with
– THD+N: 0.025% RL= 32 ΩUSB 2.0 compliant full-speed protocol controller and
– SNR = 98 dB S/PDIF. The USB-protocol controller works with no
software code, but USB descriptors can be modified
– Dynamic Range: 98 dB in some areas (for example, vendor ID/product ID)
– PO= 12 mW, RL= 32 Ωthrough the use of an external ROM (PCM2704C/6C)
– Oversampling Digital Filter or serial peripheral interface (SPI) (PCM2705C/7C).
The PCM2704C/5C/6C/7C also employ SpAct™
– Passband Ripple = ±0.04 dB architecture, TI's unique system that recovers the
– Stop-Band Attenuation = –50 dB audio clock from USB packet data. On-chip analog
– Single-Ended Voltage Output phase-locked loops (PLLs) with SpAct enable
playback with low clock jitter.
– Analog LPF Included
• Multiple Functions:
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SpAct is a trademark of Texas Instruments.
3System Two, Audio Precision are trademarks of Audio Precision, Inc.
4SPI is a trademark of Motorola, Inc.
5I2S, I2C are trademarks of NXP Semiconductors.
6All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current specification and package information, refer to the Package Option Addendum located at
the end of this data sheet or see the respective device product folders at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range unless otherwise noted. VALUE UNIT
VBUS –0.3 to 6.5 V
Supply voltage VCCP, VCCL, VCCR, VDD –0.3 to 4 V
Supply voltage differences VCCP, VCCL, VCCR, VDD ±0.1 V
Ground voltage differences PGND, AGNDL, AGNDR, DGND, ZGND ±0.1 V
HOST –0.3 to 6.5 V
D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT,
Digital input voltage SSPND, CK, DT, PSEL, FSEL, TEST, TEST0, TEST1, –0.3 to (VDD + 0.3) < 4 V
FUNC0, FUNC1, FUNC2, FUNC3
VCOM –0.3 to (VCCP + 0.3) < 4 V
Analog input voltage VOUTR –0.3 to (VCCR + 0.3) < 4 V
VOUTL –0.3 to (VCCL + 0.3) < 4 V
Input current (any pins except supplies) ±10 mA
Ambient temperature under bias –40 to +125 °C
Storage temperature –55 to +150 °C
Junction temperature +150 °C
Package temperature (IR reflow, peak) +260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range. MIN NOM MAX UNIT
VBUS 4.35 5 5.25
Supply voltage V
VCCP, VCCL, VCCR, VDD 3 3.3 3.6
Digital input logic level TTL-compatible
Digital input clock frequency 11.994 12 12.006 MHz
Analog output load resistance 16 32 Ω
Analog output load capacitance 100 pF
Digital output load capacitance 20 pF
Operating free-air temperature, TA–25 85 °C
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
All specifications at TA= +25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
PCM2704CDB, PCM2705CDB
PCM2706CPJT, PCM2707CPJT
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
DIGITAL INPUT/OUTPUT
Host interface Apply USB revision 1.1, full-speed
Audio data format USB isochronous data format
INPUT LOGIC
VIH 2 3.3
VIL –0.3 0.8
Input logic level VDC
VIH(1) 2 5.5
VIL(1) –0.3 0.8
IIH(2) VIN = 3.3 V ±10
IIL (2) VIN = 0 V ±10
Input logic current μA
IIH VIN = 3.3 V 65 100
IIL VIN = 0 V ±10
OUTPUT LOGIC
VOH(3) IOH = –2 mA 2.8
VOL(3) IOL = 2 mA 0.3
Output logic level VDC
VOH IOH = –2 mA 2.4
VOL IOL = 2 mA 0.4
CLOCK FREQUENCY
Input clock frequency, XTI 11.994 12 12.006 MHz
fSSampling frequency 32, 44.1, 48 kHz
DAC CHARACTERISTICS
Resolution 16 Bits
Audio data channel 1, 2 Channel
DC ACCURACY
Gain mismatch, channel-to-channel ±2 ±8 % of FSR
Gain error ±2 ±8 % of FSR
Bipolar zero error ±3 ±6 % of FSR
DYNAMIC PERFORMANCE (4)
RL> 10 kΩ, self-powered, 0.006 0.01 %
VOUT = 0 dB
Line (5)
Total harmonic RL> 10 kΩ, bus-powered,
THD+N 0.012 0.02 %
distortion + noise VOUT = 0 dB
RL= 32 Ω, self-/
Headphone 0.025 %
bus-powered, VOUT = 0 dB
THD+N Total harmonic distortion + noise VOUT = –60 dB 2 %
Dynamic range EIAJ, A-weighted 90 98 dB
SNR Signal-to-noise ratio EIAJ, A-weighted 90 98 dB
Channel separation 60 70 dB
(1) HOST pin.
(2) D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI pins.
(3) FUNC0, FUNC1, FUNC2 pins.
(4) fIN = 1 kHz, using the System Two™ Cascade audio measurement system by Audio Precision™ in RMS mode with a 20-kHz low-pass
filter (LPF) and 400-Hz high-pass filter (HPF).
(5) THD+N performance varies slightly, depending on the effective output load, including dummy load R7, R8 in Figure 34.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= +25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
PCM2704CDB, PCM2705CDB
PCM2706CPJT, PCM2707CPJT
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
ANALOG OUTPUT
Output voltage 0.55 VCCL, 0.55 VCCR VPP
Center voltage 0.5 VCCP V
Line AC-coupling 10 kΩ
Load impedance Headphone AC-coupling 16 32 Ω
–3 dB 140 kHz
LPF frequency response f = 20 kHz –0.1 dB
DIGITAL FILTER PERFORMANCE
Passband 0.454 fSHz
Stop band 0.546 fSHz
Passband ripple ±0.04 dB
Stop band attenuation –50 dB
Delay time 20/fSs
POWER SUPPLY REQUIREMENTS
VBUS Bus-powered 4.35 5 5.25
Voltage range VDC
VCCP, VCCL, VCCR,Self-powered 3 3.3 3.6
VDD
Line DAC operation 23 30 mA
Supply current Headphone DAC operation (RL= 32 Ω) 35 46
Line/headphone Suspend mode (6) 150 190 μA
Line DAC operation 76 108 mW
Power dissipation Headphone DAC operation (RL= 32 Ω) 116 166
(self-powered) Line/headphone Suspend mode (6) 495 684 μW
Line DAC operation 115 158 mW
Power dissipation Headphone DAC operation (RL= 32 Ω) 175 242
(bus-powered) Line/headphone Suspend mode (6) 750 998 μW
Internal power-supply VCCP, VCCL, VCCR,Bus-powered 3.2 3.35 3.5 VDC
voltage (7) VDD
TEMPERATURE RANGE
Operating temperature –25 +85 °C
(6) In USB suspended state.
(7) VDD, VCCP, VCCL, VCCR pins. These pins work as output pins of internal power supply for bus-powered operation.
4Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
THERMAL INFORMATION PCM2704C,
PCM2705C
THERMAL METRIC(1) UNITS
DB
32 PINS
θJA Junction-to-ambient thermal resistance 68.2
θJCtop Junction-to-case (top) thermal resistance 27.2
θJB Junction-to-board thermal resistance 29.5 °C/W
ψJT Junction-to-top characterization parameter 2.7
ψJB Junction-to-board characterization parameter 29.1
θJCbot Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION PCM2706C,
PCM2707C
THERMAL METRIC(1) UNITS
PJT
32 PINS
θJA Junction-to-ambient thermal resistance TBD
θJCtop Junction-to-case (top) thermal resistance TBD
θJB Junction-to-board thermal resistance TBD °C/W
ψJT Junction-to-top characterization parameter TBD
ψJB Junction-to-board characterization parameter TBD
θJCbot Junction-to-case (bottom) thermal resistance TBD
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PGND
VCCP
HOST
FUNC3
FUNC0
HID0/MS
HID1/MC
HID2/MD
VBUS
D+
D-
VDD
DGND
FUNC1
FUNC2
DOUT
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCOM
32
FSEL
9
AGNDR
31
TEST
10
VCCR
30
SSPND
11
V R
OUT
29
XTI
12
V L
OUT
28
XTO
13
VCCL
27
CK
14
AGNDL
26
DT
15
ZGND+
25
PSEL
16
XTO
CK
DT
PSEL
DOUT
DGND
VDD
D-
D+
VBUS
ZGND
AGNDL
VCCL
V L
OUT
XTI
SSPND
TEST0
TEST1
HID2/MD
HID1/MC
HID0/MS
HOST
VCCP
PGND
VCOM
AGNDR
VCCR
V R
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
DEVICE INFORMATION
PCM2704C, PCM2705C
DB PACKAGE
(TOP VIEW)
PCM2706C, PCM2707C
PJT PACKAGE
(TOP VIEW)
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
Table 1. Pin Descriptions: DB Package (PCM2704C/PCM2705C)
TERMINAL
NAME NO. I/O DESCRIPTION
AGNDL 12 — Analog ground for headphone amplifier of L-channel
AGNDR 17 — Analog ground for headphone amplifier of R-channel
CK 2 O Clock output for external ROM (PCM2704C). Must be left open (PCM2705C).
D+ 9 I/O USB differential input/output plus(1)
D– 8 I/O USB differential input/output minus(1)
DGND 6 — Digital ground
DOUT 5 O S/PDIF output
DT 3 I/O Data input/output for external ROM (PCM2704C). Must be left open with pull-up resistor (PCM2705C).(1)
HID0/MS 22 I HID key state input (mute), active high (PCM2704C). MS input (PCM2705C).(2)
HID1/MC 23 I HID key state input (volume up), active high (PCM2704C). MC input (PCM2705C).(2)
HID2/MD 24 I HID key state input (volume down), active high (PCM2704C). MD input (PCM2705C).(2)
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
HOST 21 I operation (low: 100 mA, high: 500 mA).(3)
PGND 19 — Analog ground for DAC, OSC, and PLL
PSEL 4 I Power source select (low: self-power, high: bus-power)(1)
SSPND 27 O Suspend flag, active low (low: suspend, high: operational)
TEST0 26 I Test pin. Must be set high(1)
TEST1 25 I Test pin. Must be set high(1)
VBUS 10 — Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
VCCL 13 — Analog power supply for headphone amplifier of L-channel(4)
VCCP 20 — Analog power supply for DAC, OSC, and PLL(4)
VCCR 16 — Analog power supply for headphone amplifier of R-channel(4)
VCOM 18 — Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
VDD 7 — Digital power supply(4)
VOUTL 14 O DAC analog output for L-channel
VOUTR 15 O DAC analog output for R-channel
XTI 28 I Crystal oscillator input(1)
XTO 1 O Crystal oscillator output
ZGND 11 — Ground for internal regulator
(1) LV-TTL level.
(2) LV-TTL level with internal pulldown.
(3) LV-TTL level, 5-V tolerant.
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
Table 2. Pin Descriptions: PJT Package (PCM2706C/PCM2707C)
TERMINAL
NAME NO. I/O DESCRIPTION
AGNDL 26 — Analog ground for headphone amplifier of L-channel
AGNDR 31 — Analog ground for headphone amplifier of R-channel
CK 14 O Clock output for external ROM (PCM2706C). Must be left open (PCM2707C).
D+ 23 I/O USB differential input/output plus(1)
D– 22 I/O USB differential input/output minus(1)
DGND 20 — Digital ground
DOUT 17 O S/PDIF output/I2S data output
DT 15 I/O Data input/output for external ROM (PCM2706C). Must be left open with pull-up resistor (PCM2707C).(1)
FSEL 9 I Function select (low: I2S data output, high: S/PDIF output)(1)
FUNC0 5 I/O HID key state input (next track), active high (FSEL = 1). I2S LR clock output (FSEL = 0).(2)
FUNC1 19 I/O HID key state input (previous track), active high (FSEL = 1). I2S bit clock output (FSEL = 0).(2)
FUNC2 18 I/O HID key state input (stop), active high (FSEL = 1). I2S system clock output (FSEL = 0).(2)
FUNC3 4 I HID key state input (play/pause), active high (FSEL = 1). I2S data input (FSEL = 0).(2)
HID0/MS 6 I HID key state input (mute), active high (PCM2706C). MS input (PCM2707C).(2)
HID1/MC 7 I HID key state input (volume up), active high (PCM2706C). MC input (PCM2707C).(2)
HID2/MD 8 I HID key state input (volume down), active high (PCM2706C). MD input (PCM2707C).(2)
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
HOST 3 I operation. (low: 100 mA, high: 500 mA).(3)
PGND 1 — Analog ground for DAC, OSC, and PLL
PSEL 16 I Power source select (low: self-power, high: bus-power)(1)
SSPND 11 O Suspend flag, active low (low: suspend, high: operational)
TEST 10 I Test pin. Must be set high(1)
VBUS 24 — Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
VCCL 27 — Analog power supply for headphone amplifier of L-channel(4)
VCCP 2 — Analog power supply for DAC, OSC, and PLL(4)
VCCR 30 — Analog power supply for headphone amplifier of R-channel(4)
VCOM 32 — Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
VDD 21 — Digital power supply(4)
VOUTL 28 O DAC analog output for L-channel
VOUTR 29 O DAC analog output for R-channel
XTI 12 I Crystal oscillator input(1)
XTO 13 O Crystal oscillator output
ZGND 25 — Ground for internal regulator
(1) LV-TTL level.
(2) LV-TTL level with internal pulldown.
(3) LV-TTL level, 5-V tolerant.
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
ZGNDDGNDAGNDRAGNDLPGND
VCCP VCCL VCCR VDD
SSPND
VBUS
D+
D-
CK
DT
HOST
HID0/MS
HID1/MC
HID2/MD
XTO
XTI 12 MHz
TEST1
TEST0
PSEL
DOUT
V R
OUT
V L
OUT
VCOM
5-V to 3.3-V
Voltage Regulator
DAC
Power
Manager
Analog
PLL
S/PDIF Encoder
USB
Protocol
Controller
Control
Endpoint
USB SIE
XCVR
FIFO
Buffer
ISO-Out
Endpoint
HID
Endpoint
EEPROM
Interface(1)
Serial Peripheral
Interface(2)
Tracker
(SpAct)
PLL (x 8) 96 MHz
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAMS
PCM2704C/PCM2705C
(1) Applies to PCM2704CDB.
(2) Applies to PCM2705CDB.
Figure 1.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
ZGNDDGNDAGNDRAGNDLPGND
VCCP VCCL VCCR VDD
SSPND
VBUS
D+
D-
CK
DT
HOST
HID0/MS
HID1/MC
HID2/MD
XTO
XTI 12 MHz
TEST
PSEL
FUNC3
FUNC2
FUNC1
FUNC0
FSEL
DOUT
V R
OUT
V L
OUT
VCOM
5-V to 3.3-V
Voltage Regulator
DAC
Power
Manager
Analog
PLL
S/PDIF
Encoder
USB
Protocol
Controller
Control
Endpoint
USB SIE
XCVR
FIFO
Buffer
ISO-Out
Endpoint
HID
Endpoint
EEPROM
Interface(1)
Serial Peripheral
Interface(2)
Tracker
(SpAct)
PLL (x 8) 96 MHz
I S
Interface
2
HID3: Next Track(1)
HID4: Previous Track(1)
HID5: Stop(1)
HID6: Play/Pause(1)
DOUT
LRCK
BCK
SYSCK
DIN
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
PCM2706C/PCM2707C
(1) Applies to PCM2706CPJT.
(2) Applies to PCM2707CPJT.
Figure 2.
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
0
0.5
1
1.5
2-
-
-
-
Amplitude (dB)
0.01 0.1 1 10 100
Frequency (kHz)
G003
0
20
40
60
80
-
-
-
-
Amplitude (dB)
1 10 100 1k 10k
Frequency (kHz)
G004
0 1 2 3 4
G001
0
20
40
60
80
100
-
-
-
-
-
-
-
120
140
Amplitude (dB)
Frequency (× f )
S
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS: INTERNAL FILTER
All specifications at TA= 25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).
DAC Digital Interpolation Filter Frequency Response
AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY
Figure 3. Frequency Response Figure 4. Passband Ripple
DAC Analog Low-Pass Filter Frequency Response
AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY
Figure 5. Passband Characteristics Figure 6. Stop Band Characteristics
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
0.05
0.04
0.03
0.02
0.01
0
Total Harmonic Distortion + Noise (%)
G007
4 4.5 5 5.5
Supply Voltage (V)
10 kW
32 W
Bus-Powered
V = 0 dB
OUT
3 3.2 3.3 3.5 3.6
Supply Voltage (V) G008
3.1 3.4
0.05
0.04
0.03
0.02
0.01
0
Total Harmonic Distortion + Noise (%)
10 kW
32 W
Self-Powered
V = 0 dB
OUT
0.05
0.04
0.03
0.02
0.01
0
Total Harmonic Distortion + Noise (%)
-50 100
Free-Air Temperature (°C) G005
-25 0 25 50 75
10 kW
32 W
Bus-Powered
V = 0 dB
OUT
0.05
0.04
0.03
0.02
0.01
0
Total Harmonic Distortion + Noise (%)
-50 100
Free-Air Temperature (°C) G006
-25 0 25 50 75
10 kW
32 W
Self-Powered
V = 0 dB
OUT
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS: GENERAL
All specifications at TA= +25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
Figure 7. Figure 8.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE
Figure 9. Figure 10.
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
105
103
101
99
97
95
Dynamic Range and SNR (dB)
G013
4 4.5 5 5.5
Supply Voltage (V)
Bus-Powered
SNR
Dynamic Range
3 3.2 3.3 3.5 3.6
Supply Voltage (V) G014
3.1 3.4
Self-Powered
105
103
101
99
97
95
Dynamic Range and SNR (dB)
SNR
Dynamic Range
105
103
101
99
97
95
Dynamic Range and SNR (dB)
-50 100
Free-Air Temperature (°C) G011
-25 0 25 50 75
SNR
Dynamic Range
Bus-Powered
105
103
101
99
97
95
Dynamic Range and SNR (dB)
-50 100
Free-Air Temperature (°C) G012
-25 0 25 50 75
SNR
Dynamic Range
Self-Powered
0.05
0.04
0.03
0.02
0.01
0
Total Harmonic Distortion + Noise (%)
30 35 40 45 50
Sampling Frequency (kHz) G009
10 kW
32 W
Bus-Powered
V = 0 dB
OUT
0.05
0.04
0.03
0.02
0.01
0
Total Harmonic Distortion + Noise (%)
30 35 40 45 50
Sampling Frequency (kHz) G010
10 kW
32 W
Self-Powered
V = 0 dB
OUT
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA= +25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY vs SAMPLING FREQUENCY
Figure 11. Figure 12.
DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR
vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
Figure 13. Figure 14.
DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR
vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE
Figure 15. Figure 16.
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200
150
100
50
0
Suspend Current ( A)m
4 4.5 5 5.5
Supply Voltage (V) G017
-40 0 40 60 100
Free-Air Temperature (°C)
G018
-20 20 80
200
150
100
50
0
Suspend Current ( A)m
30 35 40 45 50
Sampling Frequency (kHz) G015
105
103
101
99
97
95
Dynamic Range and SNR (dB)
SNR
Dynamic Range
Bus-Powered
30 35 40 45 50
Sampling Frequency (kHz) G016
105
103
101
99
97
95
Dynamic Range and SNR (dB)
SNR
Dynamic Range
Self-Powered
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA= +25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR
vs SAMPLING FREQUENCY vs SAMPLING FREQUENCY
Figure 17. Figure 18.
SUSPEND CURRENT SUSPEND CURRENT
vs SUPPLY VOLTAGE vs FREE-AIR TEMPERATURE
Figure 19. Figure 20.
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0 5 10 15 20
G019
0
20
40
60
80
100
-
-
-
-
-
-
-
120
140
Amplitude (dB)
Frequency (kHz)
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
TYPICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA= +25°C, VBUS = 5 V, fS= 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY
Figure 21. Output Spectrum (–60 dB, N = 8192) Figure 22. Output Spectrum (–60 dB, N = 8192)
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SBFS036A –AUGUST 2011–REVISED JULY 2012
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DETAILED DESCRIPTION
Clock and Reset
For both USB and audio functions, the PCM2704C/5C/6C/7C require a 12-MHz (±500 ppm) clock that can be
generated by the onboard oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to the XTI pin (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C) and the XTO pin (pin 1 for
the PCM2704C/5C, pin 13 for the PCM2706C/7C) with one large (1-MΩ) resistor and two small capacitors; the
capacitance of these components depends on the specified load capacitance of the crystal resonator. An
external clock can be supplied from XTI (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C). If an
external clock is supplied, XTO (pin 1 for the PCM2704C/5C, pin 13 for the PCM2706C/7C) must be left open.
No clock disabling pin is provided; therefore, it is not recommended to use the external clock supply. SSPND (pin
27 for the PCM2704C/5C, pin 11 for the PCM2706C/7C) cannot use clock disabling.
The PCM2704C/5C/6C/7C have an internal power-on reset circuit, and it works automatically when VDD (pin 7 for
the PCM2704C/5C, pin 21 for the PCM2706C/7C) exceeds 2-V typical (1.6 V to 2.4 V), which is equivalent to
VBUS (pin 10 for the PCM2704C/5C, pin 24 for the PCM2706C/7C) exceeding 3-V typical for bus-powered
applications. Approximately 700 μs is required until an internal reset release occurs.
Operation Mode Selection
The PCM2704C/5C/6C/7C have the following mode-select pins.
Power Configuration Select/Host Detection
PSEL (pin 4 for the PCM2704C/5C, pin 16 for the PCM2706C/7C) is dedicated to selecting the power source.
This selection affects the configuration descriptor. While in bus-powered operation, the maximum power
consumption from VBUS is determined by the HOST pin (pin 21 for the PCM2704C/5C, pin 3 for the
PCM2706C/7C). For self-powered operation, the HOST pin must be connected to VBUS of the USB bus with a
pulldown resistor to detect attach and detach. (To avoid excessive suspend current, the pulldown should be a
high-value resistor.) Table 3 summarizes the power configuration select options.
Table 3. Power Configuration Select
PSEL DESCRIPTION
0 Self-powered
1 Bus-powered
HOST DESCRIPTION
0 Detached from USB (self-powered)/100 mA (bus-powered)
1 Attached to USB (self-powered)/500 mA (bus-powered)
Function Select (PCM2706C/7C Only)
FSEL (pin 9) determines the function of the FUNC0–FUNC3 pins (pins 4, 5, 18, and 19) and DOUT (pin 17).
When the I2S interface is required, FSEL must be low. Otherwise, FSEL must be high. Table 4 lists the
functionality of the FUNC0-FUNC3 pins, based on the FSEL pin.
Table 4. Function Select
FSEL DOUT FUNC0 FUNC1 FUNC2 FUNC3
0 Data out (I2S) LRCK (I2S) BCK (I2S) SYSCK (I2S) Data in (I2S)
1 S/PDIF data Next track (HID) (1) Previous track (HID) (1) Stop (HID) (1) Play/pause (HID) (1)
(1) Valid on the PCM2706C only; no function assigned on the PCM2707C.
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SBFS036A –AUGUST 2011–REVISED JULY 2012
USB Interface
Control data and audio data are transferred to the PCM2704C/5C/6C/7C via the D+ pin (pin 9 for the
PCM2704C/5C, pin 23 for the PCM2706C/7C) and D– pin (pin 8 for the PCM2704C/5C, pin 22 for the
PCM2706C/7C). D+ should be pulled up with a 1.5-kΩ(±5%) resistor. To avoid back voltage in self-powered
operation, the device must not provide power to the pull-up resistor on D+ while VBUS of the USB port is inactive.
All data to/from the PCM2704C/5C/6C/7C are transferred at full speed. The information shown in Table 5 is
provided in the device descriptor. Some parts of the device descriptor can be modified through external ROM
(PCM2704C/6C) or SPI™ (PCM2705C/7C).
Table 5. Device Descriptor
DEVICE DESCRIPTOR DESCRIPTION
USB revision 1.1 compliant
Device class 0x00 (device defined interface level)
Device subclass 0x00 (not specified)
Device protocol 0x00 (not specified)
Max packet size for endpoint 0 8 bytes
Vendor ID 0x08BB (default value, can be modified)
0x27C4/0x27C5/0x27C6/0x27C7 (These values correspond to the model number, and the value can
Product ID be modified.)
Device release number 1.0 (0x0100)
Number of configurations 1
Vendor strings BurrBrown from Texas Instruments (default value, can be modified)
Product strings USB AUDIO DAC (default value, can be modified)
Serial number Not supported
The information given in Table 6 is contained in the configuration descriptor. Some parts of the configuration
descriptor can be modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).
Table 6. Configuration Descriptor
CONFIGURATION DESCRIPTOR DESCRIPTION
Interface Three interfaces
0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can
Power attribute be modified.)
0x0A, 0x32, or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on
Max power PSEL and HOST. This value can be modified.)
The information listed in Table 7 is contained in the string descriptor. Some parts of the string descriptor can be
modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).
Table 7. String Descriptor
STRING DESCRIPTOR DESCRIPTION
#0 0x0409
#1 BurrBrown from Texas Instruments (default value, can be modified)
#2 USB AUDIO DAC (default value, can be modified)
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Analog Out
IT
TID1
OT
TID2
FU
UID3
Standard Audio Control Interface (I/F #0)
Endpoint #0
Endpoint #2
(I/F #1)
Endpoint #5
(I/F #2)
Default
Endpoint
Audio Streaming
Interface
HID Interface
PCM2704C/5C/6C/7C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
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Device Configuration
Figure 23 illustrates the USB audio function topology. The PCM2704C/5C/6C/7C have three interfaces. Each
interface is enabled by different alternative settings.
Figure 23. USB Audio Function Topology
Interface #0 (Default/Control Interface)
Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes
the standard audio control interface. The audio control interface consists of a terminal. The
PCM2704C/5C/6C/7C have three terminals:
• Input terminal (IT #1) for isochronous-out stream
• Output terminal (OT #2) for audio analog output
• Feature unit (FU #3) for DAC digital attenuator
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel
audio streams consisting of left and right channels. Output terminal #2 is defined as a speaker (terminal type
0x0301). Feature unit #3 supports these sound control features:
• Volume control
• Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB
in steps of 1 dB. Changes are made by incrementing or decrementing one step (that is, 1 dB) for every 1/fStime
interval, until the volume level reaches the requested value. Each channel can be set to a separate value. The
master volume control is not supported. A request to the master volume is stalled and ignored. The built-in digital
mute controller can be manipulated by an audio-class-specific request. A master mute control request is
acceptable. A mute control request to an individual channel is stalled and ignored. The digital volume control
does not affect either the S/PDIF or I2S outputs (PCM2706C/7C only).
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SBFS036A –AUGUST 2011–REVISED JULY 2012
Interface #1 (Isochronous-Out Interface)
Interface #1 is for the audio-streaming data-out interface. Interface #1 has the alternative settings described in
Table 8. Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
Table 8. Interface #1 Parameters
ALTERNATIVE TRANSFER SAMPLING RATE
DATA FORMAT
SETTING MODE (kHz)
00 Zero bandwidth
01 16-bit Stereo Twos complement (PCM) Adaptive 32, 44.1, 48
02 16-bit Mono Twos complement (PCM) Adaptive 32, 44.1, 48
Interface #2 (HID Interface)
Interface #2 is the interrupt-data-in interface. The HID consumer control device consists of interface #2.
Alternative setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported for any model, in any configuration.
HID Items Reported
Basic HID Operation
Interface #2 can report these three key statuses for any model. These statuses can be set by the HID0–HID2
pins (PCM2704C/6C) or the SPI port (PCM2705C/7C).
• Mute (0xE2)
• Volume up (0xE9)
• Volume down (0xEA)
Extended HID Operation (PCM2705/6/7)
By using the FUNC0–FUNC3 pins (PCM2706C) or the SPI port (PCM2705C/7C), these additional conditions can
be reported to the host.
• Play/Pause (0xCD)
• Stop (0xB7)
• Previous (0xB6)
• Next (0xB5)
Auxiliary HID Status Report (PCM2705C/7C)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI
command or external ROM. This definition must be described as on the report descriptor with a three-byte usage
ID. AL A/V Capture (0x0193) is assigned as the default value for this status flag.
Endpoints
The PCM2704C/5C/6C/7C has three endpoints:
• Control endpoint (EP #0)
• Isochronous-out audio data-stream endpoint (EP #2)
• HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint controls all functions of the
PCM2704C/5C/6C/7C by standard USB request and USB audio-class-specific request from the host. The
isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The
isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an
interrupt-in endpoint. The HID endpoint reports HID status every 10 ms.
The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent
endpoint from the isochronous-out endpoint. This configuration means that the effect of HID operation depends
on the host software. Typically, the HID function controls the primary audio-out device.
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11 1
1 1 1
222
222
3 3
3 3
14 14
14 14
15 15
15 15
16 16
16 16
SYSCK
(256 f )
S
LRCK
BCK
(64 f )
S
DOUT
DIN
MSB MSB MSBLSB LSB
L-Channel R-Channel
1/fS
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
DAC
The PCM2704C/5C/6C/7C have a DAC that uses an oversampling technique with 128-fS, second-order, multi-bit
noise shaping. This technique provides extremely low quantization noise in the audio band, and the built-in
analog low-pass filter removes the high-frequency components of the noise-shaping signal. The DAC analog
outputs, VOUTL and VOUTR , are sent through the headphone amplifier and can provide 12 mW at 32 Ωas well as
1.8 VPP into a 10-kΩload.
Digital Audio Interface: S/PDIF Output
The PCM2704C/5C/6C/7C employ S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF
output DOUT, as well as to DAC analog outputs VOUTL and VOUTR. The interface format and timing follow the
IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is
not supported in the I2S I/F enable mode. The implementation of this feature is optional. Note that it is the
responsibility of the user to determine whether or not to implement this feature in the end application.
Channel Status Information
Channel status information is fixed, and includes consumer application, PCM mode, copyright, and digital/digital
converter data. All other bits are fixed as 0s, except for the sample frequency, which is set automatically
according to the data received through the USB.
Copyright Management
Digital audio data output always is encoded as original with SCMS control. Only one generation of digital
duplication is allowed.
Digital Audio Interface: I2S Interface Output (PCM2706C/7C)
The PCM2706C and PCM2707C can support the I2S interface, which is enabled by the FSEL pin (pin 9). In the
I2S interface-enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT,
respectively. These pins provide digital output/input data in the 16-bit I2S format, which also is accepted by the
internal DAC. I2S interface format and timing are shown in Figure 24,Figure 25, and Figure 26.Table 9 and
Table 10 list the audio interface timing and audio clock timing characteristics, respectively.
Figure 24. Audio Data Interface Format
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t(SLL)
t(SBL)
t(SLH)
t(SBH)
LRCK
(Output)
SYSCK
(Output)
BCK
(Output)
t(BCH) t(BCL) t(BL)
t(BD) t(LD)
t(DH)
t(DS)
t(BCY)
LRCK (Output)
BCK (Output)
DOUT (Output)
DIN (Input)
50% of VDD
50% of VDD
50% of VDD
50% of VDD
PCM2704C, PCM2705C
PCM2706C, PCM2707C
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SBFS036A –AUGUST 2011–REVISED JULY 2012
Figure 25. Audio Interface Timing
Table 9. Audio Interface Timing Characteristics(1)
SYMBOL PARAMETER MIN MAX UNIT
t(BCY) BCK pulse cycle time 300 ns
t(BCH) BCK pulse duration, high 100 ns
t(BCL) BCK pulse duration, low 100 ns
t(BL) LRCK delay time from BCK falling edge –20 40 ns
t(BD) DOUT delay time from BCK falling edge –20 40 ns
t(LD) DOUT delay time from LRCK edge –20 40 ns
t(DS) DIN setup time 20 ns
t(DH) DIN hold time 20 ns
(1) Load capacitance of LRCK, BCK, and DOUT is 20 pF.
Figure 26. Audio Clock Timing
Table 10. Audio Clock Timing Characteristics(1)
SYMBOL PARAMETER MIN MAX UNIT
t(SLL), t(SLH) LRCK delay time from SYSCK rising edge –5 10 ns
t(SBL), t(SBH) BCK delay time from SYSCK rising edge –5 10 ns
(1) Load capacitance is 20 pF.
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DESCRIPTOR DATA MODIFICATION
The descriptor data can be modified through the I2C™ port by external ROM (PCM2704C/6C) or through the SPI
port by an SPI host such as an MCU (PCM2705C/7C) under a particular configuration of the PSEL and HOST
pins. Setting both the PSEL and the HOST pins high is necessary to modify the descriptor data; the D+ pin pull-
up resistor must not be activated before programming the descriptor data through the external ROM or SPI port
is completed. The descriptor data must be sent from an external ROM to the PCM2704C/6C or from the SPI host
to the PCM2705C/7C in LSB first format, with a specified byte order. Additionally, the power attribute and max
power contents must be consistent with the PSEL setting and the power usage from the USB VBUS of the end
application. Therefore, descriptor data modification in self-powered configuration (PSEL = low) is not supported.
External ROM Descriptor (PCM2704C/6C)
The PCM2704C/6C support an external ROM interface to override internal descriptors. Pin 3 (for the
PCM2704C) or pin 15 (for the PCM2706C) is assigned as DT (serial data), and pin 2 (for the PCM2704C) or pin
14 (for the PCM2706C) is assigned as CK (serial clock) of the I2C interface when using the external ROM
descriptor. Descriptor data are transferred from the external ROM to the PCM2704C/6C through the I2C interface
the first time when the device is activate after a power-on reset. Before completing a read of the external ROM,
the PCM2704C/6C reply with NACK for any USB command request from the host to the device itself. The
descriptor data, which can be in the external ROM, must meet these parameters:
• String descriptors must be described in ANSI ASCII code (1 byte for each character).
• String descriptors are converted automatically to unicode strings for transmission to the host.
• The device address of the external ROM is fixed as 0xA0.
The data bits must be sent from LSB to MSB on the I2C bus. This condition means that each byte of data must
be stored with its bits in reverse order. A read operation is performed at a frequency of XTI/384 (approximately
30 kHz). The power attribute and max power contents must be consistent with the end application circuit
configuration (the PSEL setting and the actual power usage from VBUS of the USB connector); otherwise, it may
cause improper or unexpected PCM2704C/6C operation.
The data must be stored from address 0x00 and must consist of 57 bytes, according to the parameters listed
below:
• Vendor ID (2 bytes)
• Product ID (2 bytes)
• Product string (16 bytes in ANSI ASCII code)
• Vendor string (32 bytes in ANSI ASCII code)
• Power attribute (1 byte)
• Max power (1 byte)
• Auxiliary HID usage ID in report descriptor (3 bytes)
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S P
DT
CK
Start
Condition
Stop
Condition
Device Address R/W ACK ACK ACK
DATA DATA NACK
1 7-1 8-1 8-8 9 9 9 9
R/ : Read operation if ‘1’; otherwise, Write operation
ACK: Acknowledgement of a byte if ‘0’
DATA: 8 bits (1 byte)
NACK: No acknowledgement if ‘1’
W
PCM2704C, PCM2705C
PCM2706C, PCM2707C
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SBFS036A –AUGUST 2011–REVISED JULY 2012
Figure 27 illustrates the timing for an external ROM read operation. The timing characteristics are summarized in
Table 11.
Figure 27. External ROM Read Operation
Table 11. External ROM Read Operation Characteristics
M M M S S M S M S M M
S Device address R/W ACK DATA ACK DATA ACK . . . NACK P
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t(BUF) t(D-SU)
t(S-HD)
t(CK-F)
t(HI) t(RS-SU)
t(LOW)
t(CK-R) t(RS-HD)
t(D-HD)
t(DT-R)
t(DT-F)
t(P-SU)
Start
Repeated
Start Stop
DT
CK
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
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Figure 28 shows the timing for an external ROM read interface. The respective timing characteristics are
summarized in Table 12.
Figure 28. External ROM Read Interface Timing Requirements
Table 12. External ROM Read Interface Timing Characteristics
SYMBOL PARAMETER MIN MAX UNIT
f(CK) CK clock frequency 100 kHz
t(BUF) Bus free time between a STOP and a START condition 4.7 μs
t(LOW) Low period of the CK clock 4.7 μs
t(HI) High period of the CK clock 4 μs
t(RS-SU) Setup time for START/repeated START condition 4.7 μs
t(S-HD) Hold time for START/repeated START condition 4 μs
t(RS-HD)
t(D-SU) Data setup time 250 ns
t(D-HD) Data hold time 0 900 ns
t(CK-R) Rise time of CK signal 20 + 0.1 CB1000 ns
t(CK-F) Fall time of CK signal 20 + 0.1 CB1000 ns
t(DT-R) Rise time of DT signal 20 + 0.1 CB1000 ns
t(DT-F) Fall time of DT signal 20 + 0.1 CB1000 ns
t(P-SU) Setup time for STOP condition 4 μs
CBCapacitive load for DT and CK lines 400 pF
VNH Noise margin at high level for each connected device (including hysteresis) 0.2 VDD V
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SBFS036A –AUGUST 2011–REVISED JULY 2012
External ROM Example
External ROM data (sample set)
0xBB, 0x08, 0x04, 0x27,
0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x80,
0x7D,
0x0A, 0x93, 0x01
Explanation
Data are stored beginning at address 0x00.
Vendor ID: 0x08BB
Product ID: 0x2704
Product string: Product strings (16 bytes).
Vendor string: Vendor strings are placed here (32 bytes, 31 visible characters are followed by 1 space).
Power attribute (bmAttribute): 0x80 (Bus-powered).
Max power (maxPower): 0x7D (250 mA).
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture).
Note that the data bits must be sent from LSB to MSB on the I2C bus. Therefore, each data byte must be stored
with its bits in reverse order.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
MC
MS
MD
MC
MS
MD
16 Bits
16 Bits FramesN?
NFrames
(2) Continuous Write Operation
(1) Single Write Operation
MSB MSB
MSBMSB
LSB
LSB MSBLSB LSB
LSB
MS
MC
MD
50% of VDD
50% of VDD
50% of VDD
t(MLS)
t(MCH)
t(MCL)
t(MCY)
t(MDS)
t(MDH)
t(MLH)
t(MHH)
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
Serial Programming Interface (PCM2705C/7C)
The PCM2705C/7C supports a serial interface (SPI) to program the descriptor and to set the HID state.
Descriptor data are described in the External ROM Descriptor section. Figure 29 illustrates the SPI timing;
Table 13 lists the respective timing characteristics.
Figure 29. SPI Timing Diagram
Table 13. SPI Timing Characteristics
SYMBOL PARAMETER MIN MAX UNIT
t(MCY) MC pulse cycle time 100 ns
t(MCL) MC low-level time 50 ns
t(MCH) MC high-level time 50 ns
t(MHH) MS high-level time 100 ns
t(MLS) MS falling edge to MC rising edge 20 ns
t(MLH) MS hold time 20 ns
t(MDH) MD hold time 15 ns
t(MDS) MD setup time 20 ns
Figure 30 shows the SPI write timing sequence.
Figure 30. SPI Write Operation
26 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
SPI Register (PCM2705C/7C)
Table 14. SPI Register Description
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 ST 0 ADDR 0 D0 D1 D2 D3 D4 D5 D6 D7
D[7:0] Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7 Reports MUTE HID status to the host (active high)
D6 Reports volume-up HID status to the host (active high)
D5 Reports volume-down HID status to the host (active high)
D4 Reports next-track HID status to the host (active high)
D3 Reports previous-track HID status to the host (active high)
D2 Reports stop HID status to the host (active high)
D1 Reports play/pause HID status to the host (active high)
D0 Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB
Contents of the power attribute and max power must be consistent with the actual application circuit
configuration (the PSEL setting and the actual power usage from VBUS of the USB connector); otherwise, it may
cause improper or unexpected PCM2705C/7C operation.
ADDR Starts write operation for internal descriptor reprogramming (active high)
This bit resets the descriptor ROM address counter and indicates that subsequent words should be ROM data
(described in the External ROM Example section). 456 bits of ROM data must be continuously followed after
this bit has been asserted. The data bits must be sent from LSB (D0) to MSB (D7).
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an HID status write when
ST is set low.Determines the function of the lower 8-bit data.Table 15 summarizes the functionality of ST
ST and ADDR bit combinations.
0: HID status write
1: Descriptor ROM data write
Table 15. Functionality of ST and ADDR Bit Combinations
ST ADDR FUNCTION
0 0 HIS status write
0 1 HIS status write and descriptor ROM address reset
1 0 Descriptor ROM data write
1 1 Reserved
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
Ready for Setup Ready for Playback
VDD
0 V
D+ / D-
SSPND
V L
V R
OUT
OUT
2.0 V (typ)
Bus Idle
Bus Reset Set Configuration
SOF
First Audio Data
SOF SOF
Second Audio Data
3.3 V (typ)
BPZ
1 ms
Device Setup
700 sm
Internal Reset
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
USB Host Interface Sequence
Power-On, Attach, and Playback Sequence
The PCM2704C/5C/6C/7C are ready for setup when the reset sequence has finished and the USB bus is
attached. After a connection has been established (through the set-up process), the PCM2704C/5C/6C/7C are
ready to accept USB audio data. While waiting for the audio data (that is, the device is in an idle state), the
analog output is set to bipolar zero (BPZ).
Upon receiving the audio data, the PCM2704C/5C/6C/7C stores the first audio packet into the internal storage
buffer. The packet contains 1 ms of audio data. The PCM2704C/5C/6C/7C start playing the audio data after
detecting the next subsequent start-of-frame (SOF) packet. Figure 31 shows the initial operation sequence for
the device.
Figure 31. Initial Sequence
28 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
D+ / D-
SSPND
V L
V R
OUT
OUT
Idle
Active
Active 2.5 ms
5 ms Suspend
Detach
1 ms
VBUS
D+ / D-
V L
V R
OUT
OUT
SOF SOF SOF SOF SOF
Audio Data Audio Data Last Audio Data
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
Play, Stop, and Detach Sequence
When the host finishes or aborts playback, the PCM2704C/5C/6C/7C stop playing after the last audio data output
is complete. Figure 32 illustrates the play, stop, and detach sequence.
Figure 32. Play, Stop, and Detach Sequence
Suspend and Resume Sequence
The PCM2704C/5C/6C/7C enter a suspended state after the USB bus has been in a constant idle state for
approximately 5 ms. While the PCM2704C/5C/6C/7C are in this suspended state, the SSPND flag (pin 27 for the
PCM2704C/5C, pin 11 for the PCM2706C/7C) is asserted. The PCM2704C/5C/6C/7C wake up immediately
when detecting a non-idle state on the USB bus. Figure 33 shows the operating sequence for the suspend and
resume process.
Figure 33. Suspend and Resume
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
SCL
11
12
13
14
18
17
16
15
R9
C4
GND
R1
C2
X1
C1
SDA
S/PDIF OUT
C7
R2
C3
R3
R4
C6C5
+C8
+
C9
+
C10
C11
R5
C12
R6R7R8
C13
+
C14
+
PCM2704CDB
External ROM
(Optional)
(3)
USB ‘B’
Connector
D-
D+
VBUS
SUSPEND
TPA200x
Power Amp
MUTE
VOLUME+
VOLUME-
XTO XTI
CK
DT
PSEL(2)
DOUT
DGND
VDD
D-
D+
VBUS
VCCP
(3)
ZGND
PGND
AGNDL AGNDR
VCCL VCCR
V L
OUT
(1) V R
OUT
(1)
VCOM
HOST(2)
HID0/MS
HID1/MC
HID2/MD
TEST1
TEST0
SSPND
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
EXAMPLE CIRCUITS
Operating Environment
For current information on the PCM2704C/2705C/2706C/2707C operating environments, see the Updated
Operating Environments for PCM270X, PCM290X Applications application report, SLAA374, available through
the TI website at www.ti.com.
Typical Circuit Connection 1: USB Speaker
Figure 34 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3to C7: 1-μF
ceramic capacitors. C8: 10-μF electrolytic capacitor. C9, C10: 100-μF electrolytic capacitors (depending on tradeoff between required
frequency response and discharge time for resume). C11, C12: 0.022-μF ceramic capacitors. C13, C14: 1-μF electrolytic capacitors. R1: 1-MΩ
resistor. R2, R9: 1.5-kΩresistors. R3, R4: 22-Ωresistors. R5, R6: 16-Ωresistors. R7, R8: 330-Ωresistors (depending on tradeoff between
required THD performance and pop-noise level for suspend).
(1) Output impedance of VOUTL and VOUTR during suspended mode or lack of power supply is 26 kΩ±20%, which is the discharge path for
C9and C10.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.
Figure 34. Bus-Powered Application
NOTE
The circuit illustrated in Figure 34 is for information only. The entire board design should
be considered to meet the USB specification as a USB-compliant product.
30 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCOM
32
FSEL
9
AGNDR
31
TEST
10
VCCR
30
SSPND
11
V R
OUT
(1)
29
XTI
12
V L
OUT
(1)
28
XTO
13
VCCL
27
CK
14
AGNDL
26
DT
15
ZGND+
25
PSEL(2)
16
PGND
VCCP
(3)
HOST(2)
FUNC3
FUNC0
HID0/MS
HID1/MC
HID2/MD
VBUS
D+
D-
VDD
DGND
FUNC1
FUNC2
DOUT
PCM2706CPJT
+
VOLUME-
VOLUME+
MUTE
NEXT TRACK
PLAY/PAUSE
C5
C3C4
C6
SUSPEND
R1
R4
R3
R2
R11
C2
C8C7
X1
C1
SCL
SDA
External ROM
(Optional)
(3)
STOP
PREVIOUS TRACK
GND
USB ‘B’
Connector
D-
D+
VBUS
+
C9
+
C10
R9R10
R5
C12
C11
R6R7R8
Headphone
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
Typical Circuit Connection 2: Remote Headphone
Figure 35 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3to C5, C7,
C8: 1-μF ceramic capacitors. C6: 10-μF electrolytic capacitor. C9, C10: 100-μF electrolytic capacitors (depending on required frequency
response). C11, C12: 0.022-μF ceramic capacitors. R1: 1-MΩresistor. R2, R11: 1.5-kΩresistors. R3, R4: 22-Ωresistors. R5, R6: 16-Ωresistors.
R7to R10: 3.3-kΩresistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ±20%, which is the discharge path for C9
and C10.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.
Figure 35. Bus-Powered Application
NOTE
The circuit illustrated in Figure 35 is for information only. The entire board design should
be considered to meet the USB specification as a USB-compliant product.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCOM
32
FSEL
9
AGNDR
31
TEST
10
VCCR
30
SSPND
11
V R
OUT
(1)
29
XTI
12
V L
OUT
(1)
28
XTO
13
VCCL
27
CK
14
AGNDL
26
DT
15
ZGND+
25
PSEL(2)
16
PGND
VCCP
(3)
HOST(2)
FUNC3
FUNC0
HID0/MS
HID1/MC
HID2/MD
VBUS
D+
D-
VDD
DGND
FUNC1
FUNC2
DOUT
PCM2707CPJT
+
+
C5
C3C4
C6
SUSPEND
R1
R4
R3
R12
R2
(3)
R5
C2
C7
X1
C1
GND
USB ‘B’
Connector
D-
D+
VBUS
(3)
+
C8
+
C9
R10 R11
R6
C11
C10
R7R8R9
Headphone
Power
3.3 V
GND
TAS300x(4)
2
I S I/F
Audio Device
DIN
LRCK
MS
MC
MD
BCK
SYSTEM CLOCK
DOUT
(3)
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A –AUGUST 2011–REVISED JULY 2012
www.ti.com
Typical Circuit Connection 3: DSP Surround Processing Amplifier
Figure 36 illustrates a typical circuit connection for an I2S- and SPI-enabled self-powered application.
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3, C4: 1-μF
ceramic capacitors. C5, C7: 0.1-μF ceramic capacitor and 10-μF electrolytic capacitor. C6: 10-μF electrolytic capacitors. C8, C9: 100-μF
electrolytic capacitors (depending on required frequency response). C10, C11: 0.022-μF ceramic capacitors. R1, R12: 1-MΩresistors. R2, R5:
1.5-kΩresistors. R3, R4: 22-Ωresistors. R6, R7: 16-Ωresistors. R8to R11: 3.3-kΩresistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ±20%, which is the discharge path for C8
and C9.
(2) Descriptor programming through SPI is only available when PSEL and HOST are high.
(3) D+ pull-up must not be activated (high: 3.3 V) while the device is detached from USB or power supply is not applied on VDD and VCCx.
VBUS of USB (5 V) can be used to detect USB power status.
(4) MS must be high until the PCM2707C power supply is ready and the SPI host (the DSP) is ready to send data. Also, the SPI host must
handle the D+ pull-up if the descriptor is programmed through the SPI. D+ pull-up must not be activated (high = 3.3 V) before programming of
the PCM2707C through the SPI is complete.
Figure 36. Self-Powered Application
NOTE
The circuit illustrated in Figure 36 is for information only. The entire board design should
be considered to meet the USB specification as a USB-compliant product.
32 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A –AUGUST 2011–REVISED JULY 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2011) to Revision A Page
• Changed product status from Mixed Status to Production Data .......................................................................................... 1
• Changed Features section to show full compliance with USB2.0 Specification (but still using USB1.1 descriptors) .......... 1
• Changed Description section to show USB2.0 compliance (USB1.1 was absorbed into 2.0 specification) ........................ 1
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM2704CDB ACTIVE SSOP DB 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2704CDBR ACTIVE SSOP DB 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2705CDB ACTIVE SSOP DB 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2705CDBR ACTIVE SSOP DB 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2706CPJT PREVIEW TQFP PJT 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2706CPJTR PREVIEW TQFP PJT 32 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2707CPJT PREVIEW TQFP PJT 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM2707CPJTR PREVIEW TQFP PJT 32 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM2704CDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PCM2705CDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM2704CDBR SSOP DB 28 2000 367.0 367.0 38.0
PCM2705CDBR SSOP DB 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PJT (S-PQFP–N32) PLASTIC QUAD FLATPACK
4203540/A 11/01
1
0,45
0,30
32
7,00 SQ
0,95
1,05
Seating Plane
0,45
0,75
0,25
Gage Plane
0,80 0,20
SQ
9,00
1,00
1,20 0,10
0,05
0,15
0,20
0,09
M
0°– 7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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