General Description
The MAX3784 5Gbps equalizer provides compensation
for transmission-medium losses in up to 40in of FR4. It
is optimized for short run length, balanced codes such
as 8b10b, as found in multiplexed 1.25Gbps Ethernet
systems.
The equalizer uses differential CML data inputs and
outputs. A standby mode provides low power when the
part is not in use. The MAX3784 is available in a 4mm ×
4mm 16-pin QFN package that consumes only 185mW
at +3.3V.
Features
♦Spans 40in (1m) of FR4 PC Board
♦0.18UI Deterministic Jitter Up to 40in
♦Low Power Consumption: 185mW
♦Equalization Reduces Intersymbol Interference
♦Single +3.3V Supply
♦Standby Mode
♦Small 4mm ×4mm 16-Pin QFN Package
MAX3784
5Gbps PC Board Equalizer
________________________________________________________________ Maxim Integrated Products 1
1
2
3
4
5678
9
10
11
16
12
131415
VCC
VCC
VCC
IN+
IN-
GND
GND
GND
N.C.
N.C.
N.C.
N.C.
N.C.
EN
OUT+
OUT-
NOTE: THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND
FOR CORRECT THERMAL AND ELECTRICAL PERFORMANCE.
MAX3784
TOP VIEW
QFN
Pin Configuration
LINE CARD
+3.3V
5Gbps
+3.3V
T/R 1
Rx
Tx
T/R 2
Rx
Tx
T/R 3
Rx
Tx
T/R 4
Rx
Tx
T/R 1
T/R 2
T/R 3
T/R 4
Rx
Tx
1.25Gbps
1.25Gbps
1.25Gbps
1.25Gbps
SWITCH
Rx
Tx
SWITCH CARD
MAX3784
OUT IN
MAX3784
IN OUT
PC BOARD
BACKPLANE
EQUALIZER
EQUALIZER
Typical Application Circuit
19-2565; Rev 1; 5/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-
PACKAGE
PACKAGE
CODE
MAX3784UGE 0°C to +85°C16 QFN G1644-1
Ordering Information
Applications
Chassis Life Extension
MAX3784
5Gbps PC Board Equalizer
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +3V to +3.6V, TA= 0°C to +85°C. Typical values are at VCC = +3.3V and TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC.................................................-0.5V to +6V
Input Voltage............................................(-0.5V) to (VCC + 0.5V)
Continuous Output Current...............................-25mA to +25mA
Continuous Power Dissipation (TA= +85°C)
16-Pin QFN (derate 25mW/°C above +85°C) ............1600mW
Operating Ambient Temperature Range ................0°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EN = low 30
Supply Power EN = high 185 250 mW
10Hz < f < 100Hz 100
100Hz < f < 1MHz 40Supply Noise Tolerance (Note 1)
1MHz < f < 2.5GHz 10
mVP-P
Latency From input to output 200 ps
CML RECEIVER INPUT
Input Voltage Swing VIN Measured differentially at point A in Figure 1
(Note 2) 400 1000 mVP-P
Return Loss 100MHz to 2.5GHz 15 dB
Input Resistance Differential 80 100 120 Ω
EQUALIZATION
20in 0.13 0.21
Residual Deterministic Jitter,
5Gbps Table 1 (Notes 2, 3, 4, 5) 40in 0.18 0.23 UIP-P
20in 0.08 0.14
Residual Deterministic Jitter,
2.5Gbps Table 1 (Notes 2, 3, 4, 5) 40in 0.13 0.28 UIP-P
20in 0.04 0.07
Residual Deterministic Jitter,
1.25Gbps Table 1 (Notes 2, 3, 4, 5) 40in 0.07 0.15 UIP-P
Random Jitter (Notes 5, 6) 1.3 1.9 psRMS
CML TRANSMITTER OUTPUT (into 100Ω ±1Ω)
Output Voltage Swing VODifferential swing, measured differentially at
point C in Figure 1 400 600 mVP-P
Transition Time tf, tr20% to 80% (Notes 5, 8) 30 45 60 ps
Output Resistance Single ended 40 50 60 Ω
MAX3784
5Gbps PC Board Equalizer
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +3.6V, TA= 0°C to +85°C. Typical values are at VCC = +3.3V and TA= +25°C, unless otherwise noted.)
Note 1: Allowed supply noise during jitter tests.
Note 2: Test pattern. This is a combination of K28.5± characters running at the full bit rate and at one-quarter the bit rate. This simu-
lates the multiplexing of four each 1.25Gbps Ethernet data streams.
Pattern (hex) 100 bits
00 FFFF F0F0 FF 0000 0F0F (quarter rate K28.5+, quarter rate K28.5-)
3EB05 (K28.5± 00 1111 1010 11 0000 0101)
Note 3: Difference in deterministic jitter between reference points A and C in Figure 1.
Note 4: Signal source amplitude range is 400mVP-P to 1000mVP-P, differential. Signal is applied differentially at point A as shown in
Figure 1. The deterministic jitter at point B must be from media-induced loss and not from clock-source modulation.
Deterministic jitter is measured at the 50% vertical level of the signal at point C.
Note 5: Guaranteed by design and characterization.
Note 6: Test pattern is K28.5 with 40in trace.
Note 7: On-chip pullup resistor of 40kΩtypical. Negative current indicates equalizer sources current.
Note 8: Using 00 0001 1111 or equivalent pattern. Measured over entire input voltage range, max and min media loss and within 2in
of output pins.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ENABLE CONTROL PIN
Input High Voltage 1.5 V
Input Low Voltage 0.5 V
Input High Current (Note 5) -150 +10 µA
Input Low Current (Note 5) -150 +10 µA
SIGNAL
SOURCE
A
BACKPLANE PC BOARD MAX3784
EQUALIZER
IN OUT
L ≤ 40in
6mil LINE
BC
SMA CONNECTOR SMA CONNECTOR
Figure 1. Test Conditions
PARAMETER CONDITIONS MIN TYP MAX UNITS
Transmission Line Edge-coupled stripline 6 mil
Relative Permittivity FR4 or similar 4.4 4.5
Loss Tangent FR4 or similar 0.02 0.022
Metal Thickness 0.7mil (0.5oz copper) 0.7 mil
Impedance Differential 90 100 110 Ω
Table 1. PC Board Assumptions (PC board material is FR4)
MAX3784
5Gbps PC Board Equalizer
4_______________________________________________________________________________________
Typical Operating Characteristics
(VCC = +3.3V, measurements done at 5Gbps, 800mVP-P board input with 100-bit pattern from Note 2 of the EC Table,T
A= +25°C,
unless otherwise noted.)
55mV/
div
EQUALIZER INPUT EYE DIAGRAM
BEFORE EQUALIZATION AT 5Gbps
(40in, FR4, 6mil STRIPLINE)
MAX3784 toc01
32ps/div
55mV/
div
EQUALIZER OUTPUT EYE DIAGRAM
AFTER EQUALIZATION AT 5Gbps
(40in, FR4, 6mil STRIPLINE)
MAX3784 toc02
32ps/div
55mV/
div
EQUALIZER OUTPUT EYE DIAGRAM
AFTER EQUALIZATION AT 5Gbps
(20in, FR4, 6mil STRIPLINE)
MAX3784 toc03
32ps/div
0
10
5
20
15
25
30
05
DIFFERENTIAL RETURN LOSS
MAX3784 toc04
FREQUENCY (GHz)
RETURN LOSS (dB)
2134
0
30
20
10
40
50
60
70
80
90
100
02010 30 40 50 60
DETERMINISTIC JITTER
vs. LINE LENGTH
MAX3784 toc05
LINE LENGTH (in)
(FR4 6mil STRIPLINE)
DETERMINISTIC JITTER (ps)
1.25GHz
2.5GHz
5GHz
0
30
20
10
40
50
60
70
80
90
100
200 600400 800 1000 1200
DETERMINISTIC JITTER vs. AMPLITUDE
(20in FR4 STRIPLINE)
MAX3784 toc06
INPUT AMPLITUDE (mVP-P)
(FIGURE 1, POINT A)
DETERMINISTIC JITTER (ps)
1.25GHz
2.5GHz
5GHz
0
30
20
10
40
50
60
70
80
90
100
200 600400 800 1000 1200
DETERMINISTIC JITTER vs. AMPLITUDE
(40in FR4 STRIPLINE)
MAX3784 toc07
INPUT AMPLITUDE (mVP-P)
(FIGURE 1, POINT A)
DETERMINISTIC JITTER (ps)
1.25GHz
2.5GHz
5GHz
0
100
300
200
400
500
LATENCY vs. TEMPERATURE
MAX3784 toc08
TEMPERATURE (°C)
LATENCY (ps)
05025 75 100
0
10
20
30
40
50
60
70
80
0255075100
SUPPLY CURRENT vs. TEMPERATURE
MAX3784 toc09
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ICC
ISHUTDOWN
Detailed Description
General Theory of Operation
The MAX3784 adaptive equalizer extends the reach of
transmission lines in high-frequency backplane inter-
connect applications. It can be used for up to 20-bit
CID (coded), NRZ data operating at 5Gbps as found in
4 ×1G Ethernet (5Gbps). Internally, the MAX3784 is
comprised of an equalizer control loop and limiting out-
put driver. The equalizer reduces intersymbol interfer-
ence (ISI), compensating for frequency-dependent
media-induced loss. The equalization control detects
the spectral contents of the input signal and provides a
control voltage to the equalizer core, adapting it to dif-
ferent media. The equalizer operation is optimized for
short-run, DC-balanced transmission codes.
Standby Mode
Standby saves power when the equalizer is not in use.
The EN logic input must be set high or open for normal
operation. Logic low at EN forces the equalizer into the
standby state.
CML Input and Output Buffers
The input and output buffers are implemented using cur-
rent-mode logic (CML). Equivalent circuits are shown in
Figures 3 and 4. For details on interfacing with CML, see
Maxim Application Note HFAN-1.0: Interfacing Between
CML, PECL, and LVDS. The common-mode voltage of
the input and output is above 2.5V. AC-coupling capaci-
tors are required when interfacing this part with devices
terminated in voltages such as 1.8V. Values of 0.10µF or
greater are recommended.
MAX3784
5Gbps PC Board Equalizer
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1, 7, 12 VCC +3.3V Supply Voltage
2IN+ Positive Input, CML
3IN- Negative Input, CML
4, 6, 9 GND Supply Ground
5, 8, 14, 15,
16 N.C. No Connection. Leave unconnected.
10 OUT- Negative Output, CML
11 OUT+ Positive Output, CML
13 EN Enable Equalizer. A logic high or open selects normal operation. A logic low selects low-power
standby mode.
EP Exposed
Pad
Connect to Ground. The exposed pad must be soldered to the circuit board ground plane for proper
thermal and electrical performance.
IN+
IN-
EN
LIMITER
5Gbps EQUALIZER
OUT+
OUT-
VCC
EQUALIZER
OFFSET
CANCELLATION
LOWPASS FILTER 50Ω
100Ω
40kΩ
50Ω
VCC
MAX3784
Figure 2. Functional Diagram
MAX3784
Applications Information
Alternate Data Rates
The MAX3784 is optimized for automatic operation at
5Gbps. Equalization at other data rates, such as
1.25Gbps and 2.5Gbps, is possible. See the Typical
Operating Characteristics for Deterministic Jitter vs.
Line Length and Deterministic Jitter vs. Amplitude for
typical performance at these data rates.
Layout Considerations
Circuit board layout and design can significantly affect
the MAX3784’s performance. Use good high-frequency
design techniques, including minimizing ground induc-
tance and connections and using controlled-imped-
ance transmission lines for the high-frequency data
signals. Route signals differentially to reduce EMI sus-
ceptibility and crosstalk. Solder the exposed pad to
supply ground for proper thermal and electrical opera-
tion.
Place power-supply decoupling capacitors as close as
possible to the VCC pins.
5Gbps PC Board Equalizer
6_______________________________________________________________________________________
50Ω
50Ω
VCC
250µA
Figure 3. CML Input Equivalent Circuit
VCC
50Ω50Ω
OUT+
OUT-
Figure 4. CML Output Equivalent Circuit
MAX3784
5Gbps PC Board Equalizer
_______________________________________________________________________________________ 7
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12,16,20, 24L QFN.EPS
E
1
2
21-0106
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
MAX3784
5Gbps PC Board Equalizer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12,16,20, 24L QFN.EPS
E
1
2
21-0106
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
E
2
2
21-0106
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
