SEPTEMBER 2004
DSC-2967/12
1
©2004 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆High-speed address/chip select access time
– Military: 20/25/35/45/55/70/85/100ns (max.)
– Industrial: 25/35ns (max.)
– Commercial: 15/20/25/35ns (max.)
◆◆
◆◆
◆Low power consumption
◆◆
◆◆
◆Battery backup operation – 2V data retention voltage
(L Version only)
◆◆
◆◆
◆Produced with advanced CMOS high-performance
technology
◆◆
◆◆
◆Inputs and outputs directly TTL-compatible
◆◆
◆◆
◆Three-state outputs
◆◆
◆◆
◆Available in 28-pin DIP, CERDIP and SOJ
◆◆
◆◆
◆Military product compliant to MIL-STD-883, Class B
Description
The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using IDT’s high-performance, high-reliability CMOS
technology.
Address access times as fast as 15ns are available and the circuit
offers a reduced power standby mode. When CS1 goes HIGH or CS2
goes LOW, the circuit will automatically go to, and remain in, a low-
power stand by mode. The low-power (L) version also offers a battery
backup data retention capability at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28-
pin 600 mil CERDIP.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Functional Block Diagram
ADDRESS
DECODER 65,536 BIT
MEMORY ARRAY
I/O CONTROL
2967 drw 01
WE
CS
V
CC
GND
I/O
0
I/O
7
CONTROL
LOGIC
OE
2
CS
1
A
0
A
12
07
IDT7164S
IDT7164L
CMOS Static RAM
64K (8K x 8-Bit)
2
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Pin Configurations
Pin Descriptions
Absolute Maximum Ratings(1)
DIP/SOJ
Top View
Truth Table(1,2,3)
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
2967 drw 02
5
6
7
8
9
10
11
12
A12 1
2
3
424
23
22
21
20
19
18
17
D28-1
D28-3
P28-1
P28-2
SO28-5
13
14
28
27
26
25
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
VCC
WE
A8
A9
A11
OE
A10
CS1
I/O7
16
15
I/O2
GND
I/O6
I/O5
I/O4
I/O3
NC
CS2
,
Name Description
A
0
- A
12
Address
I/O
0
- I/O
7
Data Inp ut/ Outp ut
CS
1
Chip Select
CS
2
Chip Select
WE Write Enable
OE Output Enable
GND Ground
V
CC
Power
29 67 t b l 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
Symbol Rating Com'l. Mil. Unit
V
TERM
(2)
Terminal Vo ltage
with Re s p e ct
to G ND
-0.5 to +7.0 -0.5 to +7.0 V
T
A
Operating
Temperature 0 to +70 -55 to +125
o
C
T
BIAS
Temperature
Under Bias -55 to +125 -65 to +135
o
C
T
STG
Sto rage Te mpe rature -55 to +125 -65 to +150
o
C
P
T
Powe r Dis sip atio n 1. 0 1.0 W
I
OUT
DC Output Curre nt 50 50 mA
2967 tb l 02
NOTES:
1. CS2 will power-down CS1, but CS1 will not power-down CS2.
2. H = VIH, L = VIL, X = don't care.
3. VLC = 0.2V, VHC = VCC - 0.2V
WE CS
1
CS
2
OE I/O Function
X H X X High-Z Deselected - Standby (I
SB
)
X X L X High-Z Deselected - Standby (I
SB
)
XV
HC
V
HC
or
V
LC
X High-Z Deselected - Standby (I
SB1
)
XXV
LC
X High-Z Deselected - Standby (I
SB1
)
H L H H Hig h-Z Outp ut Di sa bl e d
HL HLDATA
OUT
Read Data
LLHXDATA
IN
Wri te Data
2967 tbl 03
Grade Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5V ± 10%
Industrial -40
O
C to +85
O
C0V 5V ± 10%
Commercial 0
O
C to + 70
O
C0V 5V ± 10%
2967 tb l 04
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Inp ut HIGH Vo ltag e 2. 2
____
V
CC
+ 0.5 V
V
IL
Input LOW Vo ltage -0.5
(1)
____
0.8 V
2967 tb l 05
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
3
DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
Capacitance (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itance V
IN
= 0V 8 pF
C
I/O
I/O Capac itanc e V
OUT
= 0V 8 pF
2967 tbl 06
Symbol Parameter Power
7164S15
7164L15 7164S20
7164L20 7164S25
7164L25
Unit
Com'l. Com'l. Mil. Com'l. Ind. Mil.
I
CC1
Operating Power Supply Current
CS
1
= V
IL
, CS
2
= V
IH
, Outp uts Ope n
V
CC
= Max., f
=
0
(2)
S 110 100 110 90 90 110 mA
L 100 90 100 80 80 100
I
CC2
Dynamic Ope rating Current
CS
1
= V
IL
, CS
2
= V
IH
, Outp uts Ope n
V
CC
= Max., f = f
MAX
(2)
S 180 170 180 170 170 180 mA
L 150 150 160 150 150 160
I
SB
Standby Power Supply Current
(TTL L e v el), CS
1
> V
IH
, CS
2
< V
IL
,
Outputs Open, V
CC
= Max., f = f
MAX
(2)
S 20 2020202020 mA
L 3 35335
I
SB1
Full Standby Power Supply Current
(CMOS Le vel ), f = 0
(2)
, V
CC
= Max.
1. CS
1
> V
HC
and CS
2
> V
HC
, or
2. CS
2
< V
LC
S 15 1520151520 mA
L 0.2 0.2 1 0.2 0.2 1
2967 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Symbol Parameter Power
7164S35
7164L35 7164S45
7164L45 7164S55
7164L55 7164S70
7164L70 7164S85/100
7164L85/100
Unit
Com'l. Ind.Mil. Mil. Mil. Mil. Mil.
I
CC1
Operating Power Supply Current
CS
1
= V
IL
, CS
2
= V
IH
, Outputs Op en
V
CC
= Max., f
=
0
(2)
S 90 90 100 100 100 100 100 mA
L80809090909090
I
CC2
Dy nam ic Op e rating Curre n t
CS
1
= V
IL
, CS
2
= V
IH
, Outputs Op en
V
CC
= Max ., f = f
MAX
(2)
S 150 150 160 160 160 160 160 mA
L 130 130 140 130 125 120 120
I
SB
Standby Po wer Supply Current
(TTL Le ve l), CS
1
> V
IH
, CS
2
< V
IL
,
Outp uts Op e n, V
CC
= Max ., f = f
MAX
(2)
S20202020202020
mA
L3355555
I
SB1
Full Standb y Powe r Supply Current
(C MOS L evel), f = 0
(2)
, V
CC
= Max.
1. CS
1
> V
HC
and CS
2
> V
HC
, or
2. CS
2
< V
LC
S15152020202020
mA
L0.20.211111
2967 tbl 08
4
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
DC Electrical Characteristics (VCC = 5.0V ± 10%)
AC Test Conditions
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
2967 drw 03
480Ω
30pF*
255Ω
DATA
OUT
5V
,
2967 drw 04
480Ω
5pF*
255Ω
DATA
OUT
5V
,
Symbol Parameter Test Conditions
IDT7164S IDT7164L
UnitMin. Max. Min. Max.
|I
LI
|Input Leakag e Current V
CC
= Max.,
V
IN
=
GND to V
CC
MIL.
COM' L. & IND
____
____
10
5
____
____
5
2µA
|I
LO
| Output Leakag e Current V
CC
= Max., CS
1
= V
IH
,
V
OUT
= GND to V
CC
MIL.
COM' L. & IND
____
____
10
5
____
____
5
2µA
V
OL
Output Low Voltage I
OL
= 8mA, V
CC
= Min.
____
0.4
____
0.4 V
I
OL
= 10mA , V
CC
= Min.
____
0.5
____
0.5
V
OH
Output High Voltage I
OH
= -4mA, V
CC
= Min. 2.4
____
2.4
____
V
2967 t bl 0 9
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Typ.
(1)
V
CC
@ Max.
V
CC
@
Sym bol Param eter Test Condi tion Min. 2.0V 3.0V 2. 0V 3. 0V Unit
V
DR
V
CC
fo r Data Re te ntio n
____
2.0
____ ____ ____ ____
V
I
CCDR
Data Re tentio n Current MIL.
COM ' L. & IND
____
____
10
10 15
15 200
60 300
90 µA
t
CDR
(3)
Chip Deselect to Data
Re tentio n Time 1. CS
1
> V
HC
CS
2
> V
HC
, or
2. CS
2
< V
LC
0
____ ____ ____ ____
ns
t
R
(3)
Ope ratio n Re co ve ry Time t
RC
(2)
____ ____ ____ ____
ns
I
I
LI
I
(3)
Input Leakage Current
____ ____ ____
22
µA
29 67 t b l 10
Inp ut P ul s e Le v e ls
Inp ut Ris e / Fall Ti me s
Inp ut Ti ming Re fe re nce Le v e ls
Outp ut Refere nce Lev els
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 11
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
NOTES:
1. 0° to +70°C temperature range only.
2. 0° to +70°C and –55°C to +125°C temperature ranges only.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter
7164S15
(1)
7164L15
(1)
7164S20
(2)
7164L20
(2)
7164S25
7164L25 7164S35
7164L35
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cy cle Time 15
____
20
____
25
____
35
____
ns
t
AA
Address Access Time
____
15
____
19
____
25
____
35 ns
t
ACS1
(3)
Chip Se lect-1 Access Time
____
15
____
20
____
25
____
35 ns
t
ACS2
(3)
Chip Se lect-2 Access Time
____
20
____
25
____
30
____
40 ns
t
CLZ1,2
(4)
Chip Se lect-1, 2 to Output in Low-Z 5
____
5
____
5
____
5
____
ns
t
OE
Outp ut Enable to Outp ut Valid
____
7
____
8
____
12
____
18 ns
t
OLZ
(4)
O utput E n a ble to Output in Low-Z 0
____
0
____
0
____
0
____
ns
t
CHZ1,2
(4)
Chip Select-1,2 to Output in High-Z
____
8
____
9
____
13
____
15 ns
t
OHZ
(4)
Outp ut Dis abl e to Outp ut i n Hig h -Z
____
7
____
8
____
10
____
15 ns
t
OH
Outp ut Hold from Address Change 5
____
5
____
5
____
5
____
ns
t
PU
(4)
Chip Select to Power Up Time 0
____
0
____
0
____
0
____
ns
t
PD
(4)
Chi p De se l e ct to Po we r Do wn Ti me
____
15
____
20
____
25
____
35 ns
Wri te Cycle
t
WC
Write Cycle Time 15
____
20
____
25
____
35
____
ns
t
CW1,2
Chip Se lect to End-o f-Write 14
____
15
____
18
____
25
____
ns
t
AW
Address Valid to End-of-Write 14
____
15
____
18
____
25
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 14
____
15
____
21
____
25
____
ns
t
WR1
Write Recovery Time (CS
1
, WE)0
____
0
____
0
____
0
____
ns
t
WR2
Write Recovery Time (CS
2
)5
____
5
____
5
____
5
____
ns
t
WHZ
(4)
Write Enable to Output in High-Z
____
6
____
8
____
10
____
14 ns
t
DW
Data to Write Time Overlap 8
____
10
____
13
____
15
____
ns
t
DH1
Data Hold from Write Tim e (CS
1
, WE)0
____
0
____
0
____
0
____
ns
t
DH2
Data Hol d fr om Wri te Ti me (CS
2
)5
____
5
____
5
____
5
____
ns
t
OW
(4)
Output Active from End-of-Write 4
____
4
____
4
____
4
____
ns
2967 tb l 12
6
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (con't.) (VCC = 5.0V ± 10%, Military Temperature Ranges)
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter
7164S45
7164L45 7164S55
7164L55 7164S70
7164L70 7164S85/100
7164L85/100
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cy cle Time 45
____
55
____
70
____
85/100
____
ns
t
AA
Address Access Time
____
45
____
55
____
70
____
85/100 ns
t
ACS1
(1)
Chip Se lect-1 Access Time
____
45
____
55
____
70
____
85/100 ns
t
ACS2
(1)
Chip Se lect-2 Access Time
____
45
____
55
____
70
____
85/100 ns
t
CLZ1,2
(2)
Chip Se lect-1, 2 to Output in Low-Z 5
____
5
____
5
____
5
____
ns
t
OE
Outp ut Enable to Outp ut Valid
____
25
____
30
____
35
____
40 ns
t
OLZ
(2)
O utput E n a ble to Output in Low- Z 0
____
0
____
0
____
0
____
ns
t
CHZ1,2
(2)
Chip Select-1,2 to Output in High-Z
____
20
____
25
____
30
____
35 ns
t
OHZ
(2)
Outp ut Dis abl e to Outp ut i n Hig h -Z
____
20
____
25
____
30
____
35 ns
t
OH
Outp ut Hold from Address Change 5
____
5
____
5
____
5
____
ns
t
PU
(2)
Chip Select to Power Up Time 0
____
0
____
0
____
0
____
ns
t
PD
(2)
Chi p De se l e ct to Po we r Do wn Ti me
____
45
____
55
____
70
____
85/100 ns
Wri te Cycle
t
WC
Write Cycle Time 45
____
55
____
70
____
85/100
____
ns
t
CW1,2
Chip Se lect to End-o f-Write 33
____
50
____
60
____
75
____
ns
t
AW
Address Valid to End-of-Write 33
____
50
____
60
____
75
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
50
____
60
____
75
____
ns
t
WR1
Write Recovery Time (CS
1
, WE)0
____
0
____
0
____
0
____
ns
t
WR2
Write Recovery Time (CS
2
)5
____
5
____
5
____
5
____
ns
t
WHZ
(2)
Write Enable to Output in High-Z
____
18
____
25
____
30
____
35 ns
t
DW
Data to Write Time Overlap 20
____
25
____
30
____
35
____
ns
t
DH1
Data Hold from Write Tim e (CS
1
, WE)0
____
0
____
0
____
0
____
ns
t
DH2
Data Hol d fr om Wri te Ti me (CS
2
)5
____
5
____
5
____
5
____
ns
t
OW
(2)
Output Active from End-of-Write 4
____
4
____
4
____
4
____
ns
2967 tb l 13
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
7
Timing Waveform of Read Cycle No. 1(1)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 2(1,2,4)
Timing Waveform of Read Cycle No. 3(1,3,4)
ADDRESS
CS
1
OE
DATA
OUT
CS
2
t
RC
t
AA
t
OH
t
ACS2
t
CLZ2(5)
t
OE
t
ACS1
t
CLZ1(5)
t
OLZ (5)
t
CHZ2(5)
t
OHZ (5)
t
CHZ1(5)
DATA VALID
2967 drw 05
2967 drw 06
ADDRESS
DATA
OUT
t
RC
t
AA
t
OH
t
OH
DATA VALID
DATA
OUT
t
ACS2 (5)
CS
1
CS
2
t
CLZ2
t
ACS1 (5)
t
CLZ1
t
PU
t
PD
I
CC
I
SB
t
CHZ2(5)
t
CHZ1(5)
DATA VALID
POWER
SUPPLY
CURRENT
2967 drw 07
8
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1)
NOTES:
1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3 . During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
write pulse width is as short as the specified tWP.
6. Transition is measured ±200mV from steady state.
ADDRESS
t
WC
t
WHZ(6)
2967 drw 08
CS
1
DATA
OUT
CS
2
t
AS
t
AW
t
WR1(2)
WE
t
WP
t
OW(6)
DATA
IN
t
DH1,2
t
DW
DATA VALID
(3) (5)
ADDRESS
CS
1
CS
2
t
WC
t
AS
WE
t
CW
t
WR2(2)
t
AW
DATA
IN
t
DH1,2
t
DW
DATA VALID
t
WR1(2)
(4)
2967 drw 09
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
9
Ordering Information — Commercial
Low VCC Data Retention Waveform
2967 drw 10
DA
T
A
RETENTION
MODE
4.5V 4.5V
V
DR
≥2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS V
DR
X
Power
XX
Speed
XXX
Package X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
Y*
P**
TP*
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
300 mil Plastic DIP (P28-2)
15
20
25
35
S
LStandard Power
Low Power
Device
Type
7164
IDT
Speed in nanoseconds
2967 drw 11
,
* Available for 15ns and 20ns speed grades only.
** Available for 25ns and 35ns speed grades only.
X
GRestricted hazardous substancwe device
10
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Ordering Information — Industrial
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
IIndustrial (–40°C to +85°C)
P
Y600 mil Plastic DIP (P28-1)
300 mil Plastic SOJ (PJ28)
25
35
S
LStandard Power
Low Power
Device
Type
7164
IDT
Speed in nanoseconds
2967 drw 12
,
X
GRestricted hazardous substance device
Ordering Information — Military
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
BMilitary (–55°C to +125°C)
Compliant with MIL-STD-883, Class B
D
TD 600 mil CERDIP (D28-1)
300 mil CERDIP (D28-3)
20*
25
35
45
55
70
85
100**
S
LStandard Power
Low Power
Device
Type
7164
IDT
Speed in nanoseconds
2967 drw 13
* Available only in 600mil CERDIP (D28-1) and 300mil CERDIP
(D28-1) and 300mil CERDIP (D28-3) packaging for a low power.
** Available only in 600 mil CERDIP (D28-1) packaging.
6.42
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
11
Datasheet Document History
1/13/2000 Updated to new format
Pp. 1, 2, 3, 5, 10 Added Industrial Temperature range offerings
Pp. 1, 3, 9 Removed commercial 70ns speed grade offering
Pp. 1, 3, 6, 10 Added 100ns speed grade specification details
Pg. 3 Revised notes and footnotes in DC Electrical tables
Pp. 5, 6 Revised notes and footnotes in AC Electrical tables
Pg. 8 Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes
Pp. 9, 10 Separated Ordering Information into commercial, industrial, and military offerings
Pg. 11 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
12/07/01 Pg. 10 Add PJ28 to Industrial temperature.
09/30/04 Pg. 9,10 Added "restricted hazardous substance device" to ordering information.
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2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054 fax:408-492-8674 800 544-7726
www.idt.com
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