SCAN182245A - Fairchild Semiconductor

December 1993

Revised August 2000

SCAN182245A Non-Inverting Transceiver with 25

Ω

Series Resistor Output s

SCAN182245A

Non-Inverting Transceiver

with 25Ω Series Resistor Output s

General Description

The SCAN182245A is a high performance BiCMOS bidi-

rectional line driver featuring separate data inputs orga-

nized in to du al 9-b it b y te s with byte -or i ent ed ou tpu t e na bl e

and direction control s ignals. This device is comp liant with

IEEE 1149.1 Standard Test Access Port and Boundary

Scan Architecture with the incorporation of the defined

boundary- scan te st log i c an d t est acce ss po rt cons i sting of

Test Data Input (TDI), Test Data Out (TDO), Test Mode

Select (TMS), and Test Clock (TCK).

Features

■High performance BiCMOS technology

■25Ω series resistors in outputs eliminate the need for

external terminating resistors

■Dual output enable control signals

■3-STATE outputs for bus-oriented applications

■25 mil pitch SSOP (Shrink Small Outline Package)

■IEEE 1149.1 (JTAG ) Compliant

■Includes CLAMP, IDCODE and HIGHZ instructions

■Additional instr uctio ns SAM PL E-IN, SAM P LE-OUT and

EXTEST-OUT

■Power Up 3-STATE for hot insert

■Member of Fairchild’s SCAN Products

Ordering Code:

Devices also available in Ta pe and Reel. Speci fy by append ing the suffix let t er “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

SCAN182245ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-1 18, 0.300 Wide

Pin Name s Description

A1(0–8) Side A1 Inputs or 3-STATE Outputs

B1(0–8) Side B1 Inputs or 3-STATE Outputs

A2(0–8) Side A2 Inputs or 3-STATE Outputs

B2(0–8) Side B2 Inputs or 3-STATE Outputs

G1, G2 Output Enable Pins (Active LOW)

DIR1, DIR2 Direction of Data Flow Pins

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SCAN182245A

Tr uth Tables

H = HIGH Voltage Le ve l

L = LOW Voltage Level X = Immaterial

Z = High Impedance

Note 1: Inactive-to-Active transition must occur to enable outputs upon power-up.

Functional Description

The SCAN182245A consists of two sets of nine non-invert-

ing bidirectional buffers with 3-STATE outputs and is

intended for bus-oriented applications. Direction pins (DIR1

and DIR2) LOW enables data from B Ports to A Ports,

when HIGH enables data from A Ports to B Ports. The Out-

put En able pins (G1 and G2 ) when HIGH disables bo th A

and B Ports by placing them in a high impedance condition.

Block Diagrams

A1, B1, G1 and DIR1

Note: BSR stands for Bo undary Sc an Register.

A2, B2, G2 and DIR2

Note: BSR stands f or Bounda ry Scan R egister.

Tap Controller

Inputs A1(0–8) B1(0–8)

(Note 1) DIR1

LLH

←H

LLL

←L

LHH

→H

LHL

→L

HXZZ

Inputs A2(0–8) B2(0–8)

(Note 1) DIR2

LLH

←H

LLL

←L

LHH

→H

LHL

→L

HXZZ

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SCAN182245A

Description of BOUNDARY-SCAN Circuitry

The scan cells u sed in th e BOUNDARY-SCAN register are

one of th e following two types depending upon their loca-

tion. Scan cell TYPE1 is intended to solely observe system

data, while TYPE2 has the additional ability to control sys-

tem data.

Scan cell TYPE1 is located on each system input pin while

scan cell TYPE2 is located at each system output pin as

well as at each of the two internal active-high output enable

signals. AOE controls the activity of the A-outputs while

BOE controls the activity of the B-outputs. Each will acti-

vate th eir respective outputs by lo ading a logic high.

The BYPASS register is a single bit shift register stage

identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

SCAN182245A Product IDCODE

(32-Bit Code per IEEE 1149.1)

The INS TRU CTION r egister is a n 8-b it reg ister which c ap-

tures the default value of 10 000001 ( SAMPLE/P RELOAD)

during the CAPTUR E-IR inst ructi on comm and. Th e benef it

of capturing SAMPLE/PRELOAD as the default instruction

during CAPTURE-IR is that the user is no longer required

to shift in the 8-bit ins truction for SAMPLE/P RELOAD . The

sequence of: CAPTURE-IR → EXIT1-IR → UPDATE-IR

will update the SAMPLE/PRELOAD instruction. For more

information refer to the section on instruction definitions.

Instruction Register Scan Chain Definition

MSB → LSB

Scan Cell TYPE1

Scan Cell TYPE2

Versio

nEntity Part Manufacture

rRequired

Number ID by 1149.1

0000 111111 000000000

000000001111 1

MSB MSB

Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGH-Z

01000001 SAMPLE-IN

01000010 SAMPLE-OUT

00100010 EXTEST-OUT

10101010 IDCODE

11111111 BYPASS

All Others BYPASS

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SCAN182245A

Description of BOUNDARY-SCAN Circuitry (Continued)

BOUNDARY-SCAN Register

Scan Chain Definition (80 Bits in Length)

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SCAN182245A

Description of BOUNDARY-SCAN Circuitry (Continu ed)

Input BOUNDARY-SCAN Register

Scan Chain Definition (40 Bits in Length)

When Sample In is Active

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SCAN182245A

Description of BOUNDARY-SCAN Circuitry (Continued)

Output BOUNDARY-SCAN Register

Scan Chain Definition (40 Bits in Length)

When Sample Out and EXTEST-Out are Active

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SCAN182245A

Description of BOUNDARY-SCAN Circuitry (Continu ed)

BOUNDARY-SCAN Register Definition Index

Bit No. Pin Name Pin No. Pin Type Scan Cell Type Bit No. Pin Name Pin No. Pin Type Scan Cell Type

79 DIR1 3 Input TYPE1

Control

Signals

35 B102 Input TYPE1

B1–in

78 G1 54 Input TYPE1 34 B114 Input TYPE1

77 AOE1Internal TYPE2 33 B125 Input TYPE1

76 BOE1Internal TYPE2 32 B137 Input TYPE1

75 DIR2 26 Input TYPE1 31 B148 Input TYPE1

74 G2 31 Input TYPE1 30 B1510 Input TYPE1

73 AOE2Internal TYPE2 29 B1611 Input TYPE1

72 BOE2Internal TYPE2 28 B1713 Input TYPE1

71 A1055 Input TYPE1

A1–in

27 B1814 Input TYPE1

70 A1153 Input TYPE1 26 B2015 Input TYPE1

B2–in

69 A1252 Input TYPE1 25 B2116 Input TYPE1

68 A1350 Input TYPE1 24 B2218 Input TYPE1

67 A1449 Input TYPE1 23 B2319 Input TYPE1

66 A1547 Input TYPE1 22 B2421 Input TYPE1

65 A1646 Input TYPE1 21 B2522 Input TYPE1

64 A1744 Input TYPE1 20 B2624 Input TYPE1

63 A1843 Input TYPE1 19 B2725 Input TYPE1

62 A2042 Input TYPE1

A2–in

18 B2827 Input TYPE1

61 A2141 Input TYPE1 17 A1055 Output TYPE2

A1–out

60 A2239 Input TYPE1 16 A1153 Output TYPE2

59 A2338 Input TYPE1 15 A1252 Output TYPE2

58 A2436 Input TYPE1 14 A1350 Output TYPE2

57 A2535 Input TYPE1 13 A1449 Output TYPE2

56 A2633 Input TYPE1 12 A1547 Output TYPE2

55 A2732 Input TYPE1 11 A1646 Output TYPE2

54 A2830 Input TYPE1 10 A1744 Output TYPE2

53 B102 Output TYPE2

B1–out

9A1

843 Output TYPE2

52 B114 Output TYPE2 8 A2042 Output TYPE2

A2–out

51 B125 Output TYPE2 7 A2141 Output TYPE2

50 B137 Output TYPE2 6 A2239 Output TYPE2

49 B148 Output TYPE2 5 A2338 Output TYPE2

48 B1510 Output TYPE2 4 A2436 Output TYPE2

47 B1611 Output TYPE2 3 A2535 Output TYPE2

46 B1713 Output TYPE2 2 A2633 Output TYPE2

45 B1814 Output TYPE2 1 A2732 Output TYPE2

44 B2015 Output TYPE2

B2–out

0A2

830 Output TYPE2

43 B2116 Output TYPE2

42 B2218 Output TYPE2

41 B2319 Output TYPE2

40 B2421 Output TYPE2

39 B2522 Output TYPE2

38 B2624 Output TYPE2

37 B2725 Output TYPE2

36 B2827 Output TYPE2

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SCAN182245A

SCAN ABT Live Insertion and Power Cycling Characteristics

SCAN ABT is intended to serve in Live Insertion backplane

applications. It provides 2nd Level Isolation1 which indi-

cates that while external circuitry to control the output

enable pin is unnecessary, there may be a need to imple-

ment differential length backplane connector pins for VCC

and GND. As well, pre-bias circuitry for backplane pins

may be necessary to avoid c apacitive loading effects dur-

ing live insertion.

SCAN ABT provides control of output enable pins during

power cycling via the circuit in Figure 1. It essentially con-

trols the Gn pin u ntil VCC reaches a known level.

During power-up, when VCC ramps through the 0.0V to

0.7V range, all internal device circuitry is inactive, leaving

output and I/O pin s of th e device in hi gh imp edance. From

approximately 0.8V to 1.8V VCC, the Power-On-Reset cir-

cuitry, (POR), in Figure 1 becomes active and maintains

device high impedance mo de. The POR does this by pro-

viding a low from its output that resets the flip-flop The out-

put, Q , of the flip-flop then goes high and disables the NOR

gate fro m an incid ental low in put on the G n pin. After 1.8V

VCC, the POR circuitry becomes inactive and ceases to

control the flip-flop. To brin g the device out of high imped-

ance, the Gn input m us t r ece i v e an i n ac t iv e -t o- ac tive tran s i-

tion, a high-to-low transition on Gn in this case to change

the state of th e flip-flop. Wit h a low on the Q output of the

flip-flop , t he NOR g ate is free to a llow propa gati on of a G n

signal.

During power-down, the Power-On-Reset circuitry will

become acti ve and rese t the flip- fl op at ap pro xima tel y 1.8 V

VCC. Again, the Q output of the flip-flop returns to a high

and disables the NOR gate from inputs from the Gn pin.

The device will then remain in high impedance for the

remaining ramp down from 1.8V to 0.0V VCC.

Some suggestions to help the designer with live insertion

issues:

•The Gn pin can float during power-up until the Power-

On-Reset circuitry becomes inactive.

•The Gn pin can float on power-down only after the

Power-On-Reset has become active.

The description of the functionality of the Power-On-Reset

circuitry can best be described in the diagram of Figure 2.

FIGURE 1.

1Section 7, “Des ign Consi deration fo r F ault Toler ant Backpla nes”, Applicat ion Note AN-881.

SCA N ABT includ es additional power-on reset cir c uit ry not otherwise inclu ded in ABT devices.

FIGURE 2.

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SCAN182245A

Absolute Maximum Ratings(Note 2) Recomm ended Operating

Conditions

Note 2: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 3: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.

DC Electrical Characteristics

Note 4: Guaranteed not tested.

Storage Temperature −65°C to +150°C

Ambient Temperature under Bias −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 3) −0.5V to +7.0V

Input Curr en t (Note 3) −30 mA to +5.0 mA

Voltage Applied to Any Output

in the Disab led or

Power-Off State −0.5V to +5.5V

in the HIGH State −0.5V to VCC

Current Applied to Output

in LOW State (Max) Twi ce the Rated IOL (mA)

DC Latchup Source Current −500 mA

Over Voltage Latchup (I/O) 10V

ESD (HBM) Min. 2000V

Free Air Ambient Temperature −40°C to +85°C

Supply Voltage +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns

Enable Input 20 mV/ns

Symbol Parameter VCC Min Typ Max Units Conditions

VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized LOW Signal

VCD Input Clamp Diode Voltage Min −1.2 V IIN = −18 mA

VOH Output HIGH Voltage Min 2.5 V IOH = −3 mA

Min 2.0 V IOH = −32 mA

VOL Output LOW Voltage Min 0.8 V IOL = 15 mA

IIH Input HIGH Current All Others Max 5 µAV

IN = 2.7V (Note 4)

Max 5 µAV

IN = VCC

TMS, TDI Max 5 µAV

IN = VCC

IBVI Input HIGH Current Breakdown Test Max 7 µAV

IN = 7.0V

IBVIT Input HIGH Current Breakdown Test (I/O) Max 100 µAV

IN = 5.5V

IIL Input LOW Current All Others Max −5µAV

IN = 0.5V (Note 4)

Max −5µAV

IN = 0.0V

TMS, TDI Max −385 µAV

IN = 0.0V

VID Input Leakage Test 0.0 4.75 V IID = 1.9 µA

All Other Pins Grounded

IIH + IOZH Output Leakage Current Max 50 µAV

OUT = 2.7V

IIL + IOZL Output Leakage Current Max −50 µAV

OUT = 0.5V

IOZH Output Leakage Current Max 50 µAV

OUT = 2.7V

IOZL Output Leakage Current Max −50 µAV

OUT = 0.5V

IOS Output Short-Circuit Current Max −100 −275 mA VOUT = 0.0V

ICEX Output HIGH Leakage Current Max 50 µAV

OUT = VCC

IZZ Bus Drainage Test 0.0 100 µAV

OUT = 5.5V, All Others GND

ICCH Power Supply Current Max 250 µAV

OUT = VCC; TDI, TMS = VCC

Max 1.0 mA VOUT = VCC; TDI, TMS = GND

ICCL Power Supply Current Max mA VOUT = LOW; TDI, TMS = VCC

Max 65.8 mA VOUT = LOW; TDI, TMS = GND

ICCZ Power Supply Current Max 250 µA TDI, TMS = VCC

Max 1.0 mA TDI, TMS = GND

ICCT Additional ICC/Input All Other Inputs Max 2.9 mA VIN = VCC − 2.1V

TDI, TMS inputs Max 3 mA VIN = VCC − 2.1V

ICCD Dynamic ICC No Load Max 0.2 mA/ Outputs Open

MHz One Bit Toggling, 50% Duty Cycle

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SCAN182245A

AC Electrical Characteristi cs

Normal Operation:

Note 5: Voltage Range 5.0V ± 0.5V

AC Electrical Characteristi cs

Scan Test Operation

Note 6: Voltage Range 5.0V ± 0.5V

Note: All Propa gation De lay s involvin g TCK are m easured f rom the falling edge of TCK.

Symbol Parameter

VCC TA = −40°C to +85°C

Units

(V) CL = 50 pF

(Note 5) Min Typ Max

tPLH

tPHL Propagation Delay 5.0 1.0 3.1 5.2 ns

A to B, B to A 1.5 4.4 6.5

tPLZ Disable Time 5.0 1.5 4.8 8.6 ns

tPHZ 1.5 5.2 8.9

tPZL Enable Time 5.0 1.5 5.5 9.1 ns

tPZH 1.5 4.6 8.2

Symbol Parameter

VCC TA = −40°C to +85°C

Units

(V) CL = 50 pF

(Note 6) Min Typ Max

tPLH

tPHL Propagation Delay 5.0 2.9 6.1 10.2 ns

TCK to TDO 4.2 7.7 12.1

tPLZ Disable Time 5.0 2.1 5.9 10.7 ns

tPHZ TCK to TDO 3.3 7.4 12.5

tPZL

tPZH Enable Time 5.0 4.6 8.7 13.7 ns

TCK to TDO 2.8 6.8 11.5

tPLH Propagation Delay 5.0 2.8 6.3 10.7 ns

tPHL TCK to Data Out during Update-DR State 4.5 8.2 13.0

tPLH Propagation Delay 5.0 3.3 7.2 12.2 ns

tPHL TCK to Data Out during Update-IR State 5.0 9.3 14.8

tPLH Propagation Delay 5.0 3.7 8.4 14.0 ns

tPHL TCK to Data Out during Test Logic Reset State 5.7 10.8 17.2

tPLZ Disable Time 5.0 2.8 7.6 13.9 ns

tPHZ TCK to Data Out during Update-DR State 3.5 8.4 14.5

tPLZ Disable Time 5.0 3.6 8.7 15.1 ns

tPHZ TCK to Data Out during Update-IR State 3.8 9.2 15.9

tPLZ Disable Time 5.0 4.0 9.8 17.1 ns

tPHZ TCK to Data Out during Test Logic Reset State 4.2 9.9 16.6

tPZL Enable Time 5.0 4.4 9.3 15.5 ns

tPZH TCK to Data Out during Update-DR State 3.0 7.5 13.3

tPZL Enable Time 5.0 5.2 10.7 17.4 ns

tPZH TCK to Data Out during Update-IR State 3.9 9.0 15.4

tPZL Enable Time 5.0 5.7 12.0 19.8 ns

tPZH TCK to Data Out during Test Logic Reset State 3.0 10.2 17.6

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SCAN182245A

AC Operating Requirements

Scan Test Operation

Note 7: Voltage Range 5.0V ± 0.5V

Note 8: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26 , 27–35, 36–44, 45 –53, 54–62, 63–71).

Note 9: Timing pe rt ains to BSR 74 and 78 only.

Note 10: Timing pertains to BSR 75 and 79 only.

Note 11: Timing pertains to BSR 72, 73, 76 and 77 only.

Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.

Capacitance

Note 12: CI/O is measured at f requency f = 1 MHz, per MIL-STD-883B, Method 3012.

Symbol Parameter

VCC TA = −40°C to +85°C

Units

(V) CL = 50 pF

(Note 7) Guaranteed Minimum

tSSetup Time 5.0 4.8 ns

Data to TCK (Note 8)

tHHold Time 5.0 2.5 ns

Data to TCK (Note 8)

tSSetup Time, H or L 5.0 4.1 ns

G1, G2 to TCK (Note 9)

tHHold Time, H or L 5.0 1.7 ns

TCK to G1, G2 (Note 9)

tSSetup Time, H or L 5.0 4.2 ns

DIR1, DIR2 to TCK (Note 10)

tHHold Time, H or L 5.0 2.3 ns

TCK to DIR1, DIR2 (Note 10)

tSSetup Time 5.0 3.8 ns

Internal OE to TCK (Note 11)

tHHold Time, H or L 5.0 2.3 ns

TCK to Internal OE (Note 10)

tSSetup Time, H or L 5.0 8.7 ns

TMS to TCK

tHHold Time, H or L 5.0 1.5 ns

TCK to TMS

tSSetup Time, H or L 5.0 6.7 ns

TDI to TCK

tHHold Time, H or L 5.0 5.0 ns

TCK to TDI

tWPulse Width TCK: H 5.0 10.2 ns

L8.5

fMAX Maximum TCK 5.0 50 MHz

Clock Frequency

tPU Wait Time, 5.0 100 ns

Power Up to TCK

tDN Power Down Delay 0.0 100 ms

Symbol Parameter Typ Units Conditions, TA = 25°C

CIN Input Capacitance 5.9 pF VCC = 0.0V (Gn, DIRn)

CI/O (Note 12) Output Capacitance 13.7 pF VCC = 5.0V (An, Bn)

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SCAN182245A Non-Invertin g Transceiver with 25

Ω

Series Resistor Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Packag e Num b er MS56A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices o r syste ms a re device s or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical com ponent in any compon ent of a life supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilure of the lif e su pp ort

device or system, or to affect its safety or effectiveness.