50 VBIAS 2 GND 3 22 GND 24 GND 23 IN_A 21 GND 50 20 GND 19 GND LNA RFIN 4 50 50 50 50 18 RFOUT GND 5 17 GND 16 VDD_SW 50 PACKAGE BASE GND 20106-001 GND 14 15 VSS_SW IN_B 13 GND 11 GND 10 50 GND 12 VA 6 GND 8 Military Test instrumentation Communications 25 GND ADL8111 VDD_PA 1 VB 7 APPLICATIONS 26 GND 27 OUT_A FUNCTIONAL BLOCK DIAGRAM Small signal gain of 12.5 dB typical from 10 MHz to 500 MHz Broad operation from 10 MHz to 8000 MHz OIP3 of 34 dBm typical from 10 MHz to 500 MHz Internal amplifier state, output P1dB of 17 dBm typical from 5000 MHz to 8000 MHz Noise figure of 2.8 dB typical from 10 MHz to 500 MHz Low insertion loss of 2 dB typical for the internal bypass switch state from 10 MHz to 500 MHz Wide operating temperature range of -40C to +85C RoHS-compliant, 6 mm x 6 mm, 28-terminal LGA ESD rating of 750 V (Class 1B) 28 GND FEATURES OUT_B 9 Data Sheet 10 MHz to 8000 MHz Bypass Amplifier ADL8111 Figure 1. GENERAL DESCRIPTION The ADL8111 is a low noise amplifier (LNA) with a nonreflective bypass switch that provides broadband operation from 10 MHz to 8000 MHz. The ADL8111 provides a low noise figure of 2.8 dB with a high output third-order intercept (OIP3) of 34 dBm simultaneously, which delivers a high dynamic range. The ADL8111 provides a gain of 12.5 dB that is stable over frequency, temperature, power supply, and from device to device. linearity values. The addition of switches also offers high input intercept performance and prevents distortion on the high signal level applications. The ADL8111 has a high electrostatic discharge (ESD) rating of 750 V (Class 1B) and is fully specified for operation across a wide temperature range of -40C to +85C. The ADL8111 is offered in a 6 mm x 6 mm, 28-terminal land grid array (LGA) package. The integration of an amplifier and two single-pole, quadthrow (SP4T) nonreflective switches allows multiple gain and Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL8111 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 External Bypass A State ................................................................7 Applications ....................................................................................... 1 Internal Amplifier State ............................................................. 10 Functional Block Diagram .............................................................. 1 Internal Bypass State .................................................................. 14 General Description ......................................................................... 1 External Bypass B State .............................................................. 16 Revision History ............................................................................... 2 Test Circuits..................................................................................... 19 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 20 Absolute Maximum Ratings ............................................................ 5 Signal Path States for Digital Control Inputs .......................... 20 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 21 Power Derating Curves ................................................................ 5 Recommended Bias Sequencing .............................................. 21 ESD Caution .................................................................................. 5 Evaluation PCB ............................................................................... 22 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board Schematic ..................................................... 23 Interface Schematics..................................................................... 6 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 24 REVISION HISTORY 4/2019Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet ADL8111 SPECIFICATIONS Drain bias voltage (VDD_PA) = +5 V, quiescent drain supply current (IDQ_PA) = 70 mA, negative bias voltage (VSS_SW) = -3.3 V, positive bias voltage (VDD_SW) = +3.3 V, and TA = 25C, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range INTERNAL AMPLIFIER STATE Small Signal Gain Gain Flatness Input Return Loss Output Return Loss Radio Frequency (RF) Settling Time Switching Speed Rise Time (tRISE) and Fall Time (tFALL) Turn On Time (tON) and Turn Off Time (tOFF) Output 1 dB Compression (P1dB) Output Third-Order Intercept (OIP3) Noise Figure VDD_PA INTERNAL BYPASS SWITCH STATE Insertion Loss RF Settling Time Switching Speed tRISE/tFALL tON/tOFF Input Third-Order Intercept (IIP3) 0.5 dB Compression (P0.5dB) P1dB Return Loss On State Return Loss Off State VDD_SW VSS_SW EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES Insertion Loss RF Settling Time Switching Speed tRISE/tFALL tON/tOFF IIP3 P0.5dB P1dB Return Loss On State Return Loss Off State VDD_SW VSS_SW Test Conditions/Comments Min Typ 10 11.2 Max Unit 5000 MHz 12.5 0.5 24 17 dB dB dB dB 50% VA/VB to 0.5 dB margin of final RFOUT 50% VA/VB to 0.1 dB margin of final RFOUT 170 260 ns ns 10% to 90% RFOUT 50% VA/VB to 90%/10% RF 40 160 19.5 34 2.8 5.0 ns ns dBm dBm dB V 17 3.0 5.5 2 dB 50% VA/VB to 0.5 dB margin of final RFOUT 50% VA/VB to 0.1 dB margin of final RFOUT 175 260 ns ns 10% to 90% RFOUT 50% VA/VB to 90%/10% RF 60 160 58 34 35 18 30 3.3 -3.3 ns ns dBm dBm dBm dB dB V V 3.0 -3.6 3.6 -3.0 1 dB 50% VA/VB to 0.5 dB margin of final RFOUT 50% VA/VB to 0.1 dB margin of final RFOUT 180 230 ns ns 10% to 90% RFOUT 50% VA/VB to 90%/10% RF 70 175 59 35.5 36 22 25 3.3 -3.3 ns ns dBm dBm dBm dB dB V V 3.0 -3.6 Rev. 0 | Page 3 of 24 3.6 -3.0 ADL8111 Data Sheet VDD_PA = +5 V, IDQ_PA = 70 mA, VSS_SW = -3.3 V, VDD_SW = +3.3 V, and TA = 25C, unless otherwise noted. Table 2. Parameter OVERALL FUNCTION Frequency Range INTERNAL AMPLIFIER STATE Small Signal Gain Gain Flatness Input Return Loss Output Return Loss P1dB OIP3 Noise Figure VDD_PA INTERNAL BYPASS SWITCH STATE Insertion Loss IIP3 1 P0.5dB Return Loss On State Return Loss Off State VDD_SW VSS_SW EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES 2 Insertion Loss IIP3 P0.5dB Return Loss On State Return Loss Off State VDD_SW VSS_SW 1 2 Test Conditions/Comments Min Typ 5000 10.6 3.0 11.5 1 14 16 17 32 4.5 5.0 3.0 -3.6 2.7 58 34 18 22 3.3 -3.3 3.0 -3.6 1.5 57.5 34.5 17 20 3.3 -3.3 Max Unit 8000 MHz 5.5 dB dB dB dB dBm dBm dB V 3.6 -3.0 dB dBm dBm dB dB V V 3.6 -3.0 dB dBm dBm dB dB V V IIP3 and compression data for the internal bypass and the External Bypass B states is the same as the External Bypass A state data. External Bypass A and External Bypass B were tested with an external 50 transmission line on the evaluation board. Table 3. Total Supply Current by VDD Parameter Supply Current VDD_PA = 5 V VDD_SW = +3.3 V VSS_SW = -3.3 V Min Typ Max 70 30 30 Unit mA A A Table 4. Logic Control Voltage Digital Control Inputs Low High Min 0 1.4 Typ Max 0.8 VDD_SW + 0.3 Rev. 0 | Page 4 of 24 Unit V V Current <1 A typical <1 A typical Data Sheet ADL8111 ABSOLUTE MAXIMUM RATINGS POWER DERATING CURVES Table 5. 0 28 dBm -5 -10 -15 -25 0.01 100 1k 10k Figure 2. Power Derating for RFIN Port 20 dBm 0 0.61 W -2 175C 260C -40C to +125C -40C to +85C Class 1B (Passed 750 V) -4 -6 -8 -10 -12 -14 -18 10k 100k 1M 10M 100M 1G 10G FREQUENCY (Hz) 20106-003 -16 Figure 3. Power Derating for Terminated Path 2 0 POWER DERATING (dB) -2 THERMAL RESISTANCE Thermal performance is directly linked to the printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. -4 -6 -8 -10 -12 -14 JC is the junction to case thermal resistance. -16 Table 6. Thermal Resistance -18 10k 1 10 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. JC 148 1 FREQUENCY (MHz) See the Ordering Guide section for additional information. Package Type CC-28-31 0.1 30 dBm 20106-002 -20 Unit C/W 100k 1M 10M 100M 1G 10G FREQUENCY (Hz) Figure 4. Power Derating for Hot Switching Power JC was determined by simulation under the following conditions: the heat transfer is due solely to thermal conduction from the channel through the ground paddle to the PCB, and the ground paddle is held constant at an 85C operating temperature. ESD CAUTION Rev. 0 | Page 5 of 24 20106-004 1 5 POWER DERATING (dB) RF Input Power (RFIN) - Internal Amplifier State RFIN - Internal Bypass, External Bypass A, External Bypass B RFIN (IN_A, OUT_A, IN_B, and OUT_B) Termination Path (VDD_SW, VA, VB = 3.3 V, VSS = -3.3 V, TA = 85C, and Frequency = 2 GHz) Hot Switch Power Level (IN_A, OUT_A, IN_B, and OUT_B), VDD_SW = 3.3 V, TA = 85C, and Frequency = 2 GHz Hot Switch Power Level (Internal Amplifier State) Continuous Power Dissipation, PDISS (TA = 85C, Derate 6.8 mW/C Above 85C) Channel Temperature Maximum Peak Reflow Temperature (Moisture Sensitivity Level 3, MSL3)1 Storage Temperature Range Operating Temperature Range ESD Sensitivity (Human Body Model) Rating +7 V dc -0.3 V to +3.7 V -3.7 V to +0.3 V -0.3 V to VDD + 0.3 V 20 dBm 31 dBm POWER DERATING (dB) Parameter VDD_PA VDD_SW Range VSS_SW Range Control Voltage (VA, VB) Range ADL8111 Data Sheet GND IN_A GND GND GND OUT_A GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 28 27 26 25 24 23 22 GND 5 VA 6 VB 7 GND GND TOP VIEW (Not to Scale) GND GND 8 9 10 11 12 13 14 GND 20 GND 19 GND 18 RFOUT 17 GND 16 VDD_SW 15 VSS_SW NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 20106-005 4 21 GND RFIN IN_B 3 GND GND ADL8111 GND 2 GND VBIAS GND 1 OUT_B VDD_PA Figure 5. Pin Configuration--Top View Not to Scale Table 7. Pin Function Descriptions Pin No. 1 2 Mnemonic VDD_PA VBIAS 3, 5, 8, 10 to 12, 14, 17, 19 to 22, 24 to 26, 28 4 GND 6, 7 VA, VB 9, 13 OUT_B, IN_B VSS_SW VDD_SW RFOUT 15 16 18 23, 27 RFIN IN_A, OUT_A EPAD Description Drain Bias Voltage. See Table 2. Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the external resistor. See Figure 9 for the interface schematic. RF and DC Ground. See Figure 6 for the interface schematic. RF Input. These pins are dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. Control Input. See Table 2, Table 4, and Table 5. See Figure 8 and Figure 7 for the interface schematics. These pins are dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. Negative Bias Voltage. See Table 2. Positive Bias Voltage. See Table 2. RF Output. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. These pins are dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. Exposed Pad. The exposed pad must be connected to RF and dc ground. INTERFACE SCHEMATICS VA 20106-006 GND Figure 8. VA Interface Schematic Figure 6. GND Interface Schematic VBIAS 20106-109 20106-007 VDD_SW VB 20106-008 VDD_SW Figure 9. VBIAS Interface Schematic Figure 7. VB Interface Schematic Rev. 0 | Page 6 of 24 Data Sheet ADL8111 TYPICAL PERFORMANCE CHARACTERISTICS 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz) -6 -8 -12 -14 -16 -18 -20 -1 -1 -2 -2 INSERTION LOSS (dB) 0 -3 -4 -5 +85C +25C -40C -7 3 4 5 6 7 8 FREQUENCY (GHz) 5 6 7 8 Figure 11. Insertion Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the Test Circuit) +85C +25C -40C -6 -7 -9 2 4 -5 -8 1 3 -4 -9 0 2 -3 -8 -10 1 Figure 13. Broadband Insertion and Return Loss vs. Frequency, State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) 0 -6 +85C +25C -40C -10 FREQUENCY (GHz) -10 20106-011 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 14. Insertion Loss Over Temperature vs. Frequency, State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) 0 0 +85C +25C -40C +85C +25C -40C -5 INPUT RETURN LOSS (dB) -5 -10 -15 -20 -10 -15 -20 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 -25 20106-012 -25 Figure 12. Input Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the Test Circuit) 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 20106-015 INSERTION LOSS (dB) -4 0 Figure 10. Broadband Insertion and Return Loss vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the Test Circuit) INPUT RETURN LOSS (dB) -2 20106-014 RFIN TO OUT_A INPUT RETURN LOSS RFIN TO OUT_A INSERTION LOSS RFIN TO OUT_A OUTPUT RETURN LOSS 0 20106-013 BROADBAND INSERTION AND RETURN LOSS (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 20106-010 BROADBAND INSERTION AND RETURN LOSS (dB) EXTERNAL BYPASS A STATE Figure 15. Input Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Rev. 0 | Page 7 of 24 ADL8111 Data Sheet 0 -10 -15 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 16. Input Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the Test Circuit) -20 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 19. Output Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) 0 -10 -15 -20 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 17. Off State Return Loss vs. Frequency Over Temperature, State = External Bypass A, Path = OUT_B (Refer to Figure 75 for the Test Circuit) +85C +25C -40C -5 -10 -15 -20 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 20106-021 OFF STATE RETURN LOSS (dB) +85C +25C -40C -5 20106-018 OFF STATE RETURN LOSS (dB) -15 0 0 Figure 20. Off State Return Loss vs. Frequency Over Temperature, State = External Bypass A, Path = IN_B (Refer to Figure 75 for the Test Circuit) 0 0 RFIN TO OUT_B +85C RFIN TO OUT_B +25C RFIN TO OUT_B -40C -10 RFIN TO RFOUT +85C RFIN TO RFOUT +25C RFIN TO RFOUT -40C -10 -20 ISOLATION (dB) -20 -30 -40 -50 -30 -40 -50 -60 -60 -70 -70 -80 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 20106-019 ISOLATION (dB) -10 -25 20106-017 -20 +85C +25C -40C -5 Figure 18. Isolation vs. Frequency Over Temperature, State = External Bypass A (Refer to Figure 75 for the Test Circuit) -80 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 21. Isolation vs. Frequency Over Temperature, State = External Bypass A (Refer to Figure 75 for the Test Circuit) Rev. 0 | Page 8 of 24 20106-022 INPUT RETURN LOSS (dB) OUTPUT RETURN LOSS (dB) +85C +25C -40C -5 20106-020 0 Data Sheet ADL8111 0 65 60 IN_B TO RFOUT, +85C IN_B TO RFOUT, +25C IN_B TO RFOUT, -40C -10 55 50 -20 IIP3 (dBm) ISOLATION (dB) 45 -30 -40 -50 40 35 30 +85C +25C -40C 25 20 -60 15 10 -70 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 0 20106-024 0 Figure 22. Isolation vs. Frequency Over Temperature, State = External Bypass A (Refer to Figure 75 for the Test Circuit) 0 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 24. IIP3 vs. Frequency Over Temperature, State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) 40 40 36 36 32 32 28 P1dB (dBm) +85C +25C -40C 24 20 16 20 16 12 12 8 8 4 4 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 0 20106-025 0 +85C +25C -40C 24 0 1 2 3 4 5 FREQUENCY (GHz) Figure 23. P0.5dB vs. Frequency Over Temperature, State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) 6 7 8 20106-027 28 P0.5dB (dBm) 1 20106-026 5 -80 Figure 25. P1dB Compression vs. Frequency Over Temperature, State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Rev. 0 | Page 9 of 24 ADL8111 Data Sheet INTERNAL AMPLIFIER STATE 16 16 12 14 12 4 S11 S21 S22 0 RESPONSE (dB) -4 -8 6 5.5V 5.0V 4.5V 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz) 0 0 14 14 12 12 RESPONSE (dB) 16 6 +85C +25C -40C 4 5 6 7 8 10 8 6 +85C +25C -40C 2 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 20106-030 0.02 FREQUENCY (GHz) Figure 27. Gain Over Temperature vs. Frequency (10 MHz to 100 MHz) State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 -5 INPUT RETURN LOSS (dB) -5 -15 +85C +25C -40C 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 3 4 5 6 7 8 +85C +25C -40C -10 -15 -20 0.10 FREQUENCY (GHz) Figure 28. Input Return Loss vs. Frequency (10 MHz to 100 MHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) -25 20106-031 -20 2 Figure 30. Gain vs. Frequency Over Temperature (100 MHz to 10 GHz) State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 -10 1 FREQUENCY (GHz) 0 -25 0.01 4 4 2 0 0.01 3 Figure 29. Gain vs Frequency Over VDD (100 MHz to 10 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 16 8 2 FREQUENCY (GHz) Figure 26. Broadband Gain and Return Loss vs. Frequency (100 MHz to 10 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 10 1 20106-033 0 20106-029 -20 20106-032 2 -16 RESPONSE (dB) 8 4 -12 INPUT RETURN LOSS (dB) 10 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 20106-034 RESPONSE (dB) 8 Figure 31. Input Return Loss vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) Rev. 0 | Page 10 of 24 Data Sheet ADL8111 0 OUTPUT RETURN LOSS (dB) -10 -15 -20 -25 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 FREQUENCY (GHz) Figure 32. Output Return Loss vs. Frequency (10 MHz to 100 MHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) -15 -20 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 35. Output Return Loss vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 10 +85C +25C -40C 8 8 NOISE FIGURE (dB) 7 6 5 4 3 7 6 5 4 3 2 2 1 1 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 FREQUENCY (GHz) 0 20106-037 0 0.01 +85C +25C -40C 9 Figure 33. Noise Figure vs. Frequency Over Temperature (10 MHz to 100 MHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 20106-040 9 Figure 36. Noise Figure vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 0 RFIN TO OUT_B, +85C RFIN TO OUT_B, +25C RFIN TO OUT_B, -40C -10 RFIN TO OUT_A, +85C RFIN TO OUT_A, +25C RFIN TO OUT_A, -40C -10 -20 ISOLATION (dB) -20 -30 -40 -50 -30 -40 -50 -60 -60 -70 -70 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 34. Isolation vs. Frequency Over Temperature, State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) -80 20106-038 -80 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 20106-041 NOISE FIGURE (dB) -10 -25 10 ISOLATION (dB) +85C +25C -40C -5 20106-039 +85C +25C -40C -5 20106-036 OUTPUT RETURN LOSS (dB) 0 Figure 37. Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) Rev. 0 | Page 11 of 24 ADL8111 Data Sheet 0 0 IN_B TO RFOUT, +85C IN_B TO RFOUT, +25C IN_B TO RFOUT, -40C -10 -10 -30 -40 -50 -50 -60 -70 -70 1 3 2 5 4 6 7 8 FREQUENCY (GHz) Figure 38. Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) -80 0 2 3 4 5 6 7 8 Figure 41. Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 +85C +25C -40C +85C +25C -40C -5 REVERSE ISOLATION (dB) -5 -10 -15 -20 -25 -30 -10 -15 -20 -25 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 -35 20106-044 0.02 Figure 39. Reverse Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 3 4 5 6 7 8 Figure 42. Reverse Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 40 40 35 35 30 30 OIP3 (dBm) 45 20 2 FREQUENCY (GHz) 45 25 1 20106-047 -30 FREQUENCY (GHz) 25 20 15 15 10 10 +85C +25C -40C 0.02 0.03 0.04 0.05 0.06 0.07 FREQUENCY (GHz) 0.08 0.09 +85C +25C -40C 5 0.10 0 20106-045 5 0 0.01 1 FREQUENCY (GHz) 0 -35 0.01 IN_A TO RFOUT, +85C IN_A TO RFOUT, +25C IN_A TO RFOUT, -40C Figure 40. OIP3 vs. Frequency Over Temperature (10 MHz to 100 MHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 20106-048 0 REVERSE ISOLATION (dB) -40 -60 -80 OIP3 (dBm) -30 20106-046 ISOLATION (dB) -20 20106-043 ISOLATION (dB) -20 Figure 43. OIP3 vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) Rev. 0 | Page 12 of 24 ADL8111 45 45 40 40 35 35 30 30 OIP3 (dBm) 25 20 15 20 15 10 5.5V 5.0V 4.5V 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 5.5V 5.0V 4.5V 5 0.10 FREQUENCY (GHz) 0 20106-050 5 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 44. OIP3 vs. Frequency Over VDD (10 MHz to 100 MHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 20106-052 10 Figure 46. OIP3 vs. Frequency Over VDD (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 24 24 20 20 16 16 P1dB (dBm) P1dB (dBm) 25 12 12 8 8 +85C +25C -40C 0 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 5.5V 5.0V 4.5V 4 8 20106-051 4 Figure 45. P1dB vs. Frequency Over Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) Rev. 0 | Page 13 of 24 0 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 47. P1dB vs. Frequency Over VDD (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76 for the Test Circuit) 20106-053 OIP3 (dBm) Data Sheet ADL8111 Data Sheet 0 0 -2 -1 -4 -2 -8 INSERTION LOSS (dB) RFIN TO RFOUT INPUT RETURN LOSS RFIN TO RFOUT INSERTION LOSS RFIN TO RFOUT OUTPUT RETURN LOSS -6 -10 -12 -14 -16 -3 -4 -5 RFIN TO RFOUT, +85C RFIN TO RFOUT, +25C RFIN TO RFOUT, -40C -6 -7 -18 -8 -20 -24 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz) -10 0 3 4 5 6 7 8 Figure 51. Insertion Loss Over Temperature vs. Frequency, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) 0 0 RFIN TO RFOUT OUTPUT RETURN LOSS, +85C RFIN TO RFOUT OUTPUT RETURN LOSS, +25C RFIN TO RFOUT OUTPUT RETURN LOSS, -40C RFIN TO RFOUT INPUT RETURN LOSS, +85C RFIN TO RFOUT INPUT RETURN LOSS, +25C RFIN TO RFOUT INPUT RETURN LOSS, -40C -5 INPUT RETURN LOSS (dB) -5 -10 -15 -15 -20 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) -25 20106-056 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 49. Input Return Loss Over Temperature vs. Frequency, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) 20106-059 -20 -10 Figure 52. Output Return Loss Over Temperature vs. Frequency, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) 0 0 RFIN TO OUT_A, +85C RFIN TO OUT_A, +25C RFIN TO OUT_A, -40C -10 RFIN TO OUT_B, +85C RFIN TO OUT_B, +25C RFIN TO OUT_B, -40C -10 -20 ISOLATION (dB) -20 -30 -40 -50 -30 -40 -50 -60 -70 -70 -80 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 20106-057 -60 Figure 50. Isolation vs. Frequency Over Temperature, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) -80 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 53. Isolation vs. Frequency Over Temperature, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) Rev. 0 | Page 14 of 24 20106-060 INPUT RETURN LOSS (dB) 2 FREQUENCY (GHz) Figure 48. Broadband Insertion and Return Loss vs. Frequency, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) ISOLATION (dB) 1 20106-058 -9 -22 20106-055 BROADBAND INSERTION AND RETURN LOSS (dB) INTERNAL BYPASS STATE Data Sheet ADL8111 0 0 IN_A TO RFOUT, +85C IN_A TO RFOUT, +25C IN_A TO RFOUT, -40C -10 -30 -40 -50 -40 -50 -60 -60 -70 -70 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) -80 0 36 36 32 32 28 28 P1dB (dBm) 40 24 20 +85C +25C -40C 8 4 4 4 5 6 7 8 FREQUENCY (GHz) Figure 55. P0.5dB vs. Frequency Over Temperature, State = Internal Bypass, Path = RFIN to RFOUT (Refer to Figure 77 for the Test Circuit) 45 40 35 30 +85C +25C -40C 15 10 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 20106-064 5 0 2 3 4 5 6 7 8 Figure 58. P1dB vs. Frequency Over Temperature, State = Internal Bypass, Path = RFIN to RFOUT (Refer to Figure 77 for the Test Circuit) 50 0 1 FREQUENCY (GHz) 55 20 8 +85C +25C -40C 0 60 25 7 0 20106-063 3 6 16 8 2 5 20 12 1 4 24 12 0 3 Figure 57. Isolation vs. Frequency Over Temperature, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) 40 0 2 FREQUENCY (GHz) Figure 54. Isolation vs. Frequency Over Temperature, State = Internal Bypass (Refer to Figure 77 for the Test Circuit) 16 1 20106-066 -80 P0.5dB (dBm) -30 20106-065 ISOLATION (dB) -20 20106-062 ISOLATION (dB) -20 IIP3 (dBm) IN_B TO RFOUT, +85C IN_B TO RFOUT, +25C IN_B TO RFOUT, -40C -10 Figure 56. IIP3 vs. Frequency Over Temperature, State = Internal Bypass, Path = RFIN to RFOUT (Refer to Figure 77 for the Test Circuit) Rev. 0 | Page 15 of 24 ADL8111 Data Sheet RFIN TO OUT_B INPUT RETURN LOSS RFIN TO OUT_B INSERTION LOSS RFIN TO OUT_B OUTPUT RETURN LOSS -8 -10 -12 -14 -16 -18 -20 -22 -24 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz) -10 -12 -14 -16 -18 -20 -22 -24 -2 -2 INPUT RETURN LOSS (dB) 0 -5 -6 RFIN TO OUT_B, +85C RFIN TO OUT_B, +25C RFIN TO OUT_B, -40C -7 -6 4 5 6 7 8 FREQUENCY (GHz) Figure 60. Insertion Loss Over Temperature vs. Frequency, State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the Test Circuit) 6 7 8 IN_B TO RFOUT, +85C IN_B TO RFOUT, +25C IN_B TO RFOUT, -40C -7 -9 3 5 -5 -9 2 4 -4 -8 1 3 -3 -8 0 2 Figure 62. Broadband Insertion and Return Loss vs. Frequency, State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) -1 -4 1 FREQUENCY (GHz) 0 -10 -10 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 63. Insertion Loss Over Temperature vs. Frequency, State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) 0 0 RFIN TO OUT_B +85C RFIN TO OUT_B +25C RFIN TO OUT_B -40C IN_B TO RFOUT, +85C IN_B TO RFOUT, +25C IN_B TO RFOUT, -40C -5 INPUT RETURN LOSS (dB) -5 -10 -15 -20 -10 -15 -20 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 -25 20106-071 -25 Figure 61. Input Return Loss Over Temperature vs. Frequency, State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the Test Circuit) 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 20106-074 INPUT RETURN LOSS (dB) -8 -1 -3 IN_B TO RFOUT INPUT RETURN LOSS IN_B TO RFOUT INSERTION LOSS IN_B TO RFOUT OUTPUT RETURN LOSS -6 0 20106-070 INSERTION LOSS (dB) Figure 59. Broadband Insertion and Return Loss vs. Frequency, State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the Test Circuit) -4 20106-072 -6 0 -2 20106-073 -4 BROADBAND INSERTION AND RETURN LOSS (dB) 0 -2 20106-069 BROADBAND INSERTION AND RETURN LOSS (dB) EXTERNAL BYPASS B STATE Figure 64. Input Return Loss Over Temperature vs. Frequency, State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) Rev. 0 | Page 16 of 24 Data Sheet ADL8111 0 -10 -15 -20 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 65. Output Return Loss Over Temperature vs. Frequency, State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the Test Circuit) -15 -20 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 68. Output Return Loss Over Temperature vs. Frequency, State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) 0 -10 -15 -20 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 66. Off State Return Loss vs. Frequency Over Temperature, State = External Bypass B, Path = IN_A (Refer to Figure 78 for the Test Circuit) OUT_A OFF STATE, +85C OUT_A OFF STATE, +25C OUT_A OFF STATE, -40C -5 -10 -15 -20 -25 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 20106-080 OFF STATE RETURN LOSS (dB) IN_A OFF STATE, +85C IN_A OFF STATE, +25C IN_A OFF STATE, -40C -5 20106-077 Figure 69. Off State Return Loss vs. Frequency Over Temperature, State = External Bypass B, Path = OUT_A (Refer to Figure 78 for the Test Circuit) 0 0 IN_A TO RFOUT, +85C IN_A TO RFOUT, +25C IN_A TO RFOUT, -40C -10 RFIN TO OUT_A, +85C RFIN TO OUT_A, +25C RFIN TO OUT_A, -40C -10 -20 ISOLATION (dB) -20 -30 -40 -50 -30 -40 -50 -60 -70 -70 -80 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 20106-078 -60 Figure 67. Isolation vs. Frequency Over Temperature, State = External Bypass B (Refer to Figure 78 for the Test Circuit) -80 0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 70. Isolation vs. Frequency Over Temperature, State = External Bypass B (Refer to Figure 78 for the Test Circuit) Rev. 0 | Page 17 of 24 20106-081 OFF STATE RETURN LOSS (dB) -10 -25 0 ISOLATION (dB) IN_B TO RFOUT, +85C IN_B TO RFOUT, +25C IN_B TO RFOUT, -40C -5 20106-079 OUTPUT RETURN LOSS (dB) RFIN TO OUT_B, +85C RFIN TO OUT_B, +25C RFIN TO OUT_B, -40C -5 20106-076 OUTPUT RETURN LOSS (dB) 0 ADL8111 Data Sheet 0 65 60 RFIN TO RFOUT, +85C RFIN TO RFOUT, +25C RFIN TO RFOUT, -40C -10 55 50 -20 -30 IIP3 (dBm) ISOLATION (dB) 45 -40 -50 40 35 30 +85C +25C -40C 25 20 -60 15 10 -70 1 2 3 4 5 6 7 8 FREQUENCY (GHz) 0 20106-083 0 Figure 71. Isolation vs. Frequency Over Temperature, State = External Bypass B (Refer to Figure 78 for the Test Circuit) 0 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 73. IIP3 vs. Frequency Over Temperature, State = External Bypass B, Path = RFIN to OUT_B or IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) 40 40 36 36 32 32 28 28 20 16 20 16 12 12 8 8 4 4 0 0 1 2 3 4 5 FREQUENCY (GHz) 6 7 8 +85C +25C -40C 24 0 0 1 2 3 4 5 FREQUENCY (GHz) Figure 72. P0.5dB vs. Frequency Over Temperature, State = External Bypass B, Path = RFIN to OUT_B or IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) 6 7 8 20106-086 24 P0.5dB (dBm) +85C +25C -40C 20106-084 P0.5dB (dBm) 1 20106-085 5 -80 Figure 74. P0.5dB vs. Frequency Over Temperature, State = External Bypass B, Path = RFIN to OUT_B or IN_B to RFOUT (Refer to Figure 78 for the Test Circuit) Rev. 0 | Page 18 of 24 Data Sheet ADL8111 TEST CIRCUITS OUT_A OUT_A IN_A RFIN IN_A RFOUT AMP AMP OUT_B IN_A AMP OUT_A IN_A AMP RFOUT RFIN OUT_B IN_B 20106-028 RFIN IN_B Figure 77. Internal Bypass State Figure 75. External Bypass A State OUT_A 20106-054 IN_B RFOUT RFOUT OUT_B IN_B Figure 78. External Bypass B State Figure 76. Internal Amplifier State Rev. 0 | Page 19 of 24 20106-068 OUT_B 20106-009 RFIN ADL8111 Data Sheet THEORY OF OPERATION OUT_A RFIN AMP OUT_B RFOUT IN_B Figure 80. Internal Amplifier, VA = 0 V and VB = 3.3 V OUT_A IN_A AMP SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS RFIN RFOUT IN_A OUT_B RFOUT RFIN 20106-089 OUT_A IN_A 20106-088 The ADL8111 integrates an amplifier with two switching networks located at the RF input and output. The internal amplifier uses a gallium arsenide (GaAs) LNA die from the HMC8411. The switching network employs robust silicon-oninsulator (SOI) technology for fast switching and a short settling time. This integrated solution has four different signal path states available: an internal amplifier, an internal bypass, External Bypass A, and External Bypass B. Signal path states are controlled through the digital pins, VA and VB, using 1.4 V high and 0 V low logic (see Figure 79 to Figure 82). The internal amplifier is biased up by applying 5 V to VDD_PA, and the internal switches are biased up by applying +3.3 V and -3.3 V to VDD_SW and VSS_SW, respectively. DC bias to the switches is independent of the LNA. Turning off bias to VDD_PA to the LNA provides better isolation between RF ports. IN_B Figure 81. Internal Bypass, VA = 3.3 V and VB = 0 V AMP OUT_B IN_B 20106-087 OUT_A IN_A AMP Figure 79. External Bypass A, VA = 0 V and VB = 0 V RFOUT OUT_B IN_B 20106-090 RFIN Figure 82. External Bypass B, VA = 3.3 V and VB = 3.3 V Table 8. Truth Table State Name External Bypass A Internal Amplifier Internal Bypass External Bypass B VA Low Low High High Digital Control Inputs VB Low High Low High Signal Path State RFIN to OUT_A, IN_A to RFOUT RFIN to RFOUT through amplifier path RFIN to RFOUT through bypass path RFIN to OUT_B, IN_B to RFOUT Rev. 0 | Page 20 of 24 Data Sheet ADL8111 APPLICATIONS INFORMATION The basic connections for operating the ADL8111 are shown in Figure 83. A 5 V dc bias is supplied to the amplifier on VDD_PA, +3.3 V dc bias supply to VDD_SW and -3.3 V dc bias supply to VSS_SW. VA and VB are digital inputs set path states shown in Table 7. High logic state is set at 1.4 V and low logic state is set at 0 V. The LNA within the ADL8111 operates in self-biased mode where the VBIAS pin is connected to a 560 external resistor to achieve a 70 mA supply current. Refer to Table 9 for the recommended resistor values to achieve different IDQ currents. RECOMMENDED BIAS SEQUENCING During Power-Up The recommended bias sequence during power-up follows: 1. 2. 3. 4. Set VDD_SW = 3.3 V. Set VSS_SW = -3.3 V. Set VDD_PA = 5 V. Apply the RF signal. During Power-Down The recommended bias sequence during power-down follows: 1. 2. 3. 4. Turn off the RF signal. Set VDD_PA = 0 V. Set VSS_SW = 0 V. Set VDD_SW = 0 V. The bias conditions, VDD_PA = 5 V at IDQ = 70 mA, is the recommended operating point to achieve optimum performance. The data used in this data sheet was taken with the recommended bias condition. Using the HMC8411 with different bias conditions can provide different performance than what is shown in the Typical Performance Characteristics section. Table 9. Recommended Bias Resistor Values at VDD_PA = 5 V RBIAS () 226 560 1.1 k Rev. 0 | Page 21 of 24 IDQ (mA) 85 70 55 ADL8111 Data Sheet EVALUATION PCB The ADL8111-EVALZ is the evaluation board for the ADL8111 with fully populated components as shown in Figure 83 and its schematic shown in Figure 84. The board is fabricated with four layers using Rogers 4350. Signal lines have characteristic impedance of 50 . Package ground leads and the exposed paddle are soldered to the ground plane. Adequate amounts of via holes connect the top and bottom ground planes. The evaluation board is available from Analog Devices, Inc., upon request. Gerber files can be found on the ADL8111 product webpage. GND VDD_PA GND VDD_PA J7 J8 J1 J2 J9 J10 VSS_SW VB VDD_SW 20106-091 VA Figure 83. ADL8111-EVALZ Evaluation Board PCB Rev. 0 | Page 22 of 24 Data Sheet ADL8111 EVALUATION BOARD SCHEMATIC R1 560 J1 VBIAS 22 23 24 50 1 10pF U1 50 PAD3 2 21 3 20 4 RFIN J4 - VA J4 - VB 19 50 5 50 6 RFOUT 17 50 7 50 16 PAD1 J4 - VDD_SW 15 J4 - VSS_SW PAD2 14 13 12 11 50 10 9 8 50 J9 J10 OUT_B IN_B Figure 84. ADL8111-EVALZ Evaluation Board Schematic Table 10. Bill of Material for Evaluation PCB ADL8111-EVALZ Item J1, J2, J7, J8, J9, J10 J3, J4 U1 C1 R1 J2 18 Description SRI SMA RF connectors DC header pins ADL8111 10 pF, 5% tolerance, 0201, ceramic capacitor 560 , 1/16 W, 0402, thick film resistor Rev. 0 | Page 23 of 24 GND 20106-092 C1 25 VDD_PA 26 IN_A 27 OUT_A 28 J8 PAD4 J3 - VDD_PA J7 ADL8111 Data Sheet OUTLINE DIMENSIONS 0.35 0.30 0.25 0.50 0.45 0.40 PIN 1 INDICATOR 28 22 1 21 3.90 REF SQ 3.90 BSC SQ 15 0.65 BSC TOP VIEW PKG-005742 1.43 MAX SIDE VIEW 7 14 8 BOTTOM VIEW 0.10 REF 1.00 REF FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.366 0.326 0.286 SEATING PLANE 1.83 BSC SQ 03-02-2018-A PIN 1 CORNER AREA 6.10 6.00 5.90 Figure 85. 28-Terminal Land Grid Array [LGA] (CC-28-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL8111ACCZN ADL8111ACCZN-R7 ADL8111-EVALZ 1 2 Temperature Range -40C to +85C -40C to +85C MSL Rating 2 MSL3 MSL3 Package Description 28-Terminal Land Grid Array [LGA] 28-Terminal Land Grid Array [LGA] Evaluation Board All models are RoHS compliant parts. See the Absolute Maximum Ratings section for additional information. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D20106-0-4/19(0) Rev. 0 | Page 24 of 24 Package Option CC-28-3 CC-28-3