10 MHz to 8000 MHz Bypass Amplifier
Data Sheet ADL8111
Rev. 0 Document Feedback
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FEATURES
Small signal gain of 12.5 dB typical from 10 MHz to 500 MHz
Broad operation from 10 MHz to 8000 MHz
OIP3 of 34 dBm typical from 10 MHz to 500 MHz
Internal amplifier state, output P1dB of 17 dBm typical from
5000 MHz to 8000 MHz
Noise figure of 2.8 dB typical from 10 MHz to 500 MHz
Low insertion loss of 2 dB typical for the internal bypass
switch state from 10 MHz to 500 MHz
Wide operating temperature range of −40°C to +85°C
RoHS-compliant, 6 mm × 6 mm, 28-terminal LGA
ESD rating of ±750 V (Class 1B)
APPLICATIONS
Military
Test instrumentation
Communications
FUNCTIONAL BLOCK DIAGRAM
50Ω 50Ω
50Ω 50Ω
50Ω 50Ω
PACKAGE
BASE
GND
ADL8111
28
25
26
27
22
23
24
IN_A
GND
GND
GND
GND
OUT_
A
GND
18
19
20
21
17
16
15
VDD_SW
VSS_SW
GND
RFOUT
GND
GND
GND
2
1
3
4
5
6
7
VA
VB
GND
RFIN
VBIAS
GND
V
DD_P
A
8
9
10
11
13
14
12
OUT_B
GND
GND
GND
IN_B
GND
GND
LNA
50Ω 50Ω
20106-001
Figure 1.
GENERAL DESCRIPTION
The ADL8111 is a low noise amplifier (LNA) with a nonreflective
bypass switch that provides broadband operation from 10 MHz
to 8000 MHz. The ADL8111 provides a low noise figure of
2.8 dB with a high output third-order intercept (OIP3) of 34 dBm
simultaneously, which delivers a high dynamic range. The
ADL8111 provides a gain of 12.5 dB that is stable over frequency,
temperature, power supply, and from device to device.
The integration of an amplifier and two single-pole, quad-
throw (SP4T) nonreflective switches allows multiple gain and
linearity values. The addition of switches also offers high input
intercept performance and prevents distortion on the high
signal level applications.
The ADL8111 has a high electrostatic discharge (ESD) rating of
±750 V (Class 1B) and is fully specified for operation across a wide
temperature range of −40°C to +85°C. The ADL8111 is offered
in a 6 mm × 6 mm, 28-terminal land grid array (LGA) package.
ADL8111 Data Sheet
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Power Derating Curves ................................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics..................................................................... 6
Typical Performance Characteristics ............................................. 7
External Bypass A State ................................................................7
Internal Amplifier State ............................................................. 10
Internal Bypass State .................................................................. 14
External Bypass B State .............................................................. 16
Test Circuits ..................................................................................... 19
Theory of Operation ...................................................................... 20
Signal Path States for Digital Control Inputs .......................... 20
Applications Information .............................................................. 21
Recommended Bias Sequencing .............................................. 21
Evaluation PCB ............................................................................... 22
Evaluation Board Schematic ..................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
4/2019―Revision 0: Initial Version
Data Sheet ADL8111
Rev. 0 | Page 3 of 24
SPECIFICATIONS
Drain bias voltage (VDD_PA) = +5 V, quiescent drain supply current (IDQ_PA) = 70 mA, negative bias voltage (VSS_SW) = −3.3 V, positive
bias voltage (VDD_SW) = +3.3 V, and TA = 25°C, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 10 5000 MHz
INTERNAL AMPLIFIER STATE
Small Signal Gain 11.2 12.5 dB
Gain Flatness ±0.5 dB
Input Return Loss 24 dB
Output Return Loss 17 dB
Radio Frequency (RF) Settling Time
50% VA/VB to 0.5 dB margin of final RFOUT 170 ns
50% VA/VB to 0.1 dB margin of final RFOUT 260 ns
Switching Speed
Rise Time (tRISE) and Fall Time (tFAL L ) 10% to 90% RFOUT 40 ns
Turn On Time (tON) and Turn Off Time (tOFF) 50% VA/VB to 90%/10% RF 160 ns
Output 1 dB Compression (P1dB) 17 19.5 dBm
Output Third-Order Intercept (OIP3) 34 dBm
Noise Figure 2.8 dB
VDD_PA 3.0 5.0 5.5 V
INTERNAL BYPASS SWITCH STATE
Insertion Loss 2 dB
RF Settling Time
50% VA/VB to 0.5 dB margin of final RFOUT 175 ns
50% VA/VB to 0.1 dB margin of final RFOUT
260
ns
Switching Speed
tRISE/tFAL L 10% to 90% RFOUT 60 ns
tON/tOFF 50% VA/VB to 90%/10% RF 160 ns
Input Third-Order Intercept (IIP3) 58 dBm
0.5 dB Compression (P0.5dB) 34 dBm
P1dB 35 dBm
Return Loss On State 18 dB
Return Loss Off State 30 dB
VDD_SW 3.0 3.3 3.6 V
VSS_SW −3.6 −3.3 −3.0 V
EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES
Insertion Loss 1 dB
RF Settling Time
50% VA/VB to 0.5 dB margin of final RFOUT
180
ns
50% VA/VB to 0.1 dB margin of final RFOUT 230 ns
Switching Speed
tRISE/tFALL 10% to 90% RFOUT 70 ns
tON/tOFF 50% VA/VB to 90%/10% RF 175 ns
IIP3 59 dBm
P0.5dB 35.5 dBm
P1dB 36 dBm
Return Loss On State 22 dB
Return Loss Off State 25 dB
VDD_SW 3.0 3.3 3.6 V
VSS_SW −3.6 −3.3 −3.0 V
ADL8111 Data Sheet
Rev. 0 | Page 4 of 24
VDD_PA = +5 V, IDQ_PA = 70 mA, VSS_SW = −3.3 V, VDD_SW = +3.3 V, and TA = 25°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 5000 8000 MHz
INTERNAL AMPLIFIER STATE
Small Signal Gain 10.6 11.5 dB
Gain Flatness ±1 dB
Input Return Loss 14 dB
Output Return Loss 16 dB
P1dB 17 dBm
OIP3 32 dBm
Noise Figure 4.5 dB
VDD_PA 3.0 5.0 5.5 V
INTERNAL BYPASS SWITCH STATE
Insertion Loss 2.7 dB
IIP31 58 dBm
P0.5dB
34
dBm
Return Loss On State 18 dB
Return Loss Off State 22 dB
VDD_SW 3.0 3.3 3.6 V
VSS_SW −3.6 −3.3 −3.0 V
EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES 2
Insertion Loss 1.5 dB
IIP3 57.5 dBm
P0.5dB 34.5 dBm
Return Loss On State 17 dB
Return Loss Off State 20 dB
VDD_SW 3.0 3.3 3.6 V
VSS_SW −3.6 −3.3 −3.0 V
1 IIP3 and compression data for the internal bypass and the External Bypass B states is the same as the External Bypass A state data.
2 External Bypass A and External Bypass B were tested with an external 50 Ω transmission line on the evaluation board.
Table 3. Total Supply Current by VDD
Parameter Min Typ Max Unit
Supply Current
VDD_PA = 5 V 70 mA
VDD_SW = +3.3 V 30 μA
VSS_SW = −3.3 V 30 μA
Table 4. Logic Control Voltage
Digital Control Inputs Min Typ Max Unit Current
Low 0 0.8 V <1 μA typical
High 1.4 VDD_SW + 0.3 V <1 μA typical
Data Sheet ADL8111
Rev. 0 | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VDD_PA +7 V dc
VDD_SW Range
−0.3 V to +3.7 V
VSS_SW Range −3.7 V to +0.3 V
Control Voltage (VA, VB) Range −0.3 V to VDD +
0.3 V
RF Input Power (RFIN) − Internal Amplifier State 20 dBm
RFIN − Internal Bypass,
External Bypass A, External Bypass B
31 dBm
RFIN (IN_A, OUT_A, IN_B, and OUT_B)
Termination Path (VDD_SW, VA, VB = 3.3 V,
VSS = −3.3 V, TA = 85°C, and Frequency =
2 GHz)
28 dBm
Hot Switch Power Level (IN_A, OUT_A, IN_B,
and OUT_B), VDD_SW = 3.3 V, TA = 85°C,
and Frequency = 2 GHz
30 dBm
Hot Switch Power Level (Internal Amplifier
State)
20 dBm
Continuous Power Dissipation, PDISS
(TA = 85°C, Derate 6.8 mW/°C Above 85°C)
0.61 W
Channel Temperature 175°C
Maximum Peak Reflow Temperature
(Moisture Sensitivity Level 3, MSL3)1
260°C
Storage Temperature Range −40°C to +125°C
Operating Temperature Range −40°C to +85°C
ESD Sensitivity (Human Body Model)
Class 1B
(Passed ±750 V)
1 See the Ordering Guide section for additional information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to the printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package Type θJC Unit
CC-28-31 148 °C/W
1 θJC was determined by simulation under the following conditions: the heat
transfer is due solely to thermal conduction from the channel through the
ground paddle to the PCB, and the ground paddle is held constant at an
85°C operating temperature.
POWER DERATING CURVES
5
0
–5
–10
–15
–20
–25
0.01 0.1 110 100 1k 10k
POWER DE RATING (d B)
FREQUENCY (MHz)
20106-002
Figure 2. Power Derating for RFIN Port
20106-003
2
0
–4
–6
–8
–2
–10
–12
–14
–16
–1810k 100k 1M 10M 100M 1G 10G
POWER DE RATING (d B)
FREQUENCY ( Hz )
Figure 3. Power Derating for Terminated Path
20106-004
2
0
–4
–6
–8
–2
–10
–12
–14
–16
–1810k 100k 1M 10M 100M 1G 10G
POWER DE RATING (d B)
FREQUENCY ( Hz )
Figure 4. Power Derating for Hot Switching Power
ESD CAUTION
ADL8111 Data Sheet
Rev. 0 | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
GND GND
GND GND
2
3
4
5
6
7
VDD_PA
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF AND DC GROUND.
VBIAS
GND
RFIN
GND
VA
VB
21
20
19
18
17
16
15
GND
GND
GND
RFOUT
GND
VDD_SW
VSS_SW
8 9 10 11 12 13 14
GND
OUT_B
GND
GND
GND
IN_B
GND
28 27 26 25 24 23 22
GND
OUT_A
GND
GND
GND
IN_A
GND
20106-005
ADL8111
TOP VIEW
(No t t o Scal e)
Figure 5. Pin Configuration—Top View Not to Scale
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD_PA Drain Bias Voltage. See Table 2.
2 VBIAS Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the
external resistor. See Figure 9 for the interface schematic.
3, 5, 8, 10 to 12, 14, 17, 19 to
22, 24 to 26, 28
GND
RF and DC Ground. See Figure 6 for the interface schematic.
4 RFIN RF Input. These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required
if the RF line potential is not equal to 0 V dc.
6, 7 VA, VB Control Input. See Table 2, Table 4, and Table 5. See Figure 8 and Figure 7 for the interface
schematics.
9, 13 OUT_B,
IN_B
These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
15 VSS_SW Negative Bias Voltage. See Table 2.
16 VDD_SW Positive Bias Voltage. See Table 2.
18 RFOUT RF Output. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if
the RF line potential is not equal to 0 V dc.
23, 27 IN_A,
OUT_A
These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS
GND
20106-006
Figure 6. GND Interface Schematic
VDD_SW
VB
20106-007
Figure 7. VB Interface Schematic
VDD_SW
VA
20106-008
Figure 8. VA Interface Schematic
VBIAS
20106-109
Figure 9. VBIAS Interface Schematic
Data Sheet ADL8111
Rev. 0 | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
EXTERNAL BYPASS A STATE
0
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
010987654321
BROADBAND I NS E RTI ON AND RET URN LO S S ( dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_A INP UT RETURN LOSS
RFIN TO OUT_A INSERTION LOSS
RFIN TO OUT_A OUTPUT RETURN LOSS
20106-010
Figure 10. Broadband Insertion and Return Loss vs. Frequency,
State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the
Test Circuit)
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0 87654321
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-011
Figure 11. Insertion Loss Over Temperature vs. Frequency,
State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-012
Figure 12. Input Return Loss Over Temperature vs. Frequency,
State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the
Test Circuit)
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0 87654321 FRE QUENCY ( GHz)
20106-013
+85°C
+25°C
–40°C
BROADBAND I NS E RTI ON AND RET URN LO S S ( dB)
Figure 13. Broadband Insertion and Return Loss vs. Frequency,
State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the
Test Circuit)
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0 87654321
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-014
Figure 14. Insertion Loss Over Temperature vs. Frequency,
State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-015
Figure 15. Input Return Loss Over Temperature vs. Frequency,
State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the
Test Circuit)
ADL8111 Data Sheet
Rev. 0 | Page 8 of 24
0
–25
–20
–15
–10
–5
08
76
54
3
21
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-017
Figure 16. Input Return Loss Over Temperature vs. Frequency,
State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the
Test Circuit)
0
–25
–20
–15
–10
–5
08765
43
2
1
OFF STATE RETURN LOSS (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-018
Figure 17. Off State Return Loss vs. Frequency Over Temperature,
State = External Bypass A, Path = OUT_B (Refer to Figure 75 for the Test
Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B +85° C
RFIN TO O UT_B +25° C
RFIN TO O UT_B –40°C
20106-019
Figure 18. Isolation vs. Frequency Over Temperature,
State = External Bypass A (Refer to Figure 75 for the Test Circuit)
0
–25
–20
–15
–10
–5
0 8
7
65
4
3
2
1
OUTPUT RE TURN L OSS ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-020
Figure 19. Output Return Loss Over Temperature vs. Frequency,
State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0876
5
4
32
1
OFF STATE RETURN LOSS (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-021
Figure 20. Off State Return Loss vs. Frequency Over Temperature,
State = External Bypass A, Path = IN_B (Refer to Figure 75 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO RFOUT +85°C
RFIN TO RFOUT +25°C
RFIN TO RF OUT –40°C
20106-022
Figure 21. Isolation vs. Frequency Over Temperature,
State = External Bypass A (Refer to Figure 75 for the Test Circuit)
Data Sheet ADL8111
Rev. 0 | Page 9 of 24
0
–80
–70
–60
–50
–40
–30
–20
–10
0 8
7
65
4
32
1
ISOLATION (dB)
FRE Q UE NCY ( GHz)
IN_B TO RFO UT, + 85°C
IN_B TO RFO UT, + 25°C
IN_B TO RFO UT, –40°C
20106-024
Figure 22. Isolation vs. Frequency Over Temperature,
State = External Bypass A (Refer to Figure 75 for the Test Circuit)
0
4
8
12
16
20
24
28
32
36
40
0123 4 5 6 7 8
P0.5dB (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-025
Figure 23. P0.5dB vs. Frequency Over Temperature,
State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to
Figure 75 for the Test Circuit)
65
0
10
20
30
40
50
60
5
15
25
35
45
55
0 87654321
II P 3 ( dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-026
Figure 24. IIP3 vs. Frequency Over Temperature,
State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to
Figure 75 for the Test Circuit)
0
4
8
12
16
20
24
28
32
36
40
012345678
P1dB (dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
20106-027
Figure 25. P1dB Compression vs. Frequency Over Temperature,
State = External Bypass A, Path = RFIN to OUT_A or IN_A to RFOUT (Refer to
Figure 75 for the Test Circuit)
ADL8111 Data Sheet
Rev. 0 | Page 10 of 24
INTERNAL AMPLIFIER STATE
16
–20
–4
12
–12
4
–8
8
–16
0
010
987654321
RESPONSE (dB)
FRE Q UE NCY ( GHz)
S11
S21
S22
20106-029
Figure 26. Broadband Gain and Return Loss vs. Frequency (100 MHz to 10 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
16
0
2
6
10
14
4
8
12
0.01 0.100.09
0.08
0.07
0.06
0.050.040.03
0.02
RESPONSE (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-030
Figure 27. Gain Over Temperature vs. Frequency (10 MHz to 100 MHz)
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0
–25
–15
–5
–20
–10
0.01 0.100.090.080.070.060.050.040.030.02
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-031
Figure 28. Input Return Loss vs. Frequency (10 MHz to 100 MHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
087
6
54
32
1FRE Q UE NCY ( GHz)
16
0
2
6
10
14
4
8
12
RESPONSE (dB)
20106-032
5.5V
5.0V
4.5V
Figure 29. Gain vs Frequency Over VDD (100 MHz to 10 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0 87654321 FRE QUENCY ( GHz)
+85°C
+25°C
–40°C
16
0
2
6
10
14
4
8
12
RESPONSE (dB)
20106-033
Figure 30. Gain vs. Frequency Over Temperature (100 MHz to 10 GHz)
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0 87654321 FRE QUENCY ( GHz)
0
–25
–15
–5
–20
–10
INPUT RETURN L OSS ( dB)
+85°C
+25°C
–40°C
20106-034
Figure 31. Input Return Loss vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
Data Sheet ADL8111
Rev. 0 | Page 11 of 24
0.01 0.10
0.090.08
0.070.06
0.050.040.030.02 FREQUENCY ( GHz)
+85°C
+25°C
–40°C
0
–25
–15
–5
–20
–10
OUTPUT RE TURN L OSS ( dB)
20106-036
Figure 32. Output Return Loss vs. Frequency (10 MHz to 100 MHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0.01 0.100.090.080.070.06
0.050.040.030.02 FREQUENCY ( GHz)
+85°C
+25°C
–40°C
10
0
1
2
3
4
5
6
7
8
9
NOISE FIGURE (dB)
20106-037
Figure 33. Noise Figure vs. Frequency Over Temperature (10 MHz to 100 MHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B, + 85°C
RFIN TO O UT_B, + 25°C
RFIN TO O UT_B, –40°C
20106-038
Figure 34. Isolation vs. Frequency Over Temperature,
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
+85°C
+25°C
–40°C
0
–25
–15
–5
–20
–10
OUTPUT RE TURN L OSS ( dB)
087
65
4
3
2
1FRE Q UE NCY ( GHz)
20106-039
Figure 35. Output Return Loss vs. Frequency Over
Temperature (100 MHz to 8 GHz), State = Internal Amplifier (Refer to Figure 76
for the Test Circuit)
0 87
65
4
3
21 FRE QUENCY ( GHz)
+85°C
+25°C
–40°C
10
0
1
2
3
4
5
6
7
8
9
NOISE FIGURE (dB)
20106-040
Figure 36. Noise Figure vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_A, + 85°C
RFIN TO O UT_A, + 25°C
RFIN TO O UT_A, –40°C
20106-041
Figure 37. Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
ADL8111 Data Sheet
Rev. 0 | Page 12 of 24
0
–80
–70
–60
–50
–40
–30
–20
–10
08
76
5
43
21
ISOLATION (dB)
FRE Q UE NCY ( GHz)
IN_B TO RFO UT, + 85°C
IN_B TO RFO UT, + 25°C
IN_B TO RFO UT, –40°C
20106-043
Figure 38. Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0
–35
–25
–15
–5
–30
–20
–10
0.01 0.10
0.09
0.080.07
0.06
0.050.04
0.030.02
REVERSE ISOLATIO N (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-044
Figure 39. Reverse Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
45
0
10
20
40
5
15
30
35
25
0.01 0.100.090.080.070.060.050.040.03
0.02
OI P 3 ( dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-045
Figure 40. OIP3 vs. Frequency Over Temperature (10 MHz to 100 MHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
087
6
54
3
2
1
ISOLATION (dB)
FRE Q UE NCY ( GHz)
IN_A TO RFO UT, + 85°C
IN_A TO RFO UT, + 25°C
IN_A TO RFO UT, –40°C
20106-046
Figure 41. Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0
–35
–25
–15
–5
–30
–20
–10
REVERSE ISOLATION (d B)
+85°C
+25°C
–40°C
0 87654321 FRE QUENCY ( GHz)
20106-047
Figure 42. Reverse Isolation vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
45
0
10
20
40
5
15
30
35
25
OI P 3 ( dBm)
+85°C
+25°C
–40°C
0 87654321 FRE QUENCY ( GHz)
20106-048
Figure 43. OIP3 vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
Data Sheet ADL8111
Rev. 0 | Page 13 of 24
45
0
10
20
40
5
15
30
35
25
0.01 0.100.09
0.08
0.070.06
0.050.040.030.02
OI P 3 ( dBm)
FRE Q UE NCY ( GHz)
5.5V
5.0V
4.5V
20106-050
Figure 44. OIP3 vs. Frequency Over VDD (10 MHz to 100 MHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0 87654321 FRE QUENCY ( GHz)
+85°C
+25°C
–40°C
24
0
4
12
20
8
16
P1d B ( dBm)
20106-051
Figure 45. P1dB vs. Frequency Over Temperature (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
45
0
10
20
40
5
15
30
35
25
OI P 3 ( dBm)
5.5V
5.0V
4.5V
0 8
7
65
4
3
2
1FRE Q UE NCY ( GHz)
20106-052
Figure 46. OIP3 vs. Frequency Over VDD (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
0 87654321 FRE QUENCY ( GHz)
24
0
4
12
20
8
16
P1d B ( dBm)
5.5V
5.0V
4.5V
20106-053
Figure 47. P1dB vs. Frequency Over VDD (100 MHz to 8 GHz),
State = Internal Amplifier (Refer to Figure 76 for the Test Circuit)
ADL8111 Data Sheet
Rev. 0 | Page 14 of 24
INTERNAL BYPASS STATE
0
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
010
987654321
BROADBAND I NS E RTI ON AND RET URN LO S S ( dB)
FRE Q UE NCY ( GHz)
RFIN TO RFOUT INPUT RETURN LOSS
RFIN TO RFOUT INSERTION LOSS
RFIN TO RFOUT OUTPUT RETURN LOSS
20106-055
Figure 48. Broadband Insertion and Return Loss vs. Frequency,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
0
–25
–20
–15
–10
–5
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
RFIN TO RFOUT INPUT RETURN LOSS, +85°C
RFIN TO RFOUT INPUT RETURN LOSS, +25°C
RFIN TO RF OUT INPUT RET URN LO S S , –40°C
20106-056
Figure 49. Input Return Loss Over Temperature vs. Frequency,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_A, + 85°C
RFIN TO O UT_A, + 25°C
RFIN TO O UT_A, –40°C
20106-057
Figure 50. Isolation vs. Frequency Over Temperature,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
087
6
54
32
1
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
RFIN TO RFOUT, +85°C
RFIN TO RFOUT, +25°C
RFIN TO RFOUT, –40°C
20106-058
Figure 51. Insertion Loss Over Temperature vs. Frequency,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
0
–25
–20
–15
–10
–5
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
RFIN TO RFOUT OUTPUT RETURN LOSS, +85°C
RFIN TO RFOUT OUTPUT RETURN LOSS, +25°C
RFIN TO RFOUT OUTPUT RETURN LOSS, –40°C
20106-059
Figure 52. Output Return Loss Over Temperature vs. Frequency,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B, + 85°C
RFIN TO O UT_B, + 25°C
RFIN TO O UT_B, –40°C
20106-060
Figure 53. Isolation vs. Frequency Over Temperature,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
Data Sheet ADL8111
Rev. 0 | Page 15 of 24
0
–80
–70
–60
–50
–40
–30
–20
–10
0 8
7
65
4
32
1
ISOLATION (dB)
FRE Q UE NCY ( GHz)
IN_A TO RFO UT, + 85°C
IN_A TO RFO UT, + 25°C
IN_A TO RFO UT, –40°C
20106-062
Figure 54. Isolation vs. Frequency Over Temperature,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
40
0
4
8
12
16
20
24
28
32
36
0 87654321
P0.5dB (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-063
Figure 55. P0.5dB vs. Frequency Over Temperature,
State = Internal Bypass, Path = RFIN to RFOUT (Refer to Figure 77 for the Test
Circuit)
60
0
10
20
30
40
50
5
15
25
35
45
55
0 87654321
II P 3 ( dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-064
Figure 56. IIP3 vs. Frequency Over Temperature,
State = Internal Bypass, Path = RFIN to RFOUT (Refer to Figure 77 for the Test
Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 8
7
65
43
2
1
ISOLATION (dB)
FRE Q UE NCY ( GHz)
IN_B TO RFO UT, + 85°C
IN_B TO RFO UT, + 25°C
IN_B TO RFO UT, –40°C
20106-065
Figure 57. Isolation vs. Frequency Over Temperature,
State = Internal Bypass (Refer to Figure 77 for the Test Circuit)
40
0
4
8
12
16
20
24
28
32
36
0 87654321
P1d B ( dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-066
Figure 58. P1dB vs. Frequency Over Temperature,
State = Internal Bypass, Path = RFIN to RFOUT (Refer to Figure 77 for the Test
Circuit)
ADL8111 Data Sheet
Rev. 0 | Page 16 of 24
EXTERNAL BYPASS B STATE
0
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
010
987654321
BROADBAND I NS E RTI ON AND RET URN LO S S ( dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B INP UT RETURN LOSS
RFIN TO OUT_B INSERTION LOSS
RFIN TO OUT_B OUTPUT RETURN LOSS
20106-069
Figure 59. Broadband Insertion and Return Loss vs. Frequency,
State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the
Test Circuit)
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0 87654321
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B, + 85°C
RFIN TO O UT_B, + 25°C
RFIN TO O UT_B, –40°C
20106-070
Figure 60. Insertion Loss Over Temperature vs. Frequency,
State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B +85° C
RFIN TO O UT_B +25° C
RFIN TO O UT_B –40°C
20106-071
Figure 61. Input Return Loss Over Temperature vs. Frequency,
State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the
Test Circuit)
0
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
BROADBAND I NS E RTI ON AND RET URN LO S S ( dB)
IN_B TO RFO UT INP UT RETURN LOSS
IN_B TO RFOUT INSERTION LOSS
IN_B TO RFOUT OUTPUT RETURN LOSS
0 87654321 FRE QUENCY ( GHz)
20106-072
Figure 62. Broadband Insertion and Return Loss vs. Frequency,
State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the
Test Circuit)
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
IN_B TO RFO UT, + 85°C
IN_B TO RFO UT, + 25°C
IN_B TO RFO UT, –40°C
20106-073
Figure 63. Insertion Loss Over Temperature vs. Frequency,
State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0 87654321
INPUT RETURN L OSS ( dB)
FRE Q UE NCY ( GHz)
IN_B TO RFO UT, + 85°C
IN_B TO RFO UT, + 25°C
IN_B TO RFO UT, –40°C
20106-074
Figure 64. Input Return Loss Over Temperature vs. Frequency,
State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the
Test Circuit)
Data Sheet ADL8111
Rev. 0 | Page 17 of 24
0
–25
–20
–15
–10
–5
08
76
54
3
21
OUTPUT RE TURN L OSS ( dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_B, + 85°C
RFIN TO O UT_B, + 25°C
RFIN TO O UT_B, –40°C
20106-076
Figure 65. Output Return Loss Over Temperature vs. Frequency,
State = External Bypass B, Path = RFIN to OUT_B (Refer to Figure 78 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0 8
76
543
2
1
OFF STATE RETURN LOSS (dB)
FRE Q UE NCY ( GHz)
IN_A OFF STATE, +85°C
IN_A OFF STATE, +25°C
IN_A O FF S TAT E , –40°C
20106-077
Figure 66. Off State Return Loss vs. Frequency Over Temperature,
State = External Bypass B, Path = IN_A (Refer to Figure 78 for the Test Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
IN_A TO RFO UT, + 85°C
IN_A TO RFO UT, + 25°C
IN_A TO RFO UT, –40°C
20106-078
Figure 67. Isolation vs. Frequency Over Temperature,
State = External Bypass B (Refer to Figure 78 for the Test Circuit)
0
–25
–20
–15
–10
–5
0 8
7
65
43
2
1
OUTPUT RE TURN L OSS ( dB)
FRE Q UE NCY ( GHz)
IN_B TO RFO UT, + 85°C
IN_B TO RFO UT, + 25°C
IN_B TO RFO UT, –40°C
20106-079
Figure 68. Output Return Loss Over Temperature vs. Frequency,
State = External Bypass B, Path = IN_B to RFOUT (Refer to Figure 78 for the
Test Circuit)
0
–25
–20
–15
–10
–5
0876
5
4
3
21
OFF STATE RETURN LOSS (dB)
FRE Q UE NCY ( GHz)
OUT_A OFF STATE, +85°C
OUT_A OFF STATE, +25°C
OUT_A OFF STATE, –40°C
20106-080
Figure 69. Off State Return Loss vs. Frequency Over Temperature,
State = External Bypass B, Path = OUT_A (Refer to Figure 78 for the Test
Circuit)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 87654321
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO O UT_A, + 85°C
RFIN TO O UT_A, + 25°C
RFIN TO O UT_A, –40°C
20106-081
Figure 70. Isolation vs. Frequency Over Temperature,
State = External Bypass B (Refer to Figure 78 for the Test Circuit)
ADL8111 Data Sheet
Rev. 0 | Page 18 of 24
0
–80
–70
–60
–50
–40
–30
–20
–10
08
76
5
43
21
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFIN TO RFOUT, +85°C
RFIN TO RFOUT, +25°C
RFIN TO RFOUT, –40°C
20106-083
Figure 71. Isolation vs. Frequency Over Temperature,
State = External Bypass B (Refer to Figure 78 for the Test Circuit)
0
4
8
12
16
20
24
28
32
36
40
012345678
P0.5dB (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-084
Figure 72. P0.5dB vs. Frequency Over Temperature,
State = External Bypass B, Path = RFIN to OUT_B or IN_B to RFOUT (Refer to
Figure 78 for the Test Circuit)
65
0
10
20
30
40
50
60
5
15
25
35
45
55
0 8
7
65
4
3
2
1
II P 3 ( dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
20106-085
Figure 73. IIP3 vs. Frequency Over Temperature,
State = External Bypass B, Path = RFIN to OUT_B or IN_B to RFOUT (Refer to
Figure 78 for the Test Circuit)
0
4
8
12
16
20
24
28
32
36
40
012345678
P0.5dB (dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
20106-086
Figure 74. P0.5dB vs. Frequency Over Temperature,
State = External Bypass B, Path = RFIN to OUT_B or IN_B to RFOUT (Refer to
Figure 78 for the Test Circuit)
Data Sheet ADL8111
Rev. 0 | Page 19 of 24
TEST CIRCUITS
OUT_A
RFOUT
RFIN
IN_A
OUT_B IN_B
AMP
20106-009
Figure 75. External Bypass A State
OUT_A
RFOUT
RFIN
IN_A
OUT_B IN_B
AMP
20106-028
Figure 76. Internal Amplifier State
RFOUTRFIN
OUT_B IN_B
AMP
OUT_A IN_A
20106-054
Figure 77. Internal Bypass State
OUT_A
RFOUTRFIN
IN_A
OUT_B IN_B
AMP
20106-068
Figure 78. External Bypass B State
ADL8111 Data Sheet
Rev. 0 | Page 20 of 24
THEORY OF OPERATION
The ADL8111 integrates an amplifier with two switching
networks located at the RF input and output. The internal
amplifier uses a gallium arsenide (GaAs) LNA die from the
HMC8411. The switching network employs robust silicon-on-
insulator (SOI) technology for fast switching and a short
settling time. This integrated solution has four different signal
path states available: an internal amplifier, an internal bypass,
External Bypass A, and External Bypass B. Signal path states are
controlled through the digital pins, VA and VB, using 1.4 V
high and 0 V low logic (see Figure 79 to Figure 82). The internal
amplifier is biased up by applying 5 V to VDD_PA, and the
internal switches are biased up by applying +3.3 V and −3.3 V
to VDD_SW and VSS_SW, respectively. DC bias to the switches
is independent of the LNA. Turning off bias to VDD_PA to the
LNA provides better isolation between RF ports.
SIGNAL PATH STATES FOR DIGITAL CONTROL
INPUTS
OUT_A
RFOUT
RFIN
IN_A
OUT_B IN_B
AMP
20106-087
Figure 79. External Bypass A, VA = 0 V and VB = 0 V
OUT_A
RFOUTRFIN
IN_A
OUT_B IN_B
AMP
20106-088
Figure 80. Internal Amplifier, VA = 0 V and VB = 3.3 V
RFOUTRFIN
OUT_B IN_B
AMP
OUT_A IN_A
20106-089
Figure 81. Internal Bypass, VA = 3.3 V and VB = 0 V
OUT_A
RFOUTRFIN
IN_A
OUT_B IN_B
AMP
20106-090
Figure 82. External Bypass B, VA = 3.3 V and VB = 3.3 V
Table 8. Truth Table
State Name
Digital Control Inputs
Signal Path State VA VB
External Bypass A Low Low RFIN to OUT_A, IN_A to RFOUT
Internal Amplifier Low High RFIN to RFOUT through amplifier path
Internal Bypass High Low RFIN to RFOUT through bypass path
External Bypass B High High RFIN to OUT_B, IN_B to RFOUT
Data Sheet ADL8111
Rev. 0 | Page 21 of 24
APPLICATIONS INFORMATION
The basic connections for operating the ADL8111 are shown in
Figure 83. A 5 V dc bias is supplied to the amplifier on VDD_PA,
+3.3 V dc bias supply to VDD_SW and −3.3 V dc bias supply to
VSS_SW.
VA and VB are digital inputs set path states shown in Table 7.
High logic state is set at 1.4 V and low logic state is set at 0 V.
The LNA within the ADL8111 operates in self-biased mode
where the VBIAS pin is connected to a 560 Ω external resistor
to achieve a 70 mA supply current. Refer to Table 9 for the
recommended resistor values to achieve different IDQ currents.
RECOMMENDED BIAS SEQUENCING
During Power-Up
The recommended bias sequence during power-up follows:
1. Set VDD_SW = 3.3 V.
2. Set VSS_SW = −3.3 V.
3. Set VDD_PA = 5 V.
4. Apply the RF signal.
During Power-Down
The recommended bias sequence during power-down follows:
1. Turn off the RF signal.
2. Set VDD_PA = 0 V.
3. Set VSS_SW = 0 V.
4. Set VDD_SW = 0 V.
The bias conditions, VDD_PA = 5 V at IDQ = 70 mA, is the
recommended operating point to achieve optimum
performance. The data used in this data sheet was taken with
the recommended bias condition. Using the HMC8411 with
different bias conditions can provide different performance
than what is shown in the Typical Performance Characteristics
section.
Table 9. Recommended Bias Resistor Values at VDD_PA = 5 V
RBIAS (Ω) IDQ (mA)
226 85
560 70
1.1 k 55
ADL8111 Data Sheet
Rev. 0 | Page 22 of 24
EVALUATION PCB
The ADL8111-E VA L Z is the evaluation board for the ADL8111
with fully populated components as shown in Figure 83 and its
schematic shown in Figure 84. The board is fabricated with four
layers using Rogers 4350. Signal lines have characteristic
impedance of 50 Ω. Package ground leads and the exposed
paddle are soldered to the ground plane. Adequate amounts of
via holes connect the top and bottom ground planes. The
evaluation board is available from Analog Devices, Inc., upon
request. Gerber files can be found on the ADL8111 product
webpage.
20106-091
VDD_PA GND
GND
J8
J2
J10
VDD_PA
J7
J1
J9
VB VSS_SW
VDD_SW
VA
Figure 83. ADL8111-EVALZ Evaluation Board PCB
Data Sheet ADL8111
Rev. 0 | Page 23 of 24
EVALUATION BOARD SCHEMATIC
20106-092
50Ω50Ω
560Ω
R1
10pF
C1
50Ω50Ω
50Ω50Ω
50Ω50Ω1
2
3
4
5
6
7
J4 – VA
J3 – VDD_PA
J1
RFIN J2
RFOUT
J4 – VB
VDD_PA
VBIAS
J9
OUT_B
J10
J4 – VDD_SW
J4 – VSS_S W
GND
IN_B
J7
OUT_A
J8
IN_A
PAD1
PAD3
U1
21
20
19
18
17
16
15
8
9
10
11
12
13
14
PAD2
PAD4
28
27
26
25
24
23
22
Figure 84. ADL8111-EVALZ Evaluation Board Schematic
Table 10. Bill of Material for Evaluation PCB ADL8111-EVALZ
Item Description
J1, J2, J7, J8, J9, J10 SRI SMA RF connectors
J3, J4 DC header pins
U1 ADL8111
C1 10 pF, 5% tolerance, 0201, ceramic capacitor
R1 560 Ω, 1/16 W, 0402, thick film resistor
ADL8111 Data Sheet
Rev. 0 | Page 24 of 24
OUTLINE DIMENSIONS
03-02-2018-A
PKG-005742
6.10
6.00
5.90
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
7
8
15
14
21
22 28
0.65
BSC
0.10
REF
3.90 REF
SQ
1.83 BSC
SQ
3.90 BSC
SQ
0.35
0.30
0.25
0.50
0.45
0.40
0.366
0.326
0.286
1.00 REF
1.43 M AX
PIN 1
INDIC
ATOR
PIN 1
CORNER ARE A
SEATING
PLANE
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PADS, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
Figure 85. 28-Terminal Land Grid Array [LGA]
(CC-28-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
ADL8111ACCZN −40°C to +85°C MSL3 28-Terminal Land Grid Array [LGA] CC-28-3
ADL8111ACCZN-R7 −40°C to +85°C MSL3 28-Terminal Land Grid Array [LGA] CC-28-3
ADL8111-EVALZ Evaluation Board
1 All models are RoHS compliant parts.
2 See the Absolute Maximum Ratings section for additional information.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20106-0-4/19(0)
