RPY222 Philips Components EVALUATION BOARD 1. PATTERN RECOGNITION SIGNAL PROCESSING INTRODUCTION The performance of conventional! PIR systems is ultimately limited by the amount of information that can be obtained from a standard dual element sensor, The RPY222 contains two independent sensors, the outputs of which can be processed separately to provide a degree of intelligence and consequent reduction in false triggers (Ref. 1}. The signal processing circuit for the RPY222 (Fig.1) basically consists of 43 standard logic gates and atimer IC. tn order to eliminate the time consuming task of constructing this circuit, an evaluation board has been developed. This allows direct connection of the front end circuitry to a processing circuit providing all the necessary facilities for testing and evaluation. The evaluation board consists of just two ICs and a few resistors and capacitors (Fig.2). One IC is the NE556 Dual Timer and the other is the Philips PLS 155 Field-Programmable Logic Sequencer. The PLS 155 allows all the logic functions of the signal processing circuit to be programmed onto the one 20 pin IC. PLS155 PROGRAMMABLE LOGIC DEVICE (PLD) Details on the architecture and features of this device can be found in the PLS 155 data sheet, which is included in the Philips Components PLD data book (Ref.2). Experience has shown that a circuit which has been designed using standard logic does not program efficiently onto aPLD. A better way to design programmable logic is to consider the system as a black box with a number of inputs and outputs. The system is then defined as a relationship between the inputs and outputs in the form of Boolean equations and state equations. Defining a system in the form of a state diagram gives a visible representaion of the different states and the relationship between them. It can be seen from Fig.3 that there are two identical but completely separate state diagrams required to describe the overall system performance. One represents the state transition corresponding to the positive signals and the other to the negative signals. Once all the necessary equations for the system have been defined, it is a fairly simple process, with the aid of the AMAZE software package, to program a device. Firstly the pins are labelled and configured, according to the requirements of the system, using the pin-list editor (Fig.4). Then the Boolean equations are entered using the Boolean equation entry file (Fig.5). The flip-flops are also configured here, in this case all four are programmed to J-K Toggle mode. The next stage is the entry of the state equations, which is performed using the state equation entry file {Fig.6). Information is entered into this file in a free format. A state transition !anguage similar to Pascal is used, as can be seen in Fig.6. Taking these three files, pin list file, Boolean entry file and state entry file, AMAZE can then goto assemble the information and produce a fuse map. The fuse map is represented in the form of a program table (Fig.7), which is the equivalent of a truth table. Before down loading the fuse map to the programmer, the device can be checked for accurate operation using the AMAZE simulator. Any changes can then be made before the device is programmed, which can help to prevent unnecessary wastage of devices. a PHILIPS February 1989 1RPY222 EVALUATION BOARD 3. EXTERNAL CONNECTIONS (see Fig.8) The only external connections are via connector 1 Pind : Vec G5 V) Pin6 : GND(OV) Pin2 : +A Pin3 : -A Comparator outputs from front Pin4d : +B end circuitry (note i) Pin5 : B Notes: i. !t is essential that the high to low transition on the comparator outputs are bounce free. Pull down resistors on the comparator outputs may be required. 4. ON-BOARD JUMPERS J1: This jumper connects either one of the two alarm outputs to the LED, D1. a) Alarm pin 7 on IC1 indicates that an intruder sequence has been detected. or b) AlarmT pin 19 on [C1 indicates that an intruder sequence has been detected and the time delay has elapsed. J2: This jumper allows the time delay to be selected. The two resistors connected are R4 and R5 which have values of 10 MQ and 4.7 MQ respectively. The 10 MQ value gives a time delay of approx 5 seconds and the 4.7 MQ gives a time delay of approx 2.5 seconds. Alternative time delays can be easily implemented by changing R4 or R65 for values which can be calculated from the following equation: T ~ 1.1 RC seconds where R = R4 or R5 in 2 and C = C3 in F (C3 = 0.47 uF) 5. STATE BITS PT1 has four pins which give access to the values of the 4 state bits SBO, SB1, SB2 and SB3. By referring to the state transfer information, Fig.6, it is possible to monitor the bits and confirm that the system is operating correctly. They provide a valuable tool when fault finding. 6. CLOCK FREQUENCY There are two main factors which determine the optimum clock frequency. i. From experimental results it has been found that an intruder sequence can contain pulses (one from each channel) that differ in time by a minimum of approximately 10 ms. In order that these two pulses appear to have occurred at different moments in time, the clock speed must not be greater than 10 ms to provide adequate resolution. ii. It hag also been found that noise spikes which produce simultaneous signals on both channels can, asa result of amplitude and phase differences in the front end circuitry, appear at the comparator outputs slightly delayed with respect to each other. To try and counteract this problem the clock is made as slow as possible to ensure that these pulses appear to be simultaneous. Taking these two constraints dictates an optimum clock speed of approximately 5 ms. 7. PCB The component and track layout for side 1 and side 2 of the PCB can be seen in Fig.8 and Fig.9 respectively. : ~ February 1989 PH iL PSPattern recognition signal processing RPY222 EVALUATION BOARD 8. COMPONENT LIST Resistors R1 10 kQ R2 10 kQ R3 2.2kQ2 R4 10MQ R5 4.7MQ R6 330 2 R7 6.8 kQ Semiconductors Ic1 PLS155 IC2 NE556 D1 LED 9. REFERENCES AND PUBLICATIONS Capacitors cl 1 PF c2 1 pF C3 0.47 uF C4 330 nF C5 22 nF C6 22 nF C7 2.2 nF c8 2.2 nF cg 10 nF c10 0.1 uF C11 to uF C12 47 uF 1. Passive Infrared (PIR) Intruder Alarms, Philips Technical Publication, TP213, July 1986. 2. Semi-custom Programmable Logic Devices (PLD), Philips Data Handbook, IC 13. 3. Introduction to RPY222 sensor, see pages 1 to 17 of this publication. PHILIPS, PHILIPS February 1989 3I RPY222 EVALUATION BOARD -o160] puepuels Buisn 11n9419 Burssad0id |euBbis 1 6I4 az 4 ? ya 3 $ C 7 % , p9 | t gor aie | \ \ | 304 ad L. Pe -_-- 146 POL 201 ANdLno Pak -~ i. + $$th4 Ae4-0 ae . {| aA r TAT = = WoL 7 orm a t @ Ms 4 February 1989 PH i Li PSRPY222 Pattern recognition signal processing EVALUATION BOARD de 08 Laas i [2 3 4 Ss 6 => Re ya20g9 | = = al 2 2 okt ood | Fig.2 Signal processing circuit using a PLS155. e00ae/ i g i g wae == se az be ET8/ RK | oS cba tae 4 2 # o Ole be nhad HS oft ev0ere/ a . aS i tt TELE ! ro oo Hy te O@2E710/ nord Lp eee e/ 3 j i ose aRe yl __ | f 8 a g sj aette iRPY222 EVALUATION BOARD PLUS SBO,SB1 11 A+tB+ (AZB_) (Ag=Be) R +TIMER 01 pist (A+tB+) +TIMER A+B+ 00 p2nd A4+B+ M3275 Fig.3 State diagram representation of system. PIN LIST LABEL ** ENC** PIN PIN ** FNC ** LABEL CLOCK * CK ** 1-1 I-20 ** +5V **VCC AP ** | ** 2-l I-19 ** QO **ALARMT AM ** e 3-1 P 1-18 ** /O **TRIGGER BP ** | ee 4-I L -17 ** /O **SB3 BM ** | ** 5-l Ss I-16 ** /O **SB2 ALARM ** QO ** 6I 1 I-15 ** /O **SBt RESETN we ** 7-l 5 I-14 ** /O **SBO OSCO **Q ** 8-l 5 I-13 ** | **TIMEOUT Oscl ** /B ** g9-l 1-12 ** /O **TIMRES GND ** OV ** 10-1 I-11 ** /DE **N/C Fig.4 AMAZE pin list file. 6 February 1989 PH I Li PSRPY222 Pattern recognition signal processing EVALUATION BOARD @DEVICE TYPE @DEVICE SELECTION PLS155 @DRAWING alarm/pls155 @REVISION @DATE @STATE VECTORS @SYMBOL @COMPANY [sb0,sb 1,sb2,sb3] @NAME @DESCRIPTION pres = 11-b; @COMMON PRODUCT TERM plist =01~-b; p2nd = 00b; res =sbO*sb1*sb2*sb3; p3rd = 10b; pjmp ~ @COMPLEMENT ARRAY mres mist = /e =Kres); mand = m3rd @1/0 DIRECTION mjmp = all d3 =osca; reset = 1111b; @FLIP FLOP CONTROL @INPUT VECTORS @OUTPUT VECTORS fe =1; @TRANSITIONS @OUTPUT ENABLE olus inputs @REGISTER LOAD @ASY NCHRONOUS PRESET/RESET while [pres] @FLIP FLOP MODE if [ap*/bp*resetn] then [p1st] @LOGIC EQUATION if [/ap* bp *resetn] then [p1st} while [p1st] timer if [/ap*/bp*resetn* timeout} then [pres] if [ap* bp* resetn* timeout] then [p2nd] trigger=/{/c* resetn); if [/timeout* resetn] then [pres] timres=/{restalarmt+/resetn}; while [p2nd] if [ap*/bp*resetn*timeout] then (p3rd] alarm outputs if [/ap*bp*resetn* timeout] then [p3rd] if [/ap*/bp*resetn* timeout] then [pjmp} alarm = (sb0*/sb1)+(sb2*/sb3}; if [/timeout* resetn] then [pjmp] alarmt=((sbO%sb 1)+(sb2* /sb3))* /timeout; minus inputs on while [mres} Fig.5 AMAZE Boolean Equation entry file. then [m1st] then [m1st] if [am*/bm*resetn] if [/am*bm*resetn] while [mst] if [/am*/bm*resetn ] if [am*bm*resetn } if [/timeout* resetn] while {m2nd] if [am*/bm*resetn* timeout] then [m3rd] if [/am*bm*resetn*timeout] then [m3rd] if [/am*bm*resetn* timeout] then [mjmp] if [/timeout* resetn] then [mjmp] then [mres]} then [m2nqd] then [mres] reset while [all] if [/resetn] then [reset] Fig.6 AMAZE state equation entry file. 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Oi ce C3 SW1 Fig.8 PCB layout (side 1). PH i LI PS | [ February 1989 9RPY222 EVALUATION BOARD C414 cg R3 R4 RS c1e 2 |e o| oe re I fH o| |e Cd] . e ca |e e u e |. e e | e e e e @ S e8& elle $e e of e-| > ot ef e |PT4 e e e Jd e Ice @ e e oe | Da 0/0 @ RS @ c7 cSce C4 e c3 SW1 Fig.9 PCB layout (side 2). M89-1957/Y 10 February 1989 | PHILIPS