January 2011 Doc ID 16885 Rev 3 1/20
20
ST3DV520A
High bandwidth switch with 20- to 10-bit MUX/DEMUX
Features
■Low RON: 4.0 Ω typical
■VCC operating range: 3.0 to 3.6 V
■Enhanced ESD protection: > 8 kV (contact) and
15 kV (HBM)
■Channel on capacitance: 9.5 pF typical
■Switching time speed: 9 ns
■Near to zero propagation delay: 250 ps
■Very low crosstalk: -45 dB at 250 MHz
■Bit-to-bit skew: 200 ps
■> 600 MHz -3 dB typical bandwidth (or data
frequency)
■Package: QFN56
Table 1. Device summary
Order code Package Packing
ST3DV520AQTR QFN56 Tape and reel
QFN56
www.st.com
Contents ST3DV520A
2/20 Doc ID 16885 Rev 3
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ST3DV520A Description
Doc ID 16885 Rev 3 3/20
1 Description
The ST3DV520A 20- to 10-bit multiplexer/demultiplexer is a high bandwidth bidirectional
switch with low RON suitable for analog video applications.
The signal from each input is multiplexed into one of two selected outputs, while the
unselected switch goes into Hi-Z status. The device is designed for very low crosstalk, low
bit-to-bit skew and low I/O capacitance.
The ST3DV520A supports high definition (HD) video switching standards and is also
suitable for general-purpose switching that requires high signal integrity.
Pin description ST3DV520A
4/20 Doc ID 16885 Rev 3
2 Pin description
Figure 1. Pin connection (top through view)
Table 2. Pin description
Pin Symbol Name and function
2, 3, 7, 8, 11, 12, 14, 15, 19, 20 A, B, C, D, E, F, G, H, I, J 10-bit bus
22, 23, 48, 47, 43, 42, 37, 36,
32, 31
A0, B0, C0, D0, E0, F0, G0,
H0, I0, J0 10-bit multiplexed to bus 0
25, 26, 46, 45, 41, 40, 35, 34,
30, 29
A1, B1, C1, D1, E1, F1, G1,
H1, I1, J1 10-bit multiplexed to bus 1
5, 51, 52, 54 N/C Not connected
17 SEL Bus and LED switch selection
4, 10, 18, 27, 38, 50, 56 VCC Supply voltage
1, 6, 9, 13, 16, 21, 24, 28, 33,
39, 44, 49, 53, 55 GND Ground
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ST3DV520A Pin description
Doc ID 16885 Rev 3 5/20
Figure 2. Input equivalent circuit
Table 3. Switch function table
SEL Function
L 10-bit bus to 10-bit multiplexed bus 0
H 10-bit bus to 10-bit multiplexed bus 1
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Maximum ratings ST3DV520A
6/20 Doc ID 16885 Rev 3
3 Maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Recommended operating conditions
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Supply voltage to ground -0.5 to 4.6 V
VIO DC input output voltage -0.5 to 4.6 V
VIC DC control input voltage -0.5 to 4.6 V
IODC output current(1)
1. If VIO x IO does not exceed the maximum limit of PD.
120 mA
PDPower dissipation 0.5 W
Tstg Storage temperature -65 to 150 °C
TLLead temperature (10 sec) 300 °C
Table 5. Recommended operating conditions
Symbol Parameter
Value
Unit
Min Typ Max
VCC Supply voltage to ground 3 – 3.6 V
VIC DC control input voltage (SEL) 0 – 5 V
VIO DC input/output voltage 0 – VCC V
TAOperating temperature -40 – 85 °C
ST3DV520A Electrical characteristics
Doc ID 16885 Rev 3 7/20
4 Electrical characteristics
Table 6. DC electrical characteristics (VCC = 3.3 V ±10%)
Symbol Parameter Test condition
Value
Unit-40 to 85 °C
Min Typ Max
VIH Voltage input high (SEL) High level guaranteed 2 – – V
VIL Voltage input low (SEL) Low level guaranteed -0.5 – 0.8 V
VIK Clamp diode voltage (SEL) VCC = 3.6 V
IIN = -18 mA –-0.8-1.2V
IIH Input high current (SEL) VCC = 3.6 V
VIN = VCC
––±5µA
IIL Input low current (SEL) VCC = 3.6 V
VIN = GND ––±5µA
IOFF(SW)(1) Leakage current through the switch
common terminals (A to J)
VCC = 3.6 V
A to J = VCC
LED1 to LED3 = VCC
A0 to J0 = 0 V
A1 to J1 = floating
SEL = VCC
––±1µA
IOFF(SEL) SEL pin leakage current VCC = 0 V
SEL = 0 to 3.6 V ––±1µA
RON Switch ON resistance(2)
VCC = 3.0 V
VIN = 1.5 to VCC
IIN = -40 mA
–4.06.5Ω
RFLAT ON resistance flatness (2) (3)
VCC = 3.0 V
VIN at 1.5 and VCC
IIN = -40 mA
–0.5–Ω
ΔRON
ON resistance match between
channel
ΔRON = RONMAX-RONMIN (2)(4)
VCC = 3.0 V
VIN = 1.5 to VCC
IIN = -40 mA
–0.41Ω
1. Refer to Figure 4: Test circuit for leakage current (IOFF) on page 11.
2. Measured by voltage drop between channels at indicated current through the switch. ON resistance is determined by the
lower of the voltages.
3. Flatness is defined as the difference between the RONMAX and RONMIN of ON resistance over the specified range.
4. ΔRON measured at same VCC, temperature and voltage level.
Electrical characteristics ST3DV520A
8/20 Doc ID 16885 Rev 3
Table 7. Capacitance (TA = 25 °C, f = 1 MHz)
Table 8. Power supply characteristics
Table 9. Dynamic electrical characteristics (VCC = 3.3 V ±10%)
Symbol Parameter Test condition
Value
Unit
Min Typ Max
CIN
SEL pin input
capacitance(1)
1. Refer to Figure 5 on page 11.
DC = 0.25 V
AC = 0.5 VPP
f=1MHz
–23pF
COFF
Switch off
capacitance(2)
2. Refer to Figure 6 on page 12.
DC = 0.25 V
AC = 0.5 VPP
f=1MHz
–45pF
CON
Switch on
capacitance(3)
3. Refer to Figure 7 on page 12.
DC = 0.25 V
AC = 0.5 VPP
f=1MHz
–9.511pF
Symbol Parameter Test condition
Value
Unit-40 to 85 °C
Min Typ Max
ICC
Quiescent power
supply
VCC = 3.6 V, VIN = VCC or
GND – 150 500 µA
Symbol Parameter Test condition
Value
Unit-40 to 85 °C
Min Typ Max
Xtalk Crosstalk(1)
1. Refer to Figure 9 on page 14.
RL= 100 Ω
f = 250 MHz –-45–dB
OIRR Off isolation(2)
2. Refer to Figure 10 on page 15.
RL= 100 Ω
f = 250 MHz –-37–dB
BW -3 dB bandwidth(3)
3. Refer to Figure 8 on page 13.
RL= 100 Ω
0 < VIN ≤
3.6 V –600–MHz
ST3DV520A Electrical characteristics
Doc ID 16885 Rev 3 9/20
Table 10. Switching characteristics (TA = 25 °C, VCC = 3.3 V ±10%)
Table 11. ESD performance
Symbol Parameter Test condition
Value
Unit
Min Typ Max
tPD Propagation delay VCC = 3 to 3.6 V – 0.25 – ns
tPZH,
tPZL
Line enable time, SE
to x to x0 or x to x1 VCC = 3 to 3.6 V 0.5 6.5 15 ns
tPHZ,
tPLZ
Line disable time, SE
to x to x0 or x to x1 VCC = 3 to 3.6 V 0.5 6.5 8.5 ns
tSK(O)
Output skew
between center port
to any other port
VCC = 3 to 3.6 V – 0.1 0.2 ns
tSK(P)
Skew between
opposite transition of
the same output
(tPHL, tPLH)
VCC = 3 to 3.6 V – 0.1 0.2 ns
Symbol Test condition
Value
Unit
Min Typ Max
ESD
Contact discharge(1)
IEC61000-4-2
1. Refer to Figure 3: Diagram for suggested VCC decoupling on page 10.
–±8–kV
Human body model
(MIL-STD-883) –±15–kV
Electrical characteristics ST3DV520A
10/20 Doc ID 16885 Rev 3
Figure 3. Diagram for suggested VCC decoupling
1. Applicable for system level ESD test.
2. 100 nF capacitors must be used as local bypass capacitors between the adjacent VCC and GND pairs
(total 7).
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ST3DV520A Electrical characteristics
Doc ID 16885 Rev 3 11/20
Figure 4. Test circuit for leakage current (IOFF)
Figure 5. Test circuit for SEL pin input capacitance (CIN)
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Electrical characteristics ST3DV520A
12/20 Doc ID 16885 Rev 3
Figure 6. Test circuit for switch off capacitance (COFF)
Figure 7. Test circuit for switch on capacitance (CON)
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ST3DV520A Electrical characteristics
Doc ID 16885 Rev 3 13/20
Figure 8. Test circuit for bandwidth measurement (BW)
1. CL includes probe and jig capacitance.
Frequency response is measured at the output of the ON channel. For example, when
VSEL = 0 and A is the input, the output is measured at A0. All unused analog I/O ports are
left open.
HP8753ES setup:
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBm
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Electrical characteristics ST3DV520A
14/20 Doc ID 16885 Rev 3
Figure 9. Test circuit for crosstalk measurement (xtalk)
1. CL includes probe and jig capacitance.
2. A 50 Ω termination resistor is needed to match the loading of the network analyzer.
Crosstalk is measured at the output of the non-adjacent ON channel. For example, when
VSEL = 0, and B is the input, the output is measured at D. All unused analog input ports are
connected to GND and output ports are left open.
HP8753ES setup:
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBm
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ST3DV520A Electrical characteristics
Doc ID 16885 Rev 3 15/20
Figure 10. Test circuit for off isolation measurement (OIRR)
1. CL includes probe and jig capacitance.
2. A 50 Ω termination resistor is needed to match the loading of the network analyzer.
Off isolation is measured at the output of the OFF channel. For example, when VSEL = 0,
and B is the input, the output is measured at B1. All unused analog input ports are
connected to GND and output ports are left open.
HP8753ES setup:
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBm
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Package mechanical data ST3DV520A
16/20 Doc ID 16885 Rev 3
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 11. Package outline for QFN56 (11 x 5 mm) - pitch 0.5 mm
7576329-A
ST3DV520A Package mechanical data
Doc ID 16885 Rev 3 17/20
Figure 12. Footprint recommendation for QFN56 (11 x 5 mm) - pitch 0.5 mm
Table 12. Mechanical data for QFN56 (11 x 5 mm) - pitch 0.5 mm
Symbol
Millimeters
Min Typ Max
A 0.700.750.80
A1 – – 0.05
A3 0.20 –
b 0.200.250.30
D 10.90 11.00 11.10
D2 8.30 8.40 8.50
D3 –9.50–
E 4.905.005.10
E2 2.30 2.40 2.50
E3 –3.50–
e – 0.50 –
L 0.300.400.50
Package mechanical data ST3DV520A
18/20 Doc ID 16885 Rev 3
Figure 13. Carrier tape information for QFN56 (11 x 5 mm) - pitch 0.5 mm
7875978_K
ST3DV520A Revision history
Doc ID 16885 Rev 3 19/20
Figure 14. Reel information for QFN56 (11 x 5 mm) - pitch 0.5 mm
6 Revision history
Table 13. Document revision history
Date Revision Changes
11-Dec-2009 1 Initial release.
07-Apr-2010 2 Corrected circuit drawing errors in Figure 2: Input equivalent circuit.
Modified text in the Description on page 1.
11-Jan-2011 3
Document reformatted, replaced VDD by VCC in Figure 1, Ta b l e 2 ,
Figure 3, to Figure 10, moved notes below Figure 8 to Figure 10,
corrected typo in Ta b le 5 to Ta bl e 7 , Ta bl e 9 , Figure 3 to Figure 10.
ST3DV520A
20/20 Doc ID 16885 Rev 3
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