256-Position, One-Time Programmable,
Dual-Channel, I2C Digital Potentiometers
Data Sheet AD5172/AD5173
Rev. I Document Feedback
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FEATURES
2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget resistance
setting provides a low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with user-
defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm
Fast settling time: tS = 5 μs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5173 )
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 μA maximum
Wide operating temperature: −40°C to +125°C
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAMS
A
1
V
DD
GND
SDA
SCL
W1
RDAC
REGIST ER 1
SERIAL INPUT
REGISTER
B1 A2 W2
RDAC
REGISTER 2
B2
FUSE
LINKS
12
/
8
0
4103-001
Figure 1. AD5172 Functional Block Diagram
V
DD
GND
SDA
SCL
AD0
AD1
W1
RDAC
REGIST ER 1
ADDRESS
DECODE
SERIAL INPUT
REGISTER
B1 W2
RDAC
REGISTER 2
B2
FUSE
LINKS
12
/
8
04103-002
Figure 2. AD5173 Functional Block Diagram
GENERAL DESCRIPTION
The AD5172/AD5173 are dual-channel, 256-position, one-time
programmable (OTP) digital potentiometers1 that employ fuse
link technology to achieve memory retention of resistance
settings. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting
in memory more than once. These devices perform the same
electronic adjustment function as mechanical potentiometers or
variable resistors but with enhanced resolution, solid-state reliabil-
ity, and superior low temperature coefficient performance.
The AD5172/AD5173 are programmed using a 2-wire, I2C®-
compatible digital interface. Unlimited adjustments are allowed
before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after a fuse is blown. However,
the OTP setting is restored during subsequent power-up condi-
tions. This allows users to treat these digital potentiometers as
volatile potentiometers with a programmable preset.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5172/AD5173 Data Sheet
Rev. I | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics: 2.5 k............................................... 4
Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 5
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 15
Theory of Operation ...................................................................... 16
One-Time Programming (OTP) .............................................. 16
Programming the Variable Resistor and Voltage ................... 16
Programming the Potentiometer Divider ............................... 17
ESD Protection ........................................................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
Power Supply Considerations ................................................... 18
Layout Considerations ............................................................... 19
I2C Interface .................................................................................... 20
Write Mode ................................................................................. 20
Read Mode .................................................................................. 20
I2C Controller Programming .................................................... 21
I2C-Compatible, 2-Wire Serial Bus .......................................... 22
Level Shifting for Different Voltage Operation ...................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
Data Sheet AD5172/AD5173
Rev. I | Page 3 of 28
REVISION HISTORY
8/13Rev. H to Rev. I
Changed VA, VB, VW to GND and Digital Inputs and Output
Voltage to GND Rating to −0.3 V to +7 V or VDD + 0.3 V
(whichever is less); Table 4 ............................................................... 7
Changes to Ordering Guide ........................................................... 25
4/09Rev. G to Rev. H
Changes to DC CharacteristicsRheostat Mode Parameter and
to DC CharacteristicsPotentiometer Divider Mode Parameter,
Table 1 ................................................................................................. 3
12/08Rev. F to Rev. G
Changes to OTP Supply Voltage Parameter, Table 1 .................... 3
Changes to OTP Supply Voltage Parameter, Table 2 .................... 5
Changes to Table 5 and Table 6 ....................................................... 8
Changes to One-Time Programming (OTP) Section ................ 15
Changes to Power Supply Considerations Section, Figure 46,
and Figure 46 Caption .................................................................... 17
Changes to Ordering Guide ........................................................... 23
7/08Rev. E to Rev. F
Changes to Power Supplies Parameter in Table 1 and Table 2 .... 3
Updated Fuse Blow Condition to 400 ms Throughout ................ 5
1/08Rev. D to Rev. E
Changes to Features .......................................................................... 1
Changes to General Description ..................................................... 1
Changes to OTP Supply Voltage and OTP Supply Current in
Table 1 ................................................................................................. 3
Changes to OTP Supply Voltage and OTP Supply Current in
Table 2 ................................................................................................. 5
Added OTP Program Time in Table 3............................................ 6
Changes to Table 4 ............................................................................ 7
Changes to Table 5 and Table 6 ....................................................... 8
Inserted Figure 30............................................................................ 13
Replaced One-Time Programming (OTP) Section .................... 15
Replaced Power Supply Considerations Section ......................... 17
Deleted Device Programming Software Section ......................... 20
Replaced I2C-Compatible, 2-Wire Serial Bus Section ................ 21
Changes to Ordering Guide ........................................................... 23
6/06Rev. C to Rev. D
Changes to Features .......................................................................... 1
Changes to One-Time Programming (OTP) Section ................ 15
Changes to Figure 44 and Figure 45 ............................................. 17
Changes to Power Supply Considerations Section ..................... 18
Changes to Figure 46 and Figure 47 ............................................. 18
Changes to Device Programming Software Section................... 19
Updated Outline Dimensions........................................................ 24
6/05Rev. B to Rev. C
Added Footnote 8, Footnote 9, and Footnote 10 to Table 1 ........ 3
Added Footnote 8 to Table 2 ............................................................ 5
Changes to Table 5 and Table 6 ....................................................... 9
Changes to Power Supply Considerations Section ..................... 17
Changes to I2C-Compatible 2-Wire Serial Bus Section ............. 23
Added Level Shifting for Different Voltage Operation Section ....... 24
Updated Outline Dimensions........................................................ 25
Changes to Ordering Guide ........................................................... 25
10/04Rev. A to Rev. B
Updated Format ................................................................ Universal
Changes to Specifications................................................................. 3
Changes to One-Time Programming (OTP) Section ................ 13
Changes to Power Supply Considerations Section ..................... 15
Changes to Figure 44 and Figure 45 ............................................. 15
Changes to Figure 46 and Figure 47 ............................................. 16
11/03Rev. 0 to Rev. A
Changes to Electrical Characteristics2.5 kΩ ............................. 3
11/03Revision 0: Initial Version
AD5172/AD5173 Data Sheet
Rev. I | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICSRHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect 14 ±2 +14 LSB
Nominal Resistor Tolerance3 ∆RAB TA = 25°C 20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICSPOTENTIOMETER DIVIDER
MODE4
Differential Nonlinearity5 DNL −1.5 ±0.1 +1.5 LSB
Integral Nonlinearity5 INL −2 ±0.6 +2 LSB
Voltage Divider Temperature Coefficient
(ΔV
W
/V
W
)/ΔT
Code = 0x80
15
Full-Scale Error
V
WFSE
Code = 0xFF
14
−5.5
0
Zero-Scale Error VWZSE Code = 0x00 0 4.5 12 LSB
RESISTOR TERMINALS
Voltage Range6 VA, VB, VW GND VDD V
Capacitance A, B7 CA, CB f = 1 MHz, measured to
GND, code = 0x80
45 pF
Capacitance W7 CW f = 1 MHz, measured to
GND, code = 0x80
60 pF
Shutdown Supply Current8 IA_SD VDD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High9 VIH VDD = 5 V 0.7 VDD VDD + 0.5 V
Input Logic Low9 VIL VDD = 5 V 0.5 +0.3 VDD V
AD0 and AD1
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance7 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD_RANGE 2.7 5.5 V
OTP Supply Voltage9, 10 VDD_OTP TA = 25°C 5.6 5.7 5.8 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
OTP Supply Current9, 11, 12 IDD_OTP VDD_OTP = 5.0 V, TA = 25°C 100 mA
Power Dissipation13 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 33 µW
Power Supply Sensitivity
PSS
V
DD
= 5 V ± 10%,
code = midscale
±0.02
±0.08
DYNAMIC CHARACTERISTICS14
Bandwidth, −3 dB BW Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,
f = 1 kHz
0.1 %
Data Sheet AD5172/AD5173
Rev. I | Page 5 of 28
Parameter Symbol Conditions Min Typ 1 Max Unit
VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB
error band
1 µs
Resistor Noise Voltage Density eN_WB RWB = 1.25 k, RS = 0 Ω 3.2 nV/Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10 Different from the operating power supply; the power supply for OTP is used one time only.
11 Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12 See Figure 30 for an energy plot during an OTP program.
13 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14 All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICSRHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect 2.5 ±0.25 +2.5 LSB
Nominal Resistor Tolerance3 ΔRAB TA = 25°C 20 +20 %
Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICSPOTENTIOMETER DIVIDER
MODE4
Differential Nonlinearity5 DNL −1 ±0.1 +1 LSB
Integral Nonlinearity5 INL −1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF 2.5 −1 0 LSB
Zero-Scale Error
V
WZSE
Code = 0x00
0
1
2.5
LSB
RESISTOR TERMINALS
Voltage Range6 VA, VB, VW GND VDD V
Capacitance A, B7 CA, CB f = 1 MHz, measured to
GND, code = 0x80
45 pF
Capacitance W7 CW f = 1 MHz, measured to
GND, code = 0x80
60 pF
Shutdown Supply Current8 IA_SD VDD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High
9
V
IH
V
DD
= 5 V
0.7 V
DD
V
DD
+ 0.5
V
Input Logic Low9 VIL VDD = 5 V 0.5 +0.3 VDD V
AD0 and AD1
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance7 CIL 5 pF
AD5172/AD5173 Data Sheet
Rev. I | Page 6 of 28
Parameter Symbol Conditions Min Typ 1 Max Unit
POWER SUPPLIES
Power Supply Range VDD_RANGE 2.7 5.5 V
OTP Supply Voltage9, 10 VDD_OTP TA = 25°C 5.6 5.7 5.8 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
OTP Supply Current
9, 11, 12
I
DD_OTP
V
DD_OTP
= 5.0 V, T
A
= 25°C
100
mA
Power Dissipation13 PDISS VIH = 5 V or VIL = 0 V,
VDD = 5 V
33 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%,
code = midscale
±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS14
Bandwidth, −3 dB BW RAB = 10 kΩ, code = 0x80 600 kHz
RAB = 50 kΩ, code = 0x80 100 kHz
RAB = 100 kΩ, code = 0x80 40 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
0.1 %
VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB
error band
2 µs
Resistor Noise Voltage Density eN_WB RWB = 5 kΩ, RS = 0 9 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10 Different from the operating power supply; the power supply for OTP is used one time only.
11 Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12 See Figure 30 for an energy plot during an OTP program.
13 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14 All dynamic characteristics use VDD = 5 V.
Data Sheet AD5172/AD5173
Rev. I | Page 7 of 28
TIMING CHARACTERISTICS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency fSCL 400 kHz
Bus-Free Time Between Stop and Start, tBUF t
1 1.3 μs
Hold Time (Repeated Start), tHD;STA t
2 After this period, the first clock
pulse is generated.
0.6 μs
Low Period of SCL Clock, tLOW t
3 1.3 μs
High Period of SCL Clock, tHIGH t
4 0.6 μs
Setup Time for Repeated Start Condition, tSU;STA t
5 0.6 μs
Data Hold Time, tHD;DAT2 t
6 0.9 μs
Data Setup Time, tSU;DAT t
7 100 ns
Fall Time of Both SDA and SCL Signals, tF t
8 300 ns
Rise Time of Both SDA and SCL Signals, tR t
9 300 ns
Setup Time for Stop Condition, tSU;STO t
10 0.6 μs
OTP Program Time t11 400 ms
1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).
2 The maximum tHD;DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
04103-0-039
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 3. I2C Interface Detailed Timing Diagram
AD5172/AD5173 Data Sheet
Rev. I | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Rating
VDD to GND 0.3 V to +7 V
VA, VB, VW to GND −0.3 V to +7 V or
VDD + 0.3 V
(whichever is less)
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1
Pulsed ±20 mA
Continuous
±5 mA
Digital Inputs and Output Voltage to GND −0.3 V to +7 V or
VDD + 0.3 V
(whichever is less)
Operating Temperature Range 40°C to +125°C
Maximum Junction Temperature (T
JMAX
)
150°C
Storage Temperature Range 65°C to +150°C
Reflow Soldering
Peak Temperature
260°C
Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance2
θJA for 10-Lead MSOP 200°C/W
1 The maximum terminal current is bound by the maximum current handling
of the switches, the maximum power dissipation of the package, and the
maximum applied voltage across any two of the A, B, and W terminals at a
given resistance.
2 The package power dissipation is (TJMAX − TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet AD5172/AD5173
Rev. I | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
B1 1
A1 2
W2 3
GND 4
VDD 5
W1
10
B2
9
A2
8
SDA
7
SCL
6
AD5172
TOP VIEW
(Not t o Scale)
04103-045
Figure 4. AD5172 Pin Configuration
Table 5. AD5172 Pin Function Descriptions
Pin
No. Mnemonic Description
1 B1 B1 Terminal. GND VB1 VDD.
2 A1 A1 Terminal. GND VA1 VDD.
3 W2 W2 Terminal. GND VW2 VDD.
4 GND Digital Ground.
5 VDD Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, VDD needs to be a minimum
of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.
6 SCL Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If this pin is driven
directly from a logic controller without a
pull-up resistor, ensure that the VIH minimum
is 0.7 V × VDD.
7 SDA Serial Data Input/Output. Requires a pull-up
resistor. If this pin is driven directly from a
logic controller without a pull-up resistor,
ensure that the VIH minimum is 0.7 V × VDD.
8 A2 A2 Terminal. GND VA2 VDD.
9 B2 B2 Terminal. GND VB2 VDD.
10 W1 W1 Terminal. GND VW1 VDD.
B1 1
AD0 2
W2 3
GND 4
VDD 5
W1
10
B2
9
AD1
8
SDA
7
SCL
6
AD5173
TOP VIEW
(Not t o Scale)
04103-046
Figure 5. AD5173 Pin Configuration
Table 6. AD5173 Pin Function Descriptions
Pin
No. Mnemonic Description
1 B1 B1 Terminal. GND VB1 VDD.
2 AD0 Programmable Address Bit 0 for Multiple
Package Decoding.
3 W2 W2 Terminal. GND VW2 VDD.
4
GND
Digital Ground.
5
V
DD
Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, VDD needs to be a minimum
of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.
6 SCL Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If this pin is driven
directly from a logic controller without a
pull-up resistor, ensure that the VIH minimum
is 0.7 V × VDD.
7 SDA Serial Data Input/Output. Requires a pull-up
resistor. If this pin is driven directly from a
logic controller without a pull-up resistor,
ensure that the VIH minimum is 0.7 V × VDD.
8 AD1 Programmable Address Bit 1 for Multiple
Package Decoding.
9
B2
B2 Terminal. GND V
B2
V
DD
.
10 W1 W1 Terminal. GND VW1 VDD.
AD5172/AD5173 Data Sheet
Rev. I | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640160 192 224 256
CODE ( DE CIMAL )
V
DD
= 5.5V
T
A
= 25° C
R
AB
= 10kΩ
V
DD
= 2.7V
04103-003
Figure 6. R-INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEO S TAT M ODE DNL (L S B)
1289632 640160 192 224 256
CODE ( DE CIMAL )
T
A
= 25° C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
04103-004
Figure 7. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE INL (LSB)
1289632 640160 192 224 256
CODE ( DE CIMAL )
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40° C, +25° C, +85°C, + 125°C
V
DD
= 5.5V
T
A
= –40° C, +25° C, +85°C, + 125°C
04103-005
Figure 8. INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTI O MET ER MODE DNL (LSB)
1289632 640160 192 224 256
CODE ( DE CIMAL )
V
DD
= 2.7V; T
A
= –40° C, +25° C, +85°C, + 125°C
R
AB
= 10kΩ
04103-006
Figure 9. DNL vs. Code vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
POTENTIOMETER MODE INL (LSB)
1289632 640160 192 224 256
CODE ( DE CIMAL )
T
A
= 25° C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
04103-007
Figure 10. INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTI O MET ER MODE DNL (LSB)
1289632 640160 192 224 256
CODE ( DE CIMAL )
T
A
= 25° C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
04103-008
Figure 11. DNL vs. Code vs. Supply Voltages
Data Sheet AD5172/AD5173
Rev. I | Page 11 of 28
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640160 192 224 256
CODE ( DE CIMAL )
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40° C, +25° C, +85°C, + 125°C
V
DD
= 5.5V
T
A
= –40° C, +25° C, +85°C, + 125°C
04103-009
Figure 12. R-INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT M ODE DNL (LSB)
1289632 640160 192 224 256
CODE ( DE CIMAL )
V
DD
= 2.7V, 5.5V; T
A
= –40° C, +25° C, +85°C, + 125°C
R
AB
= 10kΩ
04103-010
Figure 13. R-DNL vs. Code vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
FSE, F ULL -SCALE ERROR (LSB)
1.0
1.5
2.0
TEMPERATURE ( °C)
–40 –25 –10 520 35 50 65 80 95 110 125
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10kΩ
V
DD
= 2.7V, V
A
= 2.7V
04103-011
Figure 14. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZSE, Z ERO-SCALE ERROR (LSB)
TEMPERATURE ( °C)
–40 –25 –10 520 35 50 65 80 95 110 125
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10kΩ
V
DD
= 2.7V, V
A
= 2.7V
04103-012
Figure 15. Zero-Scale Error vs. Temperature
I
DD
, S UP P LY CURRENT (µA)
0.1
1
10
–40 –7 26 59 92 125
TEMPERATURE (°C)
V
DD
= 5V
V
DD
= 3V
04103-013
Figure 16. Supply Current vs. Temperature
–20
0
20
40
60
80
100
120
RHEOSTAT MODE TEMPCO (ppm/°C)
1289632 640160 192 224 256
CODE ( DE CIMAL )
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40° C TO + 85°C, –40°C T O +125°C
V
DD
= 5.5V
T
A
= –40° C TO + 85°C, –40°C T O +125°C
04103-014
Figure 17. Rheostat Mode Tempco ΔRWBT vs. Code
AD5172/AD5173 Data Sheet
Rev. I | Page 12 of 28
–30
–20
–10
0
10
20
POTENTIOMETER MODE TEMPCO (ppm/°C)
30
40
50
1289632 640160 192 224 256
CODE ( DE CIMAL )
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40° C TO + 85°C, –40°C T O +125°C
V
DD
= 5.5V
T
A
= –40° C TO + 85°C, –40°C T O +125°C
04103-047
Figure 18. AD5172 Potentiometer Mode Tempco ΔVWBT vs. Code
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (d B)
FREQUENCY (Hz)
10k 1M100k 10M
0x80
0x40
0x20
0x10
0x08
0x04
0x010x02
04103-048
Figure 19. Gain vs. Frequency vs. Code, RAB = 2.5 k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (d B)
FREQUENCY (Hz)
1k 100k10k 1M
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
04103-049
Figure 20. Gain vs. Frequency vs. Code, RAB = 10 k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (d B)
FREQUENCY (Hz)
1k 100k10k 1M
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
04103-050
Figure 21. Gain vs. Frequency vs. Code, RAB = 50 k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (d B)
FREQUENCY (Hz)
1k 100k10k 1M
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
04103-051
Figure 22. Gain vs. Frequency vs. Code, RAB = 100 k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (d B)
FREQUENCY (Hz)
10k1k 100k 1M 10M
100kΩ
60kHz
50kΩ
120kHz
10kΩ
570kHz
2.5kΩ
2.2MHz
04103-052
Figure 23. −3 dB Bandwidth at Code = 0x80
Data Sheet AD5172/AD5173
Rev. I | Page 13 of 28
I
DD
, SUPPLY CURRENT (mA)
0.01
1
0.1
10
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL I NP UT VOLTAGE (V)
T
A
= 25° C
V
DD
= 2.7V
V
DD
= 5.5V
04103-057
Figure 24. Supply Current vs. Digital Input Voltage
SCL
V
W
04103-053
Figure 25. Digital Feedthrough
V
W1
V
W2
04103-054
Figure 26. Digital Crosstalk
V
W1
V
W2
04103-056
Figure 27. Analog Crosstalk
V
W
04103-058
Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F
SCL
V
W
04103-055
Figure 29. Large-Signal Settling Time
AD5172/AD5173 Data Sheet
Rev. I | Page 14 of 28
04103-062
CH1 20.0mA M 200ns A CH1 32.4mA
1
T 588.000ns
TCHANNEL 1
MAXIMUM:
103mA
CHANNEL 1
MINIMUM:
–1.98mA
Figure 30. OTP Program Energy for Single Fuse
Data Sheet AD5172/AD5173
Rev. I | Page 15 of 28
TEST CIRCUITS
Figure 31 to Figure 38 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1 and Table 2).
V
MS
AW
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
04103-015
Figure 31. Potentiometer Divider Nonlinearity Error (INL, DNL)
NC
I
W
V
MS
AW
B
DUT
04103-016
NC = NO CONNECT
Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL)
V
MS1
I
W
= V
DD
/R
NOMINAL
V
MS2
V
W
R
W
= [V
MS1
– V
MS2
]/I
W
AW
B
DUT
04103-017
Figure 33. Wiper Resistance
Δ
V
MS
%
PSS (%/%) =
PSRR (dB) = 20 lo g
DUT
( )
V
DD
V
A
V
MS
AW
B
V+
Δ
V
DD
%
Δ
V
MS
Δ
V
DD
V+ = V
DD ± 10%
04103-018
Figure 34. Power Supply Sensitivity (PSS, PSSR)
+5V
–5V
W
A
2.5V B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
04103-019
Figure 35. Test Circuit for Gain vs. Frequency
W
B
DUT
I
SW
CODE = 0x00
R
SW
=0.1V
I
SW
0.1V
GND TO V
DD
04103-020
Figure 36. Incremental On Resistance
V
DD
AW
B
DUT
GND
I
CM
V
CM
NC
NC
04103-021
NC = NO CONNECT
Figure 37. Common-Mode Leakage Current
V
IN
NC W1
B1 B2
W2
RDAC1
A1
RDAC2
V
DD
V
SS
V
OUT
CTA = 20 lo g[V
OUT
/V
IN
]
NC = NO CONNECT
A2
04103-022
Figure 38. Analog Crosstalk
AD5172/AD5173 Data Sheet
Rev. I | Page 16 of 28
THEORY OF OPERATION
SDA
SCL A
W
B
FUSES
EN
DAC
REG
I
2
C INT E RFACE
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONT ROL BLO CK
MUX DECODER
FUSE
REG
04103-026
Figure 39. Detailed Functional Block Diagram
The AD5172/AD5173 are 256-position, digitally controlled
variable resistors (VRs) that employ fuse link technology to
achieve memory retention of the resistance setting.
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function is activated, the device
powers up at the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5172/AD5173 presets to midscale
during initial power-on. After the wiper is set to the desired
position, the resistance can be permanently set by programming
the T bit high, with the proper coding (see Table 8 and Table 9),
and one-time VDD_OTP. The fuse link technology of the AD517x
family of digital potentiometers requires VDD_OTP to be between
5.6 V and 5.8 V to blow the fuses to achieve a given nonvolatile
setting. However, during operation, VDD can be 2.7 V to 5.5 V. As a
result, an external supply is required for one-time programming.
The user is allowed only one attempt to blow the fuses. If the user
fails to blow the fuses during this attempt, the structure of the
fuses can change such that they may never be blown, regardless
of the energy applied during subsequent events. For details, see
the Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting. Figure 39
shows a detailed functional block diagram.
Table 7. Validation Status
E1 E0 Status
0 0 Ready for programming.
1 0 Fatal error. Some fuses are not blown. Do not retry.
Discard this unit.
1 1 Successful. No further programming is possible.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal and the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the
256 possible settings.
A
W
B
A
W
B
A
W
B
04103-027
Figure 40. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminal W and Ter-
minal B. The second connection is the first tap point, which
corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 ×
50 Ω) for Data 0x01. The third connection is the next tap point,
representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so
on. Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
Data Sheet AD5172/AD5173
Rev. I | Page 17 of 28
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
0
4103-028
Figure 41. AD5172/AD5173 Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR 2
128
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB is 10 kΩ and the A terminal is open circuited,
the output resistance, RWB, is set according to the RDAC latch
codes, as listed in Table 8.
Table 8. Codes and Corresponding RWB Resistance
D (Dec) RWB (Ω) Output State
255 9961 Full scale (RAB – 1 LSB + RW)
128 5060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible destruc-
tion of the internal switch contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digi-
tally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
DR 2
128
256
)( (2)
When RAB is 10 kΩ and the B terminal is open circuited, the
output resistance, RWA , is set according to the RDAC latch
codes, as listed in Table 9.
Table 9. Codes and Corresponding RWA Resistance
D (Dec) RWA (Ω) Output State
255 139 Full scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero scale
Typical device-to-device matching is process-lot dependent
and can vary up to ±30%. Because the resistance element is
processed using thin-film technology, the change in RAB with
temperature has a very low temperature coefficient of 35 ppm/°C.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and at wiper to A, proportional to the input voltage
at A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04103-029
Figure 42. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the vol-
tage applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
WV
D
V
D
DV
256
256
256
)(
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( (4)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RWA and RWB, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.
AD5172/AD5173 Data Sheet
Rev. I | Page 18 of 28
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as
shown in Figure 43 and Figure 44.
LOGIC
340Ω
GND
04103-030
Figure 43. ESD Protection of Digital Pins
A, B, W
GND
04103-031
Figure 44. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5172/AD5173 VDD to GND power