N01S818HAT22IT - ON SEMICONDUCTOR

September, 2013 − Rev. 0

1Publication Order Number:

N01S818HA/D

N01S818HA

1 Mb Ultra-Low Power

Serial SRAM

Standard SPI Interface and Multiplex

DUAL and QUAD Interface

Overview

The ON Semiconductor serial SRAM family includes several

integrated memory devices including this 1 Mb serially accessed

Static Random Access Memory, internally organized as 128 K words

by 8 bits. The devices are designed and fabricated using

ON Semiconductor’s advanced CMOS technology to provide both

high-speed performance and low power. The devices operate with a

single chip select (CS) input and use a simple Serial Peripheral

Interface (SPI) protocol. In SPI mode, a single data-in (SI) and

data-out (SO) line is used along with the clock (SCK) to access data

within the device. In DUAL mode, two multiplexed data-in/data-out

(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed

data-in/data-out (SIO0-SIO3) lines are used with the clock to access

the memory.

The devices can operate over a wide temperature range of −40°C to

+85°C and are available in a 8-lead TSSOP package.

Features

•Power Supply Range: 1.7 to 2.2 V

•Very Low Typical Standby Current < 1 mA

•Very Low Operating Current < 10 mA

•Simple Serial Interface

♦Single-bit SPI Access

♦DUAL-bit and QUAD-bit SPI-like Access

•Flexible Operating Modes

♦Word Mode

♦Page Mode

♦Burst Mode (Full Array)

•High Frequency Read and Write Operation

♦Clock Frequency 20 MHz

•Built-in Write Protection (CS High)

•High Reliability

♦Unlimited Write Cycles

•These Devices are Pb−Free and are RoHS Compliant

♦Green TSSOP

Table 1. DEVICE OPTIONS

Device / Part Number Power Supply Speed Package Function

N01S818HAT22I 1.7 V − 2.2 V 20 MHz TSSOP−8 HOLD

http://onsemi.com

Device Package Shipping†

ORDERING INFORMATION

N01S818HAT22I TSSOP−8

(Pb−Free)

100 Units / Tube

TSSOP8 3x4.4

CASE 948BH

PACKAGE CONFIGURATION

SO / SIO1

NC / SIO2

VSS

VCC

HOLD / SIO3

SCK

SI / SIO0

N01S818HAT22IT TSSOP−8

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

N01S818HA

http://onsemi.com

Table 2. PIN NAMES

Pin Name Pin Function

CS Chip Select

SCK Serial Clock

SI / SIO0 Data Input − SPI mode

Data Input/Output 0 − DUAL and QUAD mode

SO / SIO1 Data Output − SPI mode

Data Input/Output 1 − DUAL and QUAD mode

SC / SIO2 No Connect − SPI and DUAL mode

Data Input/Output 2 − QUAD mode

HOLD / SIO3 HOLD Input − SPI and DUAL mode

Data Input/Output 3 − QUAD mode

VCC Power

VSS Ground

Figure 1. Functional Block Diagram

SRAM

Array

Control

Logic

Interface

Circuitry

Decode

Logic

Data Flow

Circuitry

SI / SIO0

SO / SIO1

SIO2

HOLD / SIO3

SCK

Table 3. CONTROL SIGNAL DESCRIPTIONS

Signal

Mode

Used Name Description

CS All Chip Select A low level selects the device and a high level puts the device in standby mode. If CS is brought

high during a program cycle, the cycle will complete and then the device will enter standby mode.

When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence

being started.

SCK All Serial Clock Synchronizes all activities between the memory and controller. All incoming addresses, data and

instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of

SCK.

SI SPI Serial Data In Receives instructions, addresses and data on the rising edge of SCK.

SO SPI Serial Data Out Data is transferred out after the falling edge of SCK.

HOLD SPI and

DUAL

Hold A high level is required for normal operation. Once the device is selected and a serial sequence

is started, this input may be taken low to pause serial communication without resetting the serial

sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low,

the HOLD function will not be invoked until the next SCK high to low transition. The device must

remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are

inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low.

Lowering the HOLD input at any time will take to SO output to High-Z.

SIO0 - 1 DUAL Serial Data

Input / Output

Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out

after the falling edge of SCK. The instruction must be set after power-up to enable the DUAL

access mode.

SIO0 - 3 QUAD Serial Data

Input / Output

Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out

after the falling edge of SCK. The instruction must be set after power-up to enable the QUAD

access mode.

N01S818HA

http://onsemi.com

Basic Operation

The 1 Mb serial SRAM is designed to interface directly

with a standard Serial Peripheral Interface (SPI) common on

many standard micro-controllers in the default state. It may

also interface with other non-SPI ports by programming

discrete I/O lines to operate the device.

The serial SRAM contains an 8-bit instruction register and

is accessed via the SI pin. The CS pin must be low and the

HOLD pin must be high for the entire operation. Data is

sampled on the first rising edge of SCK after CS goes low.

If the clock line is shared, the user can assert the HOLD input

and place the device into a Hold mode. After releasing the

HOLD pin, the operation will resume from the point where

it was held. The Hold operation is only supported in SPI and

DUAL modes.

By programming the device through a command

instruction, the dual and quad access modes may be initiated.

In these modes, multiplexed I/O lines take the place of the

SPI SI and SO pins and along with the CS and SCK control

the device in a SPI-like, two bit (DUAL) and four bit

(QUAD) wide serial manner. Once the device is put into

either the DUAL or QUAD mode, the device will remain

operating in that mode until powered down or the Reset

Mode operation is programmed.

The following table contains the possible instructions and

formats. All instructions, addresses and data are transferred

MSB first and LSB last.

Table 4. INSTRUCTION SET

Instruction Command Description

READ 03h Read data from memory starting at selected address

WRITE 02h Write (program) data to memory starting at selected address

EQIO 38h Enable QUAD I/O access

EDIO 3Bh Enable DUAL I/O access

RSTQIO FFh Reset from QUAD and DUAL to SPI I/O access

RDMR 05h Read mode register

WRMR 01h Write mode register

DEVICE OPERATIONS

Read Operation

The serial SRAM Read operation is started by by enabling

CS low. First, the 8-bit Read instruction is transmitted to the

device through the SI (or SIO0-3) pin(s) followed by the

24-bit address with the 7 MSBs of the address being “don’t

care” bits and ignored. In SPI mode, after the READ

instruction and address bits are sent, the data stored at that

address in memory is shifted out on the SO pin after the

output valid time. Additional “dummy” clock cycles (four in

DUAL and two in QUAD) are required to follow the

instruction and address inputs prior to the data being driven

out on the SIO0-3 pins while operating in these two modes.

By continuing to provide clock cycles to the device, data

can continue to be read out of the memory array in

sequentially. The internal address pointer is automatically

incremented to the next higher address after each byte of

data is read out until the highest memory address is reached.

When the highest memory address is reached, 1FFFFh, the

address pointer wraps to the address 00000h. This allows the

read cycles to be continued indefinitely. All Read operations

are terminated by pulling CS high.

Figure 2. SPI Read Sequence (Single Byte)

Instruction

04325169810711

SCK

23 22 21 20 210

76543210High−Z

24−bit address

Data Out

29 3130 32 36 37 38 3934 3533

000 00011

N01S818HA

http://onsemi.com

Figure 3. SPI Read Sequence (Sequential Bytes)

Instruction

04325169810711

SCK

23 22 21 20 210

76543210High−Z

24−bit address

Data Out from ADDR 1

29 3130 32 36 37 38 3934 3533

000 00 011

76543210

Data Out from ADDR 2

76543210 76543210

...

40 4241 43 47 48 49 5045 4644 51 5352 54 55

Don’t Care

ADDR 1

Data Out from ADDR 3 Data Out from ADDR n

Figure 4. DUAL Read Sequence

SIO[1:0]

043251121514 1613 17

SCK

A11 A0

18 2019

C3 C2 A10 A3 A2 A1 H0 H0 L0 L0 H1 H1 L1 L1

MSB MSB

Notes:

Instruction 24−bit address Data out

21 22

C1 C0 XX

23 24 25 26

C[3:0] = 03h

H0 = 2 high order bits of data byte 0

L0 = 2 low order bits of data byte 0

H1 = 2 high order bits of data byte 1

L1 = 2 low order bits of data byte 1

Figure 5. QUAD Read Sequence

SIO[3:0]

04325169810711

SCK

A5 A0

12 1413

C1 C0 A4 A3 A2 A1 H0 L0 H1 L1 H2 L2 H3 L3

MSB MSB

Notes:

Instruction 24−bit address Data out

15 16

C[1:0] = 03h

H0 = 4 high order bits of data byte 0

L0 = 4 low order bits of data byte 0

H1 = 4 high order bits of data byte 1

L1 = 4 low order bits of data byte 1

N01S818HA

http://onsemi.com

Write Operation

The serial SRAM WRITE is selected by enabling CS low.

First, the 8-bit WRITE instruction is transmitted to the

device followed by the 24-bit address with the 7 MSBs being

don’t care. After the WRITE instruction and addresses are

sent, the data to be stored in memory is shifted in on the SI

pin.

If operating in page mode, after the initial word of data is

shifted in, additional data words can be written as long as the

address requested is sequential on the same page. Simply

write the data on SI pin and continue to provide clock pulses.

The internal address pointer is automatically incremented to

the next higher address on the page after each word of data

is written in. This can be continued for the entire page length

of 32 words long. At the end of the page, the addresses

pointer will be wrapped to the 0 word address within the

page and the operation can be continuously looped over the

32 words of the same page. The new data will replace data

already stored in the memory locations.

If operating in burst mode, after the initial word of data is

shifted in, additional data words can be written to the next

sequential memory locations by continuing to provide clock

pulses. The internal address pointer is automatically

incremented to the next higher address after each word of

data is read out. This can be continued for the entire array

and when the highest address is reached, 1FFFFh, the

address counter wraps to the address 00000h. This allows

the burst write cycle to be continued indefinitely. Again, the

new data will replace data already stored in the memory

locations.

All WRITE operations are terminated by pulling CS high.

Figure 6. SPI Write Sequence

Instruction

04325169810711

SCK

23 22 21 20 21076543210

High−Z

24−bit address Data In to ADDR 1

29 3130 32 36 37 38 3934 3533

000 00 010

76543210

Data In to ADDR 2

76543210 76543210

...

40 4241 43 47 48 49 5045 4644 51 5352 54 55

ADDR 1

Data In to ADDR 3 Data In to ADDR n

High−Z

N01S818HA

http://onsemi.com

Figure 7. DUAL Write Sequence

H0 H0 L0 L0 H1 H1 Ln Ln

Data in

MSB

Notes:

SIO1:0]

043251121514 1613 17

SCK

A11 A0

18 2019

C3 C2 A10 A3 A2 A1

MSB

Instruction 24−bit address

C1 C0

C[3:0] = 02h

H0 = 2 high order bits of data byte 0

L0 = 2 low order bits of data byte 0

H1 = 2 high order bits of data byte 1

L1 = 2 low order bits of data byte 1

Figure 8. QUAD Write Sequence

04325169810711

SCK

12 13

Instruction

SIO[3:0] A5 A0

24−bit address

C1 C0 A4 A3 A2 A1 H0 L0 H1 L1 H2 L2 Hn Ln

Data in

MSB MSB

Notes: C[1:0] = 02h

H0 = 4 high order bits of data byte 0

L0 = 4 low order bits of data byte 0

H1 = 4 high order bits of data byte 1

L1 = 4 low order bits of data byte 1

READ Mode Register (RDMR)

This instruction provides the ability to read the mode

during a Write operation. The Read Mode Register

operation is executed by driving CS low, then sending the

RDMR instruction to the device. Immediately after the

instruction, the device outputs data on the SO (SIO0-3)

pin(s). To complete the operation, drive CS high to terminate

the register read.

Figure 9. SPI Read Mode Register Sequence (RDMR)

Instruction

04325169810711

SCK

76543210High−Z

Mode Register Data Out

00 000 10

12 13 14 15

N01S818HA

http://onsemi.com

Figure 10. DUAL Read Mode Register Sequence (RDMR)

C[3:0] = 05hNotes:

Instruction

0321

SCK

C3 C2 H L

MSB

Mode Bits

SIO[1:0]

LHC1 C0

Figure 11. QUAD Read Mode Register Sequence (RDMR)

C[1:0] = 05hNotes:

Instruction

0321

SCK

C1 C0 H L

MSB

Mode Bits

SIO[3:0]

Write Mode Register (WRMR)

This instruction provides the ability to write the mode

driving CS low, then sending the WRMR instruction to the

device. Immediately after the instruction, the data is driven

to the device on the SO (SIO0-3) pin(s). To complete the

operation, drive CS high to terminate the register write.

Figure 12. SPI Write Mode Register Sequence

Instruction

04325169810711

SCK

76543210

High−Z

Mode Register Data In

00 000 10

12 13 14 15

Figure 13. DUAL Write Mode Register Sequence

C[3:0] = 01hNotes:

Instruction

0321

SCK

C3 C2 H L

MSB

Mode Bits

SIO[1:0]

LHC1 C0

N01S818HA

http://onsemi.com

Figure 14. QUAD Write Mode Register Sequence

Instruction

0321

SCK

C1 C0 H L

C[1:0] = 01hNotes:

MSB

Mode Bits

SIO[3:0]

Table 5. MODE REGISTER

Bit Function

0Hold Function

1 = Hold function disabled

0 = Hold function enabled (Default)

1 Reserved

2 Reserved

3 Reserved

4 Reserved

5 Reserved

6Operating Mode

Bit 7 Bit 6

0 0 = Word Mode

1 0 = Page Mode

0 1 = Burst Mode (Default)

1 1 = Reserved

Power-Up State

The serial SRAM enters a know state at power-up time.

The device is in low-power standby state with CS = 1. A low

level on CS is required to enter a active state.

Table 6. ABSOLUTE MAXIMUM RATINGS

Item Symbol Rating Units

Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC +0.3 V

Voltage on VCC Supply Relative to VSS VCC –0.3 to 5.5 V

Power Dissipation PD500 mW

Storage Temperature TSTG –40 to 125 °C

Operating Temperature TA-40 to +85 °C

Soldering Temperature and Time TSOLDER 260°C, 10 sec °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 7. OPERATING CHARACTERISTICS (OVER SPECIFIED TEMPERATURE RANGE)

Item Symbol Test Conditions Min Typ (Note 1) Max Units

Supply Voltage VCC 1.7 2.2 V

Data Retention Voltage (Note 2) VDR 1.0 V

Input High Voltage VIH 0.7 VCC VCC + 0.3

Input Low Voltage VIL −0.3 0.2 VCC V

Output High Voltage VOH IOH = −0.4 mA VCC − 0.2 V

Output Low Voltage VOL IOL = 1 mA 0.2 V

Input Leakage Current ILI CS = VCC, VIN = 0 to VCC 1.0 mA

Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 1.0 mA

Operating Current ICC f = 20 MHz, IOUT = 0, SPI / DUAL 10 mA

f = 20 MHz, IOUT = 0, QUAD 10

Standby Current ISB CS = VCC, VIN = VSS or VCC 1 5 mA

1. Typical values are measured at VCC = VCC Typ., TA = 25°C and are not 100% tested.

2. Typical lower limit of VCC when data will be retained in the memory array, not 100% tested.

N01S818HA

http://onsemi.com

Table 8. CAPACITANCE (Note 3)

Item Symbol Test Conditions Min Max Units

Input Capacitance CIN VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF

I/O Capacitance CI/O VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF

3. These parameters are verified in device characterization and are not 100% tested.

Table 9. TIMING TEST CONDITIONS

Item Value

Input Pulse Level 0.1 VCC to 0.9 VCC

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Levels 0.5 VCC

Output Load CL = 30 pF

Operating Temperature −40 to +85°C

Table 10. TIMING

Item Symbol Min Max Units

Clock Frequency fCLK 20 MHz

Clock Period tCLK 50 ns

Clock Rise Time tR 20 ns

Clock Fall Time tF 20 ns

Clock High Time tHI 25 ns

Clock Low Time tLO 25 ns

Clock Delay Time tCLD 25 ns

CS Setup Time tCSS 25 ns

CS Hold Time tCSH 50 ns

CS Disable Time tCSD 25 ns

SCK to CS tSCS 5 ns

Data Setup Time tSU 10 ns

Data Hold Time tHD 10 ns

Output Valid From Clock Low tV 25 ns

Output Hold Time tHO 0 ns

Output Disable Time tDIS 20 ns

HOLD Setup Time tHS 10 ns

HOLD Hold Time tHH 10 ns

HOLD Low to Output High-Z tHZ 10 ns

HOLD High to Output Valid tHV 50 ns

N01S818HA

http://onsemi.com

Figure 15. SPI Input Timing

tCSS

MSB in

SCK

SI LSB in

tCLD

tCSH

tCSD

tSU tHD

High−Z

tSCS

Figure 16. SPI Output Timing

tLO

MSB out

SCK

SO LSB out

tDIS

tCSH

tHI

Don’t Care

Figure 17. SPI Hold Timing

tHS

n+2

SCK

tSU

tHZ

tHH

n+1 n High−Z

tHS

tHH

tHV nn−1

nn−1

n+2 n+1 n

HOLD

Don’t Care

N01S818HA

http://onsemi.com

Figure 18. QUAD Input Timing

tCSS

MSB in

SCK

SI0 LSB in

tCLD

tCSH

tCSD

tSU tHD

tSCS

Figure 19. QUAD Output Timing

tLO

MSB out

SCK

SIO LSB out

tDIS

tCSH

tHI

N01S818HA

http://onsemi.com

PACKAGE DIMENSIONS

TSSOP8 3x4.4 / TSSOP8 (225 mil)

CASE 948BH

ISSUE O

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

N01S818HA/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative