Apr i l 2003
Preliminary
Copyright © Alliance Semiconductor. All rights reserved.
®AS7C31025B
3.3V 128K X 8 CMOS SRAM (Center power and ground)
3/31/03, v. 042003 Alliance Semiconductor P. 1 of 8
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 8/10/12/15/20 ns address access time
- 5, 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 270 mW / max @ 8 ns
• Low power consumption: STANDBY
- 18 mW / max CMOS
• Latest 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
VCC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C31025B
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A9
A8
A4
A5
A6
A7
A12
A11
A10
32-pin TSOP 2
AS7C31025B
Selection guide
-8 -10 -12 -15 -20 Unit
Maximum address access time 8 10 12 15 20 ns
Maximum output enable access time55678ns
Maximum operating current 7570656055mA
Maximum CMOS standby current55555mA
AS7C31025B
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Functional description
The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8 bits. It
is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 8/10/12/15/20 ns with output ena b le access times (tOE) of 5, 5, 6, 7, 8 ns are ideal f or
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When
CE
is high the device enters standby mode. A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on
the input pins I/O0 through I/O7 is written on the rising edge of
WE
(wr i te cycle 1) or
CE
(write cycle 2). To avoid bu s contention , external
devices should drive I/O pins only after outputs have been disabled withRXWSXWHQDEOH
OE
RUZULWHHQDEOH (
WE
).
A read cycle is accomplished by asser ting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packa ged in common industry
standard packages.
NOTE: Stresses gr eater than those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliab ility.
Key: X = don’t care, L = low, H = high.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 o C
Ambient temperature with VCC applied Tbias –55 +125 o C
DC current into out pu t s (low) IOUT –20mA
Truth table
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
AS7C31025B
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†VIL min. = –3.0 V for pulse width less than tRC/2.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltag e VCC 3.0 3.3 3.6 V
Input voltage VIH 2.0 – VCC + 0.5 V
VIL†–0.5 – 0.8 V
Ambient operating temperature TA0–70
o C
TA–40 – 85 o C
DC operating characteristics (over the operating range)
Parameter Sym Test conditions
-8 -10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max Min Max
Input leakage
current | ILI | VCC = Max, VIN = GND to VCC –1–1–1–1–1µA
Output leakage
current | ILO | VCC = Max, CE = VIH,
Vout = GND to VCC –1–1–1–1–1µA
Operating power
supply current ICC CE = VIL, f = fMax,
IOUT = 0 mA –75–70–65–60–55
mA
Standby power
supply current
ISB CE = VIH, f = fMax, fOUT = 0 –30–30–25–20–20
mA
ISB1 CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V,
f = 0, fOUT = 0 –5–5–5–5–5mA
Output voltage VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4–0.4–0.4V
VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – 2.4 – V
Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE VIN = 0 V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF
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Key to switching waveforms
Read waveform 1 (address controlled)
Read waveform 2 (CE and OE controlled)
Read cycle (over the operating range)
Parameter Symbol
-8 -10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max Min Max
Read cycle time tRC 8 – 10 – 12 – 15 – 20 – ns
Address access time tAA – 8 – 10 – 12 – 15 – 20 ns 3
Chip enable (CE) access time tACE – 8 – 10 – 12 – 15 – 20 ns 3
Output enable (OE) access time tOE –5–5–6–7–8ns
Output hold from address change tOH 3–3–3–3–3–ns 5
CEORZWo output in low Z tCLZ 3–3–3–3–3–ns4, 5
CE high to output in high Z tCHZ –3–3–3–4–5ns4, 5
OE low to output in low Z tOLZ 0–0–0–0–0–ns4, 5
OE high to output in high Z tOHZ –4–5–6–7–8ns4, 5
P ower up time tPU 0–0–0–0–0–ns4, 5
P ower down time tPD – 8 – 10 – 12 – 15 – 20 ns 4, 5
Undefined/don’t careFalling inputRising input
Address
DOUT Data valid
tOH
tAA
tRC
current
Supply
OE
DOUT
tOE
tOLZ
tACE tCHZ
tCLZ
tPU tPD ICC
ISB
50% 50%
Data valid
tRC1
CE
tOHZ
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Write waveform 1 (WE controlled)
Write waveform 2 (CE controlled)
Write cycle (over the operating range)
Parameter Symbol
-8 -10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max Min Max
Write cycle time tWC 8 –10–12–15–20– ns
Chip enable (CE) to write end tCW 7–8–9–10–12– ns
Address setup to write end tAW 7–8–9–10–12– ns
Address setup time tAS 0–0–0–0–0– ns
Write pulse width tWP 6–7–8–9–12– ns
Write recovery time tWR 0–0–0–0–0– ns
Address hold from end of write tAH 0–0–0–0–0– ns
Data valid to write end tDW 5–5–6–8–10– ns
Data hold time tDH 0–0–0–0–0– ns 4, 5
Write enable to output in high Z tWZ –4–5–6–7–8 ns 4, 5
Output activ e from write end tOW 1–1–1–1–1– ns 4, 5
tAW tAH
tWC
Address
WE
DOUT
tDH
tOW
tDW
tWZ
tWP
tAS
Data valid
DIN
tWR
tAW
Address
CE
WE
DOUT
tCW
tWP
tDW tDH
tAH
tWZ
tWC
tAS
Data valid
DIN
tWR
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AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specif ication.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4t
CLZ and tCHZ are specified with CL = 5 pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is high for read cycle.
7CE
and OE are low for read cycle.
8 Address is valid prior to or coincident with CE transit ion low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be high during address transitions. Either CE or WE asserting high term inates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
255
Ω
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
C13
320 Ω
DOUT
GND
+3.3 V
168 Ω
Thevenin equivalent:
DOUT +1.728 V (5 V and 3.3 V)
Figure C: 3.3 V O u tpu t lo ad
255 ΩC13
480
Ω
DOUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pu lse
2 ns
AS7C31025B
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Package dimensions
32-pin TSOP 2
NN/2+1
1N/2
D
E1 E
L
ac
ZD
cbA1
ASeating plane
eD
E1
Pin 1
b
B
A1
A2 c
E
Seating
plane
E2
A
32-pin SOJ
300 mil/400 mil
Symbol
32-pin TSOP 2 (mm)
Min Max
A–1.2
A1 0.05 0.15
b0.3 0.52
C0.12 0.21
D20.82 21.08
E1 10.03 10.29
E11.56 11.96
e1.27 BSC
L0.40 0.60
ZD 0.95 REF.
α0° 5°
Symbol
32-pin SOJ
300 mil 32-pin SOJ
400 mil
Min Max Min Max
A-0.145-0.145
A1 0.025 - 0.025 -
A2 0.086 0.105 0.086 0.115
B0.026 0.032 0.026 0.032
b0.014 0.020 0.015 0.020
c0.006 0.013 0.007 0.013
D0.820 0.830 0.820 0.830
E0.250 0.275 0.360 0.380
E1 0.292 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e0.050 BSC 0.050 BSC
AS7C31025B
© C o py rig h t A llia nc e S e m ico n du c tor C or po ra tion . All righ ts re ser ve d. O ur thr ee- p oin t lo go , o ur na m e an d I nte lliw a tt ar e tra de m a rks or registered trademarks of Alliance. All other brand and
p
ro du ct n ames may b e th e trad emark s o f th eir r esp e ctiv e c ompan ie s. A llia nc e re ser ve s th e rig h t to mak e ch a ng es to th is d oc umen t and its products at any time without notice. A lliance assum es no
res po n sibilit y f or an y e rro rs tha t m a y a pp e ar in th is do c umen t. T h e d ata co nta in ed he rein re p res en ts A llia nc e’s b est d ata an d /or estim ates at the time of issu ance. Alliance reserves the right to
ch an g e o r co rr ect th is d ata at a ny time, w ith ou t n oti ce. If th e p ro d uc t de scr ibe d h e rein is u n de r d ev elo pmen t, sig nif ica nt c ha ng es to th ese sp ecif ica tion s a re p o ssib le. T h e in f or m atio n in this
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again st all claim s arising fro m such use.
3/31/03, v. 042003 Alliance Semiconductor P. 8 of 8
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Ordering Codes
Part numbering system
Package \
Access time Temperature 8 ns 10 ns 12 ns 15 ns 20 ns
TSOP 2 Commercial AS7C31025B-
8HFC AS7C31025B-
10HFC AS7C31025B-
12HFC AS7C31025B-
15HFC AS7C31025B-
20HFC
Industrial AS7C31025B-
10HFI AS7C31025B-
12HFI AS7C31025B-
15HFI AS7C31025B-
20HFI
300-mil SOJ Commercial AS7C31025B-
8TJC AS7C31025B-
10TJC AS7C31025B-
12TJC AS7C31025B-
15TJC AS7C31025B-
20TJC
Industrial AS7C31025B-
10TJI AS7C31025B-
12TJI AS7C31025B-
15TJI AS7C31025B-
20TJI
400-mil SOJ Commercial AS7C31025B-
8JC AS7C31025B-
10JC AS7C31025B-
12JC AS7C31025B-
15JC AS7C31025B-
20JC
Industrial AS7C31025B-
10JI AS7C31025B-
12JI AS7C31025B-
15JI AS7C31025B-
0JI
AS7C X1025B –XX X X
SRAM
prefix Voltage:
3 = 3.3 V CMOS Device number Access time
Package:
HF = TSOP 2 / 32 pin
TJ = SOJ 300 mil
J = SOJ 400 mil
Temperature range
C = commercial, 0° C to 70° C
I = industrial, -40° C to 85° C