CY7C1380A-100AC - Cypress Semiconductor Corp.

512K x 36 / 1M x 18 Pipelined SRAM

CY7C1380A

CY7C1382A

PRELIMINARY

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Ma y 18, 2000

Features

• Fast c lock speed: 167, 150, 133, 100 MHz

• Provi de high-performance 3-1-1-1 access rate

• Fast OE access times: 3. 4, 3.8, 4.2 and 5. 0 ns

• Optimal for depth expansion

• 3.3V (–5% / +10%) power supply

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeli ne

• Address, data, and control registers

• Internally self-tim ed Writ e Cycle

• Burst control pins (interlea ved or li near burst se-

quence)

• A utomatic power-down for portable applications

• High-density, high -speed packages

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1380A and CY7C1382A SRAMs integrate

524,288x36 and 1,048,576x18 SRAM cells with advanced

synchronous peripheral circuitry and a 2-bit counter for inter-

nal burst operation. All synchronous inputs are gated by reg-

isters controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs incl ude all addresses, all dat a

inputs, address-pipelining Chip Enable (CE), bu rs t c ont ro l i n-

puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,

BWc, BW d and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

burs t mode c ontrol (MO DE). The da ta (DQa,b,c,d) and t he data

parity (DQ Pa,b,c,d) outputs , enab l ed by OE, are al so async hro -

nous.

DQa,b,c,d and DQPa,b,c,d apply to CY7C1380 and DQa,b and

DQPa,b apply to CY7C1382. a, b, c, d each are 8 bits wide in

the case of DQ and 1 bit wide in the case of DP.

Addresses and chip enables are registered with either Ad-

dress Status Processor ( ADSP) or Address Status Controller

(ADSC) inp ut pins. Subsequent burst addresses can be inter -

nally gener ated as cont roll ed b y t he Burst Adv ance Pin (ADV).

Address , data inputs, and write cont rols are register ed on-chip

to initiate self-timed W RITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa and DQPa. BWb c ontrols DQb a nd DQPb. BWc

controls DQcand DQPd. BWd controls DQd-DQd and DQ Pd.

BWa, BWb, BWc, a nd BWd can be act ive only with BWE being

LOW. GW being LOW causes all bytes to be written. WRITE

pass-through capability allows written data available at the out-

put for the immediately next READ cycle. This device also in-

corporates pipelined enable circuit for easy depth expansion

without penalizing system per formance.

All input s and output s of the CY7C1380 A and the CY7C1382A

are JEDEC standard JESD8-5 compat ible.

Selection Guide

167 MHz 150 MHz 133 MHz 100 MHz

Maximum Access Time (ns) 3.4 3.8 4.2 5.0

Maxim um Ope rating Current (mA) Commercial 350 310 280 250

Maximum CMOS Standby Current (mA) 30 30 30 30

Shaded areas contain advance information.

PRELIMINARY CY7C1380A

CY7C1382A

Log ic Block Diagram CY7C1380A - 512K x 36

CY 7C138 2A - 1M X 18

CLK

ADV

ADSC

A[18:0]

BWE

BWd

BWc

BWb

BWa

CE1

CE3

CE2

BURST

COUNTER

ADDRESS

OUTPUT

REGISTERS INPUT

REGISTERS

512KX36

MEMORY

ARRAY

CLK CLK

CLR

SLEEP

CONTROL

36 36

(A[1;0])2

MODE

ADSP

DQa,b,c,d

DPa,b

DQd, DPd

BYTEWRITE

REGISTERS

DQc, DPc

BYTEWRITE

REGISTERS

DQb, DPb

BYTEWRITE

REGISTERS

DQa, DPa

BYTEWRITE

REGISTERS

ENABLE CE

ENABLE DELAY

CLK

ADV

ADSC

A[19:0]

BWE

BWb

BWa

CE1

CE3

CE2

BURST

COUNTER

ADDRESS

OUTPUT

REGISTERS INPUT

REGISTERS

MEMORY

ARRAY

CLK CLK

CLR

SLEEP

CONTROL

18 18

(A[1;0])2

MODE

ADSP

DQa,b

DPa,b

DQb, DPb

BYTEWRITE

REGISTERS

DQa, DPa

BYTEWRITE

REGISTERS

ENABL E CE

ENABLE DELAY

1M X 18

PRELIMINARY CY7C1380A

CY7C1382A

Pin Configurations

DDQ

SSQ

DPa

DQa

SSQ

DDQ

DQa

DDQ

SSQ

DQa

SSQ

DDQ

SSQ

DQb

SSQ

DDQ

DQb

DDQ

SSQ

DQb

DPb

SSQ

DDQ

BWb

BWa

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1382A

(1M x 18)

DQPb

DQb

DDQ

SSQ

DQb

SSQ

DDQ

DQb

DQa

DDQ

SSQ

DQa

SSQ

DDQ

DQa

DQPa

DQPc

DQc

DDQ

SSQ

DQc

SSQ

DDQ

DQc

DQd

DDQ

SSQ

DQd

SSQ

DDQ

DQd

DQPd

BWd

BWc

BWb

BWa

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1380A

(512K X 36)

100-Pin TQFP

(Top View)

PRELIMINARY CY7C1380A

CY7C1382A

Pin Configurations (continued)

234567

VDDQ

NC DQPc

DQc

DQd

DQc

DQd

AAAA

ADSP VDDQ

DQc

VDDQ

DQc

VDDQ

DQd

NC VDDQ

VDD

CLK

VDD

VSS

VDD

TDOTCK

TDI

TMS NC

NC NC

VDDQ

AAA A

AA0

DQa

DQc

DQa

DQb

DQa

DQb

VDD

DQc

VDD

DQd

ADSC

CE1

ADV

VSS

VSS DQPa

MODE

DQPd

DQPb

BWb

BWc

NC VDD NC

BWa

BWE

BWd

234567

VDDQ

NC NCDQb

DQb

AAAA

ADSP VDDQ

VDDQ

NC VDDQ

VDD

CLK

Vdd

VSS

VDD

TDOTCK

TDITMS A

ANC

VDDQ

ANC A A

AA0

DQa

DQb

DQa

VDD

DQb

VDD

DQb

ADSC

CE1

ADV

VSS

VSS NC

MODE

DQPb

DQPa

VSS

BWb

NC VDD NC

BWa

BWE

VSS

CY7C1 382A (1M x 18)

CY7C1380A (512K x 36)

PRELIMINARY CY7C1380A

CY7C1382A

Pin Definitions (100-Pin TQFP)

x18 Pin Locati ons x36 Pin Locations Name I/O Description

37, 36, 32–25,

42–50, 80–82, 99,

100

37, 36, 32–35,

42–50, 81, 82, 99,

100

Input-

Synchronous Address Inputs used to select one of the address

locat ions . Sampled at the rising ed ge of the CLK if

ADSP or ADSC is active LOW, and CE1, CE2, and

CE3 are sampled active. A[1:0] fe ed the 2-bit

counter.

93, 94 93, 94, 95, 96, BWa

BWb

BWc

BWd

Input-

Synchronous Byte Write Select Inputs, active LOW . Qualified with

BWE to conduct byte writes to the SRAM. Sampled

on the rising edge of CLK.

88 88 GW Input-

Synchronous Global Write Enable Input, active LOW. When as-

ser ted LOW on the rising edge of CLK, a global

write is conducted (ALL b ytes are written, regard-

less of the values on BWa,b,c,d and BWE).

87 87 BWE Input-

Synchronous Byte W ri te Enab le Input , activ e LOW. Sam pled on

the risin g edge of CLK. Thi s signal must be as sert-

ed LO W to conduct a byte write.

89 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs

to the device. Also used to increment the burst

counte r when ADV i s asserted LO W , during a b urst

operation.

98 98 CE1Input-

Synchronous Chip Enable 1 Input, active LOW. Sampled on the

rising edge of CLK. Used in conjunctio n with CE2

and CE3 to selec t/deselec t t he device . ADSP is i g-

nored if CE1 is HIGH.

97 97 CE2Input-

Synchronous Chip Ena ble 2 I nput, activ e HIGH. Sampl ed on t he

rising edge of CLK. Used in conjunctio n with CE1

and CE3 to select/deselect the device.

92 92 CE3Input-

Synchronous Chip Enable 3 Input, active LOW. Sampled on the

rising edge of CLK. Used in conjunctio n with CE1

and CE2 to select/deselect the device.

86 86 OE Input-

Asynchronous Output Enable, asynchronous input, active LOW.

Controls the direction of the I/O pins. When LO W,

the I/ O pins behav e as outputs. When deasserted

HIGH, I/ O pins ar e three-st ated, and act as in put

data pins. OE is masked during the f ir st clock of a

read cycle when emerging from a deselected state.

83 83 ADV Input-

Synchronous Advance In put si gnal, sampled on the ri sing edge

of CLK. When asserted, it automatically increments

the address in a burst cycle.

84 84 ADSP Input-

Synchronous Address Strobe from Processor, sampled on the

rising edge of CLK. When as serted LO W, A is ca p-

tured in the address registers. A[1:0] are also loaded

into the b urst c ounter. When ADSP and ADSC are

both asserted, o nly ADSP is recogniz ed. ASDP is

ignored when CE1 is deasserted HIGH.

PRELIMINARY CY7C1380A

CY7C1382A

85 85 ADSC Input-

Synchronous Address Strobe from Controller , sampled on the ris-

ing edge of CLK. When asserted LOW , A[x:0] is cap-

tured in the address registers. A[1:0] are also loaded

into the b urst c ounter. When ADSP and ADSC are

both asserted, only ADSP is recognized.

31 31 MODE Input-

Static Selects Burs t Order. When tied to GND se lects li n-

ear b urst sequenc e. When tied to VDDQ or left float-

ing sel e cts interleaved bur st sequence. This is a

strap pin and shoul d remain static duri ng device

operation.

64 64 ZZ Input-

Asynchronous ZZ “sleep” Input. This activ e HIGH input places the

device in a non-time criti cal “sleep” condit ion wit h

data integrity preserved.

(a) 58, 59, 62, 63,

68, 69, 72, 73

(b) 8, 9, 12, 13, 18,

19, 22, 23

(a) 52, 53, 56–59,

62, 63

(b) 68, 69, 72–75,

78, 79

(d) 18, 19, 22–25,

28, 29

DQa

DQb

DQc

DQd

I/O-

Synchronous Bidirectional Data I/O lines. As inputs, they feed

into an on-chip data regi ster that is trigger ed b y the

rising edge of CLK. As outputs, they deliver the data

contained in the memory location specified by A

during the pre vious clock rise of the read cycle. The

dire ction o f the pi ns is co ntrol led by OE. When O E

is asserted LO W, the pins behave as outputs.

When HIGH, DQa and DP a are placed i n a

three-stat e condition .

74, 24 51, 80, 1, 30 DQPa

DQPb

DQPc

DQPd

I/O-

Synchronous Bidirectional Data I/O lines. As inputs, they feed

into an on-chip data regi ster that is trigger ed b y the

rising edge of CLK. As outputs, they deliver the data

contained in the memory location specified by A

during the pre vious clock rise of the read cycle. The

dire ction o f the pi ns is co ntrol led by OE. When O E

is asserted LO W, the pins behave as outputs.

When HIGH, DQx and DPx are placed in a

three-stat e condition .

15, 41, 65, 91 15, 41, 65, 91 VDD P ow er Suppl y Power supply inputs to the core of the device.

Should be connected to 3. 3V –5% +10% power

supply.

17, 40, 67, 90 17, 40, 67, 90 VSS Ground Ground for the core of the device. Should be con-

nected to ground of the system.

4, 11, 20, 27, 54,

61, 70, 77 4, 11, 20, 27, 54, 61,

70, 77 VDDQ I/O Power

Supply Power supply for the I/O circ uit ry. Should be con-

nected to a 2.5 –5% –3.3V 10% power supply.

5, 10, 21, 26, 55,

60, 71, 76 5, 10, 21, 26, 55, 60,

71, 76 VSSQ I/O Ground Ground fo r the I/O ci rcuitry. Should be connecte d

to ground of the syst em .

1, 2, 3, 6, 7 , 14, 16,

25, 28, 29, 30, 38,

39, 51, 52, 53, 56,

57, 66, 75, 78, 79,

95, 96

14, 16, 38, 39, 66 NC -No Connects.

Pin Definitions (100-Pin TQFP) (continued)

x18 Pin Locati ons x36 Pin Locations Name I/O Description

PRELIMINARY CY7C1380A

CY7C1382A

Pin D efi n i ti o n s (119-B al l B GA )

x18 Pin Locati ons x36 Pin Locations Name I/O Description

4P, 4N, 2A, 2B, 2C,

3A, 5A, 6A, 3B , 5B,

3C , 5C, 6C, 2R, 6R,

2T, 3T, 5T, 6B, 6T

4P, 4N,

2A , 2B, 2C, 2R, 3 A ,

3B , 3C , 3T, 4T, 5A,

5B , 5C , 5T, 6A, 6B,

6C, 6R

Input-

Synchronous Add ress In puts used to se lect on e of the ad dress

locations. Sam pled at the rising edge of the CLK

if ADSP or ADSC is acti ve LO W, and CE is sam-

pled activ e. A[1:0] feed the 2-bit counter.

5L, 3G 5L, 5G, 3G, 3L BWa

BWb

BWc

BWd

Input-

Synchronous Byte Writ e Select Inputs, active LOW. Qualif ied

with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

4H 4H GW Input-

Synchronous Global Write Enabl e Input , activ e LO W. When as-

serted LOW on the risi ng edge of CLK, a glo bal

write is conducted (ALL bytes are written, rega rd-

le s s o f t h e values on B Wa,b,c,d and BWE).

4M 4M BWE Input-

Synchronous Byte Write En able Input, activ e LO W . Sampled on

the rising edge of CLK. This signal must be assert-

ed LOW to conduct a byte write.

4K 4K CLK Input-Clock Cl ock Input. Used to capture all synchronous in-

puts to the device. Also used to increment the

burst counter when ADV is asserted LO W, d uring

a burst operation.

4E 4E CE1Input-

Synchronous Chip Enable Inp ut, active LOW. Sampled on the

rising edge of CLK. ADSP is ignor ed if CE1 is

HIGH.

4F 4F OE Input-

Asynchronous O utput Enable, asynchronous inp ut, active LO W.

Contr ols t he direc tion of t he I/ O pins . When LO W,

the I /O pins b ehav e as outputs. When deasse rted

HIGH , I /O pins are t hree-stated, and act as i nput

data pi ns. OE is masked duri ng the first clock of a

read cycle when emerging from a deselected

state.

4G 4G ADV Input-

Synchronous Adv ance Input signal, sampled on the rising edge

of CLK. When asserted, it automatically incre-

ments the address in a burst cycle.

4A 4A ADSP Input-

Synchronous Add ress Strobe from Processor, sampled on the

rising edge of CLK. When asserted LOW , A is cap-

tur ed in the addres s registers. A[1:0] ar e also l oad-

ed int o the bu rst counter. When ADSP and ADSC

are both asserted, only ADSP is rec ognized.

ASDP is ignored when CE1 is deasserted HIGH.

PRELIMINARY CY7C1380A

CY7C1382A

4B 4B ADSC Input-

Synchronous Address Strobe from Controller, sampled on the

rising e dge of CLK. W hen asserted LO W, A[x:0] is

captured in the address regist ers. A[1:0] are also

loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recog-

nized.

3R 3R MODE Input-

Static Selects Burst Order. When tied to GND selects

li near burst sequence. When tied to VDDQ or le ft

floating selects interleaved burst sequence. This

is a str ap pin and should remain stati c duri ng de-

vice operation.

7T 7T ZZ Input-

Asynchronous ZZ “sleep” Input. This active HIGH input places the

de vi ce in a non- time c riti cal “sleep” cond ition wi th

data integrity preserved.

( a ) 6F, 6H, 6L, 6N,

7E, 7G, 7K, 7P

(b ) 1D, 1H, 1L , 1 N,

2E, 2G, 2K, 2M

(a) 6K, 6L, 6M, 6N,

7K, 7L, 7N, 7P

(b) 6E, 6F, 6G, 6H,

7D, 7E, 7G, 7H

2E , 2F, 2G, 2H

(d) 1K, 1L, 1N, 1P,

2K, 2L, 2M, 2N

DQa

DQb

DQc

DQd

I/O-

Synchronous Bidi rectional Data I/O lines. As inputs , they feed

into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the

data contained in the memory location specified

by A duri ng the previous clock rise of the r ead

cycle. The direction of the pins is controlled by OE.

When OE is as serted LOW, the pins beh ave as

outpu ts. When HIGH, DQx and DQPx ar e placed

in a thr ee-state condition.

U5 U5 TDO JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers dat a

on the negativ e edge of TCK.

U3 U3 TDI JTAG serial

input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the

rising edge of TCK.

U2 U2 TMS Test Mode Se-

lect

Synchronous

This pin contr ols the Test Access Port state ma-

chine. Sample d on the rising edge of TCK.

U4 U4 TCK JTAG-Clock Clock input to the JTAG circuitry.

6D, 2P 6P, 6D, 2D, 2P DQPa

DQPb

DQPc

DQPd

I/O-

Synchronous Bidi rectional Data I/O lines. As inputs , they feed

into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the

data contained in the memory location specified

by A duri ng the previous clock rise of the r ead

cycle. The direction of the pins is controlled by OE.

When OE is as serted LOW, the pins beh ave as

outpu ts. When HIGH, DQx and DPx are placed i n

a three-stat e conditio n.

2J, 4C , 4J, 4R, 5R, 6J 2J, 4C , 4J, 4R, 5R,

6J VDD Power Supply Power suppl y inputs to t he core of the device.

Should be connected to 3.3V power supply.

3D, 3E, 3F, 3H, 3K ,

3M, 3N, 3P, 5D, 5E,

5F, 5H, 5K, 5M, 5N,

3D, 3E, 3F, 3H, 3K,

3M , 3 N, 3P, 5D, 5E,

5F, 5H, 5K, 5M, 5N,

VSS Ground G round for the device. Should be connected to

ground of the system.

1A, 1F, 1J, 1M, 1U,

7A, 7F, 7J, 7M, 7U 1A , 1F, 1J, 1 M, 1U,

7A , 7F, 7J, 7 M, 7U VDDQ I/O Power

Supply Power supply for the I/O circuitry.

1B , 1C, 1E, 1G, 1K,

1P, 1R, 1T, 2D, 2F,

2H, 2L, 2N, 3J , 4D,

4L, 4T, 5J , 6E, 6G,

6K, 6M, 6P, 6U, 7B,

7C , 7D, 7H, 7L, 7N,

1B , 1C , 1R, 1T, 2T,

3J, 4D, 4L, 5J, 6T,

6U, 7B, 7C, 7R

NC -No Connects.

Pin D efi n i ti o n s (119-B al l B GA ) (continued)

x18 Pin Locati ons x36 Pin Locations Name I/O Description

PRELIMINARY CY7C1380A

CY7C1382A

Introduction

Functional Overview

All synchrono us inp uts pass th rough inp ut regi sters con tr olle d

by the rising edge of the clock. All data outputs pass through

outpu t regist ers contr olled b y the rising ed ge of the clock. Max-

imum access delay from the clock rise (tCO) is 3.8 ns (133-MHz

device).

The CY7C1380A/CY7C1382A supports secondary cache in

syst ems util izin g either a linear or inte rleaved burst seq uence .

The interleaved burst order support s Pentium® and i486 pro-

cessors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

St robe (A DSP) or th e Controller Address Stro be (ADSC). Ad-

dress advancement through the burst sequence is controlled

by the ADV input . A two-bit on-chip wrapa round bu rst counter

captures the first address in a burst sequence and automati-

call y increm ents the address for the rest of the burst access.

Byte write operations are quali fi ed with the Byte Writ e Enable

(BWE) and Byte Writ e Select (BW a,b,c,d for 1380 and BW a,b for

1382) inputs. A Global Write Enable (GW) overrides all byte

write inputs and writes data to all four bytes. All writes are

simplified wit h on-chip synchronous sel f-timed write circuitry.

Synchr onous Chip Selec ts (CE1, CE2, CE3 for TQFP / CE1 for

BGA) and an asynchronous Output Enable (OE) provide for

easy bank selection and output three-state control. ADSP is

ignored if CE1 is HIGH.

Singl e Read Accesses

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip selects are all asser ted active, and (3) the write signals

(GW, B WE ) are all deasserted HIGH. ADSP is ignored if CE1

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

responding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next cl ock the data

is allowed to propagate through the output register and onto

the data bus within 3.0 ns (200-MHz device) if OE is active

LO W. The only e xcept ion occur s when the SRAM is emergin g

from a deselected state to a selected state, its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately.

Singl e Writ e Accesses Init iated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise : (1) ADSP is asserted LOW, and (2)

chip select i s asserted acti ve . T he address presented is l oad-

ed into the address register and the address advancement

logic while bei ng delivered to the RAM core. The write signals

(GW, BWE, and BW x) and ADV input s are ignored during this

first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is ass erted LO W on the se cond clo ck rise , the

data presented to the DQx inputs is written into the corre-

sponding address location in the RAM core. If GW is HIGH,

then the write operation is controlled by BWE and BWx sig-

nals. The CY7C1380A/CY7C1382A provi des b yte write capa-

bility that is described in the Write Cycle Description table.

Asserting the Byte Write Enable input (BWE) with the select ed

Byte Write (BWa,b,c,d for CY7C1380A & BWa,b for

CY7C1382A) input will selectively write to only the desired

bytes. Bytes not selected during a byte write operation will

remain unalter ed. A synchronous self-t imed writ e me chanism

has been provided to simplify the write operations.

Because the CY7C1380A/CY7C1382A is a common I/O de-

vice, the Output Enable (OE) must be deasserted HI GH bef ore

present ing data to the DQ inputs. Doing so wil l three -st ate the

output drivers. As a safety precaution, DQ are automatically

three- stated whenever a wri te cycle i s detected, regardless of

the stat e of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and (4)

the appropriate combination of the write inputs (GW, BWE,

and BWx) are as serted act ive t o conduc t a write t o the des ired

byte(s). ADSC tri ggered write accesses r equire a si ngle clock

cycle to complete. The address presented to A[17:0] is loaded

into the address register and the address advancement logic

while being delivered to the RAM core. The ADV input is ig-

nored duri ng this cy cle. If a global wri te is con ducted, the dat a

presented to the DQ[x:0] is written into the corresponding ad-

dress location in the RAM core. If a byte write is conducted,

only the selected bytes are written. Bytes not selected during

a byte write operation will remain unaltered. A synchronous

self- timed write mechanism has been provided to simplify the

write operations.

Because the CY7C1380A/CY7C1382A is a common I/O de-

vice, the Output Enable (OE) must be deasserted HI GH bef ore

present ing data to the DQ[x:0] inputs. Doing so will three-state

the out put drivers. As a saf ety pr ecaution, DQ[x:0] are automat-

ical ly t hree-stated whenever a write cycle is det ected, regard-

less of t he state of OE.

Burst Sequences

The CY7C1380A/CY7C1382A provi des a tw o-bit wraparound

counter, fed by A[1:0], that implements either an interlea ved or

linear burst sequence. The interleaved burst sequence is de-

signed sp ecifically to support Intel® P entium appl ications. The

linear burst sequence is designed to support processors that

follow a linear burst sequence. The burst sequence is user

selectable thr ough the MODE input.

PRELIMINARY CY7C1380A

CY7C1382A

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operati ons are supported.

Sleep Mode

The ZZ input pin is an asyn chronous input. Assertin g ZZ plac-

es the SRAM in a pow er conserv ation “sleep” mode. Two cloc k

cycles are req uired t o ent er i nto or exit from thi s “sleep” mo d e .

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device m ust be deselected prior t o entering t he “sleep” mode.

CEs, ADSP, and ADSC must remain inactive for the duration

of tZZREC after the ZZ input returns LO W .

Interleaved B u rst S eq u en ce

First

Address Second

Address Third

Address Fourth

Address

A[1:0]] A[1:0] A[1:0] A[1:0]

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Sequence

First

Address Second

Address Third

Address Fourth

Address

A[1:0] A[1:0] A[1:0] A[1:0]

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Uni t

IDDZZ Sn ooze mode

standby cu rrent ZZ > VDD – 0.2V 15 mA

tZZS Device operation to

ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ re c overy time ZZ < 0.2 V 2t CYC ns

PRELIMINARY CY7C1380A

CY7C1382A

Cycle Des cr i p t i o n s[1, 2, 3, 4]

Next Cycle Add. Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ Write

Unselected None L X X 1 X 0 X X Hi-Z X

Unselected None L 1 X 0 0 X X X Hi-Z X

Unselected None L X 0 0 0 X X X Hi-Z X

Unselected None L 1 X 0 1 0 X X Hi-Z X

Unselected None L X 0 0 1 0 X X Hi-Z X

Begin Read External L 0 1 0 0 X X X Hi-Z X

Begin Read External L 0 1 0 1 0 X X Hi- Z Read

Continue Read Next L X X X 1 1 0 1 Hi-Z Read

Continue Read Next L X X X 1 1 0 0 DQ Read

Continue Read Next L X X 1 X 1 0 1 Hi-Z Read

Continue Read Next L X X 1 X 1 0 0 DQ Read

Suspend Read Cur rent L X X X 1 1 1 1 Hi-Z Read

Suspend Read Cur rent L X X X 1 1 1 0 DQ Read

Suspend Read Cur rent L X X 1 X 1 1 1 Hi-Z Read

Suspend Read Cur rent L X X 1 X 1 1 0 DQ Read

Begin Write Current L X X X 1 1 1 X Hi- Z Write

Begin Write Current L X X 1 X 1 1 X Hi-Z Write

Begin Writ e External L 0 1 0 1 0 X X Hi-Z Write

Conti n ue W ri t e Next L X X X 1 1 0 X Hi-Z W ri te

Conti n ue W ri t e Next L X X 1 X 1 0 X H i - Z Write

Suspend W rite Current L X X X 1 1 1 X Hi-Z Write

Suspend W rite Current L X X 1 X 1 1 X Hi- Z Write

ZZ “sleep” None H X X X X X X X Hi-Z X

Note:

1. X=”Don't Care.” 1= HIGH, 0 = LOW.

2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.

PRELIMINARY CY7C1380A

CY7C1382A

Wr i te C ycl e D escr i p ti o n s[5 , 6, 7]

Function (1380) GW BWE BWdBWcBWbBWa

Read 11XXXX

Write Byte 0 - DQa 101110

Write Byte 1 - DQb 101101

Write Bytes 1, 0 101100

Write Byte 2 - DQc 101011

Write Bytes 2, 0 101010

Write Bytes 2, 1 101001

Write Bytes 2, 1, 0 101000

Write Byte 3 - DQd 100111

Write Bytes 3, 0 100110

Write Bytes 3, 1 100101

Write Bytes 3, 1, 0 100100

Write Bytes 3, 2 100011

Write Bytes 3, 2, 0 100010

Write Bytes 3, 2, 1 100001

Write All Bytes 100000

Write All Bytes 0 XXXXX

Function (1382) GW BWE BWbBWa

Read 1 1 X X

Write Byte 0 - DQ[7:0] and DP01010

Write Byte 1 - DQ[15:8] and DP11001

W r it e A ll Byt e s 1 0 0 0

W r it e A ll Byt e s 0 X X X

PRELIMINARY CY7C1380A

CY7C1382A

IEEE 11 49.1 Seria l Boundary Scan (JTAG)

The CY7C1380A/ CY7C1382A incorporates a serial boundary

scan Test Access Port (TAP) in the FBGA package only. The

TQFP packa ge do es n ot off er thi s funct i onali ty. Thi s port ope r-

ates in accorda nce with I EEE Standard 1 149.1-1900, but does

not have the set of functions required for full 1149.1 compli-

ance . Thes e functi ons from the IEEE speci fica tion ar e e xcl ud-

ed becau se their inclusion places an added delay in the c riti cal

speed path of the SRAM. Note that the TAP controller func-

tions in a manner that does not conflict with the operation of

other de vices usi ng 1149.1 full y complian t TAPs. The TAP op-

erates using JEDEC standard 3.3V I/O logic levels.

Disabling the JTA G Feature

It is possible to operate the SRAM without using the JTAG

feature. To disab le the TAP contr oll er, TCK mu st be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are in-

ternally pulled up and may be unconnected. They may alter-

nately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a r eset state which will not interfere with the oper-

ation of the de vice.

Test Access Port (TAP) - Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP i s not used. The pin is

pull ed up internally, resulting in a logic HIGH lev el.

Test Da ta-In (TDI)

The TDI pin is used to seri ally inp ut i nformation into the regis-

ters and can be connected to the i nput of any of the regist ers.

The register between TDI and TDO is chosen by the instruc-

tion that is loaded into the TAP instruction register. For infor-

mation on loading the instruction register, see the TAP Con-

troller State Diagram. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (M SB) on any register.

Test Da ta Ou t (T D O)

The TDO output pin is used to serially clock data-out from the

registers. The e output is active depending upon the current

state of the TAP state machine (see TAP Controller State

Diagram). The output changes on the falling edge of TCK.

TDO is connected to the Least Significant Bit (LSB) of any

P erforming a TAP Reset

A Reset i s performed by forcing TMS HIGH (V DD) for five ris-

ing edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is oper-

ating. At power-up, the TAP is reset internally to ensure that

TDO comes up i n a high- Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and

all ow data t o be s canne d int o and out of the SRAM t est ci rcui t-

ry. Only one register can be selected at a time through the

instruction registers. Data is serially loaded into the TDI pin on

the rising edge of TCK. Data is output on the TDO pin on the

falling edge of TCK.

Instruction Regist er

Three-bit instructions can be serially loaded into the instruction

regis ter. This register is loaded when it is pl aced between the

TDI and TDO pins as shown in the TAP Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE i nstruction. It i s also loaded wi th t he IDCODE

instruction if the controller is placed in a reset state as de-

scribed i n the previous section.

When the TAP controller is in the Captu reIR state, the two leas t

significant bits are loaded with a binary "01" pattern to allow

for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shift ing data through registers, it is

sometimes advantageous to skip certain states. The bypass

regis ter i s a sing le-bi t reg ister that can be placed betw een TD I

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

densit y de vi ces . The x36 confi gur ation has a xx- bit- long reg is -

ter, and the x18 configur ation has a yy-bit-long register.

The boundary scan register is loaded with the cont ents of the

RAM Input and Output r ing when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ri ng.

The Boundary Scan Order tables show the order in which the

bits are connect ed. Each bit cor responds to one of the bumps

on the SRAM package . The MSB of the register is connected

to TDI, and the LSB is con nected to TDO.

Identi ficatio n (ID) Reg ister

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shi fted out when the TAP control ler

is in the Shi ft-DR sta te. The I D regis ter has a ve ndor code and

other i nformation described in the Identif ication Register Def i-

niti ons table.

TAP Instructi on Set

Eight different instructions are possible with the three-bit in-

struct ion register. All co mbinations are li sted in t he Ins truc tion

Code table. Three of these instructions are listed as RE-

SERVED and should not be used. The other five instructions

are described in detail below.

The TAP controller used i n thi s SRAM is not fully compli ant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are no t fully impl emented. The TAP controlle r can-

not be used to load address, data or control signals into the

PRELIMINARY CY7C1380A

CY7C1382A

SRAM and cannot preload the Input or Output buffers. The

SRAM d oes not implement t he 1149. 1 comman ds EXT EST or

INTEST or the PRELOAD portion of SAMPLE / PRELOAD;

rat her it performs a captur e of the Inputs and Output ring when

these instructions are executed.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instr uction register is placed between

TDI and TDO. During this state, instructions are shifted

thr ough the i nstruct ion r egiste r thr ough the TDI and TDO pins .

To execute the i nst ruction once it i s shif ted in, the TAP cont rol-

ler needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandator y 1149.1 instruction which is to be ex-

ecuted whenever the instruction register is loaded with all 0s.

EXTEST is not implemented in the TAP controller, and there-

fore thi s dev ice is not compliant to the 1149. 1 standard.

The TAP controller does recognize an all-0 instruction. W hen

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE / PRELOAD instruction

has been loaded. There is one difference between the two

inst ruct ions. Unl ike the SAMPLE / PRELO A D instruction, EX-

TEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE i nstruction causes a v endor-s pecific, 32-bit code

to be loaded into the instruction register. It also places the

inst ruction r egister between the TDI and TDO pins and allows

the I DCODE to be sh ift ed out of t he de vic e when the TAP con-

troller enters the Shift-DR state. The IDCODE instruction is

loade d into the inst ruction register upon p ower-up or whene ver

the TAP contr oller is given a test logi c reset stat e.

SAMPLE Z

The SAM PLE Z ins truction caus es the b oundary s can regi ster

to be connec ted betwe en the TDI and TDO pins when the TAP

contr oller is in a Shi ft-DR stat e. It also pl aces all SRAM outp uts

in to a H i g h - Z state.

SAMPLE / PRELOAD

SAMPLE / PRELOAD is a 1149.1 mand atory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP contr oller is not fully 1149.1 compl iant.

When the SAMPLE / PRELOAD instructions loaded into the

instruction register and the TAP controller in the Capture-DR

state, a snapshot of data on the inputs and output pins is cap-

tured i n the boundary scan reg ister.

The user must be a wa re that the TAP cont roller c lock can onl y

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possible

that during t he Capture-DR stat e, an input or output will under -

go a tra nsiti on. The TAP ma y th en try to capture a signal while

in transition (metastable state). This will not harm the device,

but there is no guarantee as to t he value that will be c aptured.

Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (TCS and TC H). The SRAM clock input might not

be captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE / PRELOAD instruction. If

this is an issue, it is still possible to capture all other signals

and simply ignore the value of t he CK and CK captured in the

boundary scan regi ster.

Once the da ta i s captu red, i t is p ossib l e to shi ft out the dat a by

putting the TAP into the Shift-DR state . This places the bound-

ary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while perf orming a SAMPLE / PRELOAD in-

struction will hav e the same eff ect as t he Pause- DR command .

Bypass

When t he BYPASS instruction is loaded i n the instruction reg-

ister and the TAP is placed in a Shift-DR state, the bypass

regis ter is placed between th e TDI and TDO p ins. The advan-

tage of the BYPASS instruction is that it sho rtens t he boundary

scan path when multiple devices are connected together on a

board.

Reserved

These instructions are not implemented but are reser ved for

futur e use. Do not use thes e instructions.

PRELIMINARY CY7C1380A

CY7C1382A

TAP Controller State Diagram

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

Note: The 0/1 next to each state repre sents the value at TMS at the rising edge of TCK.

PRELIMINARY CY7C1380A

CY7C1382A

TAP Co n t rol le r B lock D i ag ra m

012..

3031

Boundary Scan Regist er

Identification Regi ster

012..

012

Instructi on Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Contr oll er

TDI TDO

TCK

TMS

TAP Electrical Characteristics Over the Operating Range[5, 6]

Parameter Description Test Conditions Min. Max. Unit

VOH1 Outp ut HI GH Voltage IOH = –2.0 mA 1.7 V

VOH2 Outp ut HI GH Voltage IOH = –100 mA 2.1 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V

VOL2 Output LOW Voltage IOL = 100 mA 0.2 V

VIH Input HIG H Voltage 1.7 VDD+0.3 V

VIL Input LOW Voltage –0.3 0.7 V

IXInput Load Current GND < VI < VDDQ –5 5 mA

Notes:

5. All Voltage referenced to Ground.

6. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot:VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.

PRELIMINARY CY7C1380A

CY7C1382A

TAP AC Switchin g Char acter i stic s Over the Operati ng Range[7, 8]

Parameters Description Min. Max Unit

tTCYC TCK Clock Cycle Time 100 ns

tTF TCK Clock F requency 10 MHz

tTH TCK Clock HIGH 40 ns

tTL TCK Clock LO W 40 ns

Set-up Times

tTMSS TMS Set-up to TCK Cloc k Rise 10 ns

tTDIS TDI Set-up to TCK Clock Rise 10 ns

tCS Capture Set-up to TCK Rise 10 ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 10 ns

tTDIH TDI Hold after Clock Rise 10 ns

tCH Capture Hold afte r Clo ck Rise 10 ns

Output Times

tTDOV TCK Cl ock LOW to TDO Valid 20 ns

tTDOX TCK Clock LOW to TDO Invalid 0ns

Notes:

7. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

8. Test conditions are specified using the load in TAP AC test conditions. TR/TF = 1 ns.

PRELIMINARY CY7C1380A

CY7C1382A

TAP Timing and Test Conditions

(a)

TDO

CL=2 0 pF

Z0=50Ω

GND

1.25V

Test Clock

Test M ode Select

TCK

TMS

Te st D ata-In

TDI

Test Data-Out

TDO

tTCYC

tTMSH

tTL

tTH

tTMSS

tTDIS tTDIH

tTDOX tTDOV

50Ω

3.3V

ALL INPUT PULSES

1.50V

PRELIMINARY CY7C1380A

CY7C1382A

Identif ication Register Defini ti ons

Instruction Field 512K x 36 1M x 18 Description

Revision Number

(31:28) xxxx xxxx Reserved for version number.

De vice Depth

(27:23) 00111 01000 Defines depth of SRAM. 512K or 1M

De vice Width

(22:18) 00100 00011 Defines wit h of th e SRAM. x36 or x18

Cypress D evice ID

(17:12) xxxxx xxxxx Reserved for futu re use.

Cypress JEDEC ID

(11:1) xxxxxxxxxxx xxxxxxxxxxx Al lows unique identification of SRAM vendor.

ID Regist er Pre sence

(0) 1 1 Indicate the presence of an ID regis ter.

Scan Regi ster Si z es

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan 70 51

Identification Codes

Instruction Code Description

EXTEST 000 Captu res the Input/Output ring contents. Places the bound ary scan register

between the TDI and TDO. Forces all SRAM outputs to High-Z state. This

instruction is not 1149.1 compli ant.

IDCODE 001 Loads t he ID register wit h the vendor ID code and places the regi ster be-

tween TDI and TDO . This oper ation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register be-

tween TDI and TDO . Forces all SRAM output drivers to a High -Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Ca ptures the Inp ut/Out put ring contents. Places the bound ary scan register

between TDI and TDO. Does not aff ect the SRAM operation. This instruction

does not implement 1149.1 preload function and is therefor e not 1149.1

compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Pl aces the b ypass register between TDI and TDO . This operation does not

affect SRAM operation.

PRELIMINARY CY7C1380A

CY7C1382A

Boundary Scan Order (512K X 18)

Bit # Signal

Name Bump

ID Bit # Signal

Name Bump

1 A 2R 36 A6B

2 A 3T 37 BWa# 5L

3 A 4T 38 BWb# 5G

4 A 5T 39 BWc# 3G

5 A 6R 40 BWd# 3L

6 A 3B 41 A2B

7 A 5B 42 CE# 4E

8DQa 6P 43 A3A

9DQa 7N 44 A2A

10 DQa 6M 45 DQc 2D

11 DQa 7L 46 DQc 1E

12 DQa 6K 47 DQc 2F

13 DQa 7P 48 DQc 1G

14 DQa 6N 49 DQc 1D

15 DQa 6L 50 DQc 1D

16 DQa 7K 51 DQc 2E

17 ZZ 7T 52 DQc 2G

18 DQb 6H 53 DQc 1H

19 DQb 7G 54 NC 5R

20 DQb 6F 55 DQd 2K

21 DQb 7E 56 DQd 1L

22 DQb 6D 57 DQd 2M

23 DQb 7H 58 DQd 1N

24 DQb 6G 59 DQd 2P

25 DQb 6E 60 DQd 1K

26 DQb 7D 61 DQd 2L

27 A6A 62 DQd 2N

28 A5A 63 DQd 1P

29 ADV# 4G 64 MODE 3R

30 ADSP# 4A 65 A2C

31 ADSC# 4B 66 A3C

32 OE# 4F 67 A5C

33 BWE# 4M 68 A6C

34 GW# 4H 69 A1 4N

35 CLK 4K 70 A0 4P

Boundary Scan Order (1M X 18)

Bit # Signal

Name Bump

ID Bit # Signal

Name Bump

1 A 2R 36 DQb 2E

2 A 2T 37 DQb 2G

3 A 3T 38 DQb 1H

4 A 5T 39 NC 5R

5 A 6R 40 DQb 2K

6 A 3B 41 DQb 1L

7 A 5B 42 DQb 2M

8DQa 7P 43 DQb 1N

9DQa 6N 44 DQb 2P

10 DQa 6L 45 MODE 3R

11 DQa 7K 46 A2C

12 ZZ 7T 47 A3C

13 DQa 6H 48 A5C

14 DQa 7G 49 A6C

15 DQa 6F 50 A1 4N

16 DQa 7E 51 A0 4P

17 DQa 6D

18 A6T

19 A6A

20 A5A

21 ADV# 4G

22 ADSP# 4A

23 ADSC# 4B

24 OE# 4F

25 BWE# 4M

26 GW# 4H

27 CLK 4K

28 A6B

29 BWa# 5L

30 BWb# 3G

31 A2B

32 CE# 4E

33 A3A

34 A2A

35 DQb 1D

PRELIMINARY CY7C1380A

CY7C1382A

Maximum Ratings

(Abov e which the usefu l l ife may be impa ired. For user guide-

li nes, not tested.)

Storage Temperature ... .. ....... .. ................ ...–55°C to +15 0 °C

Ambient Temperature with

Power Applied.............................................–55°C to +12 5 °C

Supply Volt age on VDD Relative to GND........ –0. 3V to +4.6V

DC Voltage Appli ed to Outputs

in High Z State[9]................................. –0.5V to VDDQ + 0.5V

DC Input Volt age[9].............................. –0.5V to V DDQ + 0.5V

Cu r re n t in to Outp ut s (L OW )... ....... ....... .......... ....... ....... 20 mA

Static Discharge Voltage..... ................................... .. >2001V

(per MIL- STD-883, Method 3015)

Latch-Up Current............................. ........... ....... ..... >200 mA

Operating Range

Range Ambient

Temp.[10] VDD VDDQ

Com’l 0−70°C 3.3V + 10% /–5% 2.375V–VDD

Electrical Characteristics Over the Opera ti ng Range

Parameter Description Test Conditi ons Min. Max. Unit

VDD Power Suppl y Vol tage 3.3V range 3.135 3.6 V

VDDQ I/O Supply Voltage 3.3V range 3.135 3.6 V

2.5V range 2.375 VDD V

VOH Output HIGH Voltage VDD = Min. , IOH = -1.0 mA 3.3V 2.4 V

2.5V 1.7 V

VOL Output LO W Voltage VDD = Min., IOL = 1.0 mA 3.3V 0.4 V

2.5V 0.7

VIH Input HIGH Voltage 3.3 V 2.0 V

2.5V 1.7

VIL Input LOW Voltage[9] 3.3V –0.3 0.8 V

2.5V –0.3 0.7

IXInput Load Current

excep t ZZ and MODE GND £ VI £ VDDQ –5 5 mA

IZZ Input Current of MODE –30 30 mA

Input Current of ZZ Input = VSS –5mA

IOZ Out put Leaka ge

Current GND £ VI £ VDDQ, Output Disabled –2 2 mA

IDD VDD Operating Supply VDD = Max., IOUT = 0 mA ,

f = fMAX = 1/tCYC 6.0-ns cycle, 167 MH z 350 mA

6.7-ns cycle, 150 MH z 310 mA

7.5-ns cycle, 133 MH z 280 mA

10-ns cycle, 100 MHz 250 mA

ISB1 Automatic CE

Power-Down

Current—TTL Inputs

Max. VDD, Devi ce

Deselected,

VIN Š VIH or VIN <VIL

f = fMAX = 1/tCYC

6.0-ns cycle, 167 MH z 130 mA

6.7-ns cycle, 150 MH z 110 mA

7.5-ns cycle, 133 MH z 95 mA

10-ns cycle, 100 MHz 80 mA

ISB2 Automatic CE

Power-Down

Current—CMOS Inputs

Max. VDD, Devi ce

Deselected, VIN < 0.3V or

VIN > VDDQ - 0.3V, f = 0

All spee d grades 30 mA

Shaded areas contain advance information.

Notes:

9. Minimum voltage equals –2.0V for pulse durations of less than 20 ns

10. TA is the temperature.

PRELIMINARY CY7C1380A

CY7C1382A

ISB3 Automatic CE

Power-Down

Current—CMOS Inputs

Max. VDD, Devi ce

Deselected, or VIN ≤ 0.3V or

VIN > VDDQ − 0.3V

f = fMAX = 1/tCYC

6.0-ns cycle, 167 MH z 100 mA

6.7-ns cycle, 150 MH z 80 mA

7.5-ns cycle, 133 MH z 65 mA

10-ns cycle, 100 MHz 50 mA

ISB4 Automatic CS

Power-Down

Current—TTL Inputs

Max. VDD, Devi ce

Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All Speed s 20 mA

Electrical Characteristics Over the Opera ting Range (cont inued)

Parameter Description Test Conditi ons Min. Max. Unit

Capacitance[11]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25 °C, f = 1 MHz,

VDD = 3.3V,

VDDQ = 2.5V

5pF

CCLK Clock Input Capacitance 4pF

CI/O Input/Output Capacitance 8pF

AC Test Loads and Waveforms[12]

Note:

11. Tested initially and after any design or process changes that may affect these parameters.

12. Input waveform should have a slew rate of 1 V/ns.

OUTPUT

R=317Ω

R=351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL=50Ω

Z0=50Ω

VTH = 1. 5V

3.3V ALL INPUT PULSES[10]

3.0V

GND

90%

10% 90%

10%

≤1 V/ns ≤1 V/ns

(c)

R=351

PRELIMINARY CY7C1380A

CY7C1382A

Switching Characteristics Over the Operating Range[13, 14, 15]

-167 -150 -133 -100

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

tCYC Clock Cycle Time 6.0 6.7 7.5 10.0 ns

tCH Clock HIGH 2.1 2.5 3.0 3.0 ns

tCL Clock LOW 2.1 2.5 3.0 3.0 ns

tAS Ad dress Set-Up Before CLK Rise 1.5 1.5 1.5 1.5 ns

tAH Ad dress Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCO Data Output Valid After CLK Rise 3.4 3.8 4.2 5.0 ns

tDOH Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns

tADS ADSP, ADSC Set-Up Before CLK Rise 1.5 2.0 2.0 2.0 ns

tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tWES BWE, GW, BWx Set-Up Before CLK Rise 1.5 2.0 2.0 2.0 ns

tWEH BWE, GW, BWx Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tADVS ADV Set-Up Bef ore CLK Rise 1.5 2.0 2.0 2.0 ns

tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tDS Data I npu t S e t- U p B e fore C LK Ri s e 1.5 2.0 2.0 2.0 ns

tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCES Chip enab le Set-Up 1.5 2.0 2.0 2.0 ns

tCEH Chip enab le Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCHZ Clock to High- Z[14] 1.5 3.0 1.5 3.0 1.5 3.5 1.5 3.5 ns

tCLZ Clock t o Low- Z[14] 0000ns

tEOHZ OE HIGH to Output High- Z[ 14, 15] 3.0 3.5 4.0 4.0 ns

tEOLZ OE LOW to Output Low-Z[14, 15] 0000ns

tEOV OE LOW to Output Va lid[14] 3.5 3.5 4.0 4.0 ns

Notes:

13. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and

output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.

14. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from

steady-state voltage.

15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.

PRELIMINARY CY7C1380A

CY7C1382A

Swi tc h i n g Wavef o rms

Write Cy cl e Tim i n g [4 , 16 , 17]

Notes:

16. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).

17. WDx stands for Write Data to Address X.

ADSP

CLK

ADSC

ADV

ADD

Data In

tCYC

tCH

tCL

tADS

tADH

tADS tADH

tADVS tADVH

WD1 WD2 WD3

tAH

tAS

tWS tWH tWH

tWS

tCES tCEH

2b 3a

Single Write Burst Write Unselected

ADSP ignored with CE1 inactive

CE1 masks ADSP

= D ON ’T CARE

= UNDEFINED

Pipelined Write

2a 2c 2d

tDH

tDS

High-Z

Unselected with CE2

ADV Must Be Inactive for ADSP Write

ADSC initiated write

PRELIMINARY CY7C1380A

CY7C1382A

Read Cycle Timing[4, 16, 18]

Note:

18. RDx stands for Read Data from Address X.

Swi tc h i n g Wavef o rms (continued)

ADSP

CLK

ADSC

ADV

ADD

CE1

CE2

CE3

2a 2c

Data Out

tCYC tCH

tCL

tADS tADH

tADS

tADH

tADVS

tADVH

RD1 RD2 RD3

tAH

tAS

tWS tWH

tWH

tWS

tCES tCEH

tCO

tEOV

2b 2c 2d 3a

tOEHZ tDOH

tCLZ tCHZ

Singl e Read Burst Read Unselected

ADSP ignored with CE1 i nactive

Suspend Burst

CE1 masks ADSP

= DON’T CARE = UNDEFINED

Pipel ined Read

ADSC initiated read

Unse lected with CE2

PRELIMINARY CY7C1380A

CY7C1382A

Read/Write Cycle Timing[4 , 16, 17 , 18]

Swi tc h i n g Wavef o rms (continued)

ADSP

CLK

ADSC

ADV

ADD

CE1

CE2

CE3

Da ta In/Out

tCYC tCH

tCL

tADS tADH

tADS

tADH

tADVS

tADVH

RD1 WD2 RD3

tAH

tAS

tWS tWH

tWH

tWS

tCES tCEH

tEOLZ

tCO

tEOV

3a 3c 3d

tEOHZ tDOH

tCHZ

Singl e Read Burst Read Unselected

ADSP ignored with CE1 inactive

CE1 masks ADSP

= DON’T CARE = UNDEFINED

Pipelined Read

Out 2a

In 3b

Out

Out Out Out

Single Write

tDS tDH

Out

PRELIMINARY CY7C1380A

CY7C1382A

Notes:

19. Device originally deselected.

20. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.

Swi tc h i n g Wavef o rms (continued)

tAS

= DON’T CARE = UNDEFINED

tCLZ

tCHZ

tDOH

CLK

ADD

CE1

Data In/Out

ADSC

ADSP

ADV

D(C)

tCYC

tCH tCL

tADS tADH

tCEH

tCES

tWEH

tWES

tCDV

Pipeline Timing[4, 19 , 20]

ADSP ignored

with CE1 HIGH

RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4

Out 2a

Out 3a

Out 4a

Out 1a

In 2a

In 3a

In 4a

Back t o B a ck R ead s

ADSP initiated Reads

ADSC initiated Reads

PRELIMINARY CY7C1380A

CY7C1382A

Swi tc h i n g Wavef o rms (continued)

Three-State

I/Os

tEOHZ tEOV

tEOLZ

OE Switching Wavefor ms

PRELIMINARY CY7C1380A

CY7C1382A

Swi tc h i n g Wavef o rms (continued)

ADSP

CLK

ADSC

CE1

CE3

LOW

HIGH

ZZ tZZS

tZZREC

IDD IDD(active)

Three-state

I/Os

NotefjdfdhfdjfdfjdjdjdjNo

Note:

21. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.

22. I/Os are in three-state when exiting ZZ sleep mode.

ZZ Mode Timing [4, 21, 22]

CE2

IDDZZ

HIGH

PRELIMINARY CY7C1380A

CY7C1382A

Ordering Information

Speed

(MHz) Orderi ng Code Package

Name Package Type Operating

Range

167 CY7C1380A-167AC A101 100-Lead Thin Quad Flat Pack Commercial

150 CY7C1380A-150AC

133 CY7C1380A-133AC

100 CY7C1380A-100AC

167 CY7C1382A-167AC

150 CY7C1382A-150AC

133 CY7C1382A-133AC

100 CY7C1382A-100AC

167 CY7C1380A-167BGC BG119 119 Ball BGA

150 CY7C1380A-150BGC

133 CY7C1380A-133BGC

100 CY7C1380A-100BGC

167 CY7C1382A-167BGC

150 CY7C1382A-150BGC

133 CY7C1382A-133BGC

100 CY7C1382A-100BGC

Document #:38-00984-**

Intel and Pe ntium are regi stered tr adem arks of Int el Corporat ion.

PRELIMINARY CY7C1380A

CY7C1382A

Package Diagrams

100-Pin Thin Plas tic Qua d Flat pack (14 x 20 x 1.4 mm) A101

51-85050-A

PRELIMINARY CY7C1380A

CY7C1382A

of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. C ypress Semicondu ctor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Revision H is t o r y

Package D i ag ra ms (continued) 119-Lead FBGA (14 x 22 x 2.4 mm) BG119

Document Title: CY7C1380/CY7C1382

Document Number :38- 00984

REV. ECN NO . ISSUE DATE ORIG. OF

CHANGE DESCRIPTION OF CHANGE

** 3/16/2000 CXV 1. New Datasheet