128K x 16 Static RAM
CY62137BV MoBL2™
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1, 2001
1
Features
• Low voltage range:
—CY62137BV18: 1.75V−1.95V
• Ultra-low active, standby power
• Easy memory ex pans ion with CE and OE feature s
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62137BV18 is a high-performance CMOS static RAM
organized as 131,072 words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal f or prov iding More Ba ttery Lif e™ (MoBL™) i n por-
tab le applications such as cellular telephone s. The de vice also
has an autom atic po w er-do wn feature that signifi cantly redu c-
es power consumption by 99% when addresses are not tog-
gling. The device can also be put into standby mode when
dese lecte d (CE HIGH) or when CE is LO W and both BLE and
BHE are HIGH. The input/o utp ut pin s (I/O 0 thro ug h I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and W r ite E nable ( WE) inpu ts L OW. If Byt e Low Ena ble
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Read ing f rom th e device is acc ompli shed by t aking Chip E n-
able (CE) and Output Enable (OE) LO W while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appe ar o n I/O0 to I/O7. If Byte High Ena ble (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The CY62137BV18 is available in 48-ball FBGA packaging.
Logic Block Diagram
128K x 16
RAM Array I/O0–I/O7
COLUMN DECODER
A11
A12
A13
A14
A15
1024 X 2048
SENS E AMPS
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
A10
A16
ROW DECODER
A7
A6
A3
A0
A2
A1
A5
A4
A8
Power -Down
Circuit BHE
BLE
CE
2
CY62137BV MoBL2™
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Pow er Appl ie d..................................................−55°C to +125°C
Supply Voltage to Ground Potential..................−0.5V to +2.4V
DC Voltage Applied to Outputs
in High Z St ate[1] ....................................... −0.5V to VCC + 0.5V
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Output Current into Outputs (LOW ).............................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
1. VIL(min.) = −2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C.
Pin Configurati on
WE
VCC
A11
A10
NC
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA
A16
Top View
Operating Range
Device Range Ambient Temperature VCC
CY62137BV18 Industrial −40°C to +85°C 1.75V to 1.95V
Product Portfolio
VCC Range
Power Dissipation (Industrial)
Operating (ICC)Standby (ISB2)
Product VCC(min) VCC(typ)[2] VCC(max) Power Typ.[2] Max. Typ.[2] Max
CY62137BV18 1.75V 1.80V 1.95V LL 3 mA 7 mA 1 µA15 µA
3
CY62137BV MoBL2™
Electrical Characteristics Over the Op erat ing Ran ge
CY62137BV18
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage IOH = −0.1 mA VCC = 1.75V 1.5 V
VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.75V 0.2 V
VIH Input HIGH Voltage VCC = 1.95V 1.4 VCC + 0.3V V
VIL Input LOW Voltage VCC = 1.75V −0.5 0.4 V
IIX Input Load Current GND < VI < VCC −1±1+1µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1+1+1µA
ICC VCC Operating Supply
Curre nt IOUT = 0 mA,
f = fMAX = 1/tRC,
CMOS levels
VCC = 1.95V 3 7 m A
IOUT = 0 mA,
f = 1 MHz,
CMOS Levels
12mA
ISB1 Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC−0.3V,
VIN > VCC−0.3V or
VIN < 0.3V, f = fMAX (Address and
Data Only), f=0 ( OE, WE, BHE, and
BLE)
100 µA
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC−0.3V
VIN > VCC−0.3V
or VIN < 0.3V, f = 0
VCC =
1.95V LL 1 15 µA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C , f = 1 MHz ,
VCC= VCC(typ.) 6pF
COUT Output Capacitance 8pF
Thermal Resistance
Description Test Conditi ons Symbol BGA Unit
Thermal Resistance
(Junction to Ambient)[3] Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board ΘJA 55 °C/W
Thermal Resistance
(Junction to Case)[3] ΘJC 16 °C/W
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
4
CY62137BV MoBL2™
Notes:
4. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs or stable at VCC(min.) >100 µs.
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ ., and outp ut lo ading o f the s pecif ied
IOL/IOH and 30 p F load capacit ance .
AC Test Loads and Waveforms
VCC Typ
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1 VCC
OUTPUT
R2
5 pF
INCLUDING
JIG AN D
SCOPE
R1
Rise Time:
1 V/ns Fall Time:
1 V/ns
(a) (b) (c)
Parameters 1.8V Unit
R1 15294 Ohms
R2 11300 Ohms
RTH 6500 Ohms
VTH 0.85 Volts
Data Retention Characteristics (Ov er the Operating Range)
Parameter Description Conditions[5] Min. Typ.[2] Max. Unit
VDR VCC f or Data Rete ntion 1.0 1.95 V
ICCDR Data Reten tio n Curr ent VCC = 1.0V
CE > VCC − 0.3V,
VIN > VCC − 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
LL 17.5 µA
tCDR[3] Chip Deselect to Data
Retention Time 0ns
tR[4] Operation Recovery Time 100 µs
Data Retention Waveform
VCC(min.)
VCC(min.)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
CE
VCC
5
CY62137BV MoBL2™
Switching Characteristics Ov er the Operating Range[5]
70 ns
Parameter Description Min. Max. Unit
READ CYCLE
tRC Read Cyc le Tim e 70 ns
tAA Address to Data Valid 70 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 70 ns
tDOE OE LOW to Data Valid 35 ns
tLZOE OE LOW to Low Z[6] 5ns
tHZOE OE HIGH to High Z[6, 7] 25 ns
tLZCE CE LOW to Low Z[6] 10 ns
tHZCE CE HIGH to High Z[6, 7] 25 ns
tPU CE LOW to Power-Up 0ns
tPD CE HIGH to Power-Down 70 ns
tDBE BLE / BHE LOW to Data Valid 35 ns
tLZBE BLE / BHE LOW to Low Z[6, 7] 5ns
tHZBE BLE / BHE HIGH to High Z[8] 25 ns
WRITE CYCLE[8, 9]
tWC Write Cycle Tim e 70 ns
tSCE CE LOW to Write End 60 ns
tAW Address Set-Up to Write End 60 ns
tHA Address Hold from Write End 0ns
tSA Address Set-Up to Write Start 0ns
tPWE WE Pulse W idth 50 ns
tBW BLE / BHE LOW to Write End 60 ns
tSD Data Set-Up to Write End 30 ns
tHD Data Hold from Write End 0ns
tHZWE WE LOW to High Z[6, 7] 25 ns
tLZWE WE HIGH to Low Z[6] 10 ns
Switching Waveforms
Notes:
6. At any giv en temperature and voltage condition, tHZCE i s le ss th an t LZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE f or any given device.
7. tHZOE, tHZCE, a nd tHZWE are specif ied with CL = 5 pF as in part (b) of A C Test Loads. Transition is measured ±500 mV from s teady-st ate v o ltage.
8. The internal write time of the memory is defined by the overlap of CE LO W and WE LO W . Bo th signals must be LO W to initi ate a write and eit her signal can terminate
a write b y goi ng HIGH. The da ta input set- up and hold t iming s hould be ref ere nced t o the risi ng edge of the signa l tha t terminat es the write.
9. The minimum write cycle time for write cycle #3 (WE controll ed, OE LOW ) is the sum of tHZWE and tSD.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read c ycle .
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1
[10, 11]
6
CY62137BV MoBL2™
Notes:
12. Address valid prior to or coincident with CE transi tion LOW.
13. Data I/O is high impedance if OE = VIH.
14. If CE goe s HIGH simul taneously wi th WE HIGH, the output remains in a high-imp edance state .
15. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
Read Cycle No. 2 [11, 12]
50%
50%
DATA VALID
t
RC
t
ACE
t
DBE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IM PEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE
t
DOE
t
LZOE
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATA
IN VALID
NOTE
Write Cy cle No. 1 (WE Controlled) [8, 13, 14]
15
BHE/BLE tBW
9
CY62137BV MoBL2™
Typical DC and AC Characteristics
30
35
25
15
10
5
1.8 2.2
0
20
ISB (µA)
1.2
1.4
1.0
0.6
0.4
0.2
1.65 1.8 1.95 2.2 2.4
0.0
0.8
ICC
70
80
60
40
30
20
1.65 1.8 1.95 2.2
SUPPL YVOLT AGE (V)
Access Time vs. Supply Voltage
10
50
TAA (ns)
Normalized Operating Current
Standby Current vs. Supply Voltage
SUPP LY VO LTAG E (V)
SUPP LY VO LTAG E (V)
MoBL2
MoBL2
MoBL2
vs. Supply Voltage
1.95
Trut h Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
HXXXXHigh Z Deselect/Power-Down Standb y (ISB)
L X X H H High Z Deselect/Power-Down Standby (ISB)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Deselect/Output Disabled Active (ICC)
L H H H L High Z Deselect/Output Disabled Active (ICC)
L H H L H Hi gh Z Deselect/Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0 –I/O7 in Hi gh Z Write Active (ICC)
CY62137BV MoBL2™
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other than circ uitry embo died in a Cypr ess Semiconductor p roduct. Nor does it conv ey or imply an y license under pa tent or other rights. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-suppor t systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-01051-**
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
70 CY62137BV18LL-70BAI BA48 48-Ball Fine Pitch BGA Industrial
P ackage Diagrams
48-Ball ( 7.00 mm x 7.00 mm x 1.10 mm) Fine Pitch BGA BA48
51-85096-A
