DS2164Q DALLAS SEMICONDUCTOR DS2164Q G.726 ADPCM Processor FEATURES Compresses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps as per the CCITT/ ITU G.726 specification Dual, fully independent channel architecture; device can be programmed to perform either: two expansions two compressions one expansion and one compression Interconnects directly to combo-codec devices @ Input to output delay is less than 375 us Simple serial port used to configure the device Onboard Time Slot Assigner Circuit (TSAC) function allows data to be input/output at various time slots Supports Channel Associated Signaling @ Each channel can be independently idled or placed into bypass Available hardware mode requires no host processor; ideal for voice storage applications Backward-compatible with the DS2165 ADPCM Processor Chip Single +5V supply; low-power CMOS technology @ Available in 28-pin PLCC DESCRIPTION The DS2164Q ADPCM Processor Chip is a dedicated Digital Signal Processing (DSP) chip that has been opti- mized to perform Adaptive Differential Pulse Code Mod- ulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (ex- pand) 64Kbps voice data down to (up from) either 32Kbps, 24Kbps, or 16Kbps. The compression follows the algorithm specified by CCITT Recommendation G.726. The DS2164Q can switch compression algo- rithms on-the-fly. This allows the user to make maxi- mum use of the available bandwidth on a dynamic ba- sis. PIN ASSIGNMENT 28-Pin PLCC OVERVIEW The DS2164Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two indepen- dent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A 10 MHz master clock is re- quired by the DSP engine. The DS2164Q can be confi- gured to perform either two expansions, two compres- sions, or one expansion and one compression. The PCM/ADPCM data interfaces support data rates from 256 KHz to 4.096 MHz. Typically, the PCM data rates Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserv eho important oh eee re patents and other intellectual property rights, refer to Dallas Semiconductor data books. 41 041295 1/17DS2164Q will be 1.544 MHz for u-law and 2.048 MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the re- sult during a user-programmed output time slot. Each PCM interface has a control register which speci- fies functional characteristics (compress, expand, by- pass, and idle), data format (u-law or A-law), and algo- rithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port can be used to configure the device. in this mode, a novel ad- dressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level in- terconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control register bits to some of the address and serial port pins. Under the hardware mode, no external host controller is required and all PCM/ADPCM input and output time slots default to time slot 0. HARDWARE RESET RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that the device has initialized properly. RST should also be asserted when changing to or from the hardware mode. RST clears all bits of the Control Register for both channels except the IPD bits; the IPD bits for both channels are set to 1. SOFTWARE MODE Tying SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2164Q via the serial port through inputs SCLK, SDI, and CS. (See Figure 2.) Each write to the DS2164Q is either a 2-byte write or a 4-byte write. A 2- byte write consists of the Address/Command Byte (ACB), followed by a byte to configure the Control Reg- ister (CR) for either the X or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then one byte to set the input time slot and another byte to set the output time slot. ADDRESS/COMMAND BYTE In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs AQ to AS. Ifno match occurs, the device ignores the following configuration data. If an address match oc- curs, the next three bytes written are accepted as con- trol, input and output time slot data. Bit ACB.6 deter- mines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs are tristated during reg- ister updates. CONTROL REGISTER The control register establishes idle, algorithm reset, bypass, data format and channel coding for the selected channel. The X and Y side PCM interfaces can be independently disabled (output 3-stated) via IPD. When IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not be operated faster than 39 KHz. ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be cleared by the device when the algorithm reset is complete. 041295 2/17 42DS2164Q PIN DESCRIPTION Tabie 1 PIN SYMBOL TYPE DESCRIPTION 2 RST I Reset. A high-low-high transition resets the algorithm. The device should be reset on power up and when changing to or from the hardware mode. 3 TMO | Test Modes 0 and 1. Tie to Vs for normal operation. 4 TM1 6 AQ I Address Select. AO = LSB; A5 = MSB Must match address/command 7 Al word to enable the serial port. 8 A2 9 A3 10 A4 11 AS 12 SPS I Serial Port Select. Tie to Vpp to select the serial port; tie to Vss to select the hardware mode. 13 MCLK I Master Clock. 10 MHz clock for the ADPCM processing engine; may be asynchronous to SCLK, CLKX, and CLKY. 14 Vss - Signal Ground. 0.0 volts. 16 XIN I X Data In. Sampled on falling edge of CLKX during selected time slots. 17 CLKX I X Data Clock. Data clock for the X side PCM interface; must be synchro- nous with FSX. 18 FSX I X Frame Syne. 8 KHz frame sync for the X side PCM interface. 20 XOUT oO X Data Output. Updated on rising edge of CLKX during selected time slots. 21 SCLK | Serial Data Clock. Used to write to the serial port registers. 22 SDI I Serial Data In. Data for onboard control registers; sampled on the rising edge of SCLK. LSB sent first. 23 cs { Chip Select. Must be low to write to the serial port. 24 YOUT oO Y Data Output. Updated on rising edge of CLKY during selected time slots. 25 FSY | Y Frame Sync. 8 KHz frame sync for the Y side PCM interface. 26 CLKY I Y Data Clock. Data clock for the Y side PCM interface; must be synchro- nous with FSY. 27 YIN I Y Data In. Sampled on falling edge of CLKY during selected time slots. 28 Vop - Positive Supply. 5.0 volts. 041295 3/17 43DS2164Q DS2164Q BLOCK DIAGRAM Figure 1 FSX ~ CLKX XIN XOUT + _ X SIDE PCM/ADPCM DATA INTERFACE 4 SCLK SPS * cs * SDI " AQ - A5 7 SERIAL PORT CONTROL HARDWARE MODE LOGIC 7 FSY 4. CLKY ___,| YIN * YOUT < Y SIDE PCM/ADPCM DATA INTERFACE L RST TMO * T1_*| RESET AND TEST LOGIC SERIAL PORT WRITE Figure 2 = ADPCM PROCESSING ENGINE ht MCLK Vop JUUULUUUUUUUUU UU UL Kr Xai KX ne X aa Km KAS KUN 0 NeRONERIN ERE ERD ERE) ERE) ERE CRD \ NOTE: ADDRESS/COMMAND 1. A 2-byte write is shown. The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or compres- sion occurs. Bypass operates on bytewide (8 bits) slots when CP/EX is set and on nibble-wide (4 bits) siots when CP/EX is cleared. Y/N CONTROL _ A-law (U/A = 0) and p-law (U/A = 1) PCM coding is inde- pendently selected for the X and Y channels via CR.2. If BYP and IPD are cleared, then CP/EX determines if the input data is to be compressed or expanded. 041295 4/17DS2164Q ADDRESS/COMMAND BYTE Figure 3 (MSB) (LSB) - x AA as | a2 AO SYMBOL POSITION NAME AND DESCRIPTION - ACB.7 Reserved; must be 0 for proper operation XV ACB.6 X/Y Channel Select 0 = update channel Y characteristics 1 = update channel X characteristics A5 ACB.5 MSB of Device Address A4 ACB.4 A3 ACB.3 A2 ACB.2 Al ACB.1 AO ACB.0 LSB of Device Address CONTROL REGISTER Figure 4 (MSB) (LSB) ASO AS1 ALRST BYP U/A CP/EX SYMBOL POSITION NAME AND DESCRIPTION ASO CR.7 Algorithm Select 0. See Table 2. AS1 CR.6 Algorithm Select 1. See Table 2. IPD CR.5 Idle and Power Down. 0 = channel enabled 1 = channel disabled (output 3-stated) ALRST CR.4 Algorithm Reset. 0 = normal operation 1 = reset algorithm for selected channel BYP CR.3 Bypass. 0 = normal operation 1 = bypass selected channel U/A CR.2 Data Format. 0 = A-law 1 =p-law AS2 CR.1 Algorithm Select 2. See Table 2. CP/EX CR.0 Channel Coding. 0 = expand (decode) selected channel 1 = compress (encode) selected channel 041295 5/17 45DS2164Q ALGORITHM SELECT BITS Table 2 ALGORITHM SELECTED AS2 AS1 ASO 64Kbps to/from 32Kbps 0 0 0 64Kbps to/from 24Kbps 1 1 1 64Kbps to/from 16Kbps 1 0 1 INPUT TIME SLOT REGISTER Figure 5 (MSB) (LSB) - - D5 D4 D3 D2 Di DO SYMBOL POSITION NAME AND DESCRIPTION - {TR.7 Reserved: must be 0 for proper operation. - ITR.6 Reserved; must be 0 for proper operation. D5 ITR.5 MSB of input time slot register. D4 ITR.4 D3 ITR.3 D2 ITR.2 D1 ITR.1 DO ITR.O LSB of input time slot register. OUTPUT TIME SLOT REGISTER Figure 6 (MSB) (LSB) - - Ds pa | oa be | pt | io SYMBOL POSITION NAME AND DESCRIPTION - OTR.7 Reserved; must be 0 for proper operation. - OTR.6 Reserved; must be 0 for proper operation. D5 OTR.5 MSB of output time slot register. D4 OTR.4 D3 OTR.3 D2 OTR.2 D1 OTR.1 DO OTR.O LSB of output time slot register. 041295 6/17 46TIME SLOT ASSIGNMENT/ORGANIZATION Onboard counters establish when PCM and ADPCM /O occurs. The counters are programmed via the time slot registers. Time slot size (number of bits wide) is de- termined by the state of CP/EX. The number of time slots available is determined by both the state of CP/EX and U/A. (See Figures 7 through 10.) For example, if the X channel is set to compress (CP/EX = 1) and itis setto DS2164Q p-LAW PCM INTERFACE Figure 7 TIME SLOT 0 TIME SLOT N <_____> DS2164Q expect p-law data (U/A = 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up for 64 4-bit time slots. The time slot organiza- tion is not dependent on which algorithm has been se- lected. NOTE: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync. TIME SIME SLOT 31 31 TIME SLOT 0 TAIT ArT CLKX, CLKY rsxesy IT I I MSB en yw __poereaR= j/ 90000000 || DONT CARE xouT, YouT ___ STATE / / Monn / / 3-STATE DS2164Q p-LAW ADPCM INTERFACE Figure 8 TIME TIME TIME TIME TIME TIME SLOT 0 SLOT 1 SLOT N SLOT62 SLOT63 SLOTO _ ____> ance IIIT] AUT FSX, rsv_} L I| (seer |/J0000 i. I I MSB XIN, YIN DON'T CARE DON'T CARE XOUT, YOUT 3-STATE | | MSB C1 0 0 O LSB / | 3-STATE 041295 7/17 47DS2164Q DS2164Q A-LAW PCM INTERFACE Figure 9 TIME SLOT 0 TIME SLOT N TIME SLOT 31 TIME SLOT 0 cox ou SUUUUUUIL UU] PU, I roxesy IT I I a Sect XIN, YIN ____DON'TCARE | | DON'T CARE | | 3-STATE DS2164Q A-LAW ADPCM INTERFACE Figure 10 TIME TIME TIME TIME TIME TIME SLOT 0 SLOT 1 SLOT N SLOT 62 SLOT 63 SLOT 0 << $$ -<___ <$$$__> <\_> CLKX, CLKY FSX, FSY ANITANNAr/ ARAN ir I NOOK I| DONT CARE MSB XIN, YIN DON'T CARE XOUT, YOUT 3-STATE | | MSB n 10 0 LSB | | 3-STATE 041295 8/17 48DS2164Q HARDWARE MODE The hardware mode is intended for applications that do not have an external controller available or do not re- quire the extended features offered by the serial port. Tying the SPS pin to Vss disables the serial port, clears HARDWARE MODE Table 3 all internal register bits and maps the IPD, U/A, and CP/EX bits for both channels to external bits. (See Table 3.) Inthe hardware mode, both the input and output time slots default to time slot 0. (Channel X & Y) PIN # / NAME REG. LOCATION NAME AND DESCRIPTION 4/A0 CPYEX Channel X Coding Configuration (Channel X) 0 = Expand 1 = Compress 5/A1 ASO/AS1/AS2 Algorithm Select (see Table 5) (Channel X & Y) 6/A2 U/A Channel X Data Format (Channel X) 0 = A-law 1 =p-law 7/83 CP/EX Channel Y Coding Configuration (Channel Y) 0 = Expand 1 = Compress 8/A4 ASO/AS1/AS2 Aigorithm Select (see Table 5) 9/A5 U/A Channel Y Data Format (Channel Y) 0 = Alaw 1 =)-law 18/SDI IPD Channel Y Idle Select (Channel Y) 0 = Channel active 1 = Channel idle 19/CS IPD Channel X Idle Select (Channel X) 0 = Channel active 1 = Channel idle NOTES: 1. SCLK must be tied to Vgg when the hardware mode is selected. 2. When both channels are idled, power consumption is significantly reduced. 3. The DS2164Q will power-up within 800 ms after either channel is returned to active from an idle state. 49 041295 9/17DS2164Q ALGORITHM SELECT FOR HARDWARE MODE Table 4 ALGORITHM CONFIGURATION OF A1 AND A4 64Kbps to/from 32Kbps Tie both At and A4 to Vgs. 64Kbps to/from 24Kbps Hold A1 and A4 low during a hardware reset; take both A1 and Ad high after the RST pin has returned high (allow 3 us after RST returns high before taking Ai and A4 high). 64Kbps to/from 16Kbps Tie both A1 and A4 to Vpp. DS2164Q CONNECTION TO CODEC/FILTER Figure 11 CODEC/FILTER DS2164Q VEX- DX >) XIN XOUT/ TRANSMIT DATA Gx DRI YOUT yin} RECEIVE DATA ANALOG INTERFACE VFRO MCLKX MCLK be 10 MHz CLOCK BCLKX + >) CLKX BCLKR CLKY SPS |_| FSR FSY MCLKR FSX be FSX CS|/ _3-WIRE BUS FROM SCLK \ EXTERNAL CONTROLLER SDI TRANSMIT DATA CLOCK >" RECEIVE DATA CLOCK > Ao At | RECEIVE FRAME SYNC 2> AQ ADDRESS SELECT > TRANSMIT FRAME SYNG A3 (ADDRESS-0 SHOWN) TMO A4 1 AST AS & RESET CIRCUITRY (DS1231) NOTE: Suggested Codec/Filters TP305X National Semiconductor ETC505X SGS-Thomson Microelectronics MC1455XX = Motorola TCM29CXX Texas Instruments HD44238C Hitachi other generic Codec/Filter devices can be substituted. 041295 10/17 50DS2164Q PCM AND ADPCM INPUT/OUTPUT Since the organization of the input and output time slots rithms. In the figure, itis assumed that channel X is in the on the DS2164Q does not depend on the algorithm se- compression mode (CP/EX = 1) and channel Y is in the lected, italways assumes that PCM input and output will expansion mode (CP/EX = 0). Also, it is assumed that be in 8-bit bytes and that ADPCM input and output will both the input and output time slots for both channels be in 4-bit bytes. Figure 12 demonstrates how the are set to 0. DS2164Q handles the I/O for the three different algo- PCM AND ADPCM I/O EXAMPLE Figure 12 CLKX LILILI LI LILLIE MSB LSB xn L/L XX _ XX XK KK XLT MSB LSB 3-STATE xour gasps) {XXX MSB LSB. 3-STATE XOUT (24KBPS) _ XXX ~ SEE NOTE 1 MSB LSB 3-STATE XOUT (16KBPS) 0 0 ov! LILI LILI LE LI LI LILI LE Le FSY _ YIN (@2KBPS) TIZIX. XX x X77 LLLLLLLLLLL muearses, ZZZIX XX XIII TIT TT pnvensrs) ZZZIX KX XZZITILI ITLL LITT TLL. 3-STATE vout {XXX xX X KX KX Po NOTE: 1. The bit after the LSB in the 24Kbps ADPCM output will only be a 1 when the DS2164Q is operated in the software mode and is programmed to perform 24Kbps compression; in all other configurations, it will be a 0. 041295 11/17 51DS2164Q TIME SLOT RESTRICTIONS Under certain conditions, the DS2164Q does contain some restrictions on the output time slots that are avail- able. These restrictions are covered in detail in a sepa- rate application note. No restrictions occur if the DS2164Q is operated in the hardware mode. INPUT TO OUTPUT DELAY With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2164Q ito the time it is output, is always less than 375 Ls. The exact delay is determined by the input and out- put time slots selected for each channel. CHANNEL ASSOCIATED SIGNALING The DS2164Q supports Channel Associated Signaling (CAS) via its ability to automatically change fram the 32Kbps compression algorithm to the 24Kbps algo- rithm. If the DS2164Q is configured to perform the 32Kbps algorithm, then in both the hardware and soft- ware mode, it will sense the frame sync inputs (FSX and FSY) for a double wide frame sync pulse. Whenever the DS21640 receives a double wide pulse, it will automati- Cally switch from the 32Kbps algorithm to the 24Kbps al- gorithm. Switching to the 24Kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM output because this bit does not contain any useful speech information. ON-THE-FLY ALGORITHM SELECTION in the software mode, the user can switch between the three available algorithms on-the-fly. That is, the DS2164Q does not need to be reset or stopped to make the change from one aigorithm to another. The DS2164Q reads the Control Register before it starts to process each PCM or ADPCM sample. If the user wishes to switch algorithms, then the Control Register must be updated via the serial port before the first input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and ACPCM outputs will tristate during register updates. 041295 12/17 520S2164Q ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7.0V 0 to 70C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (OC to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Vie 2.0 Vect0.3 Vv Logic 0 Vit -0.3 +0.8 v Supply Vop 4.5 55 Vv CAPACITANCE (ta=25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance Cin 5 pF Output Capacitance Cout 10 pF DC ELECTRICAL CHARACTERISTICS (0C to 70C; Vpp=5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current Ippa 20 mA 1,2 Idle Supply Current IppPp 1 mA 1,2,3 Input Leakage I 4 0 +1.0 HA Output Leakage lo -1.0 +1.0 uA 4 Output Current (2.4V) lou -1.0 mA Output Current (0.4V) lot +4.0 mA NOTES: 1. CLKX = CLKY = 1.544 MHz; MCLK = 10 MHz. 2. Outputs open; inputs swinging full supply levels. 3. Both channels in idle mode. 4. XOUT and YOUT are 3-stated. 041295 13/17 53DS2164Q PCM INTERFACE AC ELECTRICAL CHARACTERISTICS (0C to 70C; Vpp=5V +10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CLKX. CLKY Period tpxy 244 3906 ns 1 CLKX, CLKY Pulse Width tWxYL 100 ns twxvH CLKX, CLKY Rise Fall Times irxy 10 20 ns texy Hold Time from CLKX, CLKY tHoLD 0 ns 2 to FSX, FSY Setup Time from FSX, FSY tsF 50 ns 2 high to CLKX, CLKY low Hold Time from GCLKX, CLKY tHr 100 ns 2 low to FSX, FSY low Setup Time for XIN, YIN to tsp 50 ns 2 CLKX, CLKY low Hold Time for XIN, YIN tub 50 ns 2 to CLKX, CLKY low Delay Time from CLKX, toxyo 10 150 ns 3 CLKY to Valid XOUT, YOUT Delay Time from CLKX, toxyz 20 150 ns 2,3,4 CLKY to XOUT, YOUT 3-stated NOTES: 1. Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames). 2. Measured at Viy = 2.0V, Viy_ = 0.8V, and 10 ns maximum rise and fall times. 3. Load = 150 pF + 2 LSTTL loads. 4. For LSB of PCM or ADPCM byte. MASTER CLOCK / RESET AC ELECTRICAL CHARACTERISTICS (OC to 70C; Vpp=5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES MCLK Period tpm 100 ns 1 MCLK Pulse Width twMH, 45 50 55 ns twa MCLK Rise/Fall Times tam: tem 10 ns RST Pulse Width tasT 1 ms NOTE: 1. MCLK = 10 MHz + 500 ppm 041295 14117 54DS2164Q SERIAL PORT AC ELECTRICAL CHARACTERISTICS (0C to 70C; Vpp=5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES SDI to SCLK Set Up toc 55 ns 1 SCLK to SDI Hold tcDH 55 ns 1 SCLK Low Time tet 250 ns 1 SCLK High Time ton 250 ns 1 SCLK Rise and Fall Time tp, tr 100 ns 1 CS to SCLK Setup tec 50 ns 1 SCLK to CS Hold tocH 250 ns 1 CS Inactive Time towH 250 ns 1 SCLK Setup to CS Falling tscc 50 ns 1 NOTE: 1. Measured at Viy = 2.0V, Vi = 0.8V, and 10ns maximum rise and fall times. PCM INTERFACE AC TIMING DIAGRAM Figure 13 < tpxy ~ tHoLD taxy texy t t _ La a ag WXYH op tWxXL CLKX iz 4 Lv NM \ CLKY NY K___ FSX FSY tHe FSX FSY It tsF tur tsp tuo XIN vn LELELEEEEEE EEE Xt oasey * K XOUT 3-STATE MSB >| toxvo tpxyz >| 041295 15/17 55DS2164Q MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14 tem tea tem t WMH tWML MCLK trast RST SERIAL PORT AC TIMING DIAGRAM Figure 15 town $m oN SS FA N tcwH ta te tocH tcc tcH tscc | > _ a ox SUP So [ so <PRILID< UTED 9 TTTTTTTITT NOTE: 1. SCLK may be either high or low when CS is taken low. 041295 16/17 56DS2164Q DS2164Q G.726 ADPCM PROCESSOR 28-PIN PLCC E _* TItTFCTCIcCI crc E1 nomoonn q q q l4 1 D2 { Doo oo oo ti Bi CH1 q r be et Z | _t = 100 q INCHES pm | MIN | MAX A 0.165 0.180 Al 0.090 0.120 A2 0.020 - B 0.026 0.033 B1 0.013 0.021 0.009 0.012 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E14 0.450 0.456 E2 0.390 0.430 L1 0.060 - N 28 - e1 0.050 BSC CH1 0.042 0.048 041295 17/17 57