Dual Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters AD9114/AD9115/AD9116/AD9117 Data Sheet FEATURES GENERAL DESCRIPTION Power dissipation @ 3.3 V, 20 mA output 191 mW @ 10 MSPS 232 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist 86 dBc @ 1 MHz output 85 dBc @ 10 MHz output AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: -162 dBc/Hz Differential current outputs: 2 mA to 20 mA 2 on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP RoHS-compliant package The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC(R) converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications. PRODUCT HIGHLIGHTS 1. APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators Rev. D The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS. 2. 3. Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2008-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9114/AD9115/AD9116/AD9117 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Descriptions .............................................................. 36 Applications ....................................................................................... 1 Digital Interface Operation ........................................................... 40 General Description ......................................................................... 1 Digital Data Latching and Retimer Section ............................ 41 Product Highlights ........................................................................... 1 Estimating the Overall DAC Pipeline Delay........................... 42 Revision History ............................................................................... 3 Reference Operation .................................................................. 43 Functional Block Diagram .............................................................. 4 Reference Control Amplifier .................................................... 43 Specifications..................................................................................... 5 DAC Transfer Function ............................................................. 43 DC Specifications ......................................................................... 5 Analog Output ............................................................................ 44 Digital Specifications ................................................................... 7 Self-Calibration........................................................................... 44 AC Specifications.......................................................................... 8 Coarse Gain Adjustment ........................................................... 45 Absolute Maximum Ratings ............................................................ 9 Using the Internal Termination Resistors ............................... 46 Thermal Resistance ...................................................................... 9 Applications Information .............................................................. 47 ESD Caution .................................................................................. 9 Output Configurations .............................................................. 47 Pin Configurations and Function Descriptions ......................... 10 Differential Coupling Using a Transformer ............................... 47 Typical Performance Characteristics ........................................... 18 Single-Ended Buffered Output Using an Op Amp ................ 47 Terminology .................................................................................... 31 Differential Buffered Output Using an Op Amp .................. 48 Theory of Operation ...................................................................... 32 Auxiliary DACs........................................................................... 48 Serial Peripheral Interface (SPI) ................................................... 33 DAC-to-Modulator Interfacing ................................................ 49 General Operation of the Serial Interface ............................... 33 Instruction Byte .......................................................................... 33 Correcting for Nonideal Performance of Quadrature Modulators on the IF-to-RF Conversion ................................ 49 Serial Interface Port Pin Descriptions ..................................... 33 I/Q Channel Gain Matching ..................................................... 49 MSB/LSB Transfers..................................................................... 34 LO Feedthrough Compensation .............................................. 50 Serial Port Operation ................................................................. 34 Results of Gain and Offset Correction .................................... 50 Pin Mode ..................................................................................... 34 Outline Dimensions ....................................................................... 51 SPI Register Map ............................................................................. 35 Ordering Guide .......................................................................... 52 Rev. D | Page 2 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 REVISION HISTORY 12/2017--Rev. C to Rev. D Changes to Figure 94 ......................................................................41 Changes to Estimating the Overall DAC Pipeline Delay Section ..42 Updated Outline Dimensions ........................................................51 Changes to Ordering Guide ...........................................................52 3/2013--Rev. B to Rev. C Change to Features Section .............................................................. 1 Change to Endnote 1, Table 1 .......................................................... 6 Changes to Figure 86 and Figure 88 .............................................34 Change to Table 13 ..........................................................................35 Change to Version Register Description, Table 14 .....................39 Changes to Table 17 and Reference Control Amplifier Section ..............................................................................................43 Changes to Using the Internal Termination Resistors Section ..............................................................................................46 Changes to Single-Ended Buffered Output Using an Op Amp Section ..............................................................................................47 Changes to Differential Buffered Output Using an Op Amp Section ..............................................................................................48 Updated Outline Dimensions ........................................................51 5/2012--Rev. A to Rev. B Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 7 Changes to Table 3 and Table 4 ....................................................... 8 Changes to Theory of Operation Section ....................................32 Changes to SCLK--Serial Clock Section .....................................33 Changes to Pin Mode Section........................................................34 Changes to Table 14 ........................................................................37 Changes to Self-Calibration Section .............................................44 Deleted Modifying the Evaluation Board to Use the ADL5370 On-Board Quadrature Modulator Section .......................................... 51 Deleted Evaluation Board Schematics and Artwork Section and Figure 111 to Figure 133, Renumbered Sequentially..................52 Updated Outline Dimensions ........................................................51 Changes to Ordering Guide ...........................................................52 Deleted Bill of Materials Section and Table 18 ............................75 3/2009--Rev. 0 to Rev. A Changes to Product Title and General Description Section ....... 1 Changes to Figure 1 .......................................................................... 4 Changed IOUTFS = 2 mA to IxOUTFS = 20 mA .................................... 5 Changes to Table 1 ............................................................................ 6 Changed IOUTFS = 2 mA to IxOUTFS = 20 mA .................................... 7 Changes to Table 2 ............................................................................ 7 Changed DVDDIO = 1.8 V to DVDDIO = 3.3 V, Table 3 and CVDD = 3.3 V to CVDD = 1.8 V, Table 4 ..................................... 8 Changes to Table 5 and Table 6 ....................................................... 9 Changes to Table 7 .......................................................................... 10 Changes to Table 8 .......................................................................... 12 Changes to Table 9 .......................................................................... 14 Changes to Table 10 ........................................................................ 16 Changes to Typical Performance Characteristics Section ......... 18 Changes to Theory of Operation Section and Figure 84 ........... 32 Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34 Changes to Table 13 ........................................................................ 35 Changes to Table 14 ........................................................................ 36 Changes to Digital Interface Operation Section and Figure 89, Figure 90, Figure 91, Figure 92, and Figure 93 ............................ 40 Changes to Figure 94, Digital Data Latching Section, and Retimer Section ............................................................................... 41 Added Reference Operation Section, Reference Control Amplifier Section, DAC Transfer Function Section, Figure 96, and Table 17 ..................................................................................... 43 Added Analog Output Section ...................................................... 44 Changes to Auxiliary DACs Section ............................................. 48 Changes to DAC to Modulator Interfacing Section, Figure 107, and Figure 108 ................................................................................. 49 Added Figure 111 to Figure 133 .................................................... 52 Added Table 18 ................................................................................ 75 8/2008--Revision 0: Initial Version Rev. D | Page 3 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet AD9117 1V 10k DB9 IREF 100A DB8 DVDDIO 1 INTO 2 INTERLEAVED DATA INTERFACE DVSS DVDD IRSET 2k QRSET 2k DB10 1.8V LDO IRCM 60 TO 260 62.5 I DAC 62.5 BAND GAP I DATA AVSS 62.5 CVSS CVDD CLKIN DCLKIO (LSB) DB0 DB1 DB2 DB5 Figure 1. Rev. D | Page 4 of 52 QOUTN RLQN QRCM 60 TO 260 CMLQ CLOCK DIST RLQP QOUTP Q DAC 62.5 DB3 IOUTP AVDD AUX2DAC DB7 DB4 IOUTN RLIP AUX1DAC Q DATA DB6 RLIN 07466-001 SPI INTERFACE DB11 CMLI FSADJI/AUXI FSADJQ/AUXQ REFIO RESET/PINMD SCLK/CLKMD SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 FUNCTIONAL BLOCK DIAGRAM Data Sheet AD9114/AD9115/AD9116/AD9117 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V Differential Nonlinearity (DNL) Precalibration Postcalibration Integral Nonlinearity (INL) Precalibration Postcalibration ACCURACY, AVDD = DVDDIO =CVDD = 1.8 V Differential Nonlinearity (DNL) Precalibration Postcalibration Integral Nonlinearity (INL) Precalibration Postcalibration MAIN DAC OUTPUTS Offset Error Gain Error Internal Reference Full-Scale Output Current 1 AVDD = 3.3 V AVDD = 1.8 V Output Common-Mode Level (8 mA CMLx Pin) Output Compliance Range AVDD = 3.3 V, 8 mA Output Common Mode Level = -0.5 Common Mode Level = 0 Common Mode Level = +1.2 Output Resistance Crosstalk, Q DAC to I DAC (fOUT = 30 MHz) Crosstalk, Q DAC to I DAC (fOUT = 60 MHz) MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage Min AD9114 Typ Max 8 AD9115 Typ Max 10 Min AD9116 Typ Max 12 Min AD9117 Typ Max 14 Unit Bits 0.02 0.02 0.06 0.04 0.4 0.2 1.4 0.6 LSB LSB 0.03 0.03 0.19 0.07 0.68 0.42 1.2 0.6 LSB LSB 0.02 0.01 0.08 0.06 0.5 0.2 1.8 1.0 LSB LSB 0.04 0.02 0.2 0.1 0.5 0.3 1.8 1.1 LSB LSB -1 -2 2 2 -0.5 Min 8 0 -0.9 -0.4 0.8 +1 +2 -1 -2 20 8 +1.2 2 2 -0.5 -0.1 +0.4 1.5 -0.9 -0.4 0.8 8 0 +1 +2 -1 -2 20 8 +1.2 2 2 -0.5 -0.1 +0.4 1.5 -0.9 -0.4 0.8 8 0 +1 +2 -1 -2 20 8 +1.2 2 2 -0.5 -0.1 +0.4 1.5 -0.9 -0.4 0.8 8 0 +1 +2 mV % of FSR 20 8 +1.2 mA mA V -0.1 +0.4 1.5 200 95 200 95 200 95 200 95 V V V M dB 76 76 76 76 dB 0 40 25 0 40 25 0 40 25 0 40 25 ppm/C ppm/C ppm/C Rev. D | Page 5 of 52 AD9114/AD9115/AD9116/AD9117 Parameter AUXDAC OUTPUTS Resolution Full-Scale Output Current (Current Sourcing Mode) Voltage Output Mode Output Compliance Range (Sourcing 1 mA) Output Compliance Range (Sinking 1 mA) Output Resistance in Current Output Mode AVSS to 1 V AUXDAC Monotonicity Guaranteed REFERENCE OUTPUT Internal Reference Voltage Output Resistance REFERENCE INPUT Voltage Compliance AVDD = 3.3 V AVDD = 1.8 V Input Resistance External Reference Mode DAC MATCHING Gain Matching ANALOG SUPPLY VOLTAGES AVDD CVDD DIGITAL SUPPLY VOLTAGES DVDD DVDDIO POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 3.3 V fDAC = 125 MSPS, IF = 12.5 MHz IAVDD IDVDD + IDVDDIO ICVDD Power-Down Mode with Clock Power-Down Mode No Clock Power Supply Rejection Ratio POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 1.8 V fDAC = 125 MSPS, IF = 12.5 MHz IAVDD IDVDD + IDVDDIO ICVDD Power-Down Mode with Clock Power-Down Mode No Clock Power Supply Rejection Ratio OPERATING RANGE 1 Min Data Sheet AD9114 Typ Max Min 10 125 VSS + 0.25 0.98 Min 10 125 VDD - 0.25 VDD VSS AD9115 Typ Max VSS + 0.25 Min 10 125 VDD - 0.25 VDD VSS AD9116 Typ Max VDD - 0.25 VDD VSS VSS + 0.25 AD9117 Typ Max Unit 10 125 Bits A VDD - 0.25 VDD VSS VSS + 0.25 V V 1 1 1 1 M 10 10 10 10 Bits 1.025 10 0.1 0.1 1.08 0.98 1.25 1.0 0.1 0.1 1 1.025 10 1.08 0.98 1.25 1.0 0.1 0.1 1 1.025 10 1.08 0.98 1.25 1.0 0.1 0.1 1 1.025 10 1.08 V k 1.25 1.0 V V M 1 -1 +1 -1 +1 -1 +1 -1 +1 % of FSR 1.7 1.7 3.5 3.5 1.7 1.7 3.5 3.5 1.7 1.7 3.5 3.5 1.7 1.7 3.5 3.5 V V 1.7 1.7 1.9 3.5 1.7 1.7 1.9 3.5 1.7 1.7 1.9 3.5 1.7 1.7 1.9 3.5 V V -40 220 55 10 3 8.5 3 -0.009 220 55 10 3 8.5 3 -0.009 220 55 10 3 8.5 3 -0.009 220 55 10 3 8.5 3 -0.009 mW mA mA mA mW mW % FSR/V 58 24 8 2 12 850 -0.007 +25 58 24 8 2 12 850 -0.007 +25 58 24 8 2 12 850 -0.007 +25 58 24 8 2 12 850 -0.007 +25 mW mA mA mA mW W % FSR/V C +85 -40 +85 Based on a 1.6 k external resistor for 20 mA full-scale current. Rev. D | Page 6 of 52 -40 +85 -40 +85 Data Sheet AD9114/AD9115/AD9116/AD9117 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter DAC CLOCK INPUT (CLKIN) VIH VIL Maximum Clock Rate SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High Minimum Pulse Width Low Minimum SDIO and to SCLK Setup, tDS Minimum SCLK to SDIO Hold, tDH Maximum SCLK to Valid SDIO, tDV Minimum SCLK to Invalid SDIO, tDNV INPUT DATA 1.8 V Q Channel or DCLKIO Falling Edge Setup Hold 1.8 V I Channel or DCLKIO Rising Edge Setup Hold 3.3 V Q Channel or DCLKIO Falling Edge Setup Hold 3.3 V I Channel or DCLKIO Rising Edge Setup Hold DVDDIO = 3.3 V VIH VIL DVDDIO = 1.8 V VIH VIL Min Typ 2.1 3 0 2.1 1.2 Rev. D | Page 7 of 52 Max Unit 0.9 125 V V MSPS 25 20 20 10 5 20 5 MHz ns ns ns ns ns ns 0.25 1.2 ns ns 0.13 1.1 ns ns -0.2 1.5 ns ns -0.2 1.6 ns ns 3 0 0.9 V V 1.8 0 0.5 V V AD9114/AD9115/AD9116/AD9117 Data Sheet AC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Output Settling Time (tST) to 0.1% Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Output Noise (IOUTFS = 20mA) SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz TWO TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 1 MHz fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz fDAC = 122.88 MSPS, fOUT = 30 MHz Min AD9114 Typ Max Min AD9115 Typ Max Min AD9116 Typ Max Min AD9117 Typ Max Unit 11.5 0.27 0.27 1471 11.5 0.27 0.27 465 11.5 0.27 0.27 117 11.5 0.27 0.27 37 ns ns ns pA/Hz 76 55 85 55 85 55 85 55 dBc dBc 81 60 81 60 81 60 82 61 dBc dBc -131 -132 -128 -141 -143 -138 -153 -153 -146 -163 -157 -149 dBc/Hz dBc/Hz dBc/Hz -78 -80 -78 -80 -78 -80 -78 -80 dBc dBc TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, IxOUTFS = 8 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz TWO TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 1 MHz fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz fDAC = 122.88 MSPS, fOUT = 30 MHz Min AD9114 Typ Max Min AD9115 Typ Max Min AD9116 Typ Max Min AD9117 Typ Max Unit 73 48 76 48 76 48 76 48 dBc dBc 76 50 76 50 76 50 76 50 dBc dBc -131 -132 -128 -143 -143 -138 -152 -151 -140 -158 -152 -141 dBc/Hz dBc/Hz dBc/Hz -69 -72 -69 -72 -69 -72 -69 -72 dBc dBc Rev. D | Page 8 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS DVDD to DVSS AVSS to DVSS, CVSS DVSS to AVSS, CVSS CVSS to AVSS, DVSS REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS DBn1 (MSB) to D0 (LSB), CS, SCLK, SDIO, RESET to DVSS CLKIN to CVSS Junction Temperature Storage Temperature Range 1 THERMAL RESISTANCE Rating -0.3 V to +3.9 V Table 6. Package Type 40-Lead LFCSP (with No Airflow Movement) -0.3 V to +2.1 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.3 V 1 JB1 19.0 JC1 3.4 Unit C/W These calculations are intended to represent the thermal performance of the indicated packages using a JEDEC multilayer test board. Do not assume the same level of thermal performance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations. -1.0 V to AVDD + 0.3 V -0.3 V to DVDDIO + 0.3 V JA 29.8 ESD CAUTION -0.3 V to CVDD + 0.3 V 125C -65C to +150C n stands for 7 for the AD9114, 9 for the AD9115, 11 for the AD9116, and 13 for the AD9117. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. D | Page 9 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet 40 39 38 37 36 35 34 33 32 31 DB6 DB7 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9114 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. 07466-005 NC NC NC NC NC DCLKIO CVDD CLKIN CVSS CMLQ 11 12 13 14 15 16 17 18 19 20 DB5 1 DB4 2 DB3 3 DB2 4 DVDDIO 5 DVSS 6 DVDD 7 DB1 8 DB0 (LSB) 9 NC 10 Figure 2. AD9114 Pin Configuration Table 7. AD9114 Pin Function Descriptions Pin No. 1 to 4 5 6 7 Mnemonic DB[5:2] DVDDIO DVSS DVDD 8 9 10 to 15 16 17 18 19 20 DB1 DB0 (LSB) NC 21 RLQN 22 23 24 QOUTN QOUTP RLQP 25 26 27 AVSS AVDD RLIP 28 IOUTP DCLKIO CVDD CLKIN CVSS CMLQ Description Digital Inputs. Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 F capacitor; however, do not otherwise connect it. The LDO should not drive external loads. Digital Inputs Digital Input (LSB). No Connect. These pins are not connected to the chip. Data Input/Output Clock. Clock used to qualify input data. Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be DVDD. LVCMOS Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. Analog Common. Analog Supply Voltage Input (1.8 V to 3.3 V). Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Rev. D | Page 10 of 52 Data Sheet Pin No. 29 30 Mnemonic IOUTN RLIN 31 CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB7 (MSB) DB6 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required). This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see the Retimer section. Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. Digital Input (MSB). Digital Input. The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad. Rev. D | Page 11 of 52 Data Sheet 40 39 38 37 36 35 34 33 32 31 DB8 DB9 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9114/AD9115/AD9116/AD9117 PIN 1 INDICATOR AD9115 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. 07466-004 DB0 (LSB) NC NC NC NC DCLKIO CVDD CLKIN CVSS CMLQ 11 12 13 14 15 16 17 18 19 20 DB7 1 DB6 2 DB5 3 DB4 4 DVDDIO 5 DVSS 6 DVDD 7 DB3 8 DB2 9 DB1 10 Figure 3. AD9115 Pin Configuration Table 8. AD9115 Pin Function Description Pin No. 1 to 4 5 6 7 Mnemonic DB[7:4] DVDDIO DVSS DVDD 8 to 10 11 12 to 15 16 17 18 19 20 DB[3:1] DB0 (LSB) NC DCLKIO CVDD CLKIN CVSS CMLQ 21 RLQN 22 23 24 QOUTN QOUTP RLQP 25 26 27 AVSS AVDD RLIP 28 29 30 IOUTP IOUTN RLIN Description Digital Inputs. Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 F capacitor; however, do not otherwise connect it. The LDO should not drive external loads. Digital Inputs. Digital Input (LSB). No Connect. These pins are not connected to the chip. Data Input/Output Clock. Clock used to qualify input data. Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be DVDD. LVCMOS Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. Analog Common. Analog Supply Voltage Input (1.8 V to 3.3 V). Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. D | Page 12 of 52 Data Sheet Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB9 (MSB) DB82 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required). This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section. Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. Digital Input (MSB). Digital Input. The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad. Rev. D | Page 13 of 52 Data Sheet 40 39 38 37 36 35 34 33 32 31 DB10 DB11 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9114/AD9115/AD9116/AD9117 PIN 1 INDICATOR AD9116 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. 07466-003 DB2 DB1 DB0 (LSB) NC NC DCLKIO CVDD CLKIN CVSS CMLQ 11 12 13 14 15 16 17 18 19 20 DB9 1 DB8 2 DB7 3 DB6 4 DVDDIO 5 DVSS 6 DVDD 7 DB5 8 DB4 9 DB3 10 Figure 4. AD9116 Pin Configuration Table 9. AD9116 Pin Function Descriptions Pin No. 1 to 4 5 6 7 Mnemonic DB[9:6] DVDDIO DVSS DVDD 8 to 12 13 14, 15 16 17 18 19 20 DB[5:1] DB0 (LSB) NC DCLKIO CVDD CLKIN CVSS CMLQ 21 RLQN 22 23 24 QOUTN QOUTP RLQP 25 26 27 AVSS AVDD RLIP 28 29 30 IOUTP IOUTN RLIN Description Digital Inputs. Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 F capacitor; however, do not otherwise connect it. The LDO should not drive external loads. Digital Inputs. Digital Input (LSB). No Connect. These pins are not connected to the chip. Data Input/Output Clock. Clock used to qualify input data. Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be DVDD. LVCMOS Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. Analog Common. Analog Supply Voltage Input (1.8 V to 3.3 V). Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. D | Page 14 of 52 Data Sheet Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB11 (MSB) DB10 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required). This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section. Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. Digital Input (MSB). Digital Input. The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad. Rev. D | Page 15 of 52 Data Sheet 40 39 38 37 36 35 34 33 32 31 DB12 DB13 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9114/AD9115/AD9116/AD9117 PIN 1 INDICATOR AD9117 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD. 07466-002 DB4 DB3 DB2 DB1 DB0 (LSB) DCLKIO CVDD CLKIN CVSS CMLQ 11 12 13 14 15 16 17 18 19 20 DB11 1 DB10 2 DB9 3 DB8 4 DVDDIO 5 DVSS 6 DVDD 7 DB7 8 DB6 9 DB5 10 Figure 5. AD9117 Pin Configuration Table 10. AD9117 Pin Function Descriptions Pin No. 1 to 4 5 6 7 Mnemonic DB[11:8] DVDDIO DVSS DVDD 8 to 14 15 16 17 18 19 20 DB[7:1] DB0 (LSB) DCLKIO CVDD CLKIN CVSS CMLQ 21 RLQN 22 23 24 QOUTN QOUTP RLQP 25 26 27 AVSS AVDD RLIP 28 29 30 IOUTP IOUTN RLIN Description Digital Inputs. Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 F capacitor; however, do not otherwise connect it. The LDO should not drive external loads. Digital Inputs. Digital Input (LSB). Data Input/Output Clock. Clock used to qualify input data. Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be DVDD. LVCMOS Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. Analog Common. Analog Supply Voltage Input (1.8 V to 3.3 V). Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. Rev. D | Page 16 of 52 Data Sheet Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB13 (MSB) DB12 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 . Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 k for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required). This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section. Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. Digital Input (MSB). Digital Input. The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad. Rev. D | Page 17 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 1.5 1.5 POSTCALIBRATION INL (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE -0.5 -1.0 -2.0 2.0 2.0 1.5 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 1.0 0.5 0 -0.5 -1.0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE -2.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 07466-010 0 Figure 7. AD9117 Precalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V) Figure 10. AD9117 Postcalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V) 1.5 1.0 1.0 POSTCALIBRATION INL (LSB) 1.5 0.5 0 -0.5 -1.0 0.5 0 -0.5 -1.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 8. AD9117 Precalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V) -1.5 07466-008 -1.5 2048 -1.5 07466-007 -2.0 0 Figure 9. AD9117 Postcalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V) POSTCALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) 0 07466-009 0 Figure 6. AD9117 Precalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V) PRECALIBRATION INL (LSB) 0.5 -1.5 07466-006 -2.0 1.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 07466-011 PRECALIBRATION INL (LSB) AVDD, DVDD, DVDDIO, CVDD = 1.8 V, IxOUTFS = 8 mA, maximum sample rate (125 MSPS), unless otherwise noted. Figure 11. AD9117 Postcalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V) Rev. D | Page 18 of 52 AD9114/AD9115/AD9116/AD9117 1.5 1.5 1.0 1.0 0.5 0 -0.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 0 -0.5 -1.0 -1.5 0.8 0.8 0.6 0.6 0.4 0.2 0 -0.2 -0.4 8192 10,240 12,288 14,336 16,384 CODE 0.2 0 -0.2 -0.4 -0.6 512 1024 1536 2048 CODE 2560 3072 3584 4096 -0.8 07466-013 0 0 0.6 0.4 0.4 POSTCALIBRATION DNL (LSB) 0.6 0.2 0 -0.2 -0.4 0 512 1024 1536 2048 CODE 2560 3072 3584 512 1024 1536 2048 CODE 2560 3072 3584 4096 Figure 16. AD9116 Postcalibration INL at 1.8 V, 8 mA 4096 07466-014 PRECALIBRATION DNL (LSB) 6144 0.4 Figure 13. AD9116 Precalibration INL at 1.8 V, 8 mA -0.6 4096 07466-016 -0.6 -0.8 2048 Figure 15. AD9117 Postcalibration DNL at 3.3 V, 20 mA POSTCALIBRATION INL (LSB) PRECALIBRATION INL (LSB) Figure 12. AD9117 Precalibration DNL at 3.3 V, 20 mA 0 Figure 14. AD9116 Precalibration DNL at 1.8 V, 8 mA 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 CODE 2560 3072 3584 Figure 17. AD9116 Postcalibration DNL at 1.8 V, 8 mA Rev. D | Page 19 of 52 4096 07466-017 -1.5 07466-012 -1.0 0.5 07466-015 POSTCALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) Data Sheet Data Sheet 0.8 0.8 0.6 0.6 POSTCALIBRATION INL (LSB) 0.4 0.2 0 -0.2 -0.4 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 -0.8 07466-018 0 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 2048 CODE 2560 3072 3584 4096 0.2 0.1 0 -0.1 -0.2 -0.3 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 -0.5 0 Figure 19. AD9116 Precalibration DNL at 3.3 V, 20 mA 0.25 0.20 0.20 0.15 0.15 POSTCALIBRATION INL (LSB) 0.25 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 512 1024 1536 2048 CODE 2560 3072 3584 4096 Figure 22. AD9116 Postcalibration DNL at 3.3 V, 20 mA 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 128 256 384 512 CODE 640 768 896 1024 07466-020 PRECALIBRATION INL (LSB) 1536 -0.4 07466-019 -0.5 1024 Figure 21. AD9116 Postcalibration INL at 3.3 V, 20 mA POSTCALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) Figure 18. AD9116 Precalibration INL at 3.3 V, 20 mA 512 07466-022 -0.8 0.2 07466-021 -0.6 0.4 Figure 20. AD9115 Precalibration INL at 1.8 V, 8 mA -0.25 0 128 256 384 512 CODE 640 768 896 Figure 23. AD9115 Postcalibration INL at 1.8 V, 8 mA Rev. D | Page 20 of 52 1024 07466-023 PRECALIBRATION INL (LSB) AD9114/AD9115/AD9116/AD9117 AD9114/AD9115/AD9116/AD9117 0.08 0.08 0.06 0.06 POSTCALIBRATION DNL (LSB) 0.04 0.02 0 -0.02 -0.04 0 -0.02 -0.04 -0.06 0 128 256 384 512 CODE 640 768 896 1024 -0.08 07466-024 0.25 0.25 0.20 0.20 0.15 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 128 256 384 512 CODE 640 768 896 1024 512 CODE 640 768 896 1024 0.05 0 -0.05 -0.10 -0.15 -0.25 0 128 256 384 512 CODE 640 768 896 1024 Figure 28. AD9115 Postcalibration INL at 3.3 V, 20 mA 0.08 0.06 0.06 POSTCALIBRATION DNL (LSB) 0.08 0.04 0.02 0 -0.02 -0.04 -0.06 0.04 0.02 0 -0.02 -0.04 -0.06 0 128 256 384 512 CODE 640 768 896 1024 07466-026 PRECALIBRATION DNL (LSB) 384 0.10 Figure 25. AD9115 Precalibration INL at 3.3 V, 20 mA -0.08 256 -0.20 07466-025 -0.25 128 Figure 27. AD9115 Postcalibration DNL at 1.8 V, 8 mA POSTCALIBRATION INL (LSB) PRECALIBRATION INL (LSB) Figure 24. AD9115 Precalibration DNL at 1.8 V, 8 mA 0 07466-028 -0.08 0.02 07466-027 -0.06 0.04 Figure 26. AD9115 Precalibration DNL at 3.3 V, 20 mA -0.08 0 128 256 384 512 CODE 640 768 896 Figure 29. AD9115 Postcalibration DNL at 3.3 V, 20 mA Rev. D | Page 21 of 52 1024 07466-029 PRECALIBRATION DNL (LSB) Data Sheet Data Sheet 0.035 0.035 0.025 0.025 POSTCALIBRATION INL (LSB) 0.015 0.005 0 -0.005 -0.015 -0.025 0.005 0 -0.005 -0.015 0 32 64 96 128 CODE 160 192 224 256 -0.035 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 128 CODE 160 192 224 256 0.005 0 -0.005 -0.010 -0.015 32 64 96 128 CODE 160 192 224 256 -0.025 0.02 0.02 POSTCALIBRATION INL (LSB) 0.03 0.01 0 -0.01 -0.02 32 64 96 128 CODE 160 192 224 32 64 96 128 CODE 160 192 224 256 Figure 34. AD9114 Postcalibration DNL at 1.8 V, 8 mA 0.03 0 0 07466-034 0 256 07466-032 PRECALIBRATION INL (LSB) 96 0.010 Figure 31. AD9114 Precalibration DNL at 1.8 V, 8 mA -0.03 64 -0.020 07466-031 -0.025 32 Figure 33. AD9114 Postcalibration INL at 1.8 V, 8 mA POSTCALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) Figure 30. AD9114 Precalibration INL at 1.8 V, 8 mA 0 07466-033 -0.025 07466-030 -0.035 0.015 Figure 32. AD9114 Precalibration INL at 3.3 V, 20 mA 0.01 0 -0.01 -0.02 -0.03 0 32 64 96 128 CODE 160 192 224 Figure 35. AD9114 Postcalibration INL at 3.3 V, 20 mA Rev. D | Page 22 of 52 256 07466-035 PRECALIBRATION INL (LSB) AD9114/AD9115/AD9116/AD9117 AD9114/AD9115/AD9116/AD9117 0.025 0.025 0.020 0.020 0.015 0.015 POSTCALIBRATION DNL (LSB) 0.010 0.005 0 -0.005 -0.010 -0.015 0.005 0 -0.005 -0.010 -0.015 -0.020 -0.020 0 32 64 96 128 CODE 160 192 224 256 -0.025 07466-036 -0.025 0.010 0 32 64 96 128 160 192 224 256 CODE Figure 36. AD9114 Precalibration DNL at 3.3 V, 20 mA 07466-039 PRECALIBRATION DNL (LSB) Data Sheet Figure 39. AD9114 Postcalibration DNL at 3.3 V, 20 mA -124 -124 AD9114 -130 -130 AD9114 -136 AD9115 NSD (dBc) NSD (dBc) -136 -142 AD9115 -142 AD9116 -148 -148 AD9117 -154 AD9116 -154 AD9117 0 10 20 30 fOUT (MHz) 40 50 -166 07466-137 -160 0 5 10 15 20 Figure 37. NSD at 8 mA vs. fOUT, 1.8 V -136 -139 -139 35 40 45 50 55 45 50 55 -142 -142 +85C +85C +25C -148 -40C -151 -145 -148 +25C -154 -154 -157 -157 0 5 10 15 20 25 30 35 40 45 50 55 fOUT (MHz) Figure 38. AD9117 NSD at Three Temperatures 8 mA vs. fOUT, 1.8 V -40C -151 -160 0 5 10 15 20 25 30 35 40 fOUT (MHz) Figure 41. AD9117 NSD at Three Temperatures 8 mA vs. fOUT, 3.3 V Rev. D | Page 23 of 52 07466-202 NSD (dBm/Hz) -145 07466-201 NSD (dBm/Hz) 30 Figure 40. NSD at 20 mA vs. fOUT, 3.3 V -136 -160 25 fOUT (MHz) 07466-200 -160 AD9114/AD9115/AD9116/AD9117 Data Sheet -130 -130 -136 1.8V, 8mA -142 NSD (dBc) -142 NSD (dBc) -136 1.8V, 4mA -148 -148 -154 -154 -160 -160 3.3V, 4mA 3.3V, 8mA 5 10 15 20 25 30 fOUT (MHz) 35 40 45 50 55 -166 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -70 -70 -80 -80 -90 -90 1.5MHz/DIV STOP 16MHz 07466-090 -60 START 1MHz -100 15 20 START 1MHz Figure 43. AD9117 Two Tone Spectrum at 1.8 V 25 30 fOUT (MHz) 35 40 45 50 55 1.5MHz/DIV STOP 16MHz Figure 46. AD9117 Two Tone Spectrum at 3.3 V 90 96 90 AD9117 AD9116 AD9115 AD9114 AD9117 AD9116 AD9115 AD9114 84 IMD (dBc) 80 70 78 72 66 60 50 5 10 15 20 25 30 fOUT (MHz) 35 40 45 50 54 Figure 44. All IMD 8 mA vs. fOUT, 1.8 V 5 10 15 20 25 30 fOUT (MHz) 35 40 Figure 47. All IMD 20 mA vs. fOUT, 3.3 V Rev. D | Page 24 of 52 45 50 07466-147 60 07466-144 IMD (dBc) 10 -50 -60 -100 5 Figure 45. AD9117 NSD at Three Output Currents vs. fOUT, 3.3 V (dBm) (dBm) Figure 42. AD9117 NSD at Two Output Currents vs. fOUT, 1.8 V 0 07466-091 0 07466-142 -166 07466-145 3.3V, 20mA Data Sheet AD9114/AD9115/AD9116/AD9117 90 84 87 78 84 81 IMD (dBc) IMD (dBc) 72 66 -40C 60 78 75 -40C 72 +25C +25C 69 54 10 15 20 25 30 35 40 45 50 63 fOUT (MHz) 5 10 15 20 25 30 35 40 45 07466-196 5 07466-195 48 +85C 66 +85C 50 fOUT (MHz) Figure 48. AD9117 IMD at Three Temperatures 8 mA vs. fOUT, 1.8 V Figure 51. AD9117 IMD at Three Temperatures 20 mA vs. fOUT, 3.3 V 90 90 85 85 80 80 -6dB 70 IMD (dBc) IMD (dBc) 75 -6dB 65 -3dB 75 -3dB 70 0dB 60 65 0dB 55 5 10 15 20 25 30 35 40 45 55 07466-092 45 50 fOUT (MHz) 5 10 15 20 25 30 35 40 45 07466-093 60 50 50 fIN (MHz) Figure 49. AD9117 IMD at Three Digital Signal Levels vs. fOUT, 1.8 V Figure 52. AD9117 IMD at Three Digital Signal Levels vs. fOUT, 3.3 V 86 92 80 86 8mA 4mA 80 68 8mA 20mA 74 62 68 56 62 50 5 10 15 20 25 30 35 40 45 50 fOUT (MHz) 56 5 10 15 20 25 30 35 40 45 50 fOUT (MHz) Figure 50. AD9117 IMD at Two Output Currents vs. fOUT, 1.8 V Figure 53. AD9117 IMD at Three Output Currents vs. fOUT, 3.3 V Rev. D | Page 25 of 52 07466-153 IMD (dBc) 4mA 07466-150 IMD (dBc) 74 Data Sheet 0 0 -10 -10 -20 -20 -30 -30 -40 -40 (dBm) -50 -50 -60 -60 -70 -70 -80 -80 -90 START 1MHz 1.5MHz/DIV 07466-088 -90 -100 STOP 16MHz -100 START 1MHz Figure 54. AD9117 Singe Tone Spectrum, 1.8 V 1.5MHz/DIV 07466-089 (dBm) AD9114/AD9115/AD9116/AD9117 STOP 16MHz Figure 57. AD9117 Singe Tone Spectrum, 3.3 V 90 96 90 80 70 SFDR (dBc) SFDR (dBc) 84 AD9117 AD9116 AD9115 AD9114 60 AD9117 AD9116 AD9115 AD9114 78 72 66 50 10 20 30 40 50 60 fOUT (MHz) 54 0 20 30 40 50 60 60 fOUT (MHz) Figure 55. SFDR at 8 mA vs. fOUT, 1.8 V Figure 58. AD9117 SFDR at 20 mA vs. fOUT, 3.3 V 90 98 84 92 78 86 -40C +25C +85C 72 SFDR (dBc) SFDR (dBc) 10 07466-158 0 07466-155 40 07466-159 60 66 60 -40C +25C +85C 80 74 68 54 62 42 0 5 10 15 20 25 30 35 fOUT (MHz) 40 45 50 55 60 07466-156 48 Figure 56. AD9117 SFDR at Three Temperatures 8 mA vs. fOUT, 1.8 V 56 0 5 10 15 20 25 30 35 fOUT (MHz) 40 45 50 55 Figure 59. AD9117 SFDR at Three Temperatures 8 mA vs. fOUT, 3.3 V Rev. D | Page 26 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 98 98 90 90 82 SFDR (dBc) 74 66 74 66 58 -3dB 50 -3dB 58 5 10 15 20 25 30 35 40 45 50 55 60 50 fOUT (MHz) 0 5 10 96 90 90 84 84 8mA SFDR (dBc) 8mA 54 54 48 48 10 20 30 40 50 40 45 50 55 60 20mA 66 60 0 35 72 60 42 30 4mA 78 07466-161 SFDR (dBc) 78 66 25 Figure 63. AD9117 SFDR at Three Digital Signal Levels vs. fOUT., 3.3 V 96 72 20 fOUT (MHz) Figure 60. AD9117 SFDR at Three Digital Signal Levels vs. fOUT, 1.8 V 4mA 15 42 60 0 fOUT (MHz) 10 20 30 40 50 60 fOUT (MHz) AC COUPLED: UNSPECIFIED BELOW 20MHz AC COUPLED: UNSPECIFIED BELOW 20MHz 10dB/DIV Figure 64. AD9117 SFDR at Three Currents vs. fOUT, 3.3V 10dB/DIV Figure 61. AD9117 SFDR at Two Currents vs. fOUT, 1.8 V INPUT ATT 8.00dB INPUT ATT 8.00dB STEP 2dB STEP 2dB CENTER 22.90MHz RES BW 30kHz VBW 300kHz SPAN 38.84MHz CENTER 22.90MHz SWEEP 126ms (601pts) RES BW 30kHz TOTAL CARRIER POWER -12.17dBm/7.87420MHz REF CARRIER POWER -12.17dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 SPAN 38.84MHz SWEEP 126ms (601pts) TOTAL CARRIER POWER -12.17dBm/7.87420MHz REF CARRIER POWER -12.17dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER UPPER dBc dBm dBc FREQ BW 1. -12.17dBm 5.000MHz 3.840MHz -77.40 -89.56 -78.68 -90.84 2. -80.85dBm 10.00MHz 3.840MHz -78.90 -91.06 -78.27 -90.43 15.00MHz 3.840MHz -78.02 -90.18 -70.99 -83.15 07466-162 OFFSET INTEG LOWER UPPER dBc dBm dBc dBm FREQ BW 1. -12.17dBm 5.000MHz 3.840MHz -77.40 -89.56 -78.68 -90.84 2. -80.85dBm 10.00MHz 3.840MHz -78.90 -91.06 -78.27 -90.43 15.00MHz 3.840MHz -78.02 -90.18 -70.99 -83.15 VBW 300kHz Figure 62. AD9117 ACLR One-Carrier, 1.8 V Figure 65. AD9117 ACLR One-Carrier, 3.3 V Rev. D | Page 27 of 52 07466-164 0 07466-095 0dB 0dB 07466-094 42 -6dB -6dB 07466-165 SFDR (dBc) 82 AD9114/AD9115/AD9116/AD9117 Data Sheet -60 -60 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL -66 ACLR (dBc) ACLR (dBc) -66 -72 15 20 25 30 35 40 45 fOUT (MHz) -78 15 20 25 30 35 40 45 fOUT (MHz) Figure 66. AD9117 One-Carrier W-CDMA First ACLR vs. fOUT, 1.8 V 07466-169 -78 07466-166 -72 Figure 69. AD9117 One-Carrier W-CDMA First ACLR vs. fOUT, 3.3 V -62 -62 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL -68 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL ACLR (dBc) ACLR (dBc) -68 -74 15 20 25 30 35 40 45 fOUT (MHz) -80 07466-167 -80 15 25 35 45 fOUT (MHz) 07466-170 -74 Figure 70. AD9117 One-Carrier W-CDMA Second ACLR vs. fOUT, 3.3 V Figure 67. AD9117 One-Carrier W-CDMA Second ACLR vs. fOUT, 1.8 V -62 -62 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL -68 ACLR (dBc) ACLR (dBc) -68 20 25 30 35 fOUT (MHz) 40 45 07466-168 -80 -80 20 25 30 35 40 45 fOUT (MHz) Figure 71. AD9117 One-Carrier W-CDMA Third ACLR vs. fOUT, 3.3 V Figure 68. AD9117 One-Carrier W-CDMA Third ACLR vs. fOUT, 1.8 V Rev. D | Page 28 of 52 07466-171 -74 -74 Data Sheet AD9114/AD9115/AD9116/AD9117 AC COUPLED: UNSPECIFIED BELOW 20MHz 10dB/DIV INPUT ATT 8.00dB INPUT ATT 8.00dB STEP 2dB STEP 2dB CENTER 22.90MHz SPAN 38.84MHz VBW 300kHz RES BW 30kHz CENTER 22.90MHz SWEEP 126ms (601pts) TOTAL CARRIER POWER -15.23dBm/7.87420MHz REF CARRIER POWER -18.09dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 07466-172 OFFSET INTEG LOWER UPPER dBc dBm dBc dBm FREQ BW 1. -18.09dBm 5.000MHz 3.840MHz -72.11 -90.24 -71.97 -90.09 2. -18.40dBm 10.00MHz 3.840MHz -72.98 -91.10 -72.55 -90.68 15.00MHz 3.840MHz -69.93 -88.05 -72.30 -90.42 Figure 72. AD9117 ACLR Two-Carrier, 1.8 V Figure 75. AD9117 ACLR Two-Carrier, 3.3 V -50 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL -50 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL -56 ACLR (dBc) ACLR (dBc) SWEEP 126ms (601pts) TOTAL CARRIER POWER -15.23dBm/7.87420MHz REF CARRIER POWER -18.09dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER UPPER dBc dBm dBc dBm FREQ BW 1. -18.09dBm 5.000MHz 3.840MHz -72.11 -90.24 -71.97 -90.09 2. -18.40dBm 10.00MHz 3.840MHz -72.98 -91.10 -72.55 -90.68 15.00MHz 3.840MHz -69.93 -88.05 -72.30 -90.42 -56 SPAN 38.84MHz VBW 300kHz RES BW 30kHz 07466-175 10dB/DIV AC COUPLED: UNSPECIFIED BELOW 20MHz -62 -62 -68 -74 15 20 25 30 fOUT (MHz) 35 40 30 35 40 Figure 76. AD9117 Two-Carrier W-CDMA First ACLR vs. fOUT, 3.3 V -50 -50 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL -56 ACLR (dBc) -62 -68 -74 15 20 25 30 fOUT (MHz) 35 40 07466-174 -68 -62 Figure 74. AD9117 Two-Carrier W-CDMA Second ACLR vs. fOUT, 1.8 V -74 15 20 25 30 fOUT (MHz) 35 40 07466-177 ACLR (dBc) 25 fOUT (MHz) Figure 73. AD9117 Two-Carrier W-CDMA First ACLR vs. fOUT, 1.8 V -56 20 07466-173 15 -74 07466-176 -68 Figure 77. AD9117 Two-Carrier W-CDMA Second ACLR vs. fOUT, 3.3 V Rev. D | Page 29 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet -50 -50 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL -56 ACLR (dBc) -62 -62 -68 -68 25 30 fOUT (MHz) 35 40 -74 20 1.0 0.3 0.8 0.1 AUXDAC INL (LSB) 0 -0.1 -0.2 -0.3 0.4 0.2 0 -0.2 -0.4 -0.6 -0.4 -0.8 128 256 384 512 CODE 640 768 896 1024 -1.0 07466-047 0 Figure 79. AD9114/AD9115/AD9116/AD9117 AUXDAC DNL 0 128 256 384 512 CODE 640 768 896 1024 07466-044 AUXDAC DNL (LSB) 40 0.6 0.2 Figure 82. AD9114/AD9115/AD9116/AD9117 AUXDAC INL 40 80 70 TOTAL CURRENT @ 8mA OUT 30 TOTAL CURRENT @ 4mA OUT 20 TOTAL CURRENT @ 20mA OUT 60 AVDD @ 8mA OUT CURRENT (mA) SUPPLY CURRENT (mA) 35 Figure 81. AD9117 Two-Carrier W-CDMA Third ACLR vs. fOUT, 3.3 V 0.4 AVDD @ 4mA OUT 10 AVDD @ 20mA OUT 50 40 TOTAL CURRENT @ 8mA OUT 30 AVDD @ 8mA OUT TOTAL CURRENT @ 4mA OUT 20 DVDD AVDD @ 4mA OUT 10 DVDD CVDD 0 20 40 60 80 fDAC (MHz) 100 120 140 CVDD 0 07466-048 0 30 fOUT (MHz) Figure 78. AD9117 Two-Carrier W-CDMA Third ACLR vs. fOUT, 1.8 V -0.5 25 07466-181 20 07466-178 -74 0 20 40 60 80 fDAC (MHz) Figure 80. AD9114/AD9115/AD9116/AD9117 Supply Current vs. fDAC, 1.8 V 100 120 140 07466-183 ACLR (dBc) -56 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL Figure 83. AD9114/AD9115/AD9116/AD9117Supply Current vs. fDAC, 3.3 V Rev. D | Page 30 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTP, the 0 mA output is expected when the inputs are all 0. For IOUTN, the 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and the ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient value (25C) to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range per degree Celsius (ppm FSR/C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/C). Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage (%) or in decibels (dB). Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB). Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. D | Page 31 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet CMLI FSADJI/AUXI FSADJQ/AUXQ REFIO RESET/PINMD SCLK/CLKMD SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 THEORY OF OPERATION AD9117 1V SPI INTERFACE DB11 IRSET 2k QRSET 2k DB10 10k DB9 IREF 100A DB8 IOUTN IOUTP 62.5 RLIP AUX1DAC AVDD 1 INTO 2 INTERLEAVED DATA INTERFACE DVSS RLIN 62.5 I DAC BAND GAP DVDDIO IRCM 60 TO 260 AVSS AUX2DAC I DATA RLQP 62.5 1.8V LDO Q DATA QOUTP Q DAC QOUTN DB7 62.5 CVSS CVDD CLKIN DCLKIO (LSB) DB0 DB1 DB2 DB3 DB4 DB5 RLQN QRCM 60 TO 260 CMLQ CLOCK DIST DB6 07466-050 DVDD Figure 84. Simplified Block Diagram Figure 84 shows a simplified block diagram of the AD9114/ AD9115/AD9116/AD9117 that consists of two DACs, digital control logic, and a full-scale output current control. Each DAC contains a PMOS current source array capable of providing a maximum of 20 mA. The arrays are divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an MSB current source. The remaining LSBs are binary weighted fractions of the current sources of the middle bits. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the main DACs (that is, >200 M). The current sources are switched to one or the other of the two output nodes (IOUTP or IOUTN) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD976x family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital I/O sections of the AD9114/AD9115/ AD9116/AD9117 have separate power supply inputs (AVDD and DVDDIO) that can operate independently over a 1.8 V to 3.3 V range. The core digital section requires 1.8 V. An optional on-chip LDO is provided for DVDDIO supplies greater than 1.8 V, or the 1.8 V can be supplied directly through DVDD. A 1.0 F bypass capacitor at DVDD (Pin 7) is required when using the LDO. The core is capable of operating at a rate of up to 125 MSPS. It consists of edge-triggered latches and the segment decoding logic circuitry. The analog section includes PMOS current sources, associated differential switches, a 1.0 V band gap voltage reference, and a reference control amplifier. Each DAC full-scale output current is regulated by the reference control amplifier and can be set from 4 mA to 20 mA via an external resistor, xRSET, connected to its full-scale adjust pin (FSADJx). The external resistor, in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IxREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IxOUTFS, is 32 x IxREF. Optional on-chip xRSET resistors are provided that can be programmed between a nominal value of 1.6 k to 8 k (20 mA to 4 mA IxOUTFS, respectively). The AD9114/AD9115/AD9116/AD9117 provide the option of setting the output common mode to a value other than AGND via the output common-mode pin (CMLI and CMLQ). This facilitates directly interfacing the output of the AD9114/AD9115/AD9116/ AD9117 to components that require common-mode levels greater than 0 V. Rev. D | Page 32 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 SERIAL PERIPHERAL INTERFACE (SPI) The serial port of the AD9114/AD9115/AD9116/AD9117 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel(R) SSR protocols. The interface allows read/write access to all registers that configure the AD9114/AD9115/AD9116/AD9117. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial interface port of the AD9114/ AD9115/AD9116/AD9117 is configured as a single I/O pin on the SDIO pin. GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle on the AD9114/ AD9115/AD9116/AD9117. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9114/AD9115/ AD9116/AD9117, coinciding with the first eight SCLK rising edges. In Phase 2, the instruction byte provides the serial port controller of the AD9114/AD9115/AD9116/AD9117 with information regarding the data transfer cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9114/AD9115/AD9116/AD9117. A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9114/ AD9115/AD9116/AD9117 and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. Using a multibyte transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. INSTRUCTION BYTE N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 12. Table 12. Byte Transfer Count N1 0 0 1 1 SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK--Serial Clock The serial clock pin is used to synchronize data to and from the AD9114/AD9115/AD9116/AD9117 and to run the internal state machines. The SCLK maximum frequency is 25 MHz. All data input to the AD9114/AD9115/AD9116/AD9117 is registered on the rising edge of SCLK. This is shown in Figure 85 and Figure 87 for write instructions where the SCLK rising edges are lined up in the middle of the data. All data is driven out of the AD9114/AD9115/ AD9116/AD9117 on the falling edge of SCLK. This is shown in Figure 86 and Figure 88 for read cycles where the SCLK falling edges line up in the middle of the data in the data transfer cycle. CS--Chip Select An active low input starts and gates a communications cycle. It allows more than one device to be used on the same serial communications lines. The SDIO/FORMAT pin reaches a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO--Serial Data I/O The SDIO pin is used as a bidirectional data line to transmit and receive data. Table 11. DB6 N1 DB5 N0 DB4 A4 DB3 A3 DB2 A2 DB1 A1 Description Transfer 1 byte Transfer 2 bytes Transfer 3 bytes Transfer 4 bytes A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The following register addresses are generated internally by the AD9114/AD9115/AD9116/AD9117 based on the LSBFIRST bit (Register 0x00, Bit 6). The instruction byte contains the information shown in Table 11. MSB DB7 R/W N0 0 1 0 1 LSB DB0 A0 R/W (Bit 7 of the instruction byte) determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. Rev. D | Page 33 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet MSB/LSB TRANSFERS INSTRUCTION CYCLE When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. If the MSB first mode is active, the serial port controller data address of the AD9114/AD9115/AD9116/AD9117 decrements from the data address written toward 0x00 for multibyte I/O operations. If the LSB first mode is active, the serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations. SERIAL PORT OPERATION The serial port configuration of the AD9114/AD9115/AD9116/ AD9117 is controlled by Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communications cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communications cycle. The same considerations apply to setting the software reset bit (Register 0x00, Bit 5). All registers are set to their default values except Register 0x00, which remains unchanged. Use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior. INSTRUCTION CYCLE INSTRUCTION CYCLE SDIO D30 D20 D10 D00 DATA TRANSFER CYCLE A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N Figure 87. Serial Register Interface Timing, LSB First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N Figure 88. Serial Register Interface Timing, LSB First Read PIN MODE The AD9114/AD9115/AD9116/AD9117 can also be operated without ever writing to the serial port. With RESET/PINMD (Pin 35) tied high, the SCLK pin becomes CLKMD to provide for clock mode control (see the Retimer section), the SDIO pin becomes FORMAT and selects the input data format, and the CS/PWRDN pin serves to power down the device. The pins are not latched at power up. If you change the format, it should change with about a 1s delay. Operation is otherwise exactly as defined by the default register values in Table 13; therefore, external resistors at FSADJI and FSADJQ are needed to set the DAC currents, and both DACs are active. This is also a convenient quick checkout mode. DAC currents can be externally adjusted in pin mode by sourcing or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ pins, as desired, with the fixed resistors installed. An op amp output with appropriate series resistance is one of many possibilities. This has the same effect as changing the resistor value. Place at least 10 k resistors in series right at the DAC to guard against accidental short circuits and noise modulation. The REFIO pin can be adjusted 25% in a similar manner, if desired. DATA TRANSFER CYCLE A1 A0 D7N D6N D5N D30 D20 D10 D00 SCLK 07466-291 A2 A1 A0 D7N D6N D5N CS SCLK R/W N1 N0 A4 A3 A2 Figure 86. Serial Register Interface Timing, MSB First Read CS SDIO R/W N1 N0 A4 A3 07466-386 SDIO 07466-289 When LSBFIRST = 0 (MSB first), the instruction and data bytes must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from a high address to a low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle. SCLK 07466-388 The serial port of the AD9114/AD9115/AD9116/AD9117 can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0). DATA TRANSFER CYCLE CS Figure 85. Serial Register Interface Timing, MSB First Write Rev. D | Page 34 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 SPI REGISTER MAP Table 13. Name SPI Control Power-Down Data Control I DAC Gain IRSET IRCML Q DAC Gain QRSET QRCML AUXDAC Q AUX CTLQ AUXDAC I AUX CTLI Reference Resistor Cal Control Cal Memory Memory Address Memory Data Memory R/W CLKMODE Version Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x14 0x1F Default 0x00 0x40 0x34 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x34 0x00 0x00 0x0A Bit 7 Bit 6 Reserved LSBFIRST LDOOFF LDOSTAT TWOS Reserved Reserved IRSETEN Reserved IRCMLEN Reserved Reserved QRSETEN Reserved QRCMLEN Reserved Bit 5 Reset PWRDN IFIRST Bit 4 LNGINS Q DACOFF IRISING Bit 1 Bit 0 Reserved I DACOFF QCLKOFF ICLKOFF EXTREF SIMULBIT DCI_EN DCOSGL DCODBL I DACGAIN[5:0] IRSET[5:0] IRCML[5:0] Q DACGAIN[5:0] QRSET[5:0] QRCML[5:0] QAUXDAC[7:0] QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] IAUXDAC[7:0] IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] Reserved RREF[5:0] PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] CALSTATQ CALSTATI Reserved CALMEMQ[1:0] CALMEMI[1:0] Reserved MEMADDR[5:0] Reserved MEMDATA[5:0] CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Version[7:0] Rev. D | Page 35 of 52 Bit 3 Bit 2 AD9114/AD9115/AD9116/AD9117 Data Sheet SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register SPI Control Power Down Data Control I DAC Gain Address 0x00 0x01 0x02 0x03 Bit 6 Name LSBFIRST 5 Reset 4 LNGINS 7 LDOOFF 6 LDOSTAT 5 PWRDN 4 Q DACOFF 3 I DACOFF 2 QCLKOFF 1 ICLKOFF 0 EXTREF 7 TWOS 5 IFIRST 4 IRISING 3 SIMULBIT 2 DCI_EN 1 DCOSGL 0 DCODBL 5:0 I DACGAIN[5:0] Description 0 (default): MSB first per SPI standard. 1: LSB first per SPI standard. Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors. Executes software reset of SPI and controllers, reloads default register values, except Register 0x00. 1: set software reset; write 0 on the next (or any following) cycle to release reset. 0 (default): the SPI instruction word uses a 5-bit address. 1: the SPI instruction word uses a 13-bit address. 0 (default): LDO voltage regulator on. 1: turns core LDO voltage regulator off. 0: indicates that the core LDO voltage regulator is off. 1 (default): indicates that the core LDO voltage regulator is on. 0 (default): all analog, digital circuitry and SPI logic are powered on. 1: powers down all analog and digital circuitry, except for SPI logic. 0 (default): turns on Q DAC output current. 1: turns off Q DAC output current. 0 (default): turns on I DAC output current. 1: turns off I DAC output current. 0 (default): turns on Q DAC clock. 1: turns off Q DAC clock. 0 (default): turns on I DAC clock. 1: turns off I DAC clock. 0 (default): turns on internal voltage reference. 1: powers down the internal voltage reference (external reference required). 0 (default): Unsigned binary input data format. 1: twos complement input data format. 0: pairing of data--Q first of pair on data input pads. 1(default): pairing of data--I first of pair on data input pads (default). 0: Q data latched on DCLKIO rising edge. 1(default): I data latched on DCLKIO rising edge (default). 0 (default): allows simultaneous input and output enable on DCLKIO. 1: disallows simultaneous input and output enable on DCLKIO. Controls the use of the DCLKIO pad for the data clock input. 0: data clock input disabled. 1(default): data clock input enabled. Controls the use of the DCLKIO pad for the data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. Controls the use of the DCLKIO pad for the data clock output. 0 (default): DCODBL data clock output disabled. 1: DCODBL data clock output enabled; paralleled with DCOSGL for 2x drive current. DAC I fine gain adjustment; alters the full-scale current, as shown in Figure 99. Default IDACGAIN = 0x00. Rev. D | Page 36 of 52 Data Sheet Register IRSET IRCML AD9114/AD9115/AD9116/AD9117 Address 0x04 0x05 Bit 7 Name IRSETEN 5:0 IRSET[5:0] 7 IRCMLEN 5:0 IRCML[5:0] Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] QRSET 0x07 7 QRSETEN 5:0 QRSET[5:0] 7 QRCMLEN 5:0 QRCML[5:0] QRCML 0x08 AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUX CTLQ 0x0A 7 QAUXEN 6:5 QAUXRNG[1:0] 4:2 QAUXOFS[2:0] 1:0 QAUXDAC[9:8] Description 0 (default): IRSET resistor value for I channel is set by an external resistor connected to the FADJI/AUXI pin. Nominal value for this external resistor is 4 k. 1: enables the on-chip IRSET value to be changed for I channel. Changes the value of the on-chip IRSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps twos complement (nonlinear), see Figure 98. 000000 (default): IRSET = 2 k. 011111: IRSET = 8 k. 100000: IRSET = 1.6 k. 111111: IRSET = 2 k. 0 (default): IRCML resistor value for the I channel is set by an external resistor connected to CMLI pin. Recommended value for this external resistor is 0 . 1: enables on-chip IRCML adjustment for I channel. Changes the value of the on-chip IRCML resistor for I channel; this adjusts the common-mode level of the DAC output stage. 000000 (default): IRCML = 60 . 100000: IRCML = 160 . 111111: IRCML = 260 . DAC Q fine gain adjustment; alters the full-scale current, as shown in Figure 99. Default QDACGAIN = 0x00. 0 (default): QRSET resistor value for Q channel is set by an external resistor connected to FADJI/AUXI pin. Nominal value for this external resistor is 4 k. 1: enables on-chip QRSET adjustment for Q channel. Changes the value of the on-chip QRSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps twos complement (nonlinear). 000000 (default): QRSET = 2 k. 011111: QRSET = 8 k. 100000: QRSET = 1.6 k. 111111: QRSET = 2 k. 0 (default): QRCML resistor value for the Q channel is set by an external resistor connected to CMLQ pin. Recommended value for this external resistor is 0 . 1: enables on-chip QRCML adjustment. Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the common-mode level of the DAC output stage. 000000 (default): QRCML = 60 . 100000: QRCML = 160 . 111111: QRCML = 260 . AUXDAC Q output voltage adjustment word LSBs. 0x3FF: sets AUXDAC Q output to full scale. 0x200: sets AUXDAC Q output to midscale. 0x000 (default): sets AUXDAC Q output to bottom of scale. 0 (default): AUXDAC Q output disabled. 1: enables AUXDAC Q output. 00 (default): sets AUXDAC Q output voltage range to 2 V. 01: sets AUXDAC Q output voltage range to 1.5 V. 10: sets AUXDAC Q output voltage range to 1.0 V. 11: sets AUXDAC Q output voltage range to 0.5 V. 000 (default): sets AUXDAC Q top of range to 1.0 V. 001: sets AUXDAC Q top of range to 1.5 V. 010: sets AUXDAC Q top of range to 2.0 V. 011: sets AUXDAC Q top of range to 2.5 V. 100: sets AUXDAC Q top of range to 2.9 V. AUXDAC Q output voltage adjustment word MSBs (default = 00). Rev. D | Page 37 of 52 AD9114/AD9115/AD9116/AD9117 Register AUXDAC I Address 0x0B Bit 7:0 Name IAUXDAC[7:0] AUX CTLI 0x0C 7 IAUXEN 6:5 IAUXRNG[1:0] 4:2 IAUXOFS[2:0] Reference Resistor 0x0D 1:0 5:0 IAUXDAC[9:8] RREF[5:0] Cal Control 0x0E 7 PRELDQ 6 PRELDI 5 CALSELQ 4 CALSELI 3 CALCLK 2:0 DIVSEL[2:0] 7 CALSTATQ 6 CALSTATI 3:2 CALMEMQ[1:0] 1:0 CALMEMI[1:0] 5:0 5:0 MEMADDR[5:0] MEMDATA[5:0] Cal Memory Memory Address Memory Data 0x0F 0x10 0x11 Data Sheet Description AUXDAC I output voltage adjustment word LSBs. 0x3FF: sets AUXDAC I output to full scale. 0x200: sets AUXDAC I output to midscale. 0x000 (default): sets AUXDAC I output to bottom of scale. 0 (default): AUXDAC I output disabled. 1: enables AUXDAC I output. 00 (default): sets AUXDAC I output voltage range to 2 V. 01: sets AUXDAC I output voltage range to 1.5 V. 10: sets AUXDAC I output voltage range to 1.0 V. 11: sets AUXDAC I output voltage range to 0.5 V. 000 (default): sets AUXDAC I top of range to 1.0 V. 001: sets AUXDAC I top of range to 1.5 V. 010: sets AUXDAC I top of range to 2.0 V. 011: sets AUXDAC I top of range to 2.5 V. 100: sets AUXDAC I top of range to 2.9 V. AUX DAC I output voltage adjustment word MSBs (default = 00). Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 97) twos complement. 000000 (default): sets the value of RREF to 10 k, VREF = 1.0 V. 011111: sets the value of RREF to 12 k, VREF = 1.2 V. 100000: sets the value of RREF to 8 k, VREF = 0.8 V. 111111: sets the value of RREF to 10 k, VREF = 1.0 V. 0 (default): preloads Q DAC calibration reference set to 32. 1: preloads Q DAC calibration reference set by user (Cal Address 1). 0 (default): preloads I DAC calibration reference set to 32. 1: preloads I DAC calibration reference set by user (Cal Address 1). 0 (default): Q DAC self-calibration done. 1: selects Q DAC self-calibration. 0 (default): I DAC self-calibration done. 1: selects I DAC self-calibration. 0 (default): calibration clock disabled. 1: calibrates clock enabled. Calibration clock divide ratio from DAC clock rate. 000 (default): divide by 256. 001: divide by 128. ... 110: divide by 4. 111: divide by 2. 0 (default): Q DAC calibration in progress. 1: calibration of Q DAC complete. 0 (default): I DAC calibration in progress. 1: calibration of I DAC complete. Status of Q DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. Status of I DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. Address of static memory to be accessed. Data for static memory access. Rev. D | Page 38 of 52 Data Sheet Register Memory R/W CLKMODE Version AD9114/AD9115/AD9116/AD9117 Address 0x12 0x14 0x1F Bit 7 Name CALRSTQ 6 CALRSTI 4 CALEN 3 SMEMWR 2 SMEMRD 1 UNCALQ 0 UNCALI 7:6 CLKMODEQ[1:0] 4 Searching 3 2 Reacquire CLKMODEN 1:0 CLKMODEI[1:0] 7:0 Version[7:0] Description 0 (default): no action. 1: clears CALSTATQ. 0 (default): no action. 1: clears CALSTATI. 0 (default): no action. 1: initiates device self-calibration. 0 (default): no action. 1: writes to static memory (calibration coefficients). 0 (default): no action. 1: reads from static memory (calibration coefficients). 0 (default): no action. 1: resets Q DAC calibration coefficients to default (uncalibrated). 0 (default): no action. 1: resets I DAC calibration coefficients to default (uncalibrated). Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retime. If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if needed to better synchronize the DACs (see the Retimer section). Datapath retimer status bit. 0 (default): clock relationship established. 1: indicates that the internal datapath retimer is searching for clock relationship (device output is not usable while this bit is high). Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship. 0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read back in CLKMODEI[1:0] and CLKMODEQ[1:0]. 1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers. Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if needed to better synchronize the DACs (see the Retimer section). Hardware version of the device. This register is set to 0x0A for the latest version of the device. Rev. D | Page 39 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet DIGITAL INTERFACE OPERATION Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format. The maximum guaranteed data rate is 250 MSPS with a 125 MHz clock. The order of data pairing and the sampling edge selection is user programmable using the IFIRST and IRISING data control bits, resulting in four possible timing diagrams. These timing diagrams are shown in Figure 89, Figure 90, Figure 91, and Figure 92. DCLKIO B C D E Z B Q DATA A C F G H D F E G NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117. Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0 B C D Z B Q DATA Y A E F G DCLKIO H D F C E DB[n:0] NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117. Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0 Z A B C D E I DATA Y A Q DATA Z B F G H C E D F 07466-054 A 07466-051 Z I DATA NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117. Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1 DCLKIO A B C D I DATA Y A Q DATA X Z E F G C B H E D DCLKIO NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117. tS tH Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1 tS tH DB[n:0] 07466-055 Z Ideally, the rising and falling edges of the clock fall in the center of the keep-in window formed by the setup and hold times, tS and tH. Refer to Table 2 for setup and hold times. A detailed timing diagram is shown in Figure 93. 07466-052 DB[n:0] A I DATA DCLKIO DB[n:0] Z 07466-053 DB[n:0] NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117. Figure 93. Setup and Hold Times for All Input Modes In addition to the different timing modes listed in Table 2, the input data can also be presented to the device in either unsigned binary or twos complement format. The format type is chosen via the TWOS data control bit. Rev. D | Page 40 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 OR DB[n:0] (INPUT) RETIMER-CLK D-FF D-FF D-FF D-FF D-FF 0 1 2 3 4 D-FF TO DAC CORE IOUT CLKIN-INT IOUT NOTES D-FFs: 0: RISING OR FALLING EDGE TRIGGERED FOR I OR Q DATA. 1, 2, 3, 4: RISING EDGE TRIGGERED. DELAY1 DELAY1 RETIMER-CLK DCLKIO-INT 5 IE IE OE DCLKIO (INPUT/OUTPUT) 07466-056 DELAY2 CLKIN (INPUT) Figure 94. Simplified Diagram of AD9114/AD9115/AD9116/AD9117 Timing The AD9114/AD9115/AD9116/AD9117 have two clock inputs, DCLKIO and CLKIN. The CLKIN is the analog clock whose jitter affects DAC performance, and the DCLKIO is a digital clock from an FPGA that needs to have a fixed relationship with the input data to ensure that the data is sampled correctly by the flip-flops on the pads. Figure 94 is a simplified diagram of the entire data capture system in the AD9114/AD9115/AD9116/AD9117. The double data rate input data (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) is latched at the pads/pins either on the rising edge or the falling edge of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines which channel data is latched first (that is, I or Q). The captured data is then retimed to the internal clock (CLKIN-INT) in the retimer block before being sent to the final analog DAC core (D-FF 4), which controls the current steering output switches. All delay blocks depicted in Figure 94 are non-inverting, and any wires without an explicit delay block can be assumed to have no delay. Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL, to logic high allows the user to get a DCLKIO output from the CLKIN input for use in the user's PCB system. It is strongly recommended that DCI_EN = DCOSGL = high, or DCI_EN = DCODBL = high not be used, even though the device may appear to function correctly. Similarly, DCOSGL and DCODBL should not be set to logic high simultaneously. Retimer The AD9114/AD9115/AD9116/AD9117 have an internal data retimer circuit that compares the CLKIN-INT and DCLKIO-INT clocks and, depending on their phase relationship, selects a retimer clock (RETIMER-CLK) to safely transfer data from the DCLKIO used at the chip's input interface to the CLKIN used to clock the analog DAC cores (D-FF 4). The retimer selects one of the three phases shown in Figure 95. The retimer is controlled by the CLKMODE SPI bits as is shown in Table 15. 1/2 PERIOD DATA CLOCK 180 90 Only one channel is shown in Figure 94 with the data pads (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) serving as double data rate pads for both channels. The default PINMD and SPI settings are IE = high (closed) and OE = low (open). These settings are enabled when RESET/PINMD (Pin 35) is held high. In this mode, the user has to supply both DCLKIO and CLKIN. In PINMD, it is also recommended that the DCLKIO and the CLKIN be in phase for proper functioning of the DAC, which can easily be ensured by tying the pins together on the PCB. If the user can access the SPI, setting Bit 2 of SPI Address 0x02, DCI_EN, to logic low causes the CLKIN to be used as the DCLKIO also. RETIMER-CLKs 270 1/4 PERIOD 1/2 PERIOD 07466-057 DIGITAL DATA LATCHING AND RETIMER SECTION Figure 95. RETIMER-CLK Phases Note that, in most cases, more than one retimer phase works and, in such cases, the retimer arbitrarily picks one phase that works. The retimer cannot pick the best or safest phase. If the user has a working knowledge of the exact phase relationship between DCLKIO and CLKIN (and thus DCLKIO-INT and CLKIN-INT because the delay is approximately the same for both clocks and equal to DELAY1), then the retimer can be forced to this phase with CLKMODEN = 1, as described in Table 15 and the following paragraphs. Rev. D | Page 41 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet Table 15. Timer Register List Bit Name CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Description Q datapath retimer clock selected output. Valid after the searching bit goes low. High indicates that the internal datapath retimer is searching for the clock relationship (DAC is not usable until it is low again). Changing this bit from 0 to 1 causes the datapath retimer circuit to reacquire the clock relationship. 0: Uses the CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: Uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both the I and Q retimers (that is, force the retimer). I datapath retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both I and Q automatic retimer values. Table 16. CLKMODEI/CLKMODEQ Details CLKMODEI[1:0]/CLKMODEQ[1:0] 00 01 10 11 DCLKIO-to-CLKIN Phase Relationship 0 to 90 90 to 180 180 to 270 270 to 360 When RESET is pulsed high and then returns low (the part is in SPI mode), the retimer runs and automatically selects a suitable clock phase for the RETIMER-CLK within 128 clock cycles. The SPI searching bit, Bit 4 of SPI Address 0x14, returns to low, indicating that the retimer has locked and the part is ready for use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to reinitiate phase detection in the I and Q retimers at any time. CLKMODEQ[1:0] and CLKMODEI[1:0] bits of SPI Address 0x14 provide readback for the values picked by the internal phase detectors in the retimer (see Table 16). To force the two retimers (I and Q) to pick a particular phase for the retimer clock (they must both be forced to the same value), CLKMODEN, Bit 2 of the SPI Address 0x14, should be set high and the required phase value is written into CLKMODEI[1:0]. For example, if the DCLKIO and the CLKIN are in phase to first order, the user could safely force the retimers to pick Phase 2 for the RETIMER-CLK. This forcing function may be useful for synchronizing multiple devices. In pin mode, it is expected that the user tie CLKIN and DCLKIO together. The device has a small amount of programmable functionality using the now unused SPI pins (SCLK, SDIO, and CS). If the two chip clocks are tied together, the SCLK pin can be tied to ground, and the chip uses a clock for the retimer that is 180 out of phase with the two input clocks (that is, Phase 2, which is the safest and best option). The chip has an additional option in pin mode when the redefined SCLK pin is high. Use this mode if using pin mode, but CLKIN and DCLKIO are not tied together (that is, not in phase). Holding SCLK high causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (that is, select a suitable RETIMER-CLK phase). The action of taking SCLK high causes the internal phase detector to reexamine the two clocks and determine the relative phase. Whenever the user wants to reevaluate the relative phase of the two clocks, the SCLK pin can be taken low and then high again. RETIMER-CLK Selected Phase 2 Phase 3 Phase 3 Phase 1 ESTIMATING THE OVERALL DAC PIPELINE DELAY DAC pipeline latency is affected by the phase of the RETIMERCLK that is selected. If latency is critical to the system and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time. Consider the case in which DCLKIO = CLKIN (that is, in phase), and the RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, I data is latched on the rising edge and Q data is latched on the falling edge). Then the latency to the output for the I channel is four clock cycles total; one clock cycle from the input interface (D-FF 1, not D-FF0 as it latches data on either edge and does not cause any delay), two clock cycles from the retimer (D-FF 2 and D-FF 4, but not D-FF 3 because it is latched on the half clock cycle or 180), and one clock cycle going through the analog core (D-FF 5). The latency to the output for the Q channel from the time the falling edge latches it at the pads in D-FF 0 is 3.5 clock cycles (no delay due to D-FF0, 1 clock cycle due to D-FF 1, 1/2 clock cycle to D-FF 2, 1 clock cycle to D-FF 4, and 1 clock cycle to D-FF 5). This latency for the AD9714/ AD9715/AD9716/AD9717 is case specific and needs to be calculated based on the RETIMER-CLK phase that is automatically selected or manually forced. Rev. D | Page 42 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9114/AD9115/AD9116/AD9117 contains an internal 1.0 V band gap reference. The internal reference can be disabled by setting Bit 0 (EXTREF) of the power-down register (Address 0x01) through the SPI interface. To use the internal reference, decouple the REFIO pin to AVSS with a 0.1 F capacitor, enable the internal reference, and clear Bit 0 of the power-down register (Address 0x01) through the SPI interface. Note that this is the default configuration. The internal reference voltage is present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA must be used to avoid loading the reference. An example of the use of the internal reference is shown in Figure 96. The AD9114/AD9115/AD9116/AD9117 contains a control amplifier that regulates the full-scale output current, IxOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 96. The output current, IxREF, is determined by the ratio of the VREFIO and an external resistor, xRSET, as stated in Equation 4 (see the DAC Transfer Function section). IxREF is mirrored to the segmented current sources with the proper scale factor to set IxOUTFS, as stated in Equation 3 (see the DAC Transfer Function section). AD9114/AD9115/ AD9116/AD9117 VBG 1.0V REFIO - + xRSET CURRENT SCALING x32 IxOUTFS 07466-218 FSADJx 0.1F I DAC OR Q DAC IxREF AVSS Figure 96. Internal Reference Configuration REFIO serves as either an input or an output, depending on whether the internal or an external reference is used. Table 17 summarizes the reference operation. Table 17. Reference Operation Reference Mode Internal External REFIO Pin Connect 0.1 F capacitor Apply external reference Register Setting Register 0x01, Bit 0 = 0 (default) Register 0x01, Bit 0 = 1 (for power saving) An external reference can be used in applications requiring tighter gain tolerances or lower temperature drift. In addition, a variable external voltage reference can be used to implement a method for gain control of the DAC output. The control amplifier allows a 10:1 adjustment span of IxOUTFS from 2 mA to 20 mA by setting IxREF between 62.5 A and 625 A (xRSET between 1.6 k and 16 k). When using a resistor larger than 4 k, split the resistor with 4 k plus the additional resistance needed, for example, 16 k made of a 4 k + 12 k combination, and add a 1 F capacitor from 4 k to ground. The wide adjustment span of IxOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9114/AD9115/AD9116/AD9117, which is proportional to IxOUTFS (see the DAC Transfer Function section). The second benefit relates to the ability to adjust the output over a 8 dB range with 0.25 dB steps, which is useful for controlling the transmitted power. The small signal bandwidth of the reference control amplifier is approximately 500 kHz. This allows the device to be used for low frequency, small signal multiplying applications. DAC TRANSFER FUNCTION The AD9114/AD9115/AD9116/AD9117 provides two differential current outputs, IOUTP/IOUTN and QOUTP/ QOUTN. IOUTP and QOUTP provide a near full-scale current output, IxOUTFS, when all bits are high (that is, DAC CODE = 2N - 1, where N = 8, 10, 12, or 14 for the AD9114, AD9115, AD9116, and AD9117, respectively), while IOUTN and QOUTN, the complementary outputs, provide no current. The current outputs appearing at the positive DAC outputs, IOUTP and QOUTP, and at the negative DAC outputs, IOUTN and QOUTN, are a function of both the input code and IxOUTFS and can be expressed as follows: Recommendations When Using an External Reference IOUTP = (IDAC CODE/2N) x IIOUTFS Apply the external reference to the REFIO pin. The internal reference can be directly overdriven by the external reference, or the internal reference can be powered down to save power consumption. QOUTP = (QDAC CODE/2 ) x IQOUTFS The external 0.1 F compensation capacitor on REFIO is not required unless specified by the external voltage reference manufacturer. The input impedance of REFIO is 10 k when the internal reference is powered up and 1 M when it is powered down. (1) N IOUTN = ((2N - 1) - IDAC CODE)/2N x IIOUTFS (2) QOUTN = ((2 - 1) - QDAC CODE)/2 x IQOUTFS N N where: IDAC CODE and QDAC CODE = 0 to 2N - 1 (that is, decimal representation). IIOUTFS and IQOUTFS are functions of the reference currents, IIREF and IQREF, respectively, which are nominally set by a reference voltage, VREFIO, and external resistors, IRSET and QRSET, respectively. IIOUTFS and IQOUTFS can be expressed as follows: IIOUTFS = 32 x IIREF (3) IQOUTFS = 32 x IQREF Rev. D | Page 43 of 52 AD9114/AD9115/AD9116/AD9117 or Data Sheet where: IIREF = VREFIO/IRSET IQREF = VREFIO/QRSET (4) IIOUTFS = 32 x VREFIO/IRSET (5) IQOUTFS = 32 x VREFIO/QRSET A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically drives a resistive load directly or via a transformer. If dc coupling is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN) should be connected to matching resistive loads, xRLOAD, that are tied to analog common, AVSS. The singleended voltage output appearing at the positive and negative nodes is VIOUTP = IOUTP x IRLOAD (6) VQOUTP = QOUTP x QRLOAD VIOUTN = IOUTN x IRLOAD (7) VQOUTN = QOUTN x QRLOAD To achieve the maximum output compliance of 1 V at the nominal 20 mA output current, IRLOAD = QRLOAD must be set to 50 . AD9114/AD9115/AD9116/AD9117 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTP/IOUTN and QOUTP/QOUTN can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the firstorder cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTP/IOUTN and QOUTP/QOUTN are complementary, they become additive when processed differentially. SELF-CALIBRATION Equation 8 highlights some of the advantages of operating the AD9114/AD9115/AD9116/AD9117 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VIDIFF, is twice the value of the single-ended voltage output (that is, VIOUTP or VIOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a single-ended output (VIOUTP and VIOUTN) or differential output of the AD9114/AD9115/AD9116/ AD9117 can be enhanced by selecting temperature tracking resistors for xRLOAD and xRSET because of their ratiometric relationship, as shown in Equation 8. The AD9114/AD9115/AD9116/AD9117 have a self-calibration feature that improves the DNL of the device. Performing a selfcalibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to produce measurable benefits. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. There is a fixed pre-divider of 16 and it is multiplied by the DIVSEL, which has a range of divide by 2 -256. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0] to produce a calibration clock frequency between these values. Separate self-calibration hardware is included for each DAC. The DACs can be self-calibrated individually or simultaneously. ANALOG OUTPUT To perform a device self-calibration, use the following procedure: The complementary current outputs in each DAC, IOUTP/ IOUTN and QOUTP/QOUTN, can be configured for singleended or differential operation. IOUTP/IOUTN and QOUTP/ QOUTN can be converted into complementary single-ended voltage outputs, VIOUTP and VIOUTN as well as VQOUTP and VQOUTN via a load resistor, xRLOAD, as described in the DAC Transfer Function section by Equation 6 through Equation 8. The differential voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN, and VQOUTP and VQOUTN, can also be converted to a single-ended voltage via a transformer or a differential amplifier configuration. The ac performance of the AD9114/AD9115/AD9116/AD9117 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at IOUTP and IOUTN is limited to 0.5 V. The distortion and noise performance of the 1. Substituting the values of IOUTP, IOUTN, IxREF, and VIDIFF can be expressed as VIDIFF = {(2 x IDAC CODE - (2N - 1))/2N} x (32 x VREFIO/IRSET) x IRLOAD (8) 2. 3. 4. Rev. D | Page 44 of 52 Write 0x00 to Register 0x12. This ensures that the UNCALI and UNCALQ bits (Bit 1 and Bit 0) are reset. Set up a calibration clock between 0.5 MHz and 4 MHz using DIVSEL[2:0], and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3). Select the DAC(s) to self-calibrate by setting either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent calibration hardware so that they can be calibrated simultaneously. Start self-calibration by setting Bit 4 (CALEN) in Register 0x12. Wait approximately 300 calibration clock cycles. Data Sheet The AD9114/AD9115/AD9116/AD9117 allow reading and writing of the calibration coefficients. There are 32 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device. 1.30 1.25 1.20 1.15 2. 3. 4. 5. 6. 2. 3. 4. 5. 6. 7. 1.00 0.90 Select which DAC core to read by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Write the address of the first coefficient (0x01) to Register 0x10. Set Bit 2 (SMEMRD) in Register 0x12 by writing 0x04 to Register 0x12. Read the 6-bit value of the first coefficient by reading the contents of Register 0x11. Clear the SMEMRD bit by writing 0x00 to Register 0x12. Repeat Step 2 through Step 4 for each of the remaining 31 coefficients by incrementing the address by 1 for each read. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. 0.85 0.80 0 8 16 24 32 CODE 40 48 56 Figure 97. Typical VREF Voltage vs. Code Option 2 While using the internal FSADJx resistors, each main DAC can achieve independently controlled coarse gain using the lower six bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. The register uses twos complement format and allows the output current to be changed in approximately 0.25 dB steps. 22 20 To write the calibration coefficients to the device, use the following steps: 18 Select which DAC core to write to by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Set Bit 3 (SMEMWR) in Register 0x12 by writing 0x08 to Register 0x12. Write the address of the first coefficient (0x01) to Register 0x10. Write the value of the first coefficient to Register 0x11. Repeat Step 2 through Step 4 for each of the remaining 31 coefficients by incrementing the address by one for each write. Clear the SMEMWR bit by writing 0x00 to Register 0x12. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. COARSE GAIN ADJUSTMENT Option 1 A coarse full-scale output current adjustment can be achieved using the lower six bits in Register 0x0D. This adds or subtracts up to 20% from the band gap voltage on Pin 34 (REFIO), and the voltage on the FSADJx resistors tracks this change. As a result, the DAC full-scale current varies by the same amount. A secondary VOUT_Q OR VOUT_I 16 IF (mA) 1. 1.05 0.95 To read the calibration coefficients, use the following steps: 1. 1.10 07466-058 7. effect to changing the REFIO voltage is that the full-scale voltage in the AUXDAC also changes by the same magnitude. The register uses twos complement format, in which 011111 maximizes the voltage on the REFIO node and 100000 minimizes the voltage. 14 12 10 8 6 4 2 0 10 20 30 40 xRSET CODE 50 60 07466-059 6. Check if the self-calibration has completed by reading Bit 6 (CALSTATI) and Bit 7 (CALSTATQ) in Register 0x0F. Logic 1 indicates that the calibration has completed. When the self-calibration has completed, write 0x00 to Register 0x12. Disable the calibration clock by clearing Bit 3 (CALCLK) in Register 0x0E. VREF (V) 5. AD9114/AD9115/AD9116/AD9117 Figure 98. Effect of xRSET Code Option 3 Even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the FSADJx pins. Any noise injected here appears as amplitude modulation of the output. Thus, a portion of the required series resistance (at least 20 k) must be installed right at the pin. A range of 10% is quite practical using this method. Option 4 As in Option 3, when the device is in pin mode, both full-scale values can be adjusted by sourcing or sinking current from the Rev. D | Page 45 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet CML REFIO pin. Noise injected here appears as amplitude modulation of the output; therefore, a portion of the required series resistance (at least 10 k) must be installed at the pin. A range of 25% is quite practical when using this method. xRCM 11.10 3.3V DAC1 3.3V DAC2 1.8V DAC1 1.8V DAC2 IOUTP 62.5 07466-061 Each main DAC has independent fine gain control using the lower six bits in Register 0x03 (I DACGAIN[5:0]) and Register 0x06 (Q DACGAIN[5:0]). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. These registers use straight binary format. One application in which straight binary format is critical is for side-band suppression while using a quadrature modulator. This is described in more detail in the Applications Information section. RLIP Figure 100. Simplified Internal Load Options Using the Internal Common-Mode Resistor These devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the DAC outputs. By default, the common-mode resistor is not connected. When enabled, it can be adjusted from ~60 to ~260 . Each main DAC has an independent adjustment using the lower six bits in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]). 260 10.90 240 220 10.80 200 RESISTANCE () 10.70 10.50 0 8 16 24 32 40 GAIN DAC CODE 48 56 64 07466-060 10.60 160 140 120 100 80 Figure 99. Typical DAC Gain Characteristics 60 USING THE INTERNAL TERMINATION RESISTORS The AD9117/AD9116/AD9115/AD9114 have four 62.5 termination internal resistors (two for each DAC output). To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent load pin. For example, on the I DAC, IOUTP must be shorted to RLIP and IOUTN must be shorted to RLIN. In addition, the CMLI or CMLQ pin must be connected to ground directly or through a resistor. If the output current is at the nominal 20 mA and the CMLI or CMLQ pin is tied directly to ground, this produces a dc common-mode bias voltage on the DAC output equal to 0.625 V. If the DAC dc bias must be higher than 0.625 V, an external resistor can be connected between the CMLI or CMLQ pin and ground. This part also has an internal common-mode resistor that can be enabled. This is explained in the Using the Internal Common-Mode Resistor section. 180 0 8 16 24 32 CODE 40 48 56 07466-062 IOUTFS (mA) IOUTN I DAC OR Q DAC Fine Gain 11.00 RLIN 62.5 Figure 101. Typical CML Resistor Value vs. Register Code Using the CMLx Pins for Optimal Performance The CMLx pins also serve to change the DAC bias voltages in the parts allowing them to run at higher dc output bias voltages. When running the bias voltage below 0.9 V and an AVDD of 3.3 V, the parts perform optimally when the CMLx pins are tied to ground. When the dc bias increases above 0.9 V, set the CMLx pins at 0.5 V for optimal performance. The maximum dc bias on the DAC output should be kept at or below 1.2 V when the supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close to 0 V and connect the CMLx pins directly to ground. Rev. D | Page 46 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 APPLICATIONS INFORMATION OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9114/AD9115/AD9116/AD9117. Unless otherwise noted, it is assumed that IxOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance. A single-ended output is suitable for applications in which low cost and low power consumption are primary concerns. DIFFERENTIAL COUPLING USING A TRANSFORMER An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 102. The distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. Transformer coupling provides excellent rejection of common-mode distortion (that is, even-order harmonics) over a wide frequency range. It also provides electrical isolation and can deliver voltage gain without adding noise. Transformers with different impedance ratios can also be used for impedance matching purposes. The main disadvantages of transformer coupling are low frequency roll-off, lack of power gain, and high output impedance. A differential resistor, RDIFF, can be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF, as reflected by the transformer, is chosen to provide a source termination that results in a low voltage standing wave ratio (VSWR). Note that approximately half the signal power is dissipated across RDIFF. SINGLE-ENDED BUFFERED OUTPUT USING AN OP AMP An op amp, such as the ADA4899-1, can be used to perform a singleended current-to-voltage conversion, as shown in Figure 103. Figure 103 is a simplified schematic. The REFIO pin must be buffered to keep the load current less than 100 nA. The AD9114/ AD9115/AD9116/AD9117 are configured with a pair of series resistors, RS, off each output. For best distortion performance, RS should be set to 0 . The feedback resistor, RFB, determines the peak-to-peak signal swing by the formula VOUT = RFB x IFS The common-mode voltage of the output is determined by the formula R VCM VREF 1 FB RB RFB I FS 2 The maximum and minimum voltages out of the amplifier are, respectively, R VMAX VREF 1 FB RB VMIN = VMAX - IFS x RFB IOUTN 29 CF +5V AD9114/AD9115/ AD9116/AD9117 IOUTP 28 RS IOUTP 28 07466-063 OPTIONAL RDIFF RFB RB RLOAD REFIO 34 Rev. D | Page 47 of 52 IOUTN 29 VOUT + Figure 102. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on IOUTP and IOUTN within the output common-mode voltage range of the device. Note that the dc component of the DAC output current is equal to IIOUTFS and flows out of both IOUTP and IOUTN. The center tap of the transformer should provide a path for this dc current. In most applications, AGND provides the most convenient voltage for the transformer center tap. The complementary voltages appearing at IOUTP and IOUTN (that is, VIOUTP and VIOUTN) swing symmetrically around AGND and should be maintained with the specified output compliance range of the AD9114/AD9115/AD9116/AD9117. - ADA4899-1 RS C -5V AVSS 25 Figure 103. Single-Supply, Single-Ended Buffer 07466-064 AD9114/AD9115/ AD9116/AD9117 AD9114/AD9115/AD9116/AD9117 Data Sheet DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP A dual op amp (see the circuit shown in Figure 104) can be used in a differential version of the single-ended buffer shown in Figure 103. Figure 104 is a simplified schematic. The REFIO pin must be buffered to keep the load current less than 100 nA. The same RC network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the DAC outputs. The feedback resistors, RFB, determine the differential peak-to-peak signal swing by the formula VOUT = 2 x RFB x IFS The maximum and minimum single-ended voltages out of the amplifier are, respectively, 1. 5 16 k VOUT = 0.5 V - I DAC - R S Figure 105 illustrates the function of all the SPI bits controlling these DACs with the exception of the QAUXEN (Register 0x0A) and IAUXEN (Register 0x0C) bits and gating to prohibit RS < 3.2 k. AVDD RNG0 RNG1 RNG: 00 = 125A fS 01 = 62A fS 10 = 31A fS 11 = 16A fS AUXDAC [9:0] VMIN = VMAX - RFB x IFS The common-mode voltage of the differential output is determined by the formula (OFS > 4 = 4) OFS2 OFS1 OFS0 16k VCM = VMAX - RFB x IFS 4k CF IOUTP 28 - ADA4841-2 Figure 105. AUXDAC Simplified Circuit Diagram + REFIO 34 The SPI speed limits the update rate of the auxiliary DACs. The data is inverted such that IAUXDAC is full scale at 0x000 and zero at 0x1FF, as shown in Figure 106. VOUT C AVSS 25 IOUTN 29 + 07466-066 REFIO 2 RS - OP AMP RFB RB AD9114/AD9115/ AD9116/AD9117 8k 16k 16k AUX PIN + RS ADA4841-2 - 3.0 2.6 Figure 104. Single-Supply Differential Buffer AUXILIARY DACs The DACs of the AD9114/AD9115/AD9116/AD9117 feature two versatile and independent 10-bit auxiliary DACs suitable for dc offset correction and similar tasks. ROFFSET ROFFSET ROFFSET ROFFSET ROFFSET 2.4 2.2 2.0 OUTPUT (V) RFB 07466-065 RB OP AMP OUTPUT VOLTAGE vs. CHANGES IN ROFFSET AND DAC CURRENT IN A 2.8 CF 1.8 1.6 = = = = = 3.3k 4k 5.3k 8k 16k 1.4 1.2 1.0 0.8 0.6 0.4 Because the AUXDACs are driven through the SPI port, they should never be used in timing-critical applications, such as inside analog feedback loops. 0.2 0 0 10 20 30 40 50 60 70 80 90 DAC CURRENT (A) 100 110 120 130 07466-067 R VMAX = VREF x 1 + FB RB To keep the pin count reasonable, these auxiliary DACs each share a pin with the corresponding FSADJx resistor. They are, therefore, usable only when enabled and when that DAC is operated on its internal full-scale resistors. A simple I-to-V converter is implemented on-chip with selectable shunt resistors (3.2 k to 16 k) such that if REFIO is set to exactly 1 V, REFIO/2 equals 0.5 V and the following equation describes the no load output voltage: Figure 106. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V No Load, AUXDAC 0x1FF to 0x000 Rev. D | Page 48 of 52 AD9114/AD9115/AD9116/AD9117 Two registers are assigned to each DAC with 10 bits for the actual DAC current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/ disable bit. Setting the QAUXOFS (Register 0x0A) and IAUXOFS (Register 0x0C) bits to all 1s disables the respective op amp and routes the DAC current directly to the respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is especially useful when the loads to be driven are beyond the limited capability of the on-chip amplifier. When not enabled (QAUXEN or IAUXEN = 0), the respective DAC output is in open circuit. DAC-TO-MODULATOR INTERFACING The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 107 and Figure 108, with the series resistor value chosen to give an appropriate adjustment range. Figure 107 also shows external load resistors in use. Often, the input commonmode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling or a dc level shift is necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, the dc blocking capacitors in Figure 107 can be removed and the on-chip resistors can be connected. MODULATOR V+ 0.1F OPTIONAL PASSIVE FILTERING I DAC 0.1F AD9114/AD9115/ AD9116/AD9117 AUXDAC1 50 50 5k TO 100k QUADRATURE MODULATOR I OR Q INPUTS 07466-268 AD9114/AD9115/ AD9116/AD9117 Figure 107. Typical Use of Auxiliary DACs Figure 108 shows a greatly simplified circuit that takes full advantage of the internal components supplied in the DAC. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. In the example shown in Figure 108, the filter must be able to pass dc to properly bias the modulator. Placing the filter at the location shown in Figure 107 and Figure 108 allows easy design of the filter, because the source and load impedances can easily be designed close to 50 for a 20 mA full-scale output. When the resistance at the modulator inputs is known, an optimum value for the series resistor can be calculated from the modulator input offset voltage ratings. AD9114/AD9115/ AD9116/AD9117 I OR Q DAC AD9114/AD9115/ AD9116/AD9117 AUXDAC 50 OPTIONAL LOW- PASS FILTERING 100 ADL5370 FAMILY I OR Q INPUTS 50 5k 07466-269 Data Sheet Figure 108. Typical Use of Auxiliary DACs When DC Coupling to Quadrature Modulator ADL537x Family CORRECTING FOR NONIDEAL PERFORMANCE OF QUADRATURE MODULATORS ON THE IF-TO-RF CONVERSION Analog quadrature modulators make it very easy to realize single sideband radios. These DACs are most often used to make radio transmitters, such as in cell phone towers. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are gain mismatch and LO feedthrough. Gain Mismatch The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. LO Feedthrough The quadrature modulator has a finite dc referred offset, as well as coupling from its LO port to the signal inputs. These can lead to a significant spectral spur at the frequency of the quadrature modulator LO. The AD9114/AD9115/AD9116/AD9117 have the capability to correct for both of these analog degradations. However, understand that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting them may be necessary. I/Q CHANNEL GAIN MATCHING Fine gain matching is achieved by adjusting the values in the DAC fine gain adjustment registers. For the I DAC, these values are in the I DAC Gain register (Register 0x03, I DACGAIN[5:0]). For the Q DAC, these values are in the Q DAC gain register (Register 0x06, Q DACGAIN[5:0]). These are 6-bit values that cover 2% of full scale. To perform gain compensation by starting from the default values of zero, raise the value of one of these registers a few steps until it can be determined if the amplitude of the unwanted image is increased or decreased. If the unwanted image increases in amplitude, remove the step and try the same adjustment on the other DAC control register. Iterate register changes until the rejection cannot be improved further. If the fine gain adjustment range is not sufficient to find a null (that is, the register goes full scale with no null apparent), adjust the course gain settings of the two DACs accordingly and try again. Variations on this simple method are possible. Rev. D | Page 49 of 52 AD9114/AD9115/AD9116/AD9117 Data Sheet To achieve LO feedthrough compensation, the user should start with the default conditions of the AUXDAC registers and then increment the magnitude of one or the other AUXDAC output voltages. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either decreasing the output voltage of the AUXDAC being adjusted or try adjusting the output voltage of the other AUXDAC. It may take practice before an effective algorithm is achieved. The AD9114/AD9115/AD9116/ AD9117 evaluation board can be used to adjust the LO feedthrough down to the noise floor, although this is not stable over temperature. 449.0 450.0 451.0 452.5 FREQUENCY (MHz) Figure 109. AD9114/AD9115/AD9116/AD9117 and ADL5370 with a SingleTone Signal at 450 MHz, No Gain or LO Compensation dB RESULTS OF GAIN AND OFFSET CORRECTION The results of gain and offset correction can be seen in Figure 109 and Figure 110. Figure 109 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 110 shows the output spectrum after correction. The LO feedthrough spur at 450 MHz has been suppressed to the noise level. This result can be achieved by applying the correction, but the correction must be repeated after a large change in temperature. 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 447.5 07466-070 To achieve LO feedthrough compensation in a circuit, each output of the two AUXDACs must be connected through a 10 k resistor to one side of the differential DAC output. See the Auxiliary DACs section for details of how to use AUXDACs. The purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, thereby adding a slight dc bias to one or the other of the quadrature modulator signal inputs. 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 447.5 449.0 450.0 FREQUENCY (MHz) 451.0 452.5 07466-071 LO FEEDTHROUGH COMPENSATION Note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. It can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the DACs and quadrature modulators. Phase mismatch is frequency dependent; therefore, routines must be developed to adjust it if wideband signals are desired. dB Note that LO feedthrough compensation is independent of phase compensation. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. Therefore, it is recommended that the gain adjustment be performed prior to LO compensation. Figure 110. AD9114/AD9115/AD9116/AD9117 and ADL5370 with a SingleTone Signal at 450 MHz, Gain and LO Compensation Optimized Rev. D | Page 50 of 52 Data Sheet AD9114/AD9115/AD9116/AD9117 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 0.60 MAX 0.60 MAX 31 30 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12 MAX 0.50 BSC 0.50 0.40 0.30 10 21 20 11 0.20 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.30 0.23 0.18 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTOM VIEW) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 06-01-2012-D 5.85 5.75 SQ 5.65 PIN 1 INDICATOR PIN 1 INDICATOR 40 1 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 111. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm x 6 mm and 0.85 mm Package Height (CP-40-1) Dimensions shown in millimeters DETAIL A (JEDEC 95) 0.30 0.23 0.18 31 40 30 1 0.50 BSC 4.25 4.10 SQ 3.95 EXPOSED PAD 21 TOP VIEW 0.80 0.75 0.70 PKG-004354 SEATING PLANE SIDE VIEW 0.45 0.40 0.35 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 10 BOTTOM VIEW 11 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5. Figure 112. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm x 6 mm and 0.75 mm Package Height (CP-40-9) Dimensions shown in millimeters Rev. D | Page 51 of 52 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 10-23-2017-B PIN 1 INDICATOR 6.10 6.00 SQ 5.90 AD9114/AD9115/AD9116/AD9117 Data Sheet ORDERING GUIDE Model 1 AD9114BCPZ AD9114BCPZRL7 AD9115BCPZ AD9115BCPZRL7 AD9116BCPZ AD9116BCPZRL7 AD9117BCPZ AD9117BCPZRL7 AD9117BCPZN AD9117BCPZNRL7 AD9114-DPG2-EBZ AD9115-DPG2-EBZ AD9116-DPG2-EBZ AD9117-DPG2-EBZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP 40-Lead LFCSP Evaluation Board Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. (c)2008-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07466-0-12/17(D) Rev. D | Page 52 of 52 Package Option CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-9 CP-40-9