16M x 36 Bit 5V FPM SIMM Fast Page Mode (FPM) DRAM SIMM 361606-S54s20TD 72 Pin 16Mx36 FPM SIMM Unbuffered, 4k Refresh, 5V General Description Pin Assignment The module is a 16Mx36 bit, 20 chip, 5V, 72 Pin SIMM module consisting of (12) 16Mx4 (TSOP), (1) Voltage Regulator and (7) Bus Switches. The module is unbuffered and supports Fast Page Mode (FPM) access. Pin # Symbol 1 Vss 2 DQ0 3 DQ18 4 DQ1 5 DQ19 6 DQ2 7 DQ20 8 DQ3 9 DQ21 10 Vcc 11 NC 12 A0 13 A1 14 A2 15 A3 16 A4 17 A5 18 A6 * Active Low Features * * * * * * * * * * * JEDEC-Standard 72-pin Single Inline Memory Module (SIMM) Unbuffered 60ns access time Supports Fast Page Mode (FPM) access cycles. Based on 16Mx4 DRAM Power Supply: 5.0V 0.5V 64ms, 4096-cycle refresh Pin # 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 NC RAS2* DQ26 DQ8 Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Symbol DQ17 DQ35 Vss CAS0* CAS2* CAS3* CAS1* RAS0* NC NC WE* NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 Pin # 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss Refresh modes, RAS* ONLY refresh, and CBR refresh. Seven Presence Detect (PD) lines LVTTL Compatible Inputs and Outputs Gold/Tin PCB connector 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 1 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM X36 DRAM SIMM, 1BANK with X4 DRAMs RAS0 CAS0 DQ(0:3) U1 DQ(8) U9 A0 : A11 DQ0 : 35 CAS DQ(4:7) U2 RAS WE CAS1 Vcc DQ(9:12) U3 DQ(17) U10 R E G I S T E R 10K REGE CK DQ(13:16) U4 RAS2 CAS2 WE DQ(18:21) U5 DQ(26) U11 DQ(35) U12 A0 - A11 WE : DRAMs U1 - U12 A0 - A11 : DRAMs U1 - U12 U6 CAS3 Bypass: DQ(27:30) DQ(31:34) 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 U7 One 0.22uF capacitor per DRAM device. VCC U1 - U12 VSS U1 - U12 U8 2 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM Pin RAS# CAS# WE# A# DQ0-DQ35 Vdd Vss PD# Name Row Address Strobe Column Address Strobe Write Enable Address Lines Data Lines Power Supply Ground Presence Detect Lines NC No Connection CAS# is used to strobe column addresses WE# is used to control read/write cycles. Address lines are multiplexed to specify the row and column address. Data input/output lines. Power Supply 5.0V0.5V Ground Presence detect lines are used to specify Module type. Lines are either grounded or NC in module (see Presence Detect Matrix). Line is not connected in module. Presence Detect Matrix Module Type 361606-S54m20TD 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 PD1 Vss PD2 NC 3 PD3 NC PD4 NC PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature NOTE: Iout Pt Topr Tst 50 12 0 to +70 -55 to +125 mA W C C Permanent damage may occur if absolute maximum ratings are exceeded. Device should be operated within recommended operating conditions only. DC Characteristics (TA = 0 to 70C, Vcc = 5.0V 0.5V) Parameter Supply voltage Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Symbol Vss Vcc Vih Vil Voh Vol Min 0 4.5 2.4 -1.0 2.4 - Typ 0 5.0 - Max 0 5.5 Vcc+1.0 0.8 0.4 Units V V V V V V Note 16 16 16 DC Current Consumption (TA = 0 to 70C, Vcc = 5.0V 0.5V) Parameter Standby Current (TTL) Standby Current (CMOS) Operating Current Random Read/Write Operating Current Fast Page Mode Refresh Current: RAS#-Only Refresh Current: CAS# before RAS# 16Mx36 5V FPM SIMM DS812 -0F - 05-13-99 Symbol ICC1 ICC2 ICC3 ICC4 ICC6 ICC7 Test Condition (RAS# = CAS# = VIH) All inputs = Vcc - 0.2V RAS#, CAS#, address cycling. tRC = tRC[MIN] RAS# = VIL, CAS#, Address cycling. tPC = tPC[MIN] RAS# cycling, CAS#=VIH; tRC = tRC[MIN] RAS#, CAS#, address cycling tRC = tRC[MIN] 4 -60 48 24 1728 1296 1728 1728 Unit mA mA mA mA mA mA Note 17 17 17, 18 17, 18 17 17 PNY Technologies Reserves the right to change product of specifications without notice 16M x 36 Bit 5V FPM SIMM Capacitance (TA = 0 to 70C, Vcc = 5.0V 0.5V, Vss = 0V) Parameter Input capacitance (Address) Symbol CI1 Typ - Max 65 Units pF Input capacitance (WE#, OE#) CI2 - 65 pF Input/Output capacitance (Data) CI/O - 14 pF Input capacitance (CAS#) CI3 - 20 pF Input capacitance (RAS#) C14 - 35 pF Note AC Characteristics (TA = 0 to 70C, Vcc = 5.0V 0.5V, Vss = 0V) Parameter Symbol -60 Min Max 30 Units Note ns 3, 5, 14 Access time from column address tAA Column address setup to CAS# precharge tACH 15 ns Column address hold time (from RAS#) tAR 50 ns Column address setup time tASC 0 ns Row address setup time tASR 0 Access time from CAS# tCAC Column address hold time tCAH 15 CAS# pulse width tCAS 10 CAS# to output in Low-Z tCLZ 3 ns Data output hold after CAS# LOW tCOH 3 ns CAS# precharge time tCP 10 Access time from CAS# precharge tCPA CAS# to RAS# precharge time tCRP 5 ns CAS# hold time tCSH 50 ns WRITE command to CAS# lead time tCWL 10 ns Data-in hold time tDH 10 ns 11 Data-in setup time tDS 0 ns 11 Output buffer turn-off delay tOFF 0 Fast Page-mode read or write cycle time tPC 35 Access time from RAS# tRAC RAS# to column address delay time tRAD 15 Row-address hold time tRAH 10 RAS# pulse width ns 15 ns 10 000 ns ns 35 15 ns ns ns 60 ns 2, 3 30 ns 9 ns tRAS, tRASP 60 Random read/write cycle time tRC 105 RAS# to CAS# delay time tRCD 20 Read command hold time tRCH 0 Read command setup time tRCS 0 Refresh Period (4096 cycles) tREF RAS# precharge time tRP 40 ns RAS# to CAS# precharge time tRPC 10 ns READ command hold time tRRH 0 ns RAS# hold time tRSH 17 ns WRITE command to RAS# lead time tRWL 15 t 3 Transition Time 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 10 000 ns ns 45 ns 8 ns ns 64 5 3, 4, 14 ns ms 15 ns 50 ns 7 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM AC Characteristics (TA = 0 to 70C, Vcc = 5.0V 0.5V, Vss = 0V) Parameter Symbol -60 WRITE command hold time tWCH Min 15 WRITE command hold time (RAS# referenced) tWCR 45 WE# command setup time tWCS 0 Output disable delay from WE# tWHZ Write command pulse width tWP Units ns ns ns 15 10 Note Max 10 ns ns Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. AC measurements assume tT = 5ns Assumes that tRCD tRCD (max.) and tRAD tRAD (max.). If tRCD or tRAD is greater that the maximum recommended value shown in this table, tRAC exceeds the value shown. Measured with a load circuit equivilaent to 1 TTL load and 100pF. Assumes that tRCD tRCD (max.), tRAD tRAD (max.). Assumes that tRCD tRCD (max.), tRAD tRAD (max.). tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vih and Vil. Operation with the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference point only, if tRCD is greater that the specified tRCD (max.) limit, then the access time is controlled exclusively by tCAC. Operation with the tRAD (max.) limit insures that tRAC (max.) can be met, tRAD (max.) is specified as a reference point only, if tRAD is greater that the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. Early write cycle only (tWCS tWCS (min.)) These parameters are referenced to CAS* leading edge in an early write cycle. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS* clock such as RAS* only refresh) tRASC defines RAS* pulse width in fast page mode cycles. Access time is determined by the longer of tAA or tCAC or tACP tREF defined is 4096 refresh cycle. All voltages referenced to Vss Typical maximum current consumption levels Column address changed once per cycle 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 6 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM READ CYCLE tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tRRH tCAS CAS tAR tRAD tASR tASC tRAH ROW ADDR tCAH tACH COLUMN ROW tRCS WE tRCH tAA tRAC tCAC tCLZ DQ OPEN tOFF VALID DATA OPEN DON'T CARE UNDEFINED EARLY WRITE CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD CAS tRAD tASR ADDR tAR tASC tRAH tCAH tACH ROW COLUMN ROW tCWL tRWL tWCR tWCH tWCS tWP WE tDS DQ tDH VALID DATA DON'T CARE UNDEFINED 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 7 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM FAST-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tPC tRCD tCAS tRSH tCP tCAS tCP tCAS tCP CAS tAR tRAD tASR ADDR tRAH tASC ROW tCAH tASC COLUMN tRCS tCAH tASC tCAH COLUMN COLUMN tRCS tRCS tRCH ROW tRRH tRCH tRCH WE tAA tRAC tCAC tCLZ DQ tAA tCPA tOFF tAA tCPA tCAC tCLZ tOFF VALID DATA OPEN tOFF tCAC tCLZ VALID DATA VALID DATA OPEN DON'T CARE UNDEFINED FAST-PAGE-MODE READ-EARLY-WRITE CYCLE tRASP tRP RAS tRSH tCSH tCRP tPC tRCD tCAS tCP tCAS tCP CAS tAR tRAD tASR ADDR tRAH tASC ROW tCAH tASC COLUMN COLUMN tCWL ROW tRWL tWP tRCS tWCS WE tCAH tAA tRAC tCAC tOFF NOTE 1 tDS tWCH tDH tCLZ DQ VALID DATA OPEN VALID DATA DON'T CARE NOTE 1: DO NOT DRIVE DATA PRIOR TO TRISTATE UNDEFINED 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 8 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM FAST/EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tRCD tCAS tCP tCAS tRSH tCAS tCP tCP CAS tAR tRAD tASR ADDR tRAH tACH tASC ROW tCAH tACH tASC COLUMN tCAH tACH tASC COLUMN tCWL tWCS tWCH tWP tCWL tWCS tWCH tWP tCAH COLUMN ROW tCWL tWCS tWCH tWP WE tWCR tDS DQ tCAC VALID DATA tRWL tDS tDH VALID DATA tDS tDH VALID DATA DON'T CARE UNDEFINED 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 9 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM /RAS-ONLY REFRESH CYCLE tRC tRAS tRP RAS tRPC tCRP CASL / CASH tASR tRAH ROW ADDR ROW OPEN Q WE DON'T CARE UNDEFINED CBR REFRESH CYCLE ( Addresses = DON'T CARE ) tRP RAS tRAS tRP tRAS tRPC tCP tCSR tRPC tCHR tCSR tCHR CAS OPEN DQ tWRP tWRH tWRP tWRH WE DON'T CARE UNDEFINED 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 10 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc. 16M x 36 Bit 5V FPM SIMM OUTLINE DRAWING 1.400"+/-.005" SIDEVIEW FRONT VIEW .148" .346" .148" BACK VIEW Note: Drawing is for component location only, assembly may not have all components installed. 16Mx36 5V FPM SIMM DS812 --0F - 05-13-99 11 PNY Technologies Reserves the right to change product of specifications without notice 1998 PNY Technologies, Inc.