16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
1
Pin Assignment
Pin # Symbol Pin # Symbol Pin # Symbol Pin # Symbol
1Vss 19 A10 37 DQ17 55 DQ12
2DQ0 20 DQ4 38 DQ35 56 DQ30
3DQ18 21 DQ22 39 Vss 57 DQ13
4DQ1 22 DQ5 40 CAS0* 58 DQ31
5DQ19 23 DQ23 41 CAS2* 59 Vcc
6DQ2 24 DQ6 42 CAS3* 60 DQ32
7DQ20 25 DQ24 43 CAS1* 61 DQ14
8DQ3 26 DQ7 44 RAS0* 62 DQ33
9DQ21 27 DQ25 45 NC 63 DQ15
10 Vcc 28 A7 46 NC 64 DQ34
11 NC 29 A11 47 WE* 65 DQ16
12 A0 30 Vcc 48 NC 66 NC
13 A1 31 A8 49 DQ9 67 PD1
14 A2 32 A9 50 DQ27 68 PD2
15 A3 33 NC 51 DQ10 69 PD3
16 A4 34 RAS2* 52 DQ28 70 PD4
17 A5 35 DQ26 53 DQ11 71 NC
18 A6 36 DQ8 54 DQ29 72 Vss
* Active Low
Fast Page Mode (FPM) DRAM SIMM
361606-S54s20TD 72 Pin 16Mx36 FPM SIMM
Unbuffered, 4k Refresh, 5V
Features
• JEDEC-Standard 72-pin Single Inline Memory
Module (SIMM)
• Unbuffered
• 60ns access time
• Supports Fast Page Mode (FPM) access cycles.
• Based on 16Mx4 DRAM
• Power Supply: 5.0V ± 0.5V
• 64ms, 4096-cycle refresh
• Refresh modes, RAS* ONLY refresh, and CBR refresh.
• Seven Presence Detect (PD) lines
• LVTTL Compatible Inputs and Outputs
• Gold/Tin PCB connector
General Description
The module is a 16Mx36 bit, 20 chip, 5V, 72 Pin
SIMM module consisting of (12) 16Mx4 (TSOP), (1)
Voltage Regulator and (7) Bus Switches. The module is
unbuffered and supports Fast Page Mode (FPM) access.
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
2
X36 DRAM SIMM, 1BANK with X4 DRAMs
U3
U4
U5
U6
DQ(9:12)
DQ(13:16)
DQ(18:21)
CAS1
CAS2
RAS2
U7
U8
DQ(27:30)
DQ(31:34)
CAS3
U1
U2
DQ(0:3)
DQ(4:7)
CAS0
RAS0
U9
U10
U11
U12
DQ(8)
DQ(17)
DQ(26)
DQ(35)
R
E
G
I
S
T
E
R
CK
REGE
Vcc
10K
WE
RAS
CAS
DQ0 : 35
A0 : A11
A0 - A11 A0 - A11 : DRAMs U1 - U12
WE WE : DRAMs U1 - U12
U1 - U12
VCC
VSS
Bypass:
One 0.22uF capacitor per DRAM device.
U1 - U12
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
3
Pin Name
RAS# Row Address Strobe
CAS# Column Address Strobe CAS# is used to strobe column addresses
WE# Write Enable WE# is used to control read/write cycles.
A# Address Lines Address lines are multiplexed to specify the row and column address.
DQ0-DQ35 Data Lines Data input/output lines.
Vdd Power Supply Power Supply 5.0V±0.5V
Vss Ground Ground
PD# Presence Detect Lines Presence detect lines are used to specify Module type. Lines are either
grounded or NC in module (see Presence Detect Matrix).
NC No Connection Line is not connected in module.
Presence Detect Matrix
Module Type PD1 PD2 PD3 PD4
361606-S54m20TD Vss NC NC NC
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 -0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
4
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Short circuit output current Iout 50 mA
Power dissipation Pt 12 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tst -55 to +125 °C
NOTE: Permanent damage may occur if absolute maximum ratings are exceeded.
Device should be operated within recommended operating conditions only.
DC Characteristics (TA = 0 to 70C, Vcc = 5.0V ±± 0.5V)
Parameter Symbol Min Typ Max Units Note
Supply voltage Vss 0 0 0 V
Supply voltage Vcc 4.5 5.0 5.5 V16
Input high voltage Vih 2.4 -Vcc+1.0 V16
Input low voltage Vil -1.0 -0.8 V16
Output high voltage Voh 2.4 - - V
Output low voltage Vol - - 0.4 V
DC Current Consumption (TA = 0 to 70C, Vcc = 5.0V ±± 0.5V)
Parameter Symbol Test Condition -60 Unit Note
Standby Current (TTL) ICC1 (RAS# = CAS# = VIH)48 mA 17
Standby Current (CMOS) ICC2 All inputs = Vcc - 0.2V 24 mA 17
Operating Current Random Read/Write ICC3 RAS#, CAS#, address cycling. tRC = tRC[MIN] 1728 mA 17, 18
Operating Current Fast Page Mode ICC4 RAS# = VIL, CAS#, Address cycling. tPC = tPC[MIN] 1296 mA 17, 18
Refresh Current: RAS#-Only ICC6 RAS# cycling, CAS#=VIH; tRC = tRC[MIN] 1728 mA 17
Refresh Current: CAS# before RAS# ICC7 RAS#, CAS#, address cycling tRC = tRC[MIN] 1728 mA 17
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
5
Capacitance (TA = 0 to 70C, Vcc = 5.0V ±± 0.5V, Vss = 0V)
Parameter Symbol Typ Max Units Note
Input capacitance (Address) CI1 -65 pF
Input capacitance (WE#, OE#) CI2 -65 pF
Input/Output capacitance (Data) CI/O -14 pF
Input capacitance (CAS#) CI3 -20 pF
Input capacitance (RAS#) C14 -35 pF
AC Characteristics (TA = 0 to 70C, Vcc = 5.0V ±± 0.5V, Vss = 0V)
-60Parameter Symbol Min Max Units Note
Access time from column address tAA 30 ns 3, 5, 14
Column address setup to CAS# precharge tACH 15 ns
Column address hold time (from RAS#) tAR 50 ns
Column address setup time tASC 0ns
Row address setup time tASR 0ns
Access time from CAS# tCAC 15 ns 3, 4, 14
Column address hold time tCAH 15 ns
CAS# pulse width tCAS 10 10 000 ns
CAS# to output in Low-Z tCLZ 3ns
Data output hold after CAS# LOW tCOH 3ns
CAS# precharge time tCP 10 ns
Access time from CAS# precharge tCPA 35 ns
CAS# to RAS# precharge time tCRP 5ns
CAS# hold time tCSH 50 ns
WRITE command to CAS# lead time tCWL 10 ns
Data-in hold time tDH 10 ns 11
Data-in setup time tDS 0ns 11
Output buffer turn-off delay tOFF 0 15 ns
Fast Page-mode read or write cycle time tPC 35 ns
Access time from RAS# tRAC 60 ns 2, 3
RAS# to column address delay time tRAD 15 30 ns 9
Row-address hold time tRAH 10 ns
RAS# pulse width tRAS, tRASP 60 10 000 ns
Random read/write cycle time tRC 105 ns
RAS# to CAS# delay time tRCD 20 45 ns 8
Read command hold time tRCH 0ns
Read command setup time tRCS 0ns
Refresh Period (4096 cycles) tREF 64 ms 15
RAS# precharge time tRP 40 ns
RAS# to CAS# precharge time tRPC 10 ns
READ command hold time tRRH 0ns
RAS# hold time tRSH 17 ns
WRITE command to RAS# lead time tRWL 15 ns
Transition Time tτ3 50 ns 7
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
6
AC Characteristics (TA = 0 to 70C, Vcc = 5.0V ±± 0.5V, Vss = 0V)
-60Parameter Symbol Min Max Units Note
WRITE command hold time tWCH 15 ns
WRITE command hold time (RAS# referenced) tWCR 45 ns
WE# command setup time tWCS 0ns 10
Output disable delay from WE# tWHZ 15 ns
Write command pulse width tWP 10 ns
Notes
1. AC measurements assume tT = 5ns
2. Assumes that tRCD ≤ tRCD (max.) and tRAD ≥ tRAD (max.). If tRCD or tRAD is greater that the maximum recommended value shown in this table, tRAC
exceeds the value shown.
3. Measured with a load circuit equivilaent to 1 TTL load and 100pF.
4. Assumes that tRCD ≥ tRCD (max.), tRAD ≤ tRAD (max.).
5. Assumes that tRCD ≤ tRCD (max.), tRAD ≥ tRAD (max.).
6. tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
7. Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vih and Vil.
8. Operation with the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference point only, if tRCD is greater that the
specified tRCD (max.) limit, then the access time is controlled exclusively by tCAC.
9. Operation with the tRAD (max.) limit insures that tRAC (max.) can be met, tRAD (max.) is specified as a reference point only, if tRAD is greater that the
specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
10. Early write cycle only (tWCS ≥ tWCS (min.))
11. These parameters are referenced to CAS* leading edge in an early write cycle.
12. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS*
clock such as RAS* only refresh)
13. tRASC defines RAS* pulse width in fast page mode cycles.
14. Access time is determined by the longer of tAA or tCAC or tACP
15. tREF defined is 4096 refresh cycle.
16. All voltages referenced to Vss
17. Typical maximum current consumption levels
18. Column address changed once per cycle
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
7
t
RP
t
RAS
t
RC
t
CRP
t
RCD
t
CAS
t
RSH
t
CSH
t
RRH
t
ASR
t
RAH
t
RAD
t
ACH
t
CAH
t
ASC
t
AR
t
RCS
t
RCH
t
CLZ
t
CAC
t
RAC
t
AA
t
OFF
ADDR
WE
DQ
CAS
RAS
ROW COLUMN ROW
VALID DATA
OPEN OPEN
READ CYCLE
DON'T CARE
UNDEFINED
tRP
tRAS
tRC
tCRP tRCD tCAS
tRSH
tCSH
tASR tRAH
tRAD tACH
tCAH
tASC
tAR
tWP
tWCH
tWCR
tRWL
ADDR
WE
DQ
CAS
RAS
ROW COLUMN ROW
VALID DATA
EARLY WRITE CYCLE
DON'T CARE
UNDEFINED
tWCS
tCWL
tDH
tDS
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
8
tRP
tRASP
tCRP tRCD
tCSH tCAS tCP tCAS
tPC tCP tCAS
tRSH tCP
tASR tRAH
tRAD
tAR
tASC tCAH tASC tCAH tASC tCAH
tRCS tRCH
tRCS
tRCH
tRCS
tRCH
tRRH
tOFF
tCLZ
tCAC
tCPA
tAA
tOFF
tCLZ
tCAC
tCPA
tAA
tOFF
tCLZ
tCAC
tRAC
tAA
ADDR
WE
DQ
CAS
RAS
DON'T CARE
UNDEFINED
ROW ROWCOLUMNCOLUMN COLUMN
VALID
DATA VALID
DATA VALID
DATA
OPEN OPEN
tRP
tRASP
tCRP tRCD
tCSH tCAS tCP tCAS
tPC
tRSH
tCP
tASR tRAH
tRAD
tAR
tASC tCAH tASC tCAH
tCAC
tRAC
ADDR
WE
DQ
CAS
RAS
DON'T CARE
UNDEFINED
ROW ROW
COLUMNCOLUMN
VALID DATA
VALID
DATA
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
tWP
tAA
tWCS tWCH
tRCS
OPEN
tRWL
tCWL
tCLZ
tDH
tDS
tOFF
NOTE 1
NOTE 1: DO NOT DRIVE DATA PRIOR TO TRISTATE
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
9
tRP
tRASP
tCRP tRCD
tCSH tCAS tCP tCAS
tPC tCP tCAS
tRSH tCP
tASR tRAH
tRAD
tAR
tASC tCAH tASC tCAH tASC tCAH
tWP tWP tWP
tDH
tDS
tDH
tDS
tCAC
tWCR
ADDR
WE
DQ
CAS
RAS
DON'T CARE
UNDEFINED
ROW ROW
COLUMNCOLUMN COLUMN
VALID DATA VALID DATA VALID DATA
FAST/EDO-PAGE-MODE EARLY-WRITE CYCLE
tACH
tACH
tACH
tWCH
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tCWL
tWCS
tDS
tRWL
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
10
tRP
tRAS
tRC
tCRP tRPC
tASR tRAH
ROW ROW
OPEN
/RAS-ONLY REFRESH CYCLE
DON'T CARE
UNDEFINED
ADDR
Q
RAS
WE
CASL / CASH
tRP
tRAS
tCP tCHR
OPEN
DON'T CARE
UNDEFINED
tRP tRAS
tRPC tCSR tRPC tCSR tCHR
tWRP tWRH tWRP tWRH
WE
DQ
CAS
RAS
CBR REFRESH CYCLE
( Addresses = DON'T CARE )
16M x 36 Bit 5V
FPM SIMM
16Mx36 5V FPM SIMM
DS812 --0F – 05-13-99
PNY Technologies Reserves the right to change product of specifications without notice
1998 PNY Technologies, Inc.
11
Note: Drawing is for component location only, assembly may not have all components installed.
OUTLINE DRAWING
SIDEVIEW
.148” .148”
.346”
1.400”+/-.005”
BACK VIEW
FRONT VIEW