CS53L21 Low-Power, Stereo Analog-to-Digital Converter FEATURES SYSTEM FEATURES 98-dB dynamic range (A-weighted) 24-bit conversion -88-dB THD+N 4-96 kHz sample rate Analog gain controls - +32-dB or +16-dB mic preamps Multibit delta-sigma architecture - Analog programmable gain amplifier (PGA) Low power operation +20-dB digital boost Programmable automatic level control (ALC) - Noise gate for noise suppression - Programmable threshold and attack/release rates - Stereo record (ADC): 8.72 mW @ 1.8 V - Stereo record (mic to PGA and ADC): 13.73 mW @ 1.8 V Variable power supplies Independent left/right channel control Digital volume control High-pass filter disable for DC measurements Stereo 3:1 analog input MUX - 1.8-2.5-V digital and analog - 1.8-3.3-V interface logic Power down management - ADC, mic preamplifier, PGA Software Mode (ICTM and SPITM control) Dual mic inputs - Programmable, low noise mic bias levels Hardware Mode (standalone control) - Differential mic mix for common mode noise rejection Flexible clocking options Very low 64 Fs oversampling clock reduces power consumption - Digital routing mixes - Reset Serial Audio Output Mono mixes 1.8 V to 2.5 V PCM Serial Interface Hardware Mode or I2C & SPI Software Mode Control Data Level Translator 1.8 V to 3.3 V Master or slave operation Digital Signal Processing Engine ALC Volume Controls High Pass Filters Register Configuration Multibit Oversampling ADC MUX PGA MUX Multibit Oversampling ADC MUX ALC Copyright Cirrus Logic, Inc. 2005-2015 (All Rights Reserved) http://www.cirrus.com Stereo Input 1 Stereo Input 2 PGA +32 dB Stereo Input 3 / Mic Input 1 & 2 +32 dB MIC Bias DS700F1 JUL `15 CS53L21 APPLICATIONS GENERAL DESCRIPTION Portable audio players The CS53L21 is a highly integrated, 24-bit, 96-kHz, low power stereo A/D. Based on multibit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The ADC offers many features suitable for low power, portable system applications. Digital microphones Digital voice recorders Voice recognition systems Audio/video capture cards The ADC input path allows independent channel control of a number of features. An input multiplexer selects between line-level or microphone-level inputs for each channel. The microphone input path includes a selectable programmable-gain preamp stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately. The Signal Processing Engine (SPE) controls left/right channel volume mixing, channel swap and channel mute functions. All volume-level changes may be configured to occur on soft ramp and zero cross transitions. The CS53L21 is available in a 32-pin QFN package in both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CDB53L21 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 56 for complete details. In addition to its many features, the CS53L21 operates from a low-voltage analog and digital core, making this A/D ideal for portable systems that require extremely low power consumption in a minimal amount of space. 2 DS700F1 CS53L21 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) ..................................................................... 12 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................................... 13 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 14 SWITCHING SPECIFICATIONS - IC CONTROL PORT ..................................................................... 16 SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 17 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18 DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS ................................................ 18 POWER CONSUMPTION .................................................................................................................... 19 4. APPLICATIONS ................................................................................................................................... 20 4.1 Overview ......................................................................................................................................... 20 4.1.1 Architecture ........................................................................................................................... 20 4.1.2 Line and MIC Inputs .............................................................................................................. 20 4.1.3 Signal Processing Engine ..................................................................................................... 20 4.1.4 Device Control (Hardware or Software Mode) ...................................................................... 20 4.1.5 Power Management .............................................................................................................. 20 4.2 Hardware Mode .............................................................................................................................. 21 4.3 Analog Inputs .................................................................................................................................. 22 4.3.1 Digital Code, Offset and DC Measurement ........................................................................... 22 4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 23 4.3.3 Digital Routing ....................................................................................................................... 23 4.3.4 Differential Inputs .................................................................................................................. 23 4.3.4.1 External Passive Components ................................................................................... 23 4.3.5 Analog Input Multiplexer ........................................................................................................ 24 4.3.6 MIC and PGA Gain ................................................................................................................ 25 4.3.7 Automatic Level Control (ALC) .............................................................................................. 25 4.3.8 Noise Gate ............................................................................................................................ 26 4.4 Signal Processing Engine ............................................................................................................... 27 4.4.1 Volume Controls .................................................................................................................... 27 4.4.2 Mono Channel Mixer ............................................................................................................. 27 4.5 Serial Port Clocking ........................................................................................................................ 28 4.5.1 Slave ..................................................................................................................................... 28 4.5.2 Master ................................................................................................................................... 29 4.5.3 High-Impedance Digital Output ............................................................................................. 29 4.5.4 Quarter- and Half-Speed Mode ............................................................................................. 29 4.6 Digital Interface Formats ................................................................................................................ 30 4.7 Initialization ..................................................................................................................................... 30 4.8 Recommended Power-Up Sequence ............................................................................................. 30 4.9 Recommended Power-Down Sequence ........................................................................................ 31 4.10 Software Mode ............................................................................................................................. 31 4.10.1 SPI Control .......................................................................................................................... 32 4.10.2 IC Control ........................................................................................................................... 32 4.10.3 Memory Address Pointer (MAP) .......................................................................................... 33 4.10.3.1 Map Increment (INCR) ............................................................................................. 33 5. REGISTER QUICK REFERENCE ........................................................................................................ 34 6. REGISTER DESCRIPTION .................................................................................................................. 36 DS700F1 3 CS53L21 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 36 6.2 Power Control 1 (Address 02h) ...................................................................................................... 36 6.3 MIC Power Control and Speed Control (Address 03h) ................................................................... 37 6.4 Interface Control (Address 04h) ..................................................................................................... 39 6.5 MIC Control (Address 05h) ............................................................................................................. 40 6.6 ADC Control (Address 06h) ............................................................................................................ 41 6.7 ADCx Input Select, Invert and Mute (Address 07h) ........................................................................ 42 6.8 SPE Control (Address 09h) ............................................................................................................ 43 6.9 ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address 0Bh) .......... 45 6.10 ADCx Attenuator: ADCA (Address 0Ch) and ADCB (Address 0Dh) ............................................ 46 6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh) ........................... 46 6.12 Channel Mixer (Address 18h) ....................................................................................................... 47 6.13 ALC Enable and Attack Rate (Address 1Ch) ................................................................................ 47 6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 48 6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 48 6.16 Noise Gate Configuration and Misc. (Address 1Fh) ..................................................................... 49 6.17 Status (Address 20h) (Read Only) ............................................................................................... 50 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 51 7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 51 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 51 8.1 Auto Detect Enabled ....................................................................................................................... 51 8.2 Auto Detect Disabled ...................................................................................................................... 52 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 52 9.1 Power Supply, Grounding ............................................................................................................... 52 9.2 QFN Thermal Pad .......................................................................................................................... 53 10. DIGITAL FILTERS .............................................................................................................................. 53 11. PARAMETER DEFINITIONS .............................................................................................................. 54 12. PACKAGE DIMENSIONS ................................................................................................................. 55 THERMAL CHARACTERISTICS .......................................................................................................... 55 13. ORDERING INFORMATION ............................................................................................................. 56 14. REFERENCES .................................................................................................................................... 56 15. REVISION HISTORY ......................................................................................................................... 56 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15 Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15 Figure 5.Control Port Timing - IC ............................................................................................................. 16 Figure 6.Control Port Timing - SPI Format ................................................................................................ 17 Figure 7.Analog Input Architecture ............................................................................................................ 22 Figure 8.MIC Input Mix w/Common Mode Rejection ................................................................................. 24 Figure 9.Differential Input .......................................................................................................................... 24 Figure 10.ALC ........................................................................................................................................... 25 Figure 11.Noise Gate Attenuation ............................................................................................................. 26 Figure 12.Signal Processing Engine ......................................................................................................... 27 Figure 13.Master Mode Timing ................................................................................................................. 29 Figure 14.Tri-State Serial Port .................................................................................................................. 29 Figure 15.IS Format ................................................................................................................................. 30 Figure 16.Left-Justified Format ................................................................................................................. 30 Figure 17.Initialization Flow Chart ............................................................................................................. 31 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 32 Figure 19.Control Port Timing, IC Write ................................................................................................... 33 Figure 20.Control Port Timing, IC Read ................................................................................................... 33 4 DS700F1 CS53L21 Figure 21.AIN and PGA Selection ............................................................................................................. 43 Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 51 Figure 23.ADC Passband Ripple .............................................................................................................. 53 Figure 24.ADC Stopband Rejection .......................................................................................................... 53 Figure 25.ADC Transition Band ................................................................................................................ 53 Figure 26.ADC Transition Band Detail ...................................................................................................... 53 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 21 Table 3. MCLK/LRCK Ratios .................................................................................................................... 28 DS700F1 5 CS53L21 Pin Name # LRCK 1 SDA/CDIN (MCLKDIV2) 2 SCL/CCLK (IS/LJ) 3 TSTN SCLK MCLK SDOUT (M/S) DGND VD VL RESET 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE 32 31 30 29 28 27 26 25 LRCK 1 24 AIN1B SDA/CDIN (MCLKDIV2) 2 23 AIN1A SCL/CCLK (IS/LJ) 3 22 AFILTB AD0/CS (TSTN) 4 21 AFILTA VA_PULLUP 5 20 AIN2B/BIAS TSTO 6 19 AIN2A AGND 7 18 MICIN2/BIAS/AIN3B TSTO 8 17 MICIN1/AIN3A 9 10 11 12 13 14 15 16 TSTO NIC NIC VA AGND TSTO VQ FILT+ CS53L21 Pin Description Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in IC Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port. Interface Format Selection (Input) - Hardware Mode: Selects between IS and left-Justified interface formats for the ADC. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip-select signal for SPI format. AD0/CS (TSTN) 4 VA_PULLUP 5 Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA using a 47 k resistor. TSTO 6 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). AGND 7 Analog Ground (Input) - Ground reference for the internal analog section. TSTO 8 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). 6 Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to DGND for normal operation. DS700F1 CS53L21 TSTO 9 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). NIC NIC 10 11 .Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left "floating". No other external connection should be made to this pin. VA 12 Analog Power (Input) - Positive power for the internal analog section. AGND 13 Analog Ground (Input) - Ground reference for the internal analog section. TSTO 14 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). VQ 15 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. FILT+ 16 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. MICIN1/ AIN3A 17 Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. MICIN2/ BIAS/AIN3B 18 Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. AIN2A 19 Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. AIN2B/BIAS 20 Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. AFILTA AFILTB 21 22 Filter Connection (Output) - Filter connection for the ADC inputs. AIN1A AIN1B 23 24 Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. RESET 25 Reset (Input) - The device enters a low power mode when this pin is driven low. VL 26 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. VD 27 Digital Power (Input) - Positive power for the internal digital section. DGND 28 Digital Ground (Input) - Ground reference for the internal digital section. SDOUT (M/S) 29 Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. MCLK 30 Master Clock (Input) - Clock source for the delta-sigma modulators. SCLK 31 Serial Clock (Input/Output) -- Serial clock for the serial audio interface. TSTN 32 Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal operation. Thermal Pad DS700F1 Serial Audio Data Output (Output) - Output for two's complement serial audio data. - Thermal relief pad for optimized heat dissipation. See "QFN Thermal Pad" on page 53. 7 CS53L21 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) I/O Driver Receiver RESET Input - 1.8 V - 3.3 V SCL/CCLK (IS/LJ) Input - 1.8 V - 3.3 V, with Hysteresis SDA/CDIN (MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis AD0/CS (DEM) Input - 1.8 V - 3.3 V MCLK Input - 1.8 V - 3.3 V LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V SCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V SDOUT (M/S) Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V Table 1. I/O Power Rails 8 DS700F1 CS53L21 2. TYPICAL CONNECTION DIAGRAMS See Note 4 +1.8 V or +2.5 V 1 F 0.1 F 0.1 F Note 4: Series resistance in the path of the power supplies must be avoided. 47 k VD +1.8 V or +2.5 V 1 F VA_ PULLUP VA CS53L21 AIN1A TSTN 1800 pF * 1800 pF * AIN2A LRCK SDOUT AIN2B BIAS1 RESET 1800 pF * 1 F 1800 pF * MICIN1 AIN3A SDA/CDIN AD0/CS Note 1: Resistors are required for IC control port operation Right Analog Input 1 100 Left Analog Input 2 100 k 100 k 100 Right Analog Input 2 Microphone Input 100 k 1 F BIAS2 AIN3B/MICIN2 Microphone Bias RL 0.1 F 2k See Note 1 100 k 1 F SCL/CCLK +1.8 V, +2.5 V or +3.3 V 100 k 1 F SCLK 2k Left Analog Input 1 100 100 AIN1B MCLK Digital Audio Processor 1 F See Note 3 Note 3: The value of R L is dictated by the microphone cartridge. VL FILT+ 0.1 F 10 F AGND * AFILTA AFILTB VQ DGND * 150 pF 150 pF 1 F * Capacitors must be C0G or equivalent Figure 1. Typical Connection Diagram (Software Mode) DS700F1 9 CS53L21 See Note 4 +1.8V or +2.5V 1 F 0.1 F 0.1 F +1.8V or +2.5V 47 k VD VA Note 4: Series resistance in the path of the power supplies (typically used for added filtering ) must be avoided . VA_ PULLUP CS53L21 TSTN MCLK SCLK LRCK AIN1A VL or DGND (1) SDOUT/ M/S Digital Audio Processor Left Analog Input 1 1800 pF * 1 F 100 100 k 1800 pF * 100 k 100 AIN1B Right Analog Input 1 1 F RESET IS/LJ FILT+ MCLKDIV2 DEM 10 F AGND * +1.8V, 2.5 V or +3.3V AFILTA AFILTB VQ VL 0.1 F DGND * 150 pF 150 pF 1 F * Capacitors must be C0G or equivalent (1) Pull-up to VL (47 kfor Master Mode . Pull -down to DGND for Slave Mode . Figure 2. Typical Connection Diagram (Hardware Mode) 10 DS700F1 CS53L21 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters Symbol Min Max Units DC Power Supply (Note 1) Analog Core VA 1.65 2.63 V Digital Core VD 1.65 2.63 V Serial/Control Port Interface VL 1.65 3.47 V TA -10 -40 +70 +85 C C Ambient Temperature Commercial - CNZ Automotive - DNZ Note: 1. The device will operate properly over the full range of the analog, digital core and serial/control port interface supplies. ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters Symbol Min Max Units Analog Digital Serial/Control Port Interface VA VD VL -0.3 -0.3 -0.3 3.0 3.0 4.0 V V V Input Current (Note 2) Iin - 10 mA Analog Input Voltage (Note 3) VIN AGND-0.7 VA+0.7 V VIND -0.3 VL+ 0.4 V Ambient Operating Temperature (power applied) TA -50 +115 C Storage Temperature Tstg -65 +150 C DC Power Supply Digital Input Voltage (Note 3) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. DS700F1 11 CS53L21 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) VA = 2.5 V (nominal) Min Typ Max Parameter (Note 4) VA = 1.8 V (nominal) Min Typ Max Unit Analog In to ADC (PGA bypassed) Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise -1 dBFS -20 dBFS -60 dBFS 93 90 99 96 - 90 87 96 93 - dB dB - -86 -76 -36 -80 - - -84 -73 -33 -78 - dB dB dB Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB A-weighted unweighted 92 89 98 95 - 89 86 95 92 - dB dB PGA Setting: +12 dB A-weighted unweighted 85 82 91 88 - 82 79 88 85 - dB dB -1 dBFS -60 dBFS - -88 -35 -81 - - -86 -32 -80 - dB dB -1 dBFS - -85 -79 - -83 -77 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB A-weighted unweighted - 86 83 - - 83 80 - dB dB -1 dBFS - -76 - - -74 - dB Total Harmonic Distortion + Noise PGA Setting: 0 dB Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range A-weighted unweighted - 78 74 - - 75 71 - dB dB -1 dBFS - -74 - - -71 - dB Interchannel Gain Mismatch - 0.2 - - 0.2 - dB Gain Drift - 100 - - 100 - ppm/C - 352 - - 352 - LSB 0.74*VA 0.75*VA 90 0.78*VA 0.794*VA 0.129*VA 0.022*VA 0.82*VA 0.83*VA dB - 20 39 50 - PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB Other Characteristics DC Accuracy Offset Error SDOUT Code with HPF On Input Interchannel Isolation Full-scale Input Voltage Input Impedance (Note 5) 0.74*VA ADC PGA (0 dB) 0.75*VA MIC (+16 dB) MIC (+32 dB) ADC PGA MIC 90 0.78*VA 0.82*VA 0.794*VA 0.83*VA 0.129*VA 0.022*VA 20 39 50 - Vpp Vpp Vpp Vpp k k k 4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 5. Measured between AINxx and AGND. 12 DS700F1 CS53L21 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) VA = 2.5 V (nominal) Min Typ Max Parameter (Note 4) VA = 1.8 V (nominal) Min Typ Max Unit Analog In to ADC Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise -1 dBFS -20 dBFS -60 dBFS 91 78 99 96 - 88 85 96 93 - dB dB - -86 -76 -36 -78 - - -84 -73 -33 -76 - dB dB dB Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB A-weighted unweighted 90 87 98 95 - 87 84 95 92 - dB dB PGA Setting: +12 dB A-weighted unweighted 83 80 91 88 - 80 77 88 85 - dB dB -1 dBFS -60 dBFS - -88 -35 -80 - - -86 -32 -78 - dB dB -1 dBFS - -85 -77 - -83 -75 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic Range PGA Setting: 0 dB A-weighted unweighted - 86 83 - - 83 80 - dB dB -1 dBFS - -76 - - -74 - dB Total Harmonic Distortion + Noise PGA Setting: 0 dB Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic Range A-weighted unweighted - 78 74 - - 75 71 - dB dB -1 dBFS - -74 - - -71 - dB Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Drift - 100 - - 100 - ppm/C - 352 - - 352 - LSB 90 0.78*VA 0.794*VA 0.129*VA 0.022*VA 0.82*VA 0.83*VA 0.74*VA 0.75*VA 90 0.78*VA 0.794*VA 0.129*VA 0.022*VA 0.82*VA 0.83*VA dB - - 18 40 50 - - PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB Other Characteristics DC Accuracy Offset Error SDOUT Code with HPF On Input Interchannel Isolation Full-scale Input Voltage Input Impedance (Note 5) DS700F1 0.74*VA ADC PGA (0 dB) 0.75*VA MIC (+16 dB) MIC (+32 dB) 18 ADC 40 PGA 50 MIC Vpp Vpp Vpp Vpp k k k 13 CS53L21 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Note 6) Min Typ Max Unit 0 - 0.46 Fs -0.09 - 0.17 dB Stopband 0.6 - - Fs Stopband Attenuation 33 - - dB - 7.6/Fs - s Passband (Frequency Response) to -0.1 dB corner Passband Ripple Total Group Delay High-Pass Filter Characteristics (48 kHz Fs) Frequency Response -3.0 dB -0.13 dB - 3.7 24.2 - Hz Hz Phase Deviation @ 20 Hz - 10 - Deg - - 0.17 dB - 5 0 s Passband Ripple Filter Settling Time 10 /Fs 6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz. SWITCHING SPECIFICATIONS - SERIAL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.) Parameters RESET pin Low Pulse Width Symbol (Note 7) MCLK Frequency MCLK Duty Cycle (Note 8) Min Max Units 1 - ms 1.024 38.4 MHz 45 55 % 4 8 4 50 12.5 25 50 100 kHz kHz kHz kHz 45 55 % - 64*Fs Hz 45 55 % Slave Mode Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs LRCK Duty Cycle SCLK Frequency 1/tP SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns LRCK Edge to SDOUT MSB Output Delay td(MSB) - 52 ns SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns 14 DS700F1 CS53L21 Parameters Symbol Min Fs - Max Units Master Mode (Note 9) Output Sample Rate (LRCK) All Speed Modes (Note 10) MCLK ----------------128 Hz 45 55 % - 64*Fs Hz 45 55 % td(MSB) - 52 ns SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns LRCK Duty Cycle 1/tP SCLK Frequency SCLK Duty Cycle LRCK Edge to SDOUT MSB Output Delay 7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are settled. 8. See "Example System Clock Frequencies" on page 51 for typical MCLK frequencies. 9. See"Master" on page 29. 10. "MCLK" refers to the external master clock applied. // LRCK ts(LK-SK) // tP // SCLK // td(MSB) SDOUT th(SK-SDO) // MSB // ts(SDO-SK) MSB-1 Figure 3. Serial Audio Interface Slave Mode Timing // LRCK // // SCLK // td(MSB) SDOUT tP th(SK-SDO) // MSB // ts(SDO-SK) MSB-1 Figure 4. Serial Audio Interface Master Mode Timing DS700F1 15 CS53L21 SWITCHING SPECIFICATIONS - IC CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RESET Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - s Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - s Clock Low time tlow 4.7 - s Clock High Time thigh 4.0 - s Setup Time for Repeated Start Condition tsust 4.7 - s thdd 0 - s tsud 250 - ns Rise Time of SCL and SDA trc - 1 s Fall Time SCL and SDA tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - s Acknowledge Delay from SCL Falling tack 300 3450 ns SDA Hold Time from SCL Falling (Note 11) SDA Setup time to SCL Rising 11. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop Repeated Start Start Stop SDA t buf t t high t hdst tf hdst t susp SCL t low t hdd t sud t sust tr Figure 5. Control Port Timing - IC 16 DS700F1 CS53L21 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter Symbol Min Max Units CCLK Clock Frequency fsck 0 6.0 MHz RESET Rising Edge to CS Falling tsrs 20 - ns CS Falling to CCLK Edge tcss 20 - ns CS High Time Between Transmissions tcsh 1.0 - s CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 12) tdh 15 - ns Rise Time of CCLK and CDIN (Note 13) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 13) tf2 - 100 ns 12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For fsck <1 MHz. RST tsrs CS tcss tsch tcsh tscl tr2 CCLK tf2 tdsu tdh CDIN Figure 6. Control Port Timing - SPI Format DS700F1 17 CS53L21 DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters Min Typ Max Units Nominal Voltage Output Impedance DC Current Source/Sink (Note 14) - 0.5*VA 23 - 10 V k A FILT+ - VA - V 0.8*VA 0.7*VA 0.6*VA 0.5*VA 50 1 - V V V V mA dB VQ Characteristics MIC BIAS Characteristics DC Current Source Power Supply Rejection Ratio (PSRR) 1 kHz - Power Consumption (Normal Operation Worse Case) 1 kHz - - 30 mW Power Supply Rejection Ratio (PSRR) (Note 15) 1 kHz - 60 - dB Nominal Voltage MICBIAS_LVL[1:0] = 00 MICBIAS_LVL[1:0] = 01 MICBIAS_LVL[1:0] = 10 MICBIAS_LVL[1:0] = 11 14. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors. 15. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS Parameters (Note 16) Input Leakage Current Symbol Min Max Units Iin - 10 A - 10 pF Input Capacitance 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) VOH VL - 0.2 - V Low-Level Output Voltage (IOL = 100 A) VOL - 0.2 V High-Level Input Voltage VIH 0.68*VL - V Low-Level Input Voltage VIL - 0.32*VL V 16. See "Digital I/O Pin Characteristics" on page 8 for serial and control port power rails. 18 DS700F1 CS53L21 POWER CONSUMPTION See (Note 17) Reserved bit 6 Reserved bit 5 PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN PDN_MICB PDN_MICA PDN_MICBIAS Power Control. Registers 02h 03h Operation Typical Current (mA) iVA iVD iVL (Note 18) V Total Power (mWrms) 1 Off (Note 19) x x x x x x x x x x 1.8 2.5 0 0 0 0 0 0 0 0 2 Standby (Note 20) x x x x x x 1 x x x 1.8 2.5 0.01 0.02 0 0.05 0.01 0.03 0 0.10 3 Mono Record ADC 1 1 1 1 1 0 0 1 1 1 1.8 2.5 PGA to ADC 1 1 1 0 1 0 0 1 1 1 1.8 1.85 2.03 0.03 7.05 2.07 3.05 0.05 12.94 2.35 2.03 0.03 7.95 2.5 2.58 3.08 0.05 14.29 MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 0 1.8 (with Bias) 2.5 MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 1 1.8 (no Bias) 2.5 3.67 2.05 0.03 10.36 3.95 3.09 0.05 17.71 3.27 2.03 0.03 9.61 3.52 3.08 0.05 16.62 ADC 1 1 1 1 0 0 0 1 1 1 1.8 2.5 PGA to ADC 1 1 0 0 0 0 0 1 1 1 1.8 2.69 2.12 0.03 8.72 2.93 3.18 0.04 15.40 3.65 2.12 0.03 10.45 2.5 3.91 3.17 0.04 17.84 MIC to PGA to ADC 1 1 0 0 0 0 0 0 0 1 1.8 (no Bias) 2.5 5.48 2.11 0.03 13.73 5.76 3.17 0.04 22.45 4 Stereo Record 17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation. 18. VL current will slightly increase in master mode. 19. RESET pin 25 held LO, all clocks and data lines are held LO. 20. RESET pin 25 held HI, all clocks and data lines are held HI. DS700F1 19 CS53L21 4. APPLICATIONS 4.1 4.1.1 Overview Architecture The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK). 4.1.2 Line and MIC Inputs The analog input portion of the A/D allows selection from and configuration of multiple combinations of stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC input with common mode rejection), two MIC bias outputs and independent channel control (including a high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Automatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume controls, including gain, boost, attenuation and inversion are also available. 4.1.3 Signal Processing Engine The ADC data has independent volume controls and mixing functions such as mono mixes and left/right channel swaps. 4.1.4 Device Control (Hardware or Software Mode) In Software Mode, all functions and features may be controlled via a two-wire IC or three-wire SPI control port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins. 4.1.5 Power Management Two Software Mode control registers provide independent power-down control of the ADC, PGA, MIC preamp and MIC bias, allowing operation in select applications with minimal power consumption. 20 DS700F1 CS53L21 4.2 Hardware Mode A limited feature set is available when the A/D powers up in Hardware Mode (see "Recommended PowerUp Sequence" on page 30) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available. Hardware Mode Feature/Function Summary Feature/Function Default Configuration Stand-Alone Control Power Control Device PGAx ADCx MIC Bias MICx Preamp Note Powered Up Powered Up Powered Up Powered Down Powered Down - - Enabled - - Auto-Detect Speed Mode Single-Speed Mode - - MCLK Divide (Selectable) "MCLKDIV2" pin 2 Serial Port Master / Slave Selection (Selectable) "M/S" pin 29 (Selectable) "IS/LJ" pin 3 Disabled Disabled Disabled Disabled 0 dB 0 dB Disabled Disabled - - - - - - - - Auto-Detect Speed Mode Serial Port Slave Serial Port Master Interface Control ADC Volume and Gain ADC Digital Boost Soft Ramp Zero Cross Invert PGAx Attenuator ALC Noise Gate ADCx High-Pass Filter ADCx High-Pass Filter Freeze Line/MIC Input Select ADC mix Volume and Gain Signal Processing Engine (SPE) Invert Soft Ramp Zero Cross MIX Data Selection (SPE Enable) Channel Swap ADC Enabled Continuous DC Subtraction AIN1A to PGAA AIN1B to PGAB Disabled Enabled Enabled see Section 4.5 on page 28 see Section 4.5 on page 28 see Section 4.6 on page 30 Disabled - - ADC Data to SPE - - ADCA = L; ADCB = R - - Table 2. Hardware Mode Feature Summary DS700F1 21 CS53L21 4.3 Analog Inputs AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level signals, allowing various gain and signal adjustments for each channel. ADCA_MUTE ADCA_DBOOST +20dB Digital Boost MUX MUX ADCA_ATT[7:0] 0/-96dB 1dB steps PDN_ADCA Multibit Oversampling ADC Attenuator ADCA_HPF FREEZE ADCA_HPF ENABLE INV_ADCA SOFTA PCM Serial Interface MICMIX DIGMIX MICA_BOOST PDN_MICA Noise Gate ALC NG_ALL NG_EN THRESH[3:0] NGDELAY[1:0] MICBIAS PDN_MICBIAS MICBIAS_SEL PDN_ADCB SOFTB +20dB Digital Boost ADCB_HPF FREEZE ADCB_HPF ENABLE AIN3A/ MICIN1 +16/ 32 dB PDN_PGAA ALC_ENB ALCB_SRDIS ALCB_ZCDIS MUX AIN1A AIN2A MUX MICBIAS_LVL[1:0] ADCB_DBOOST MUX PGA AINA_MUX[1:0] ALCA_SRDIS ALCA_ZCDIS ALC_ENA ALC_ARATE[5:0] ALC_RRATE[5:0] MAX[2:0] MIN[2:0] PGAA_VOL[5:0] ADC_SNGVOL SOFTA ZCROSSA +12/-3dB 0.5dB steps Attenuator ADCB_MUTE Multibit Oversampling ADC INV_ADCB ADCB_ATT[7:0] 0/-96dB 1dB steps PGAB_VOL[5:0] ADC_SNGVOL SOFTB ZCROSSB +12/-3dB 0.5dB steps PGA PDN_PGAB AINB_MUX[1:0] AIN1B AIN2B/MICBIAS MUX AIN3B/ MICIN2/ MICBIAS +16/ 32 dB MICB_BOOST PDN_MICB TO SIGNAL PROCESSING ENGINE (SPE) FROM SIGNAL PROCESSING ENGINE (SPE) Figure 7. Analog Input Architecture 4.3.1 Digital Code, Offset and DC Measurement The ADC output data is in two's complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow bit to be set to a `1'. Given the two's complement format, low-level signals may cause the MSB of the serial data to periodically toggle between `1' and `0', possibly introducing noise into the system as the bit switches back and forth. To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note that this offset is not removed (refer to "Analog Characteristics (Commercial - CNZ)" on page 12 and/or "Analog Characteristics (Automotive - DNZ)" on page 13 for the specified offset level). The A/D may be used to measure DC voltages by disabling the high-pass filter for the designated channel. DC levels are measured relative to VQ and will be decoded as positive two's complement binary numbers above VQ and negative two's complement binary numbers below VQ. Software Controls: 22 "Status (Address 20h) (Read Only)" on page 50, "ADC Control (Address 06h)" on page 41. DS700F1 CS53L21 4.3.2 High-Pass Filter and DC Offset Calibration The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high-pass filter is "frozen" during normal operation, the current value of the DC offset for the corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the A/D with the high-pass filter enabled and the DC offset not "frozen" until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Freezing the DC offset. The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits. If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using the ADCx_HPFEN bit. Software Controls: 4.3.3 "ADC Control (Address 06h)" on page 41. Digital Routing The digital output of the ADC may be internally routed to the Signal Processing Engine (SPE). ADC output volume may be controlled using the ADCMIX [6:0] bits, and channel swaps can be done using the ADCA[1:0] and ADCB[1:0] bits. This "processed" ADC data can be selected for output in place of the ADC output data using the DIGMIX bit. Software Controls: 4.3.4 "ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh)" on page 46, "Interface Control (Address 04h)" on page 39. Differential Inputs The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides common mode rejection of noise in digitally intense PCBs, where the microphone signal traverses long traces, or across long microphone cables as illustrated in Figure 8. Since the mixer provides a differential combination of the two signals, the potential input mix may exceed the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically attenuated 6 dB. Gain may be applied using either the analog PGA or MIC preamp or the digital ADCMIX volume control to readjust a small signal to desired levels. The analog inputs may also be used as a differential input pair as illustrated in Figure 9. The two channels are differentially combined when the MICMIX bit is enabled. 4.3.4.1 External Passive Components The microphone input is internally biased to VQ. Input signals must be AC coupled using external capacitors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 kW may be combined with an external capacitor of 1 mF to achieve the cutoff frequency defined by the equation, 1 fc = ----------------------------------------------- = 3.18 Hz 2 50 k 1 F An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits. DS700F1 23 CS53L21 The MICBIAS series resistor must be selected based on the requirements of the particular microphone used. The MICBIAS output pin is selected using the MICBIAS_SEL bit. Software Controls: "Interface Control (Address 04h)" on page 39, "MIC Control (Address 05h)" on page 40. MICBIAS 20 MICIN1 + // 17 + // MICIN2 18 Figure 8. MIC Input Mix w/Common Mode Rejection 2.5 V 2.15 V VA AINxA 1.25 V 0.35 V 2.15 V AINxB 1.25 V 0.35 V Full-Scale Differential Input Level (MICMIX=1) = (AINxA - AINxB) = 3.6 VPP = 1.27 VRMS Figure 9. Differential Input 4.3.5 Analog Input Multiplexer A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or bypassed around the PGA. To conserve power, the PGAs may be powered down allowing the user to select from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC preamp, however, the PGA must be powered up. Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the two input channels. Each ADC, PGA and MIC preamp has an associated input resistance. When selecting between these paths, the input resistance to the A/D will change accordingly. Refer to the input resistance characteristics in the Characteristic and Specification Tables for the input resistance of each path. Software Controls: 24 "Power Control 1 (Address 02h)" on page 36, "MIC Control (Address 05h)" on page 40 "ADCx Input Select, Invert and Mute (Address 07h)" on page 42. DS700F1 CS53L21 4.3.6 MIC and PGA Gain The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer, allowing it to be used for microphone level signals without the need for any external gain. The PGA must be powered up when using the MIC preamp. The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps. Software Controls: 4.3.7 "Power Control 1 (Address 02h)" on page 36, "ADCx Input Select, Invert and Mute (Address 07h)" on page 42, "ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address 0Bh)" on page 45, "MIC Control (Address 05h)" on page 40. Automatic Level Control (ALC) When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold. When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first and the PGA gain is then increased at a programmable release rate and maintains the resulting level above the minimum threshold. Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best level control may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds. Software Controls: "ALC Enable and Attack Rate (Address 1Ch)" on page 47, "ALC Release Rate (Address 1Dh)" on page 48, "ALC Threshold (Address 1Eh)" on page 48, "ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address 0Bh)" on page 45. Input MAX[2:0] MIN[2:0] below full scale below full scale ALC ADCx_ATT[7:0] and PGAx_VOL[4:0] volume controls should NOT be adjusted manually when ALCx is enabled. PGA Gain and/or Attenuator Output (after ALC) MAX[2:0] MIN[2:0] below full scale below full scale RRATE[5:0] ARATE[5:0] Figure 10. ALC DS700F1 25 CS53L21 4.3.8 Noise Gate The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before the noise gate attacks the signal. Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC preamp. For example: If both +32 dB preamplification and +12 dB programmable gain is applied, the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale. Ramp-down time to the maximum setting is affected by the SOFTx bit. Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog inputs are configured for differential signals (see "Differential Inputs" on page 23"Differential Inputs" on page 23), enable the NG_ALL bit to trigger the noise gate only when both inputs fall below the threshold. Software Controls: "Noise Gate Configuration and Misc. (Address 1Fh)" on page 49, "ADC Control (Address 06h)" on page 41. Output (dB) N =1 EN G -52 dB -96 -64 dB Maximum Attenuation* G N =0 EN -80 dB -40 Input (dB) THRESH[2:0] Figure 11. Noise Gate Attenuation 26 DS700F1 CS53L21 4.4 Signal Processing Engine The SPE provides various signal processing functions that apply to the ADC data. Software Controls: "SPE Control (Address 09h)" on page 43 INPUTS FROM ADCA and ADCB SIGNAL PROCESSING ENGINE (SPE) MUTE_ADCMIXA MUTE_ADCMIXB ADCMIXA_VOL[6:0] ADCMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps VOL ADCA[1:0] ADCB[1:0] Channel Swap Digital Mix to ADC Serial Interface Figure 12. Signal Processing Engine 4.4.1 Volume Controls The digital volume control functions offer independent control over the ADC signal path into the mixer. The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings. The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the rate specified by the SPE_SZC[1:0] bits. Software Controls: 4.4.2 "ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh)" on page 46 Mono Channel Mixer A channel mixer may be used to create a mix of the left and right channels for the ADC data. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap. Software Controls: DS700F1 "Channel Mixer (Address 18h)" on page 47. 27 CS53L21 4.5 Serial Port Clocking The A/D serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode. Software Control: "MIC Power Control and Speed Control (Address 03h)" on page 37, "SPE Control (Address 09h)" on page 43. Pin Hardware Control: Setting "SDOUT, M/S" pin 29 47 k Pull-down Slave 47 k Pull-up Master "MCLKDIV2" pin 2 4.5.1 Selection LO No Divide HI MCLK is divided by 2 prior to all internal circuitry. Slave LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits. Auto-Detect QSM HSM SSM DSM Disabled (Software Mode only) 512, 768, 1024, 1536, 2048, 3072 256, 384, 512, 768, 1024, 1536 128, 192, 256, 384, 512, 768 128, 192, 256, 384 512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384* 1024, 1536, 2048*, 3072* *MCLKDIV2 must be enabled. Enabled Table 3. MCLK/LRCK Ratios 28 DS700F1 CS53L21 4.5.2 Master LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled). In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits. /1 0 /2 1 / 128 Double Speed 00 / 128 Single Speed 01 / 256 Half Speed 10 / 512 Quarter Speed 11 MCLK LRCK Output (Equal to Fs) SPEED[1:0] MCLKDIV2 /2 Double Speed 00 /2 Single Speed 01 /4 Half Speed 10 /8 Quarter Speed 11 SCLK Output Figure 13. Master Mode Timing 4.5.3 High-Impedance Digital Output The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-impedance state, allowing another device to transmit serial port data without bus contention. CS53L21 Transmitting Device #2 Transmitting Device #1 SDOUT 3ST_SP SCLK/LRCK Receiving Device Figure 14. Tri-State Serial Port 4.5.4 Quarter- and Half-Speed Mode Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow lower frequency sample rates. DS700F1 29 CS53L21 4.6 Digital Interface Formats The serial port operates in standard IS or Left-Justified digital interface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the SPE on the rising edge of SCLK. Figures 15-16 illustrate the general structure of each format. Refer to "Switching Specifications - Serial Port" on page 14 for exact timing relationship between clocks and data. Software Control: "Interface Control (Address 04h)" on page 39. Hardware Control: LRCK Pin "IS/LJ" pin 3 Setting Selection LO Left-Justified Interface HI IS Interface L eft C h a n n e l R ig ht C h a n n el SCLK SDIN M SB MSB LSB AOUTA / AINxA MSB LS B AOUTB / AINxB Figure 15. IS Format LRCK L eft C h a n n e l R ig ht C h a n n el SCLK SDIN MSB LS B MSB LS B MSB AOUTB / AINxB AOUTA / AINxA Figure 16. Left-Justified Format 4.7 Initialization Figure 17 shows the initialization and power-down sequence. The A/D enters a Power-Down state on initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, ADC and switched-capacitor low-pass filters are powered down. The device remains in the Power-Down state until RESET is brought high, at which point, the control port is accessible and the desired register settings can be loaded per the descriptions in Section 4.10. If a valid write sequence to the control port is not made within approximately 10 ms, the A/D enters Hardware Mode. Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio and normal operation begins. 4.8 Recommended Power-Up Sequence 1. 2. 3. 4. 5. Hold RESET low until the power supplies are stable. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode. For Software Mode operation, set the PDN bit to `1'b in under 10 ms. This places the device in "standby". Load the desired register settings while keeping the PDN bit set to `1'b. Start MCLK to the appropriate frequency, as discussed in Section 4.5. SCLK may be applied or set to master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1. 6. Set the PDN bit to `0'b. 7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 30 DS700F1 CS53L21 4.9 Recommended Power-Down Sequence To minimize audible pops when turning off or placing the A/D in standby, 1. Mute the ADCs. 2. Set the PDN bit in the power control register to `1'b. The A/D will not power down until it reaches a fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down. 3. Bring RESET low. No Power 1. No audio signal generated. Off Mode (Power Applied) 1. No audio signal generated. 2. Control Port Registers reset to default. PDN bit = '1'b? Standby Mode 1. No audio signal generated. 2. Control Port Registers retain settings. Yes No No RESET = Low? Valid MCLK Applied? Yes No 20 ms delay Control Port Active Charge Caps 1. VQ Charged to quiescent voltage. 2. Filtx+ Charged. No Control Port Valid Write Seq. within 10 ms? Hardware Mode Minimal feature set support. Power Off Transition 1. Audible pops. ADC Initialization 2048 internal MCLK cycle delay Yes Software Mode Registers setup to desired settings. Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed. No Reset Transition 1. Pops suppressed. Valid MCLK/LRCK Ratio? Yes RESET = Low ERROR: Power removed Normal Operation Audio signal generated per control port or standalone settings. PDN bit set to '1'b (software mode only) Figure 17. Initialization Flow Chart 4.10 Software Mode The control port is used to access the registers allowing the A/D to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. DS700F1 31 CS53L21 The device enters software mode only after a successful write command using either SPI or IC protocol, with the device acting as a slave. The SPI protocol is permanently selected whenever there is a high-to-low transition on the AD0/CS pin after reset. If using the IC protocol, pin AD0/CS should be permanently connected to either VL or GND; this option allows the user to slightly alter the chip address as desired. 4.10.1 SPI Control In Software Mode, CS is the CS53L21 chip-select signal, CCLK is the control port bit clock (input into the CS53L21 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The A/D will only support write operations. Read request will be ignored. Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP autoincrement capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CCLK CHIP ADDRESS (WRITE) CDIN 1 0 0 1 0 1 0 MAP BYTE 0 INCR 6 5 4 3 DATA +n DATA 2 1 0 7 6 1 0 7 6 1 0 Figure 18. Control Port Timing in SPI Mode 4.10.2 IC Control In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected through a resistor to VL or DGND as desired. The pin's state is sensed while the CS53L21 is being reset. The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 followed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the autoincrement bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input to the CS53L21 from the microcontroller after each transmitted byte. 32 DS700F1 CS53L21 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) 1 SDA 0 0 1 0 1 MAP BYTE AD0 0 INCR 6 5 4 3 2 1 0 ACK 7 6 1 ACK DATA +n DATA +1 DATA 0 7 6 1 0 7 6 1 ACK 0 ACK STOP START Figure 19. Control Port Timing, IC Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) SDA 1 0 0 1 STOP MAP BYTE 0 1 AD0 0 INCR 6 5 4 3 2 1 CHIP ADDRESS (READ) 1 0 0 0 1 0 ACK ACK START DATA 1 AD0 1 START 7 ACK DATA +1 0 7 ACK 0 DATA + n 7 0 NO ACK STOP Figure 20. Control Port Timing, IC Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100101x0 (chip address and write operation). Receive acknowledge bit. Send MAP byte, autoincrement off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100101x1 (chip address and read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the autoincrement bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 4.10.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.10.3.1 Map Increment (INCR) The device has MAP autoincrement capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. DS700F1 33 CS53L21 5. REGISTER QUICK REFERENCE Software mode register defaults are as shown. "Reserved" registers must maintain their default state. Addr 01h 02h 03h 04h 05h 06h Function ID p 36 default Power Ctl. 1 p 36 default 3 2 1 0 Chip_ID0 1 Rev_ID2 0 Rev_ID1 0 Rev_ID0 1 PDN_PGAB 0 PDN_PGAA 0 PDN_ADCB 0 PDN_ADCA 0 PDN 0 3-ST_SP PDN_MICB PDN_MICA MCLKDIV2 Reserved 0 Reserved Reserved 1(See Note 2 1(See Note 2 on page 36) on page 36) SPEED1 SPEED0 p 37 default Interface Ctl. p 39 default MIC Control & Misc. 1 0 1 0 1 1 Reserved 0 M/S 0 Reserved 0 Reserved 0 Reserved 0 ADC_IS/LJ 0 DIGMIX 0 MICMIX 0 ADC_SNGVOL 0 ADCB_ DBOOST 0 ADCA_ DBOOST 0 MICBIAS_ SEL 0 MICBIAS_ LVL1 0 MICBIAS_ LVL0 0 MICB_ BOOST 0 MICA_ BOOST 0 ADCB_HPF EN 1 ADCB_HP FRZ 0 ADCA_HPF EN 1 ADCA_HP FRZ 0 SOFTB ZCROSSB SOFTA ZCROSSA 0 0 0 0 AINB_MUX1 AINB_MUX0 INV_ADCB INV_ADCA ADCB_ MUTE ADCA_ MUTE 0 0 0 0 0 0 0 0 Reserved 0 Reserved 1 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved FREEZE Reserved Reserved Reserved SPE_SZC1 SPE_SZC0 0 SPE_ ENABLE 0 0 0 0 1 1 0 ALCA_SR DIS ALCA_ZC DIS Reserved PGAA VOL4 PGAA VOL3 PGAA VOL2 PGAA VOL1 PGAA VOL0 0 0 0 0 0 0 0 0 ALCB_SR DIS ALCB_ZC DIS Reserved PGAB VOL4 PGAB VOL3 PGAB VOL2 PGAB VOL1 PGAB VOL0 0 0 0 0 0 0 0 0 ADCA_ ATT7 0 ADCA_ ATT6 0 ADCA_ ATT5 0 ADCA_ ATT4 0 ADCA_ ATT3 0 ADCA_ ATT2 0 ADCA_ ATT1 0 ADCA_ ATT0 0 ADCB_ ATT7 0 ADCB_ ATT6 0 ADCB_ ATT5 0 ADCB_ ATT4 0 ADCB_ ATT3 0 ADCB_ ATT2 0 ADCB_ ATT1 0 ADCB_ ATT0 0 MUTE_ADC MIXA 1 ADCMIXA VOL6 0 ADCMIXA VOL5 0 ADCMIXA VOL4 0 ADCMIXA VOL3 0 ADCMIXA VOL2 0 ADCMIXA VOL1 0 ADCMIXA VOL0 0 MUTE_ADC MIXB 1 ADCMIXB VOL6 0 ADCMIXB VOL5 0 ADCMIXB VOL4 0 ADCMIXB VOL3 0 ADCMIXB VOL2 0 ADCMIXB VOL1 0 ADCMIXB VOL0 0 p 40 default ADC Control default SPE Control p 43 default 0Ah ALCA SZC & PGAA Volume p 45 default 0Bh ALCB SZC & PGAB Volume p 45 default 0Ch ADCA Attenuator p 46 default 0Dh ADCB Attenuator p 46 default Vol. Control ADCMIXA p 46 default Vol. Control ADCMIXB p 46 default 34 4 Chip_ID1 1 PDN_ MICBIAS 1 09h 0Fh 5 Chip_ID2 0 AUTO 08h 0Eh 6 Chip_ID3 1 Speed Ctl. & Power Ctl. 2 p 41 default ADC Input Select, Invert, Mute p 42 default Reserved 07h 7 Chip_ID4 1 AINA_MUX1 AINA_MUX0 0 DS700F1 CS53L21 Addr Function 10h Reserved 11h default Reserved 12h default Reserved 13h default Reserved 14h default Reserved 15h default Reserved 16h default Reserved 17h default Reserved 19h default ADC Channel Mixer p 47 default Reserved 1Ah default Reserved 1Bh default Reserved 18h default 1Ch ALC Enable & Attack Rate p 47 default 1Dh ALC Release Rate 20h p 48 default ALC Threshold p 48 default Noise Gate Config p 49 default Status 21h p 50 default Reserved 1Eh 1Fh default DS700F1 7 6 5 4 3 2 1 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved Reserved Reserved Reserved ADCA1 ADCA0 ADCB1 ADCB0 0 0 0 0 0 0 0 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 1 1 1 1 1 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 ALC_ENB ALC_ENA 0 0 ALC_ARATE5 0 AALC_RATE4 0 ALC_ARATE3 0 ALC_ARATE2 0 ALC_ARATE1 0 ALC_ARATE0 0 Reserved Reserved 0 0 ALC_RRATE5 1 ALC_RRATE4 1 ALC_RRATE3 1 ALC_RRATE2 1 ALC_RRATE1 1 ALC_RRATE0 1 MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved 0 0 0 0 0 0 0 0 NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0 0 0 0 0 0 0 0 0 Reserved 0 SP_CLK ERR 0 Reserved 0 Reserved 1 SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL 0 0 0 0 0 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 35 CS53L21 6. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All "Reserved" registers must maintain their default state. 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) 7 Chip_ID4 6 Chip_ID3 5 Chip_ID2 4 Chip_ID1 3 Chip_ID0 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0 Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS53L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000. 6.2 Power Control 1 (Address 02h) 7 Reserved 6 Reserved 5 Reserved 4 PDN_PGAB 3 PDN_PGAA 2 PDN_ADCB 1 PDN_ADCA 0 PDN Notes: 1. To activate the power-down sequence for individual channels (A or B,) both channels must first be powered down either by enabling the PDN bit or by enabling the power-down bits for both channels. Enabling the power-down bit on an individual channel basis after the A/D has fully powered up will mute the selected channel without achieving any power savings. 2. Reserved bits 5 and 6 should always be set "high" by the user to minimize power consumption during normal operation. Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the select channels, 3.) disable the PDN bit. 36 DS700F1 CS53L21 Power Down PGA X (PDN_PGAX) Default: 0 0 - Disable 1 - Enable Function: PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control 1 (Address 02h) Note 1 above. This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to "ADCX Input Select Bits (AINX_MUX[1:0])" on page 42 for the required settings. Power Down ADC X (PDN_ADCX) Default: 0 0 - Disable 1 - Enable Function: ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page 36. Power Down (PDN) Default: 0 0 - Disable 1 - Enable Function: The entire A/D will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode. 6.3 MIC Power Control and Speed Control (Address 03h) 7 AUTO 6 SPEED1 5 SPEED0 4 3-ST_SP 3 PDN_MICB 2 PDN_MICA 1 PDN_MICBIAS 0 MCLKDIV2 Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable Function: Enables the autodetect circuitry for detecting the speed mode of the A/D when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 28. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio. DS700F1 37 CS53L21 Speed Mode (SPEED[1:0]) Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the A/D in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled (see Auto-Detect Speed Mode (AUTO) above). Tri-State Serial Port Interface (3ST_SP) Default: 0 0 - Disable 1 - Enable Function: When enabled and the device is configured as a master, all serial port outputs (clocks and data) are placed in a high impedance state. If the serial port is configured as a slave, only the SDOUT pin will be placed in a high-impedance state. The other signals will remain as inputs. Power Down MIC X (PDN_MICX) Default: 1 0 - Disable 1 - Enable Function: When enabled, the microphone preamp for channel x will be in a power-down state. Power Down MIC BIAS (PDN_MICBIAS) Default: 1 0 - Disable 1 - Enable Function: When enabled, the microphone bias circuit will be in a power-down state. MCLK Divide By 2 (MCLKDIV2) Default: 0 0 - Disabled 1 - Divide by 2 Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode. 38 DS700F1 CS53L21 6.4 Interface Control (Address 04h) 7 Reserved 6 M/S 5 Reserved 4 Reserved 3 Reserved 2 ADC_IS/LJ 1 DIGMIX 0 MICMIX Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port. ADC IS or Left-Justified (ADC_IS/LJ) Default: 0 0 - Left-Justified 1 - IS Function: Selects either the IS or Left-Justified digital interface format for the data on SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in this section "Digital Interface Formats" on page 30. Digital Mix (DIGMIX) Default: 0 DIGMIX 0 1 SPE_ENABLE x 0 1 Mix Selected ADC data to ADC serial port, SDOUT data. Reserved SPE Processed ADC data to ADC serial port, SDOUT data. Function: Routes the ADC outputs to the serial port SDOUT pin. DIGMIX selects either "raw" ADC data or SPE processed ADC data to SDOUT. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional. Microphone Mix (MICMIX) Default: 0 0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT. 1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT. Function: Selects between the ADC stereo mix or a differential mix of analog inputs A and B. DS700F1 39 CS53L21 6.5 MIC Control (Address 05h) 7 ADC_SNGVOL 6 5 4 3 2 ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0 1 0 MICB_BOOST MICA_BOOST ADC Single Volume Control (ADC_SNGVOL) Default: 0 0 - Disabled 1 - Enabled Function: The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL bit is enabled and the ALC_ENB control register is ignored. ADCx 20 dB Digital Boost (ADCx_DBOOST) Default: 0 0 - Disabled 1 - Enabled Function: Applies a 20 dB digital gain to the input signal on ADC channel x, regardless of the input path. MIC Bias Select (MICBIAS_SEL) Default: 0 0 - MICBIAS on AIN3B/MICIN2 pin 1 - MICBIAS on AIN2B pin Function: Determines the output pin for the internally generated MICBIAS signal. If set to `0'b, the MICBIAS is output on the AIN3B/MICIN2 pin. If set to `1'b, the MICBIAS is output on the AIN2B pin. MIC Bias Level (MICBIAS_LVL[1:0]) Default: 00 00 - 0.8 x VA 01 - 0.7 x VA 10 - 0.6 x VA 11 - 0.5 x VA Function: Determines the output voltage level of the MICBIAS output. 40 DS700F1 CS53L21 MIC X Preamplifier Boost (MICX_BOOST) Default: 0 0 - +16 dB Gain 1 - +32 dB Gain Function: Determines the amount of gain applied to the microphone preamplifier for channel x. 6.6 ADC Control (Address 06h) 7 6 5 4 ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ 3 SOFTB 2 ZCROSSB 1 SOFTA 0 ZCROSSA ADCX High-Pass Filter Enable (ADCX_HPFEN) Default: 1 0 - High-pass filter is disabled 1 - High-pass filter is enabled Function: When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to `0', the high-pass filter will be disabled. For DC measurements, this bit must be cleared to `0'. "ADC Digital Filter Characteristics" on page 14. ADCX High-Pass Filter Freeze (ADCX_HPFRZ) Default: 0 0 - Continuous DC Subtraction 1 - Frozen DC Subtraction Function: The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC offset is frozen, and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to `1'. See "ADC Digital Filter Characteristics" on page 14. Soft Ramp CHX Control (SOFTX) Default: 0 0 - Disabled 1 - Enabled Function: Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital attenuation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period. PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods. Soft Ramp and Zero Cross Enabled When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps and be implemented on a signal zero crossing. DS700F1 41 CS53L21 Zero Cross CHX Control (ZCROSSX) Default: 0 0 - Disabled 1 - Enabled Function: Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp and Zero Cross Enabled When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps and be implemented on a signal zero crossing. The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit. 6.7 SOFTx ZCROSSx Analog PGA Volume (PGAx_VOL[4:0]) Digital Attenuator (ADCx_ATT[7:0]) 0 0 Volume changes immediately. 0 1 Volume changes at next zero cross time. Volume changes immediately. 1 0 Volume changes in 0.5 dB steps. Change volume in 0.125 dB steps. 1 1 Volume changes in 0.5 dB steps at every signal zero-cross. Change volume in 0.125 dB steps. Volume changes immediately. ADCx Input Select, Invert and Mute (Address 07h) 7 AINB_MUX1 6 AINB_MUX0 5 AINA_MUX1 4 AINA_MUX0 3 INV_ADCB 2 INV_ADCA 1 0 ADCB_MUTE ADCA_MUTE ADCX Input Select Bits (AINX_MUX[1:0]) Default: 00 PDN_PGAx AINx_MUX[1:0] 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11 Selected Path to ADC AIN1x-->PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx AIN1x AIN2x AIN3x/MICINx Reserved Function: Selects the specified analog input signal into ADCx. The microphone preamp is only available when PDN_PGAx is disabled. See Figure 21. 42 DS700F1 CS53L21 AIN1x AIN2x AIN1x AIN3x AIN2x MUX MUX ADC PGA +16/ 32 dB AIN3x / MICINx Decoder AINx_MUX[1:0] PDN_PGAx Figure 21. AIN and PGA Selection ADCX Invert Signal Polarity (INV_ADCX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the ADC x channel. ADCX Channel Mute (ADCX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit (SOFT). 6.8 SPE Control (Address 09h) 7 Reserved 6 SPE_ENABLE 5 FREEZE 4 Reserved 3 Reserved 2 Reserved 1 SPE_SZC1 0 SPE_SZC0 SPE_ENABLE Default: 0 0 - Reserved 1 - ADC Serial Port to SPE Function: Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional. Freeze Controls (FREEZE) Default: 0 Function: DS700F1 43 CS53L21 This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. Note: 1. This bit should only be used to synchronize run-time controls, such as volume and mute, during normal operation. Using this bit before the relevant circuitry begins normal operation could cause the change to take effect immediately, ignoring the FREEZE bit. SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step. Zero Cross This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. 44 DS700F1 CS53L21 6.9 ALCX and PGAX Control: ALCA, PGAA (Address 0Ah) and ALCB, PGAB (Address 0Bh) 7 6 ALCX_SRDIS ALCX_ZCDIS 5 Reserved 4 PGAX_VOL4 3 PGAX_VOL3 2 PGAX_VOL2 1 PGAX_VOL1 0 PGAX_VOL0 ALCX Soft Ramp Disable (ALCX_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the soft ramp setting. ALC volume-level changes will take effect in one step. ALCX Zero Cross Disable (ALCX_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step. PGA X Gain Control (PGAX_VOL[4:0]) Default: 00000 Binary Code Volume Setting 11000 *** 01010 *** 00000 11111 11110 *** 11001 11010 +12 dB *** +5 dB *** 0 dB -0.5 dB -1 dB *** -3 dB -3 dB Function: The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx and ZCROSSx) from +12 dB to -3 dB. Gain settings are decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft and Zero Cross bits (ALCX_SRDIS and ALCX_ZCDIS). Note: DS700F1 When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manually. 45 CS53L21 6.10 ADCx Attenuator: ADCA (Address 0Ch) and ADCB (Address 0Dh) 7 ADCx_ATT7 6 ADCx_ATT6 5 ADCx_ATT5 4 ADCx_ATT4 3 ADCx_ATT3 2 ADCx_ATT2 1 ADCx_ATT1 0 ADCx_ATT0 ADCX Attenuation Control (ADCX_ATT[7:0]) Default: 00h Binary Code Volume Setting 0111 1111 *** 0000 0000 1111 1111 1111 1110 *** 1010 0000 *** 1000 0000 0 dB *** 0 dB -1 dB -2 dB *** -96 dB *** -96 dB Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx and ZCROSSx) from 0 to -96 dB. Levels are decoded in two's complement, as shown in the table above. Note: 6.11 When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually. ADCx Mixer Volume Control: ADCA (Address 0Eh) and ADCB (Address 0Fh) 7 6 5 4 3 2 1 0 MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0 Note: The SPE_ENABLE bit in reg09h must be set to 1 to enable function control in this register. ADCX Mixer Channel Mute (MUTE_ADCMIXX) Default: 1 0 - Disabled 1 - Enabled Function: The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by the SPEX Soft and Zero Cross bits (SPEX_SZC[1:0]). ADCX Mixer Volume Control (ADCMIXX_VOL[6:0]) Default = 000 0000 46 Binary Code Volume Setting 001 1000 *** 000 0000 111 1111 111 1110 *** +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** DS700F1 CS53L21 Binary Code Volume Setting 001 1001 -51.5 dB Function: The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the SPEX Soft and Zero Cross bits (SPE_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the table above. 6.12 Channel Mixer (Address 18h) 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 ADCA1 2 ADCA0 1 ADCB1 0 ADCB0 Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control in this register. Channel Mixer (ADCx[1:0]) Default: 00 ADCA[1:0] SDOUT ADCB[1:0] SDOUT 00 L 00 R 01 10 11 L+R -----------2 R 01 10 11 L+R -----------2 L Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. 6.13 ALC Enable and Attack Rate (Address 1Ch) 7 ALC_ENB 6 ALC_ENA 5 4 3 2 1 0 ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0 ALC Enable (ALC_ENX) Default: 0 0 - Disabled 1 - Enabled Function: Enables automatic level control for ADC channel x. Notes: 1. When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually. 2. The ALC should only be configured while the power down bit is enabled. DS700F1 47 CS53L21 ALC Attack Rate (ARATE[5:0]) Default: 000000 Binary Code Attack Time 000000 *** 111111 Fastest Attack *** Slowest Attack Function: Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the ALC threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx and ZCROSSx bit settings unless the disable bit for each function is enabled. 6.14 ALC Release Rate (Address 1Dh) 7 Reserved 6 Reserved 5 4 3 2 1 0 ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0 ALC Release Rate (RRATE[5:0]) Default: 111111 Binary Code Release Time 000000 *** 111111 Fastest Release *** Slowest Release Function: Sets the rate at which the ALC releases the PGA and digital attenuation from levels below the minimum setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] and ADCx_ATT[7:0] setting. The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx and ZCROSS bit settings unless the disable bit for each function is enabled. 6.15 ALC Threshold (Address 1Eh) 7 MAX2 6 MAX1 5 MAX0 4 MIN2 3 MIN1 2 MIN0 1 Reserved 0 Reserved Maximum Threshold (MAX[2:0]) Default: 000 MAX[2:0] Threshold Setting (dB) 48 000 0 001 -3 010 -6 011 -9 100 -12 101 -18 110 -24 111 -30 DS700F1 CS53L21 Function: Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack rate. Minimum Threshold (MIN[2:0]) Default: 000 MIN[2:0] Threshold Setting (dB) 000 0 001 -3 010 -6 011 -9 100 -12 101 -18 110 -24 111 -30 Function: Sets the minimum level at which to disengage the ALC's attenuation or amplify the input signal at a rate set in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the minimum setting. This provides a more natural sound as the ALC attacks and releases. 6.16 Noise Gate Configuration and Misc. (Address 1Fh) 7 NG_ALL 6 NG_EN 5 NG_BOOST 4 THRESH2 3 THRESH1 2 THRESH0 1 NGDELAY1 0 NGDELAY0 Noise Gate Channel Gang (NG_ALL) Default: 0 0 - Disabled 1 - Enabled Function: Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect. Noise Gate Enable (NG_EN) Default: 0 0 - Disabled 1 - Enabled Function: Enables the noise gate. Maximum attenuation is relative to all gain settings applied. DS700F1 49 CS53L21 Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0]) Default: 000 THRESH[2:0] Minimum Setting (NG_BOOST = `0'b) Minimum Setting (NG_BOOST = `1'b) 000 001 010 011 100 101 110 111 -64 dB -67 dB -70 dB -73 dB -76 dB -82 dB Reserved Reserved -34 dB -37 dB -40 dB -43 dB -46 dB -52 dB -58 dB -64 dB Function: Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST = `1'b adds 30 dB to the threshold settings. Noise Gate Delay Timing (NGDELAY[1:0]) Default: 00 00 - 50 ms 01 - 100 ms 10 - 150 ms 11 - 200 ms Function: Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx and ZCROSS bit settings unless the disable bit for each function is enabled. 6.17 Status (Address 20h) (Read Only) 7 Reserved 6 SP_CLKERR 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 ADCA_OVFL 0 ADCB_OVFL For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A "0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Serial Port Clock Error (SP_CLK Error) Default: 0 Function: Indicates an invalid MCLK to LRCK ratio. See "Serial Port Clocking" on page 28"Serial Port Clocking" on page 28 for valid clock ratios. Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. ADC Overflow (ADCX_OVFL) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the associated ADCs. 50 DS700F1 CS53L21 7. ANALOG PERFORMANCE PLOTS 7.1 ADC_FILT+ Capacitor Effects on THD+N The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion + noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N at low frequencies. Figure 22 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB53L21 using an Audio Precision analyzer. -60 1 F -64 -68 10 F -72 22 F -76 d B F S -80 Legend - Capacitor Value on ADC_FILT+ -84 -88 -92 -96 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 22. ADC THD+N vs. Frequency w/Capacitor Effects 8. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled DS700F1 Sample Rate LRCK (kHz) 1024x 1536x MCLK (MHz) 2048x* 8 11.025 12 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 512x 768x 16 22.05 24 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 256x 384x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 3072x* 24.5760 33.8688 36.8640 MCLK (MHz) 1024x* 1536x* 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 MCLK (MHz) 512x* 16.3840 22.5792 24.5760 768x* 24.5760 33.8688 36.8640 51 CS53L21 Sample Rate LRCK (kHz) 128x 64 88.2 96 8.1920 11.2896 12.2880 MCLK (MHz) 192x 256x* 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 384x* 24.5760 33.8688 36.8640 *The"MCLKDIV2" pin 4 must be set HI. 8.2 Auto Detect Disabled Sample Rate LRCK (kHz) 512x 8 11.025 12 6.1440 768x MCLK (MHz) 1024x 1536x 2048x 3072x 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 256x 384x 512x 16 22.05 24 6.1440 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 Sample Rate LRCK (kHz) 256x 32 44.1 48 8.1920 11.2896 12.2880 Sample Rate LRCK (kHz) 128x 64 88.2 96 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 MCLK (MHz) 768x 12.2880 16.9344 18.4320 1024x 1536x 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 MCLK (MHz) 384x 512x 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 MCLK (MHz) 192x 256x 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 9. PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS53L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS53L21 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS53L21 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS53L21 evaluation board demonstrates the optimum layout and power supply arrangements. 52 DS700F1 CS53L21 9.2 QFN Thermal Pad The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS53L21 evaluation board demonstrates the optimum thermal pad and via configuration. 10.DIGITAL FILTERS DS700F1 Figure 23. ADC Passband Ripple Figure 24. ADC Stopband Rejection Figure 25. ADC Transition Band Figure 26. ADC Transition Band Detail 53 CS53L21 11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 54 DS700F1 CS53L21 12.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING Dimension A A1 A3 b D D2 e E E2 L aaa bbb ddd eee MIN 0.80 0.00 0.20 3.50 3.50 0.35 Millimeters NOM 0.90 0.02 0.20 REF 0.25 5.00 BSC 3.65 0.50 BSC 5.00 BSC 3.65 0.40 0.15 0.10 0.05 0.08 MAX 1.00 0.05 MIN 0.031 0.000 0.30 0.008 3.80 0.138 3.80 0.45 0.138 0.014 Inches NOM 0.035 0.001 0.008 REF 0.010 0.197 BSC 0.144 0.020 BSC 0.197 BSC 0.144 0.016 0.006 0.004 0.002 0.003 MAX 0.039 0.002 0.012 0.150 0.150 0.018 1. Controlling dimensions are in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M. 3. This drawing conforms to JEDEC outline MO-220, variation VHHD-4. 4. Recommended reflow profile is per JEDEC/IPC J-STD-020 THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance DS700F1 2 Layer Board 4 Layer Board Symbol Min Typ Max Units JA - 52 38 - C/Watt 55 CS53L21 13.ORDERING INFORMATION Product Description Package Pb-Free CS53L21 Low-Power Stereo A/D 32L-QFN Yes CDB53L21 CS53L21 Evaluation Board - No Grade Temp Range Container Rail Commercial -10 to +70 C Tape and Reel Rail Automotive -40 to +85 C Tape and Reel - - - Order # CS53L21-CNZ CS53L21-CNZR CS53L21-DNZ CS53L21-DNZR CDB53L21 14.REFERENCES 1. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com 15.REVISION HISTORY Revision F1 JUL `15 Changes Updated voltage range in "Specified Operating Conditions" on page 11. Corrected Max passband frequency in "ADC Digital Filter Characteristics" on page 14. Updated Section 4.8 "Recommended Power-Up Sequence" on page 30. Updated Section 4.10 "Software Mode" on page 31. Added note 1 in the FREEZE control register in "SPE Control (Address 09h)" on page 43. Added note 2 in the ALC Enable register in "ALC Enable and Attack Rate (Address 1Ch)" on page 47. Replaced the package drawing, notes, and dimensions table in Section 12. "Package Dimensions" on page 55. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either "Cirrus Logic" or "Cirrus") are sold subject to Cirrus Logic's terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). 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This document and its information is provided "AS IS" without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners. Copyright (c) 2005-2015 Cirrus Logic, Inc. All rights reserved. SPI is a trademark of Motorola. 56 DS700F1