February 2009 Rev 4 1/22
22
L6390
High-voltage high and low side driver
Features
■High voltage rail up to 600 V
■dV/dt immunity ± 50 V/nsec in full temperature
range
■Driver current capability:
– 290 mA source,
– 430 mA sink
■Switching times 75/35 nsec rise/fall with
1 nF load
■3.3 V, 5 V TTL/CMOS inputs with hysteresis
■Integrated bootstrap diode
■Operational amplifier for advanced current
sensing
■Comparator for fault protections
■Smart shut down function
■Adjustable dead-time
■Interlocking function
■Compact and simplified layout
■Bill of material reduction
■Effective fault protection
■Flexible, easy and fast design
Applications
■Motor driver for home appliances, factory
automation, industrial drives.
■HID ballasts, power supply units.
Description
The L6390 is a high-voltage device manufactured
with the BCD “OFF-LINE” technology. It is a single
chip half-bridge gate driver for N-channel power
MOSFET or IGBT.
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
The IC embeds an operational amplifier suitable
for advanced current sensing in applications such
as field oriented motor control.
An integrated comparator is available for
protections against over-current,
over-temperature, etc.
SO
-
16
D
IP
-
16
Table 1. Device summary
Order codes Package Packaging
L6390 DIP-16 Tube
L6390D SO-16 Tube
L6390D013TR SO-16 Tape and reel
www.st.com
Contents L6390
2/22
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L6390 Block diagram
3/22
1 Block diagram
Figure 1. Block diagram
UV
DETECTION
LEVEL
SHIFTER
BOOTSTRAP DRIVER
S
V
CC
LVG
DRIVER
HIN
LIN
HVG
DRIVER
HVG
BOOT
OUT
LVG
UV
DETECTION
OP+
OP-
GND
OPOUT
SD/OD
DT
OPAMP
DEAD
TIME
R
LOGIC
SHOOT
THROUGH
PREVENTION
SD
LATCH
FLOATING STRUCTURE
COMPARATOR
+
V
REF
CP+
1
211
14
15
16
7
5
8
3
4
10
9
6
SMART
SD
from LVG
VCC
VCC
5V
+
-
+
-
5V
Pin connection L6390
4/22
2 Pin connection
Figure 2. Pin connection (top view)
Table 2. Pin description
Pin n # Pin name Type Function
1LIN I Low side driver logic input (active low)
2SD/OD (1)
1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows
omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
I/O Shut down logic input (active low)/open drain
(comparator output)
3 HIN I High side driver logic input (active high)
4 VCC P Lower section supply voltage
5 DT I Dead time setting
6 OP- I Opamp inverting input
7 OPOUT O Opamp output
8 GND P Ground
9 OP+ I Opamp non inverting input
10 CP+ I Comparator input
11 LVG (1) O Low side driver output
12, 13 NC Not connected
14 OUT P High side (Floating) common voltage
15 HVG (1) O High side driver output
16 BOOT P Bootstrap supply voltage
HIN
SD/OD
LIN
VCC
1
3
2
4NC
OUT
HVG
BOO
T
16
15
14
13
OPOUT
OP-
DT
CP+
LVG
NC12
11
10
9
5
7
6
8OP+
GND
L6390 Truth table
5/22
3 Truth table
Note: X: don't care
Table 3. Truth table
Input Output
SD LIN HIN LVG HVG
LXXLL
HHL L L
HLHLL
HLLHL
HHHLH
Electrical data L6390
6/22
4 Electrical data
4.1 Absolute maximum ratings
Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 1 kV (human body model)
4.2 Thermal data
Table 4. Absolute maximum rating
Symbol Parameter
Value
Unit
Min Max
Vcc Supply voltage - 0.3 21 V
Vout Output voltage Vboot - 21 Vboot + 0.3 V
Vboot Bootstrap voltage - 0.3 620 V
Vhvg High side gate output voltage Vout - 0.3 Vboot + 0.3 V
Vlvg Low side gate output voltage - 0.3 Vcc + 0.3 V
Vop+ OPAMP non-inverting input - 0.3 Vcc + 0.3 V
Vop- OPAMP inverting input - 0.3 Vcc + 0.3 V
Vcp+ Comparator input voltage - 0.3 Vcc + 0.3 V
ViLogic input voltage - 0.3 15 V
Vod Open drain voltage - 0.3 15 V
dVout/dt Allowed output slew rate 50 V/ns
Ptot Total power dissipation (TA = 25 °C) 800 mW
TJJunction temperature 150 °C
Tstg Storage temperature -50 150 °C
Table 5. Thermal data
Symbol Parameter SO-16 DIP-16 Unit
R
th(JA)
Thermal resistance junction to ambient 155 100 °C/W
L6390 Electrical data
7/22
4.3 Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Pin Parameter Test condition Min Max Unit
Vcc 4 Supply voltage 12.5 20 V
VBO (1)
1. VBO = Vboot - Vout
16-14 Floating supply voltage 12.4 20 V
Vout 14 DC output voltage - 9 (2)
2. LVG off. Vcc = 12.5 V
Logic is operational if Vboot > 5 V
Refer to AN2738 for more details
580 V
fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz
TJJunction temperature -40 125 °C
Electrical characteristics L6390
8/22
5 Electrical characteristics
5.1 AC operation
Table 7. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
t
on
1 vs 11
3 vs 15
High/low side driver turn-on
propagation delay V
out
= 0 V
Vboot = V
cc
CL = 1 nF
Vi = 0 to 3.3 V
See Figure 3.
125 200 ns
t
off
High/low side driver turn-off
propagation delay 125 200 ns
t
sd
2 vs
11, 15
Shut down to high/low side
driver propagation delay 125 200 ns
t
isd
Comparator triggering to
high/low side driver turn-off
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin CP+. 200 250 ns
MT Delay matching, HS and LS
turn-on/off 30 ns
DT 5 Dead time setting range (1)
RDT = 0, C
L
= 1 nF,
CDT = 100 nF 0.1 0.18 0.25 μs
RDT = 37 kΩ, C
L
= 1 nF,
CDT = 100 nF 0.48 0.6 0.72 μs
RDT = 136 kΩ, C
L
= 1 nF,
CDT = 100 nF 1.35 1.6 1.85 μs
RDT = 260 kΩ, C
L
= 1 nF,
CDT = 100 nF 2.6 3.0 3.4 μs
MDT Matching dead time (2)
RDT = 0, C
L
= 1 nF,
CDT = 100 nF 80 ns
RDT = 37 kΩ, C
L
= 1 nF,
CDT = 100 nF 120 ns
RDT = 136 kΩ, C
L
= 1 nF,
CDT = 100 nF 250 ns
RDT = 260 kΩ, C
L
= 1 nF,
CDT = 100 nF 400 ns
t
r
11, 15 Rise time C
L
= 1 nF 75 120 ns
t
f
Fall time C
L
= 1 nF 35 70 ns
1. See Figure 4 on page 9
2. MDT = | DTLH - DTHL | see Figure 5 on page 13
L6390 Electrical characteristics
9/22
Figure 3. Timing
Figure 4. Typical dead time vs. DT resistor value
HIN
HVG
50%
10%
90%
50%
trtf
ton toff
90%
10%
LIN
LVG
50%
10%
90%
50%
trtf
ton toff
90%
10%
LVG/HVG
SD
90%
50%
tf
tsd
10%
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Electrical characteristics L6390
10/22
5.2 DC operation
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section
Vcc_hys
4
Vcc UV hysteresis 1200 1500 1800 mV
Vcc_thON Vcc UV turn ON threshold 11.5 12 12.5 V
Vcc_thOFF Vcc UV turn OFF threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent
supply current
Vcc = 10 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
120 150 μA
I
qcc
Quiescent current
V
cc
= 15 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
720 1000 μA
V
ref
Internal reference voltage 500 540 580 mV
Bootstrapped supply voltage section (1)
VBO_hys
16
VBO UV hysteresis 1200 1500 1800 mV
VBO_thON VBO UV turn ON threshold 10.6 11.5 12.4 V
VBO_thOFF VBO UV turn OFF threshold 9.1 10 10.9 V
I
QBOU
Undervoltage VBO quiescent
current
V
BO
= 9 V
SD = 5 V; LIN and
HIN = 5 V;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
70 110 μA
I
QBO
VBO quiescent current
V
BO
= 15 V
SD = 5 V; LIN and
HIN = 5 V;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
150 210 μA
ILK High voltage leakage current Vhvg = Vout = Vboot = 600 V 10 μA
R
DS(on)
Bootstrap driver on
resistance (2) LVG ON 120 Ω
Driving buffers section
I
so
11,
15
High/low side source short
circuit current V
IN
= V
ih
(t
p
< 10 μs) 200 290 mA
I
si
High/low side sink short
circuit current V
IN
= V
il
(tp < 10 μs) 250 430 mA
L6390 Electrical characteristics
11/22
Logic inputs
V
il
1, 2, 3 Low logic level voltage 0.8 V
V
ih
High logic level voltage 2.25 V
Vil_S
1, 3 Single input voltage LIN and HIN connected
together and floating 0.8 V
I
HINh
3
HIN logic “1” input bias
current HIN = 15 V 110 175 260 μA
I
HINl
HIN logic “0” input bias
current HIN = 0 V 1 μA
ILINl
1
LIN logic “0” input bias
current LIN = 0 V 3 6 20 μA
ILINh
LIN logic “1” input bias
current LIN = 15 V 1 μA
I
SDh
2
SD logic “1” input bias
current SD = 15 V 10 40 100 μA
I
SDl
SD logic “0” input bias
current SD = 0 V 1 μA
1. VBO = Vboot - Vout
2. RDSON is tested in the following way:
RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]
where I1 is pin 16 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)
Symbol Pin Parameter Test condition Min Typ Max Unit
Electrical characteristics L6390
12/22
Table 9. OPAMP characteristics (VCC = 15 V, TJ = +25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
Vio
6, 9
Input offset voltage Vic = 0 V, Vo = 7.5 V 6 mV
Iio Input offset current Vic = 0 V, Vo = 7.5 V 440nA
Iib Input bias current (1) 100 200 nA
V
icm
Input common mode voltage
range 0V
V
OL
7
Low level output voltage RL = 10 kΩ to VCC 75 150 mV
V
OH
High level output voltage RL = 10 kΩ to GND 14 14.7 V
I
o
Output short circuit current
Source,
Vid = +1; Vo = 0 V 16 30 mA
Sink,
Vid = -1; Vo = VCC
50 80 mA
SR Slew rate Vi = 1 ÷ 4 V; CL = 100 pF;
unity gain 2.5 3.8 V/μs
GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz
Avd Large signal voltage gain RL = 2 kΩ70 85 dB
SVR Supply voltage rejection ratio vs. VCC 60 75 dB
CMRR Common mode rejection
ratio 55 70 dB
1. The direction of input current is out of the IC.
Table 10. Sense comparator characteristics (VCC = 15 V, TJ = +25 °C)
Symbol Pin Parameter Test conditions Min Typ Max Unit
Iib 10 Input bias current VCP+ = 1 V 1 μA
V
ol
2Open drain low level output
voltage Iod = - 3 mA 0.5 V
t
d_comp
Comparator delay SD/OD pulled to 5 V
through 100 kΩ resistor 90 130 ns
SR 2 Slew rate CL = 180 pF; Rpu = 5 kΩ60 V/μsec
L6390 Waveforms definitions
13/22
6 Waveforms definitions
Figure 5. Dead time and interlocking waveforms definitions
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DTLH DTHL
DTLH DTHL
DTLH DTHL
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
(*) HIN and LIN can be connected togheter and driven by just one control signal
INTERLOCKING
INTERLOCKING
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
Smart shut down function L6390
14/22
7 Smart shut down function
L6390 integrates a comparator committed to the fault sensing function. The comparator has
an internal voltage reference Vref connected to the inverting input, while the non-inverting
input is available on pin 10. The comparator input can be connected to an external shunt
resistor in order to implement a simple over-current detection function. The output signal of
the comparator is fed to an integrated MOSFET with the open drain output available on pin
2, shared with the SD input. When the comparator triggers, the device is set in shut down
state and both its outputs are set to low level leaving the half-bridge in tri-state.
Figure 6. Smart shut down timing waveforms
HIN/LIN
HVG/LVG
SD/OD
open drain gate
(internal)
upper
threshold
lower
threshold
comp
Vref
CP+
PROTECTION
Fast shut down:
the driver outputs are set in SD state
immediately after the comparator
triggering even if the SD signal
has not yet reach
the lower input threshold
real disable time
2
1
1
2
= (RON_OD // RSD) CSD
= RSD CSD
SD/OD
FROM/TO
CONTROLLER
VBIAS
SMART
SD
LOGIC
C
SD
RSD
R
ON_OD
SHUT DOWN CIRCUIT
TIME CONSTANTS
L6390 Smart shut down function
15/22
In common over-current protection architectures the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Differently from the common fault detection systems, L6390 Smart shut down architecture
allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the
propagation delay between the fault detection event and the actual outputs switch-off. In fact
the time delay between the fault and the outputs turn off is no more dependent on the RC
value of the external network connected to the pin. In the smart shut down circuitry, the fault
signal has a preferential path which directly switch off the outputs after the comparator
triggering. At the same time the internal logic turns on the open drain output and holds it on
until the SD voltage goes below the SD logic input lower threshold. The Smart shut down
system provides the possibility to increase the time constant of the external RC network
(that is the disable time after the fault event) up to very large values without increasing the
delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
Typical application diagram L6390
16/22
8 Typical application diagram
Figure 7. Application diagram
UV
DETECTION
LEVEL
SHIFTER
BOOTSTRAP DRIVER
S
VCC LVG
DRIVER
VCC
HIN
LIN
HVG
DRIVER
HVG
BOOT
H.V.
TO LOAD
OUT
LVG
Cboot
UV
DETECTION
+
-
OP+
OP-
GND
OPOUT
SD/OD
DT
OPAMP
DEAD
TIME
R
LOGIC
SHOOT
THROUGH
PREVENTION
FLOATING STRUCTURE
+
-
COMPARATOR
+
VREF
CP+
SD
LATCH
5V
1
211
14
15
16
7
5
8
3
4
10
9
6
SMART
SD
from LVG
+
FROM CONTROLLER
FROM CONTROLLER
FROM/TO
CONTROLLER
TO ADC
VBIAS
VBIAS
VCC
VCC
5V
L6390 Bootstrap driver
17/22
9 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 8.a). In the L6390 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure
8.b.
An internal charge pump (Figure 8.b) provides the DMOS driving voltage.
9.1 CBOOT selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent
capacitor. This capacitor C
EXT
is related to the MOS total gate charge:
Equation 1
The ratio between the capacitors C
EXT
and C
BOOT
is proportional to the cyclical voltage loss.
It has to be:
Equation 2
CBOOT >>> CEXT
e.g.: if Q
gate
is 30 nC and V
gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the C
BOOT
selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 μA, so if HVG T
ON
is 5 ms, C
BOOT
has
to supply 1 μC to C
EXT
. This charge on a 1 μF capacitor means a voltage drop of 1V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DSon
(typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
CEXT
Qgate
Vgate
--------------=
Bootstrap driver L6390
18/22
where Q
gate
is the gate charge of the external power MOS, R
dson
is the on resistance of the
bootstrap DMOS and T
charge
is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap
DMOS is about 1 V, if the T
charge
is 5 μs. In fact:
Equation 4
V
drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 8. Bootstrap driver
Vdrop Ich earg Rdson Vdrop
→Qgate
Tch earg
------------------ Rdson
==
Vdrop
30nC
5μs
---------------120Ω0.7V∼⋅=
TO LOAD
D99IN1067
H.V.
HVG
ab
LVG
HVG
LVG
C
BOOT
TO LOAD
H.V.
C
BOOT
D
BOOT
BOOT
V
CC
V
CC
OUT OUT
BOOT
L6390 Package mechanical data
19/22
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 9. DIP-16 mechanical data and package dimensions
DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
Package mechanical data L6390
20/22
Figure 10. SO-16 narrow mechanical data and package dimensions
DIMENSIONS
REF. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.004 0.008
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S 8° (max.)
PACKAGE AND
PACKING INFORMATION
SO-16
Weight: not available
16-LEAD SMALL OUTLINE
PACKAGE
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45°(typ.)
D(1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F(1) 3.8 4.0 0.150 0.157
G 4.60 5.30 0.181 0.208
L 0.4 1.27 0.150 0.050
M 0.62 0.024
S8° (max.)
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
SO16 (Narrow)
0016020 D
L6390 Revision history
21/22
11 Revision history
Table 11. Document revision history
Date Revision Changes
29-Feb-2008 1 First release
09-Jul-2008 2 Updated: Cover page, Table 2 on page 4, Table 3 on page 5,
Section 4 on page 6, Section 5 on page 8, Section 9.1 on page 17
17-Sep-2008 3 Updated test condition values on Ta bl e 8 and Ta b l e 9
17-Feb-2009 4 Updated Table 7 on page 8, Table 8 on page 10, Table 9 on page 11
Added Table 4 on page 9
L6390
22/22
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