● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
TN2640
Features
Low threshold (2.0V max.)
High input impedance
Low input capacitance
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
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General Description
This low threshold enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
N-Channel Enhancement-Mode
Vertical DMOS FETs
-G indicates package is RoHS compliant (‘Green’)
* MIL visual screening available
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55°C to +150°C
Soldering temperature* +300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Pin Configurations
Ordering Information
Device
Package Options BVDSS/BVDGS
(V)
RDS(ON)
(max)
(Ω)
VGS(th)
(max)
(V)
ID(ON)
(min)
(A)
TO-252 (D-PAK) 8-Lead SOIC TO-92 Die*
TN2640 TN2640K4-G TN2640LG-G TN2640N3-G TN2640ND 400 5.0 2.0 2.0
TO-252 (D-PAK) (K4)
TO-92 (N3)
8-Lead SOIC (LG)
GATE
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
SOURCE
N/C
N/C
DRAIN
DRAIN
DRAIN
DRAIN
2
TN2640
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Thermal Characteristics
Package
ID
(continuous)†
(mA)
ID
(pulsed)
(A)
Power Dissipation
@TA = 25OC
(W)
θjc
(OC/W)
θja
(OC/W)
IDR
†
(mA)
IDRM
(A)
TO-252 (D-PAK) 500 3.0 2.5‡6.25 50 500 3.0
8-Lead SOIC 260 2.0 1.3‡24 96‡260 2.0
TO-92 220 2.0 0.74 125 170 220 2.0
Notes:
† ID (continuous) is limited by max rated Tj.
‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm
Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 400 - - V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage 0.8 - 2.0 V VGS = VDS, ID = 2.0mA
ΔVGS(th) Change in VGS(th) with temperature - -2.5 -4.0 mV/OC VGS = VDS, ID = 2.0mA
IGSS Gate body leakage - 100 nA VGS = ±20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max rating
- - 1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current 1.5 3.5 - AVGS = 5.0V, VDS = 25V
2.0 4.0 - VGS = 10V, VDS = 25V
RDS(ON)
Static drain-to-source
on-state resistance
- 3.2 5.0 ΩVGS = 4.5V, ID = 500mA
- 3.0 5.0 VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/OC VGS = 10V, ID = 500mA
GFS Forward transconductance 200 330 - mmho VDS = 25V, ID = 100mA
CISS Input capacitance - 210 225
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance - 30 50
CRSS Reverse transfer capacitance - 8.0 15
8-Lead SOIC (LG)
Product Marking
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiTN
2640
Y Y W W
TO-252 (D-PAK) (K4)
TO-92 (N3)
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Si YYWW
TN2640
LLLLLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
N2640
LLLL
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
3
TN2640
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
90%
10%
90% 90%
10%
10%
PULSE
GENERATOR
VDD
RL
OUTPUT
D.U.T.
t
(ON)
td(ON)
t(OFF)
td(OFF)
tr
INPUT
INPUT
OUTPUT
10V
V
DD
RGEN
0V
0V
tf
N- Channel Switching Waveforms and Test Circuit
Sym Parameter Min Typ Max Units Conditions
td(ON) Turn-on delay time - 4.0 15
ns
VDD = 25V,
ID = 2.0A,
RGEN = 25Ω
trRise time - 15 20
td(OFF) Turn-off delay time - 20 25
tfFall time - 22 27
VSD Diode forward voltage drop - - 0.9 V VGS = 0V, ISD = 200mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.0A
Notes:
All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
1.
2.
Electrical Characteristics (TA = 25°C unless otherwise specified)
4
TN2640
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves
Output Characteristics
5.0
4.0
3.0
2.0
1.0
0
VDS (volts)
ID)
s
e
rep
m
a(
ID)serepma(
Saturation Characteristics
VDS (volts)
Maximum Rated Safe Operating Area
0 100010010
10
1.0
0.1
0.01
0.001
VDS (volts)
ID)ser
e
pma(
Thermal Response Characteristics
)dezilamron( ecna
t
siseR lamreh
T
1.0
0.8
0.6
0.4
0.2
0
0.001 100.01 0.1 1.0
tp (seconds)
Transconductance vs. Drain Current
2.0
1.6
1.2
0.8
0.4
0
0 2.01.0
GSF )sne
m
eis(
ID (amperes)
D
Power Dissipation vs. Temperature
0 15010050
3.0
2.4
1.8
1.2
0.6
0
1257525
TA (°C)
PD)sttaw(
TO-92
TC = 25°C
PD = 1.0W
SO-8
TO-92
T
A
= -55°C
V
DS
= 25V
010 20 30 5040 0 2 4 6 108
25°C
125°C
3.0 5.04.0
2.5
2.0
1.5
1.0
0.5
0
4V
8V
V
GS
= 10V
TO-92 (pulsed)
T
C
= 25°C
TO-92 (DC)
SO-8 (DC)
2V
4V
3V
6V 8V
2V
3V
6V
V
GS
= 10V
SO-8 (pulsed)
DPAK
DPAK (DC)
5
TN2640
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves (cont.)
Gate Drive Dynamic Characteristics
Q
G
(nanocoulombs)
V
S
G
)st
l
o
v(
T
j
(°C)
V
)ht(SG
)d
e
zil
am
ro
n
(
R
)N
O(
SD
)d
e
zilamro
n
(
V
TH
and R
DS
Variation with Temperature
On-Resistance vs. Drain Current
R
)NO(SD
)
s
m
ho
(
V
B
SSD
)
d
e
zilam
r
o
n
(
T
j
(°C)
Transfer Characteristics
V
GS
(volts)
I
D
)
s
erepma
(
Capacitance vs. Drain-to-Source Voltage
400
)sd
a
r
a
f
o
c
i
p( C
V
DS
(volts)
I
D
(amperes)
BV
DSS
Variation with Temperature
0 10 20 30 40
200
300
100
0
0 2 4 6 8 10
3.0
2.4
1.8
1.2
0.6
0
-50 0 50 100 150
1.15
1.10
1.05
1.00
0.95
0.90
10
8
6
4
2
0
1.4
1.2
1.0
0.8
0.6
0.4
10
8
6
4
2
012 34 5
-50 0 50 100 150
253pF
VDS = 10V
VDS = 40V
653pF
VGS = 10V
VGS = 5V
125°C
0 1.0 2.0 3.0 5.04.0
f = 1MHz
CISS
C
OSS
CRSS
0.9
2.2
1.8
1.4
1.0
0.6
0.2
25°C
T
A
= -55°C
V
DS
= 25V
0
V(th) @ 2mA
RDS(ON)@ 10V, 0.5A
6
TN2640
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3-Lead TO-252 D-PAK Package Outline (K4)
Note:
Although 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed.1.
1 2 3
4
L4 L5
b
b2
e
D1
E1
L1
L
Seating
Plane
A1
Gauge
Plane
θ
D
E
View B
Front View Side View
Rear View
View B
θ1
H
c2
A
L3
L2
b3
Note 1
Symbol A A1 b b2 b3 c2 D D1 E E1 e H L L1 L2 L3 L4 L5 θθ1
Dimen-
sion
(inches)
MIN .086 .000* .025 .030 .195 .018 .235 .205 .250 .170
.090
BSC
.370 .055
.108
REF
.020
BSC
.035 .025* .045 0O0O
NOM - - - - - - .240 - - - - .060 - - - - -
MAX .094 .005 .035 .045 .215 .035 .245 .217* .265 .182* .410 .070 .050 .040 .060 10O15O
JEDEC Registration TO-252, Variation AA, Issue E, June 2004.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-3TO252K4, Version E041309.
7
TN2640
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version 041309.
Note:
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
1.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2009 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8
TN2640
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2640
B060409
3-Lead TO-92 Package Outline (N3)
Symbol A b c D E E1 e e1 L
Dimensions
(inches)
MIN .170 .014†.014†.175 .125 .080 .095 .045 .500
NOM - - - - - - - - -
MAX .210 .022†.022†.205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
Seating Plane
1
2
3
Front View Side View
Bottom View
E1 E
D
e1
L
e
c
1 2 3
b
A