FN9181 Rev 4.00 Page 1 of 18
August 1, 2016
FN9181
Rev 4.00
August 1, 2016
ISL6752
ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier
Control
DATASHEET
The ISL6752 is a high-performance, low-pin count alternative
Zero-Voltage Switching (ZVS) full-bridge PWM controller. Like
Intersil’s ISL6551, it achieves ZVS operation by driving the upper
bridge FETs at a fixed 50% duty cycle while the lower bridge FETs
are trailing-edge modulated with adjustable resonant switching
delays. Compared to the more familiar phase-shifted control
method, this algorithm offers equivalent efficiency and improved
overcurrent and light load performance with less complexity in a
lower pin count package.
The ISL6752 features complemented PWM outputs for
Synchronous Rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
This advanced BiCMOS design features precision dead time
and resonant delay control and an oscillator adjustable to
2MHz operating frequency. Additionally, multi-pulse
suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
Related Literature
•AN1262, “Designing with the ISL6752, ISL6753 ZVS
Full-Bridge Controllers”
•AN1603, “ISL6752/54EVAL1Z ZVS DC/DC Power Supply
with Synchronous Rectifiers User Guide”
•AN1619, “Designing with ISL6752DBEVAL1Z and
ISL6754DBEVAL1Z Control Cards”
Features
• Adjustable resonant delay for ZVS operation
• Synchronous rectifier control outputs with adjustable
delay/advance
•Current-mode control
• 3% current limit threshold
• Adjustable dead time control
• 175µA start-up current
• Supply UVLO
• Adjustable oscillator frequency up to 2MHz
• Internal over-temperature protection
• Buffered oscillator sawtooth output
• Fast current sense to output delay
• Adjustable cycle-by-cycle peak current limit
• 70ns leading edge blanking
• Multi-pulse suppression
• Pb-free (RoHS compliant)
Applications
• ZVS full-bridge converters
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
Pin Configuration
ISL6752
(16 LD QSOP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
VADJ
VREF
VERR
CTBUF
RTD
RESDEL
CS
CT
VDD
OUTLR
OUTUL
OUTUR
OUTLLN
OUTLRN
GND
OUTLL
ISL6752
FN9181 Rev 4.00 Page 2 of 18
August 1, 2016
Ordering Information
PART NUMBER
(Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C)
PACKAGE
(RoHS COMPLIANT) PKG. DWG. #
ISL6752AAZA ISL 6752AAZ -40 to +105 16 Ld QSOP M16.15A
ISL6752/54EVAL1Z Evaluation Board
ISL6752DBEVAL1Z Evaluation Board
NOTES:
1. Add “T” suffix for 2.5k unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6752. For more information on MSL, please see tech brief TB363
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PARAMETERS ISL6754 ISL6753 ISL6752 ISL6551
Topology Zero-Voltage Switching (ZVS) Zero-Voltage Switching (ZVS) Zero-Voltage Switching
(ZVS)
Zero-Voltage-Switching
(ZVS)
Topology Characteristic Full-bridge ZVS Full-bridge ZVS Full-bridge ZVS Full-bridge ZVS
Control Mode Peak current-mode or voltage
mode
Peak current-mode or voltage
mode
Peak current-mode Peak current-mode
UVLO Rising (V) 8.75V 8.75V 8.75V 9.6V
UVLO Falling (V)7V7V7V8.6V
VBIAS (maximum) 20V 20V 20V 16V
No-Load Operating
Current
11mA (typica), 15.5mA
(maximum)
11mA (typical), 15.5mA
(maximum)
11mA (typical), 15.5mA
(maximum)
13mA
# of PWM Outputs6466
FET Driver IOUT
(maximum)
10mA 10mA 10mA 1A
Maximum Duty Cycle (%) 99 99 99 99
FN9181 Rev 4.00 Page 3 of 18
August 1, 2016
ISL6752
Functional Block Diagram
FIGURE 1. BLOCK DIAGRAM
OUTLL
OUTLR
OUTUL
OUTUR
VDD
PWM
STEERING
LOGIC
RESDEL
UVLO
OVER-
TEMPERATURE
PROTECTION
VREF
OSCILLATOR
CT
RTD
VDD
GND
VREF
+
-
0.33
80mV
VREF
50%
PWM
VERR
1mA
CTBUF
CS
PWM
COMPARATOR
+
-1.00V
OVERCURRENT
COMPARATOR
70ns
LEADING
EDGE
BLANKING
OUTLLN
OUTLRN
DELAY/
ADVANCE
TIMING
CONTROL
VADJ
FN9181 Rev 4.00 Page 4 of 18
August 1, 2016
ISL6752
Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter
FIGURE 2. TYPICAL APPLICATION - HIGH VOLTAGE INPUT PRIMARY SIDE CONTROL ZVS FULL-BRIDGE CONVERTER
VIN+
VIN-
RETURN
T2
R7
C15
C2
R1
R3
R2
Q11
400 VDC
U1
L1
T1
R5
VR1
R8
+
VOUT
C7
C1
Q2
Q3
R11
R10
R12
R13
C6
C3
C10
C9
C8
C12
C13
T3
Q5A
Q5B
Q8A
Q8B
CR3
CR2
+
+
Q6A
Q6B
Q7A
Q7B
VDD
R14
R15
C11
C14
U3
R16
R17
R18
Q9A
Q9B
Q10A
Q10B
U2
CR1
Q1
Q4
R4
R6
C4
VERR OUTLL
RTD
OUTLRN
OUTLLN
VREF
OUTUR
CTBUF
CT
OUTUL
RESDEL
OUTLR
VADJ VDD
CS GND
ISL6752
U5 U4
T4
C5
R19
R20
R21 R22
R23
R24
CR4
Q12
Q13
R23
C16
Q14
R24
EL7212 EL7212
C17
FN9181 Rev 4.00 Page 5 of 18
August 1, 2016
ISL6752
Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter
FIGURE 3. TYPICAL APPLICATION - HIGH VOLTAGE INPUT SECONDARY SIDE CONTROL ZVS FULL-BRIDGE CONVERTER
VIN+
VIN-
RETURN
T2
R6
C13
C2
400 VDC
U1
L1
T1
Np:Ns:Ns = 9:2:2
R2
R8
+ VOUT
C14
C1
Q2
Q3
R12
R13
R15
R14
C5C3
C10
C12
C11
T3
1:1:1
Q5
CR3
CR2
+
+
SECONDARY
BIAS
SUPPLY
R19
R18
C15
C16
U3
R17
Q9A
Q9B
Q10A
Q10B
CR1
Q1
Q4
R1
R3 C4
VERR OUTLL
RTD
OUTLRN
OUTLLN
VREF
OUTUR
CTBUF
CT
OUTUL
RESDEL
OUTLR
VADJ VDD
CS GND
ISL6752
R7
R9
R4 R5
Q16
Q15
C7 Q12A
Q12B
Q11A
Q11B
R11
CR5
R10 CR4
Q13A
Q13B
Q14A
Q14B
Q7A
Q7B
C8
Q8A
Q8B
Q6
T4
1:1:1
C9
C17
R20
R16
Q17
Np
Ns
Ns
C6
+
-
VREF
R22
R21
C18
VREF
ISL6752
FN9181 Rev 4.00 Page 6 of 18
August 1, 2016
Absolute Maximum Ratings (Note 5)Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +20.0V
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1A
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . 9VDC to 16VDC
Thermal Resistance Junction to Ambient (Typical) JA (°C/W)
16 Ld QSOP (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “typical application on Figure 2 on page 4 and Figure 3 on page 5. 9V < VDD < 20V, RTD = 10.0kΩ CT = 470pF, TA = -40°C to +105°C, Typical values
are at TA= +25°C.
PARAMETER TEST CONDITIONS
MIN
(Note 10)TYP
MAX
(Note 10)UNIT
SUPPLY VOLTAGE
Supply Voltage - - 20 V
Start-Up Current, IDD VDD = 5.0V - 175 400 µA
Operating Current, IDD RLOAD, COUT = 0 - 11.0 15.5 mA
UVLO START Threshold 8.00 8.75 9.00 V
UVLO STOP Threshold 6.50 7.00 7.50 V
Hysteresis -1.75-V
REFERENCE VOLTAGE
Overall Accuracy IVREF = 0mA to -10mA 4.850 5.000 5.150 V
Long Term Stability TA = +125°C, 1000 hours (Note 6)- 3 -mV
Operational Current (Source) -10 - - mA
Operational Current (Sink) 5- -mA
Current Limit VREF = 4.85V -15 - -100 mA
CURRENT SENSE
Current Limit Threshold VERR = VREF 0.97 1.00 1.03 V
CS to OUT Delay Excl. LEB (Note 6) - 35 50 ns
Leading Edge Blanking (LEB) Duration (Note 6)5070100ns
CS to OUT Delay + LEB TA = +25°C - - 130 ns
CS Sink Current Device Impedance VCS = 1.1V - - 20 Ω
Input Bias Current VCS = 0.3V -6.00 - -2.00 µA
CS to PWM Comparator Input Offset TA = +25°C 65 80 95 mV
PULSE WIDTH MODULATOR
VERR Pull-Up Current Source VERR = 2.50V 0.80 1.00 1.30 mA
VERR VOH ILOAD = 0mA 4.20 - - V
Minimum Duty Cycle VERR < 0.6V - - 0 %
ISL6752
FN9181 Rev 4.00 Page 7 of 18
August 1, 2016
Maximum Duty Cycle (Per Half-Cycle) VERR = 4.20V, VCS = 0V (Note 7)-94-%
RTD = 2.0kΩ, CT = 220pF - 97 - %
RTD = 2.0kΩ CT = 470pF - 99 - %
Zero Duty Cycle VERR Voltage 0.85 - 1.20 V
VERR to PWM Comparator Input Offset TA = +25°C 0.7 0.8 0.9 V
VERR to PWM Comparator Input Gain 0.31 0.33 0.35 V/V
Common-Mode (CM) Input Range (Note 6)0-4.45V
OSCILLATOR
Frequency Accuracy, Overall (Note 6) 165 183 201 kHz
-10 - 10 %
Frequency Variation with VDD TA = +25°C, (F20V- - F10V)/F10V -0.31.7%
Temperature Stability VDD = 10V, |F-40°C - F0°C|/F0°C -4.5-%
|F0°C - F105°C|/F25°C (Note 6)-1.5-%
Charge Current TA = +25°C -193 -200 -207 µA
Discharge Current Gain 19 20 23 µA/µA
CT Valley Voltage Static Threshold 0.75 0.80 0.88 V
CT Peak Voltage Static Threshold 2.75 2.80 2.88 V
CT Peak-to-Peak Voltage Static Value 1.92 2.00 2.05 V
RTD Voltage 1.97 2.00 2.03 V
RESDEL Voltage Range 0 - 2.00 V
CTBUF Gain (VCTBUFp-p/VCTp-p)V
CT = 0.8V, 2.6V 1.95 2.0 2.05 V/V
CTBUF Offset from GND VCT = 0.8V 0.34 0.40 0.44 V
CTBUF VOH V(ILOAD = 0mA, ILOAD = -2mA),
VCT = 2.6V
- - 0.10 V
CTBUF VOL V(ILOAD = 2mA, ILOAD = 0mA),
VCT = 0.8V
- - 0.10 V
OUTPUT
High Level Output Voltage (VOH)I
OUT = -10mA, VDD to VOH -0.51.0V
Low Level Output Voltage (VOL)I
OUT = 10mA, VOL to GND - 0.5 1.0 V
Rise Time COUT = 220pF, VDD = 15V (Note 6) - 110 200 ns
Fall Time COUT = 220pF, VDD = 15V (Note 6) - 90 150 ns
UVLO Output Voltage Clamp VDD = 7V, ILOAD = 1mA (Note 8)--1.25V
Output Delay/Advance Range
OUTLLN/OUTLRN relative to OUTLL/OUTLR
VADJ = 2.50V (Note 6)--3ns
VADJ < 2.425V -40 - -300 ns
VADJ > 2.575V 40 - 300 ns
Delay/Advance Control Voltage Range
OUTLLN/OUTLRN relative to OUTLL/OUTLR
OUTLxN Delayed 2.575 - 5.000 V
OUTLxN Advanced 0 - 2.425 V
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “typical application on Figure 2 on page 4 and Figure 3 on page 5. 9V < VDD < 20V, RTD = 10.0kΩ CT = 470pF, TA = -40°C to +105°C, Typical values
are at TA= +25°C. (Continued)
PARAMETER TEST CONDITIONS
MIN
(Note 10)TYP
MAX
(Note 10)UNIT
ISL6752
FN9181 Rev 4.00 Page 8 of 18
August 1, 2016
VADJ Delay Time TA = +25°C (OUTLx Delayed) (Note 9)
VADJ = 0 280 300 320 ns
VADJ = 0.5V 92 105 118 ns
VADJ = 1.0V 61 70 80 ns
VADJ = 1.5V 48 55 65 ns
VADJ = 2.0V 41 50 58 ns
TA = +25°C (OUTLxN Delayed)
VADJ = VREF 280 300 320 ns
VADJ = VREF - 0.5V 86 100 114 ns
VADJ = VREF - 1.0V 59 68 77 ns
VADJ = VREF - 1.5V 47 55 62 ns
VADJ = VREF - 2.0V 41 48 55 ns
THERMAL PROTECTION
Thermal Shutdown (Note 6) 130 140 150 °C
Thermal Shutdown Clear (Note 6) 115 125 135 °C
Hysteresis, Internal Protection (Note 6) - 15 - °C
NOTES:
6. Limits established by characterization and are not production tested.
7. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using
other values for these components. See Equations 1 through 3.
8. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
9. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time
(dead time) as determined by CT and RTD.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “typical application on Figure 2 on page 4 and Figure 3 on page 5. 9V < VDD < 20V, RTD = 10.0kΩ CT = 470pF, TA = -40°C to +105°C, Typical values
are at TA= +25°C. (Continued)
PARAMETER TEST CONDITIONS
MIN
(Note 10)TYP
MAX
(Note 10)UNIT
ISL6752
FN9181 Rev 4.00 Page 9 of 18
August 1, 2016
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize noise
immunity, bypass VDD to GND with a ceramic capacitor as
close to the VDD and GND pins as possible.
VDD is monitored for supply voltage Undervoltage Lock-Out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a low
impedance layout is necessary. Ground planes and short
traces are highly recommended.
VREF - The 5.0V reference voltage output having 3% tolerance
over line, load and operating temperature. Bypass to GND with
a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between this
pin and GND. It is charged through an internal 200µA current
source and discharged with a user adjustable current source
controlled by RTD.
RTD - This is the oscillator timing capacitor discharge current
control pin. The current flowing in a resistor connected
between this pin and GND determines the magnitude of the
current that discharges CT. The CT discharge current is
nominally 20x the resistor current. The PWM dead time is
determined by the timing capacitor discharge duration. The
voltage at RTD is nominally 2V.
CS - This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1V nominal. The CS
pin is shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series
input resistor may be required due to the delay between the
internal clock and the external power switch. This delay may
result in CS being discharged prior to the power switching
device being turned off.
OUTUL and OUTUR - These outputs control the upper bridge
FETs and operate at a fixed 50% duty cycle in alternate
sequence. OUTUL controls the upper left FET and OUTUR
controls the upper right FET. The left and right designation may
be switched as long as they are switched in conjunction with
the lower FET outputs, OUTLL and OUTLR.
RESDEL - Sets the resonant delay period between the toggle of
the upper FETs and the turn on of either of the lower FETs. The
voltage applied to RESDEL determines when the upper FETs
switch relative to a lower FET turning on. Varying the control
voltage from 0V to 2V increases the resonant delay duration
from 0 to 100% of the dead time. The control voltage divided
by 2 represents the percent of the dead time equal to the
resonant delay. In practice the maximum resonant delay must
Typical Performance Curves
FIGURE 4. REFERENCE VOLTAGE vs TEMPERATURE FIGURE 5. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
FIGURE 6. DEAD TIME (DT) vs CAPACITANCE FIGURE 7. CAPACITANCE vs FREQUENCY
-40 -25 -10 5 20 35 50 65 80 95 110
0.98
0.99
1.00
1.01
1.02
TEMPERATURE (°C)
NORMALIZED VREF
0 200 400 600 800 1000
18
19
20
21
22
23
24
25
RTD CURRENT (µA)
CT DISCHARGE CURRENT GAIN
0 102030405060708090100
10
100
RTD (kΩ)
DEAD TIME DT (ns)
1-104
1-103
CT = 1000pF
CT = 680pF
CT = 470pF
CT = 330pF CT = 220pF
CT = 100pF
0.1 1 10
10
100
CT (nF)
FREQUENCY (kHz)
1-103
RTD = 10kΩ
RTD = 50kΩ
RTD = 100kΩ
ISL6752
FN9181 Rev 4.00 Page 10 of 18
August 1, 2016
be set lower than 2V to ensure that the lower FETs, at
maximum duty cycle, are OFF prior to the switching of the
upper FETs.
OUTLL and OUTLR - These outputs control the lower bridge FETs,
are pulse width modulated, and operate in alternate sequence.
OUTLL controls the lower left FET and OUTLR controls the lower
right FET. The left and right designation may be switched as long
as they are switched in conjunction with the upper FET outputs,
OUTUL and OUTUR.
OUTLLN and OUTLRN - These outputs are the complements of
the PWM (lower) bridge FETs. OUTLLN is the complement of
OUTLL and OUTLRN is the complement of OUTLR. These
outputs are suitable for control of synchronous rectifiers. The
phase relationship between each output and its complement
is controlled by the voltage applied to VADJ.
VADJ - A 0V to 5.0V control voltage applied to this input sets
the relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained regardless of
the phase adjustment between OUTLL/OUTLR and
OUTLLN/OUTLRN.
Voltages below 2.425V result in OUTLLN/OUTLRN being
advanced relative to OUTLL/OUTLR. Voltages above 2.575V
result in OUTLLN/OUTLRN being delayed relative to
OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero phase
difference. A weak internal 50% divider from VREF results in
no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40ns to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(t/V) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR outputs
(VADJ < 2.425V), the delay time should not exceed 90% of the
dead time as determined by RTD and CT.
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external Error Amplifier
(EA) is applied to this input, either directly or through an
opto-coupler, for closed loop regulation. VERR has a nominal
1mA pull-up current source.
CTBUF - CTBUF is the buffered output of the sawtooth oscillator
waveform present on CT and is capable of sourcing 2mA. It is
offset from ground by 0.40V and has a nominal valley-to-peak
gain of 2. It may be used for slope compensation.
Functional Description
Features
The ISL6752 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous
rectifier drive. With its many protection and control features, a
highly flexible design with minimal external components is
possible. Among its many features are a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
synchronous rectifier outputs with variable delay/advance
timing, and adjustable frequency.
If synchronous rectification is not required, please consider the
ISL6753 controller.
Oscillator
The ISL6752 has an oscillator with a programmable frequency
range to 2MHz, which can be programmed with a resistor and
capacitor.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge duration is determined by
CT and a fixed 200µA internal current source. The discharge
duration is determined by RTD and CT.
Where tC and tD are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, tSW is the
oscillator period, and fSW is the oscillator frequency. One
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error due
to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces a
CT discharge current of 20mA.
The maximum duty cycle, D, and percent dead time, DT, can be
calculated from Equations 4 and 5:
tC11.5 103CT S(EQ. 1)
tD0.06 RTD CT50 10 9–
+S(EQ. 2)
tSW tCtD
+1
fSW
----------
== S(EQ. 3)
D
tC
tSW
----------
=(EQ. 4)
DT 1 D–= (EQ. 5)
ISL6752
FN9181 Rev 4.00 Page 11 of 18
August 1, 2016
Implementing Soft-Start
The ISL6752 does not have a soft-start feature. Soft-start can
be implemented externally using the components shown in
Figure 5. The RC network governs the rate of rise of the
transistor’s base, which clamps the voltage at VERR.
The values of R and C should be selected to control the rate of
rise of VERR to the desired soft-start duration. The soft-start
duration may be calculated from Equation 6.
Where VSS is the soft-start clamp voltage, Vbe is the base
emitter voltage drop of the transistor, and is the DC gain of
the transistor. If is sufficiently large, that term may be
ignored. The Schottky diode discharges the soft-start capacitor
so that the circuit may be reset quickly.
Gate Drive
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical ON-resistance of the outputs is
50Ω.
Overcurrent Operation
The cycle-by-cycle peak current control results in
pulse-by-pulse duty cycle reduction when the current feedback
signal exceeds 1.0V. When the peak current exceeds the
threshold, the active output pulse is immediately terminated.
This results in a well controlled decrease in output voltage as
the load current increases beyond the current limit threshold.
The ISL6752 will operate continuously in an overcurrent
condition.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased by
the Leading Edge Blanking (LEB) interval. The effective delay is
the sum of the two delays and is nominally 105ns.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be accomplished
by summing an external ramp with the current feedback signal
or by subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current feedback
signal is the more popular method.
From the small signal current-mode model [1] it can be shown
that the naturally-sampled modulator gain, Fm, without slope
compensation, is expressed in Equation 7:
Where Sn is the slope of the sawtooth signal and tSW is the
duration of the half-cycle. When an external ramp is added, the
modulator gain becomes Equation 8:
Where Se is slope of the external ramp and:
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the damping
factor of the double-pole located at half the oscillator
frequency. The double-pole will be critically damped if the
Q-factor is set to 1, and over-damped for Q > 1, and
under-damped for Q < 1. An under-damped condition can
result in current loop instability.
Where D is the percent of on-time during a half cycle. Setting
Q = 1 and solving for Se yields in Equation 11:
Since Sn and Se are the on-time slopes of the current ramp
and the external ramp, respectively, they can be multiplied by
tON to obtain the voltage change that occurs during tON.
Where Vn is the change in the current feedback signal during
the on-time and Ve is the voltage that must be added by the
external ramp.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding in
Equation 13:
FIGURE 8. IMPLEMENTING SOFT-START
VREF
1
2
4
3
5
6
7
89
1
0
1
1
1
2
1
3
1
4
1
5
1
6
ISL6752
VERR
R
C
tRC–1
VSS Vbe
–
VREF 0.001R
-------------------
+
-------------------------------------------
–




ln=S(EQ. 6)
Fm 1
SntSW
------------------
=(EQ. 7)
Fm 1
SnSe
+tSW
------------------------------------ 1
mcSntSW
--------------------------
== (EQ. 8)
mc1
Se
Sn
-------
+= (EQ. 9)
Q1
mc1D–0.5–
-------------------------------------------------
=(EQ. 10)
SeSn
1
---0.5+


1
1D–
------------- 1–


=(EQ. 11)
VeVn
1
---0.5+


1
1D–
------------- 1–


=(EQ. 12)
Ve
tSW VORCS
NCT LO
----------------------------------------NS
NP
--------
1
---D0.5–+


=V(EQ. 13)
ISL6752
FN9181 Rev 4.00 Page 12 of 18
August 1, 2016
Where RCS is the current sense burden resistor, NCT is the
current transformer turns ratio, LO is the output inductance, VO
is the output voltage, and NS and NP are the secondary and
primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields in
Equation 14:
Where VCS is the voltage across the current sense resistor and
IO is the output current at current limit.
Since the peak current limit threshold is 1.0V, the total current
feedback signal plus the external ramp voltage must sum to
this value.
Substituting Equations 13 and 14 into Equation 15 and solving
for RCS yields in Equation 16:
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp to
add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces the
amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is reflected
from the inductor current in the secondary.
Where VIN is the input voltage that corresponds to the duty
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense resistor,
RCS, is expressed in Equation 18:
If VCS is greater than or equal to Ve, then no additional slope
compensation is needed and RCS becomes Equation 19:
If VCS is less than Ve, then Equation 16 is still valid for the
value of RCS, but the amount of slope compensation added by
the external ramp must be reduced by VCS.
Adding slope compensation may be accomplished in the
ISL6752 using the CTBUF signal. The CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-peak
amplitude of CT (0.4V to 4.4V). A typical application sums this
signal with the current sense feedback and applies the result to
the CS pin, as shown in Figure 9.
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
Rearranging to solve for R9 yields Equation 21:
The value of RCS determined in Equations 16 must be rescaled
so, that the current sense signal presented at the CS pin is that
predicted by Equation 14. The divider created by R6 and R9
makes this necessary.
Example:
VIN = 280V
VO = 12V
LO = 2.0µH
Np/Ns = 20
Lm = 2mH
IO = 55A
Oscillator Frequency, fSW = 400kHz
Duty Cycle, D = 85.7%
NCT = 50
R6 = 499Ω
VCS
NSRCS
NPNCT
------------------------ IO
DtSW
2LO
------------------- VIN
NS
NP
--------
VO
–



+



=V(EQ. 14)
VeVCS
+1=(EQ. 15)
RCS
NPNCT
NS
------------------------ 1
IO
VO
LO
--------tSW
1
---D
2
----
+


+
----------------------------------------------------
=(EQ. 16)
IP
VIN DtSW
Lm
-----------------------------
=A(EQ. 17)
VCS
IPRCS
NCT
--------------------------
=V(EQ. 18)
RCS
NCT
NS
NP
--------IO
DtSW
2LO
--------------- VIN
NS
NP
--------
VO
–



+



VIN DtSW
Lm
-----------------------------
+
----------------------------------------------------------------------------------------------------------------------------------
=
(EQ. 19)
FIGURE 9. ADDING SLOPE COMPENSATION
R6
C4
R9
CTBUF
CS
1
2
4
3
5
6
7
8
RCS
ISL6752
VeVCS
–
DV
CTBUF 0.4–0.4+R6
R6R9
+
------------------------------------------------------------------------------
=V(EQ. 20)
R9
DV
CTBUF 0.4–VeVCS 0.4++–R6
VeVCS
–
------------------------------------------------------------------------------------------------------------------
=
(EQ. 21)
RCS
R6R9
+
R9
---------------------RCS
=(EQ. 22)
ISL6752
FN9181 Rev 4.00 Page 13 of 18
August 1, 2016
Solve for the current sense resistor, RCS, using Equation 16.
RCS = 15.1Ω.
Determine the amount of voltage, Ve, that must be added to the
current feedback signal using Equation 13.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 18.
VCS = 91mV
Using Equation 21, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
Determine the new value of RCS, R’CS, using Equation 22.
R’CS = 15.4Ω
This discussion determines the minimum external ramp that is
required. Additional slope compensation may be considered for
design margin.
If the application requires dead time of less than about 500ns,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by 300ns
to 400ns. This behavior results in a non-zero value of CTBUF
when the next half-cycle begins when the dead time is short.
Under these situations, slope compensation may be added by
externally buffering the CT signal as shown in Figure 10.
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 20 and 21
require modification. Equation 20 becomes:
and Equation 21 becomes:
The buffer transistor used to create the external ramp from CT
should have a sufficiently high gain (>200) so as to minimize the
required base current. Whatever base current is required reduces
the charging current into CT and will reduce the oscillator
frequency.
ZVS Full-Bridge Operation
The ISL6752 is a full-bridge zero-voltage switching (ZVS) PWM
controller that behaves much like a traditional hard switched
topology controller. Rather than drive the diagonal bridge
switches simultaneously, the upper switches (OUTUL, OUTUR) are
driven at a fixed 50% duty cycle and the lower switches (OUTLL,
OUTLR) are pulse width modulated on the trailing edge.
To understand how the ZVS method operates, one must include
the parasitic elements of the circuit and examine a full switching
cycle.
Figure 12, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the transformer
leakage inductance has been included as a discrete element.
The parasitic capacitance has been lumped together as switch
capacitance, but represents all parasitic capacitance in the
circuit including winding capacitance. Each switch is designated
by its position; Upper Left (UL), Upper Right (UR), Lower Left (LL),
and Lower Right (LR). The beginning of the cycle, shown in
FIGURE 10. ADDING SLOPE COMPENSATION USING CT
FIGURE 11. BRIDGE DRIVE SIGNAL TIMING
CT
DEAD TIME
OUTLL
OUTLR
OUTUR
OUTUL RESDEL
WINDOW
RESONANT
DELAY
PWM
PWM
PWM
PWM
FIGURE 12. IDEALIZED FULL-BRIDGE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
LL
D2
D1
ISL6752
FN9181 Rev 4.00 Page 14 of 18
August 1, 2016
Figure 13, is arbitrarily set as having switches UL and LR on and
UR and LL off. The direction of the primary and secondary
currents are indicated by IP and IS, respectively.
The UL to LR power transfer period terminates when switch LR
turns off as determined by the PWM. The current flowing in the
primary cannot be interrupted instantaneously, so it must find an
alternate path. The current flows into the parasitic switch
capacitance of LR and UR, which charges the node to VIN and
then forward biases the body diode of upper switch UR.
The primary leakage inductance, LL, maintains the current,
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens, the
output inductor current free-wheels through both output diodes,
D1 and D2. During the switch transition, the output inductor
current assists the leakage inductance in charging the upper and
lower bridge FET capacitance.
The current flow from the previous power transfer cycle tends to
be maintained during the free-wheeling period because the
transformer primary winding is essentially shorted. Diode D1
may conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This behavior is quite different
than occurs in a conventional hard-switched full-bridge topology
where the free-wheeling current splits nearly evenly between the
output diodes, and flows not at all in the primary.
This condition persists through the remainder of the half cycle.
During the period when CT discharges (also referred to as the
dead time), the upper switches toggle. Switch UL turns off and
switch UR turns on. The actual timing of the upper switch toggle
is dependent on RESDEL, which sets the resonant delay. The
voltage applied to RESDEL determines how far in advance the
toggle occurs prior to a lower switch turning on. The ZVS
transition occurs after the upper switches toggle and before the
diagonal lower switch turns on. The required resonant delay is
1/4 of the period of the LC resonant frequency of the circuit
formed by the leakage inductance and the parasitic capacitance.
The resonant transition may be estimated from Equation 25.
Where is the resonant transition time, LL is the leakage
inductance, CP is the parasitic capacitance, and R is the
equivalent resistance in series with LL and CP.
The resonant delay is always less than or equal to the dead time
and may be calculated using Equation 26.
Where resdel is the desired resonant delay, Vresdel is a voltage
between 0V and 2V applied to the RESDEL pin, and DT is the
dead time (see Equations 1 through 5).
When the upper switches toggle, the primary current that was
flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL and
LL until the body diode of LL is forward-biased. If RESDEL is set
properly, switch LL will be turned on at this time. The output
inductor does not assist this transition. It is purely a resonant
transition driven by the leakage inductance.
The second power transfer period commences when switch LL
closes. With switches UR and LL on, the primary and secondary
currents flow, as indicated in Figure 16.
The UR to LL power transfer period terminates when switch LL
turns off, as determined by the PWM. The current flowing in the
primary must find an alternate path. The current flows into the
parasitic switch capacitance, which charges the node to VIN and
FIGURE 13. UL TO LR POWER TRANSFER CYCLE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
FIGURE 14. UL TO UR FREE-WHEELING PERIOD
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT TRANSITION
FIGURE 16. UR TO LL POWER TRANSFER CYCLE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
LL
D2
D1 IS
IP
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
LL
D2
D1
ISL6752
FN9181 Rev 4.00 Page 15 of 18
August 1, 2016
then forward biases the body diode of upper switch UL. As before,
the output inductor current assists in this transition. The primary
leakage inductance, LL, maintains the current, which now
circulates around the path of switch UR, the transformer primary,
and switch UL. When switch LL opens, the output inductor current
free wheels predominantly through diode D1. Diode D2 may
actually conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This condition persists through
the remainder of the half-cycle.
When the upper switches toggle, the primary current that was
flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR and
LR until the body diode of LR is forward-biased. If RESDEL is set
properly, switch LR will be turned on at this time.
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires that the
leakage inductance has sufficient energy stored to fully charge
the parasitic capacitances. Since the energy stored is
proportional to the square of the current (1/2 LLIP2), the ZVS
resonant transition is load dependent. If the leakage inductance
is not able to store sufficient energy for ZVS, a discrete inductor
may be added in series with the transformer primary.
Synchronous Rectifier Outputs and Control
The ISL6752 provides double-ended PWM outputs, OUTLL and
OUTLR, and Synchronous Rectifier (SR) outputs, OUTLLN and
OUTLRN. The SR outputs are the complements of the PWM
outputs. It should be noted that the complemented outputs are
used in conjunction with the opposite PWM output, i.e., OUTLL
and OUTLRN are paired together and OUTLR and OUTLLN are
paired together.
Referring to Figure 19, the SRs alternate between being both on
during the free-wheeling portion of the cycle (OUTLL/LR off) and
one or the other being off when OUTLL or OUTLR is on. If OUTLL is
on, its corresponding SR must also be on, indicating that OUTLRN
is the correct SR control signal. Likewise, if OUTLR is on, its
corresponding SR must also be on, indicating that OUTLLN is the
correct SR control signal.
A useful feature of the ISL6752 is the ability to vary the phase
relationship between the PWM outputs (OUTLL, OUT LR) and their
complements (OUTLLN, OUTLRN) by ±300ns. This feature allows
the designer to compensate for differences in the propagation
times between the PWM FETs and the SR FETs. A voltage applied
to VADJ controls the phase relationship.
FIGURE 17. UR - UL FREE-WHEELING PERIOD
FIGURE 18. UPPER SWITCH TOGGLE AND RESONANT TRANSITION
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
FIGURE 19. BASIC WAVEFORM TIMING
FIGURE 20. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED, 0V
< VADJ < 2.425V
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
ISL6752
FN9181 Rev 4.00 Page 16 of 18
August 1, 2016
Setting VADJ to VREF/2 results in no delay on any output. The no
delay voltage has a ±75mV tolerance window. Control voltages
below the VREF/2 zero delay threshold cause the PWM outputs,
OUTLL/LR, to be delayed. Control voltages greater than the
VREF/2 zero delay threshold cause the SR outputs, OUTLLN/LRN,
to be delayed. It should be noted that when the PWM outputs,
OUTLL/LR, are delayed, the CS to output propagation delay is
increased by the amount of the added delay.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as may be
experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required using
external resistors, capacitors and diodes.
When the PWM outputs are delayed, the 50% upper outputs are
equally delayed, thus the resonant delay setting is unaffected.
On/Off Control
The ISL6753 does not have a separate enable/disable control
pin. The PWM outputs, OUTLL/OUTLR, may be disabled by pulling
VERR to ground. Doing so reduces the duty cycle to zero, but the
upper 50% duty cycle outputs, OUTUL/OUTUR, will continue
operation. Likewise, the SR outputs OUTLLN/OUTLRN will be
active high.
If the application requires that all outputs be off, then the supply
voltage, VDD, must be removed from the IC. This may be
accomplished as shown in Figure 19.
Fault Conditions
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected the outputs are
disabled low. When the fault condition clears the outputs are
re-enabled.
An overcurrent condition is not considered a fault and does not
result in a shutdown.
Thermal Protection
Internal die over-temperature protection is provided. An
integrated temperature sensor protects the device should the
junction temperature exceed +140°C. There is approximately
+15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. VDD and VREF should
be bypassed directly to GND with good high frequency
capacitance.
References
[1] Ridley, R., “A New Continuous-Time Model for Current Mode
Control”, IEEE Transactions on Power Electronics, Vol. 6, No.
2, April 1991.
FIGURE 21. WAVEFORM TIMING WITH SR OUTPUTS DELAYED,
2.575V < VADJ < 5.0V
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 22. ON/OFF CONTROL USING VDD
VERR
OUTLL
RTD
OUTLRN
OUTLLN
VREF
OUTUR
CTBUF
CT
OUTUL
RESDEL
OUTLR
VADJ VDD
CS GND
+VDD
ON/OFF
(OPEN = OFF
GND = ON)
ISL6752
FN9181 Rev 4.00 Page 17 of 18
August 1, 2016
ISL6752
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2005-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE REVISION CHANGE
August 1, 2016 FN9181.4 - Updated to new template.
- On page 1: Added “Related Literature”.
- Ordering information table on page 2: Added “ISL6752/54EVAL1Z” and “ISL6752DBEVAL1Z”. Updated
Note 1 in the ordering information table to include tape and reel options.
- Added Table 1 on page 2.
- Electrical Specifications table on page 6: Updated “REFERENCE VOLTAGE” section, from “IVREF = 0mA
to 10mA” to “0mA” to “-10mA”.
- Updated POD M16.15A to most recent revision with change as follows:
Convert to new POD format. Added land pattern.
- Added revision history and about Intersil verbiage.
ISL6752
FN9181 Rev 4.00 Page 18 of 18
August 1, 2016
Package Outline Drawing
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP)
0.150” WIDE BODY
Rev 3, 8/12
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number
95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Package length does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Package width does not include interlead flash or protrusions. Interlead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.
6. Terminal numbers are shown for reference only.
7. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be
0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.
8. Controlling dimension: MILLIMETER.
INDEX
AREA
16
1
-B-
0.17(0.007) CAMBS
-A-
M
-C-
SEATING PLANE
0.10(0.004) x 45°
0.25
0.010
GAUGE
PLANE
3.99
3.81
6.20
5.84
40.25(0.010) B
MM
0.89
0.41
0.41
0.25 5
8°
0° 1.55
1.40 0.249
0.191
4.98
4.80
31.73
1.55
0.249
0.102
0.31
0.20
7
0.635 BSC
5.59
4.06
7.11
0.38
0.635
DETAIL “X”
SIDE VIEW 1
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW 2
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Intersil:
ISL6752DBEVAL1Z