1 of 17 070802
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device errata,
click here: http://www.maxim-ic.com/errata.
FEATURES
§ Compresses/expands 64kbps PCM voice
to/from either 32kbps, 24kbps, or 16kbps
§ Dual fully independent channel architecture;
device can be programmed to perform either:
- two expansions
- two compressions
- one expansion and one compression
§ Interconnects directly to combo-codec
devices
§ Input to output delay is less than 375ms
§ Simple serial port used to configure the
device
§ On-board time-slot assigner-circuit (TSAC)
function allows data to be input/output at
various time slots
§ Supports Channel Associated Signaling
§ Each channel can be independently idled or
placed into bypass
§ Available hardware mode requires no host
processor; ideal for voice storage
applications
§ Single +5V supply; low-power CMOS
technology
§ Available in 28-pin PLCC
§ 3V operation version is available
(DS2165QL)
PIN ASSIGNMENT (Top View)
DESCRIPTION
The DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been
optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three
different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from)
either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT
Recommendation G.721 (July 1986) and ANSI document T1.301 (April 1987). The compression to
24kbps follows ANSI document T1.303. The compression to 16kbps follows a proprietary algorithm
developed by Dallas Semiconductor. The DS2165Q can switch compression algorithms on-the-fly. This
allows the user to make maximum use of the available bandwidth on a dynamic basis.
28-Pin PLCC
NC
A0
A1
A2
A3
A4
FSY
YOUT
CS
SDI
SCLK
XOUT
A5 NC
TM1
TM0
RST
NC
VDD
YIN
CLKY
SPS
MCL
K
VSS
NC
XIN
CLK
X
FS
X
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
12 13 14 15 16 17 18
www.maxim-ic.com
DS2165Q
16/24/32kbps ADPCM Processo
r
DS2165Q
DS2165Q
2 of 17
OVERVIEW
The DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two
independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM)
backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz
master clock is required by the DSP engine. The DS2165Q can be configured to perform either two
expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces
support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for m-law and
2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream
during a user-programmed input time slot, processes the data and outputs the result during a user-
programmed output time slot.
Each PCM interface has a control register that specifies functional characteristics (compress, expand,
bypass, and idle), data format (m-law or A-law), and algorithm reset control. With the SPS pin strapped
high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a
novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying
system-level interconnect.
With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control
register bits to some of the address and serial port pins. Under the hardware mode, no external host
controller is required and all PCM/ADPCM input and output time slots default to time slot 0.
HARDWARE RESET
RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin
must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the
device has initialized properly. RST should also be asserted when changing to or from the hardware
mode. RST clears all bits of the control register for both channels except the IPD bits; the IPD bits for
both channels are set to 1.
SOFTWARE MODE
Connecting SPS high enables the software mode. In this mode, an external host controller writes
configuration data to the DS2165Q by the serial port through inputs SCLK, SDI, and CS (Figure 2). Each
write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the
address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X
or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1
byte to set the input time slot and another byte to set the output time slot.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the first byte written to the serial port; it identifies
which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must
match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If
an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.
Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs
are tri-stated during register updates.
DS2165Q
3 of 17
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format, and channel coding for the
selected channel.
The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When
IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port
must not be operated faster than 39kHz.
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared
by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PIN SYMBOL TYPE FUNCTION
2RST IReset. A high-low-high transition resets the algorithm. The device should be
reset on power-up and when changing to or from the hardware mode.
3
4
TM0
TM1 ITest Modes 0 and 1. Connect to VSS for normal operation.
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
IAddress Select. A0 = LSB, A5 = MSB. Must match address/command word
to enable the serial port.
12 SPS I Serial Port Select. Connect to VDD to select the serial port; connect to VSS to
select the hardware mode.
13 MCLK I Master Clock. 10MHz clock for the ADPCM processing engine; may be
asynchronous to SCLK, CLKX, and CLKY.
14 VSS Signal Ground. 0V
16 XIN I X Data In. Sampled on falling edge of CLKX during selected time slots.
17 CLKX I X Data Clock. Data clock for the X-side PCM interface; must be
synchronous with FSX.
18 FSX I X Frame Sync. 8kHz frame sync for the X-side PCM interface.
20 XOUT O X Data Output. Updated on rising edge of CLKX during selected time slots.
21 SCLK I Serial Data Clock. Used to write to the serial port registers.
22 SDI I Serial Data In. Data for on-board control registers; sampled on the rising
edge of SCLK. LSB sent first.
23 CS IChip Select. Must be low to write to the serial port.
24 YOUT O Y Data Output. Updated on rising edge of CLKY during selected time slots.
25 FSY I Y Frame Sync. 8kHz frame sync for the Y-side PCM interface.
26 CLKY I Y Data Clock. Data clock for the Y-side PCM interface; must be
synchronous with FSY.
27 YIN I Y Data In. Sampled on falling edge of CLKY during selected time slots.
28 VDD Positive Supply. 5.0V (3.0V for DS2165QL)
DS2165Q
4 of 17
Figure 1. BLOCK DIAGRAM
Figure 2. SERIAL PORT WRITE
Note: A 2-byte write is shown.
The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or
compression occurs. Bypass operates on bytewide (8 bits) slots when CP/ EX is set and on nibble-wide
(4 bits) slots when CP/ EX is cleared.
A-law (U/
A
= 0) and m-law (U/
A
= 1) PCM coding is independently selected for the X and Y channels
by CR.2. If BYP and IPD are cleared, then CP/ EX determines if the input data is to be compressed or
expanded.
DS2165Q
5 of 17
Figure 3. ADDRESS/COMMAND BYTE
(MSB) (LSB)
X/ YA5 A4 A3 A2 A1 A0
SYMBOL POSITION FUNCTION
ACB.7 Reserved. Must be 0 for proper operation
X/ YACB.6
X/Y Channel Select
0 = update channel Y characteristics
1 = update channel X characteristics
A5 ACB.5 MSB of device address
A4 ACB.4
A3 ACB.3
A2 ACB.2
A1 ACB.1
A0 ACB.0 LSB of device address
Figure 4. CONTROL REGISTER
(MSB) (LSB)
AS0 AS1 IPD ALRST BYP U/
A
AS2 CP/ EX
SYMBOL POSITION FUNCTION
AS0 CR.7 Algorithm Select 0 (Table 2)
AS1 CR.6 Algorithm Select 1 (Table 2)
IPD CR.5
Idle and Power-Down
0 = channel enabled
1 = channel disabled (output tri-stated)
ALRST CR.4
Algorithm Reset
0 = normal operation
1 = reset algorithm for selected channel
BYP CR.3
Bypass
0 = normal operation
1 = bypass selected channel
U/
A
CR.2
Data Format
0 = A-law
1 = m-law
AS2 CR.1 Algorithm Select 2 (Table 2)
CP/ EX CR.0
Channel Coding
0 = expand (decode) selected channel
1 = compress (encode) selected channel
DS2165Q
6 of 17
Table 2. ALGORITHM SELECT BITS
ALGORITHM SELECTED AS2 AS1 AS0
64kbps to/from 32kbps 0 0 0
64kbps to/from 24kbps 1 1 1
64kbps to/from 16kbps 1 0 1
Figure 5. INPUT TIME SLOT REGISTER
(MSB) (LSB)
-D5D4D3D2D1 D0
SYMBOL POSITION FUNCTION
ITR.7 Reserved. Must be 0 for proper operation
ITR.6 Reserved. Must be 0 for proper operation
D5 ITR.5 MSB of input time slot register
D4 ITR.4
D3 ITR.3
D2 ITR.2
D1 ITR.1
D0 ITR.0 LSB of input time slot register
Figure 6. OUTPUT TIME SLOT REGISTER
(MSB) (LSB)
D5 D4 D3 D2 D1 D0
SYMBOL POSITION FUNCTION
OTR.7 Reserved. Must be 0 for proper operation
OTR.6 Reserved. Must be 0 for proper operation
D5 OTR.5 MSB of output time slot register
D4 OTR.4
D3 OTR.3
D2 OTR.2
D1 OTR.1
D0 OTR.0 LSB of output time slot register
DS2165Q
7 of 17
TIME SLOT ASSIGNMENT/ORGANIZATION
On-board counters establish when PCM and ADPCM I/O occur. The counters are programmed by the
time slot registers. Time slot size (number of bits wide) is determined by the state of CP/ EX . The number
of time slots available is determined by the state of both CP/ EX and U/
A
(Figures 7 through 10). For
example, if the X channel is set to compress (CP/ EX = 1) and it is set to expect m-law data
(U/
A
= 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up
for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected.
Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX
or CLKY after the frame sync.
Figure 7. m-LAW PCM INTERFACE
Figure 8. m-LAW ADPCM INTERFACE
DS2165Q
8 of 17
Figure 9. A-LAW PCM INTERFACE
Figure 10. A-LAW ADPCM INTERFACE
DS2165Q
9 of 17
HARDWARE MODE
The hardware mode is intended for applications that do not have an external controller available or do not
require the extended features offered by the serial port. Connecting the SPS pin to VSS disables the serial
port, clears all internal register bits, and maps the IPD, U/
A
, and CP/ EX bits for both channels to external
bits (Table 3). In the hardware mode, both the input and output time slots default to time slot 0.
Table 3. HARDWARE MODE
PIN
# NAME REGISTER LOCATION FUNCTION
6A0 CP/ EX
(Channel X)
Channel X Coding Configuration
0 = Expand
1 = Compress
7A1 AS0/AS1/AS2
(Channel X and Y) Algorithm Select (Table 4)
8A2 U/
A
(Channel X)
Channel X Data Format
0 = A-law
1 = m-law
9A3 CP/ EX
(Channel Y)
Channel Y Coding Configuration
0 = Expand
1 = Compress
10 A4 AS0/AS1/AS2
(Channel X and Y) Algorithm Select (Table 4)
11 A5 U/
A
(Channel Y)
Channel Y Data Format
0 = A-law
1 = m-law
22 SDI IPD
(Channel Y)
Channel Y Idle Select
0 = Channel Active
1 = Channel Idle
23 CS
IPD
(Channel X)
Channel X Idle Select
0 = Channel Active
1 = Channel Idle
NOTES:
1) SCLK must be connected to VSS when the hardware mode is selected.
2) When both channels are idled, power consumption is significantly reduced.
3) The NIL powers up within 800ms after either channel is returned to active from an idle state.
DS2165Q
10 of 17
Table 4. ALGORITHM SELECT FOR HARDWARE MODE
ALGORITHM CONFIGURATION OF A1 AND A4
64kbps to/from 32kbps Connect both A1 and A4 to VSS.
64kpbs to/from 24kbps
Hold A1 and A4 low during a hardware reset;
take both A1 and A4 high after the RST pin
has returned high (allow 3ms after RST
returns high before taking A1 and A4 high).
64kbps to/from 16kbps Connect both A1 and A4 to VDD.
Figure 11. DS2165Q CONNECTION TO CODEC/FILTER
Suggested Codec/Filters*
TP305X National Semiconductor
ETC505X STMicroelectronics
MC1455XX Motorola, Inc.
TCM29CXX Texas Instruments Incorporated
HD44238C Hitachi
*Other generic codec/filter devices can be substituted.
DS2165Q
DS2165Q
11 of 17
PCM AND ADPCM INPUT/OUTPUT
Since the organization of the input and output time slots on the DS2165Q does not depend on the
algorithm selected, it always assumes that PCM input and output are in 8-bit bytes and that ADPCM
input and output are in 4-bit bytes. Figure 12 demonstrates how the DS2165Q handles the I/O for the
three different algorithms. In the figure, it is assumed that channel X is in the compression mode
(CP/ EX = 1) and channel Y is in the expansion mode (CP/ EX = 0). Also, it is assumed that both the input
and output time slots for both channels are set to 0.
Figure 12. PCM AND ADPCM I/O EXAMPLE
Note 1: The bit after the LSB in the 24kbps ADPCM output is only a 1 when the DS2165Q is operated
in the software mode and is programmed to perform 24kbps compression; in all other configurations, it is
a 0.
DS2165Q
12 of 17
TIME SLOT RESTRICTIONS
Under certain conditions, the DS2165Q does contain some restrictions on the output time slots that are
available. These restrictions are covered in detail in a separate application note. No restrictions occur if
the DS2165Q is operated in the hardware mode.
INPUT TO OUTPUT DELAY
With all three compressions algorithms, the total delay, from the time the PCM data sample is captured
by the DS2165Q to the time it is output, is always less than 375ms. The exact delay is determined by the
input and output time slots selected for each channel.
CHANNEL ASSOCIATED SIGNALING
The DS2165Q supports Channel Associated Signaling (CAS) through its ability to automatically change
from the 32kbps compression algorithm to the 24kbps algorithm. If the DS2165Q is configured to
perform the 32kbps algorithm, then in both the hardware and software mode it senses the frame sync
inputs (FSX and FSY) for a double-wide frame-sync pulse. Whenever the DS2165Q receives a double-
wide pulse, it automatically switches from the 32kbps algorithm to the 24kbps algorithm. Switching to
the 24kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM
output because this bit does not contain any useful speech information.
ON-THE-FLY ALGORITHM SELECTION
In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the
DS2165Q does not need to be reset or stopped to make the change from one algorithm to another. The
DS2165Q reads the control register before it starts to process each PCM or ADPCM sample. If the user
wishes to switch algorithms, then the control register must be updated by the serial port before the first
input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and
ACPCM outputs tri-state during register updates.
DS2165Q
13 of 17
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature Range 0°C to +70°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature Range See IPC/JEDEC J-STD-020A
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 VIH 2.0 VCC + 0.3 V 5, 7
Logic 0 VIL -0.3 +0.8 V 5
Supply VDD 4.5 5.5 V 5
Logic 1 VIH 2.2 VCC + 0.3 V 6
Logic 0 VIL -0.3 +0.4 V 6
Supply VDD 2.7 3.6 V 6
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5pF
Output Capacitance COUT 10 pF
DC ELECTRICAL CHARACTERISTICS (VDD = 5V ±10%, TA = 0°C to +70°C;
VDD = 3.0V + 20% - 10% for DS2165QL)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current IDDA 20 mA 1, 2, 5
Active Supply Current IDDA 12 mA 1, 2, 6
Idle Supply Current IDDPD 1 mA 1, 2, 3
Input Leakage II-1.0 +1.0 mA
Output Leakage IO-1.0 +1.0 mA4
Output Current (2.4V) IOH -1.0 mA 5
Output Current (0.4V) IOL +4.0 mA 5
Output Current (2.2V) IOH -0.5 mA 6
Output Current (0.4V) IOL +2.0 mA 6
NOTES:
1) CLKX = CLKY = 1.544MHz; MCLK = 10MHz
2) Outputs open; inputs swinging full supply levels.
3) Both channels in idle mode.
4) XOUT and YOUT are tri-stated.
5) Applies only to 5V device.
6) Applies only to 3V device (DS2165QL).
7) CLKX, CLKY, MCLK VIH MIN = 2.4V
DS2165Q
14 of 17
PCM INTERFACE, AC ELECTRICAL CHARACTERISTICS
(VDD = 5V ±10%, TA = 0°C to +70°C; VDD = 3.0V + 20% - 10% for DS2165QL)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CLKX, CLKY Period tPXY 244 3906 ns 1
CLKX, CLKY Pulse Width tWXYL
tWXYH
100 ns
CLKX, CLKY Rise Fall Times tRXY
tFXY
10 20 ns
Hold Time from CLKX, CLKY to FSX,
FSY tHOLD 0ns2
Setup Time from FSX, FSY High to
CLKX, CLKY Low tSF 50 ns 2
Hold Time from CLKX, CLKY Low to
FSX, FSY Low tHF 100 ns 2
Setup Time for XIN, YIN to CLKX,
CLKY Low tSD 50 ns 2
Hold Time for XIN, YIN to CLKX,
CLKY Low tHD 50 ns 2
Delay Time from CLKX, CLKY to
Valid XOUT, YOUT tDXYO 10 150 ns 3
Delay Time from CLKX, CLKY to
XOUT, YOUT Tri-stated tDXYZ 20 150 ns 2, 3, 4
NOTES:
1) Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames).
Maximum operating frequency is guaranteed by design and is not a tested parameter.
2) Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times.
3) Load = 150pF + 2 LSTTL loads.
4) For LSB of PCM or ADPCM byte.
MASTER CLOCK/RESET, AC ELECTRICAL CHARACTERISTICS
(VDD = 5V ±10%, TA = 0°C to +70°C; VDD = 3.0V + 20% - 10% for DS2165QL)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
MCLK Period tPM 100 ns 1
MCLK Pulse Width tWMH,
tWML
45 50 55 ns
MCLK Rise/Fall Times tRM, tFM 10 ns
RST Pulse Width tRST 1ms
NOTES:
1) MCLK = 10MHz ±500ppm
DS2165Q
15 of 17
SERIAL PORT, AC ELECTRICAL CHARACTERISTICS
(VDD = 5V ±10%, TA = 0°C to +70°C; VDD = 3.0V + 20% - 10% for DS2165QL)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
SDI to SCLK Setup tDC 55 ns 1
SCLK to SDI Hold tCDH 55 ns 1
SCLK Low Time tCL 250 ns 1
SCLK High Time tCH 250 ns 1
SCLK Rise and Fall Time tR, tF100 ns 1
CS to SCLK Setup tCC 50 ns 1
SCLK to CS Hold tCCH 250 ns 1
CS Inactive Time tCWH 250 ns 1
SCLK Setup to CS Falling tSCC 50 ns 1
NOTES:
1) Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times.
DS2165Q
16 of 17
Figure 13. PCM INTERFACE AC TIMING DIAGRAM
Figure 14. MASTER CLOCK/RESET AC TIMING DIAGRAM
Figure 15. SERIAL PORT AC TIMING DIAGRAM
Note: SCLK can be either high or low when CS is taken low.
DS2165Q
17 of 17
28-PIN PLCC
INCHES
DIM MIN MAX
A0.165 0.180
A1 0.090 0.120
A2 0.020
B0.026 0.033
B1 0.013 0.021
C0.009 0.012
D0.485 0.495
D1 0.450 0.456
D2 0.390 0.430
E0.485 0.495
E1 0.450 0.456
E2 0.390 0.430
L1 0.060
N28
e1 0.050 BSC
CH1 0.042 0.048